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Chapter 6
– MOSFET Operation
• Capacitance
– Accumulation
– Depletion
– Inversion
• IV Characteristics
– Linear
– Saturation
– Spice Models
• Short Channel
– LDD
– Scaling
– Hot Carriers
– Oxide Breakdown
– DIBL
– Body Effect
– Gate Tunneling
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 1
Baker Ch. 6 MOSFET Operation Introduction to VLSI
– SUBSTRATE RESISTANCE
• CANNOT NEGLECT
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 2
Baker Ch. 6 MOSFET Operation Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 3
Baker Ch. 6 MOSFET Operation Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 4
Baker Ch. 6 MOSFET Operation Introduction to VLSI
CV CURVE DESCRIPTION
– KEEP IN MIND OPERATING POINT
Holes being Holes being Electrons being – ACCUMULATION != GOOD CAP
accumulated repelled attracted • SERIES RESISTANCE TO TAP
– CAN USE MOSFET AS CAP
• SHORT SOURCE TO DRAIN
• IF VGATE CHANGES, VARACTOR
– SHOULD UNDERSTAND EACH CAP
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 5
Baker Ch. 6 MOSFET Operation Introduction to VLSI
IV TERMINLOGY
ID DRAIN CURRENT
IMPLIES DRAIN TO SOURCE (IDS)
WHERE ELSE WOULD CURRENT GO FROM-TO?
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 6
Baker Ch. 6 MOSFET Operation Introduction to VLSI
– SATURATION REGION
• CURRENT IS CONSTANT
FROM • NO DEPENDENCE NO VDS
MARTIN
– TRANISTION REGION
• NEED FULL EQUATION
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 7
Baker Ch. 6 MOSFET Operation Introduction to VLSI
– TRANSCONDUCTANCE PARM
• KPN=mNCOX=mN eOX/tOX ~ 120uA/V2
• KPP=mPCOX=mP eOX/tOX ~ 40uA/V2
– MOBILITY DIFFERENCES
• mN=650 cm2/ V sec
• mP=250 cm2/ V sec
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 8
Baker Ch. 6 MOSFET Operation Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 9
Baker Ch. 6 MOSFET Operation Introduction to VLSI
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 10
Baker Ch. 6 MOSFET Operation Introduction to VLSI
tt (0.709)
1.0E-03
wfr (0.700)
• SMALL OFFSET OF VDS APPLIED
8.0E-04
LOG SCALE SHOWS Ioff
Ids
ss (0.735)
6.0E-04
4.0E-04
2.0E-04
0.0E+00
0.00 0.50 1.00 1.50 2.00 2.50
Vgs
S8 NFET 7.0/0.15 TT 30C S8 NFET 7.0/0.15 30C
1.E+00
6.0E-03 1.E-010.00 0.50 1.00 1.50 2.00 2.50
1.E-02
5.0E-03
tt (0.709)
1.E-03
Vds =0.1
4.0E-03 1.E-04
3.0E-03 1.E-05
1.E-06
Ids
2.0E-03
Ids
1.E-07
1.0E-03 1.E-08
1.E-09
0.0E+00
1.E-10
-1.0E-03 1.E-11
1.E-12
-2.0E-03
0.00 0.50 1.00 1.50 2.00 2.50
1.E-13 Ioff
1.E-14
Vgs
Vgs
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 11