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Background
Shahriar Mirabbasi
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Suggested Reading
• Most of the material in this set are based on
Unless otherwise specified, the figures in this set are from © Design of Analog CMOS
Integrated Circuits, McGraw-Hill, 2001, unless otherwise noted.
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Transistor
• Transistor stands for …
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Simplistic Model
• MOS transistors have three terminals: Gate, Source, and Drain
NMOS PMOS
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Physical Structure - 1
• Source and Drain terminals are identical except that Source provides
charge carriers, and Drain receives them.
• MOS devices have in fact 4 terminals:
– Source, Drain, Gate, Substrate (bulk)
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Physical Structure - 2
• Charge Carriers are electrons in NMOS devices, and holes in
PMOS devices.
• Electrons have a higher mobility than holes
• So, NMOS devices are faster than PMOS devices
• We rather to have a p-type substrate?!
• Actual length of the channel (Leff) is less than the length of gate
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Physical Structure - 3
• N-wells allow both NMOS and PMOS devices to reside on the
same piece of die.
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Physical Structure - 4
• MOS transistor Symbols:
electron
• In NMOS Devices: Source Drain
Current flows from Drain to Source
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion,
and (d) channel formation
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Threshold Voltage - 3
Analytically:
Qdep
VTH MS 2 F
C ox
Where:
K T N
Work Function (electrostatic potential) ln sub
q n
F
i
Q dep
Charge in the depletion region 4 q si F
N sub
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Threshold Voltage - 4
• In practice, the “native” threshold value may not be suited for
circuit design, e.g., VTH may be zero and the device may be on for
any positive gate voltage.
• When VDS is more than zero, there is some horizontal electric field
which causes a flow of electrons from source to drain.
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Long Channel Current Equations - 1
• The voltage of the surface under the gate, V(x), depends on the
voltages of Source and Drain.
• If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform.
Q C V C oxWL VGS VTH
Qd
L L L
Qd WC ox (VGS VTH )
• If VDS is not zero, the channel is tapered, and V(x) is not constant. The
charge density depends on x.
Qd ( x ) WC ox (VGS V ( x) VTH )
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Long Channel Current Equations - 3
• Current :
dQ dQ dx
I Qd velocity
dt dx dt
Velocity in terms of V(x):
dV
velocity E , E
dx
dV ( x)
velocity ( )
dx
Qd in terms of V(x):
Qd ( x ) WC ox (VGS V ( x) VTH )
• Terminology:
W
Aspect Ratio
L
Overdrive Voltage Effective Voltage VGS VTH Veff
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Long Channel Current Equations - 5
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Long Channel Current Equations - 6
• Increasing VDS causes the channel to acquire a tapered shape. Eventually,
as VDS reaches VGS – VTH the channel is pinched off at the drain. Increasing
VDS above VGS – VTH has little effect (ideally, no effect) on the channel’s
shape.
• When VDS is more than VGS – VTH the channel is pinched off, and the
horizontal electric field produces a current.
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Long Channel Current Equations - 7
1 W
ID n C ox (VGS VTH ) 2
2 L'
• Let’s, for now, assume that L’=L. The fact that
L’ is not equal to L is a second-order effect
known as channel-length modulation.
• Since ID only depends on VGS, MOS transistors in saturation can be
used as current sources.
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Long Channel Current Equations - 8
• Current Equation for NMOS:
W
n C ox VGS VTH VDS ; if VGS VTH , V DS 2(VGS VTH ) ( Deep Triode)
L
ID I DS
W 1 2
n C ox VGS VTH VDS VDS ; if VGS VTH , VDS VGS VTH (Triode)
L 2
1 W
n C ox (VGS VTH ) 2 ; if VGS VTH , VDS VGS VTH ( Saturation )
2 L
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Long Channel Current Equations - 9
• Current Equation for PMOS:
W
p C ox VSG VTH VSD ; if VSG VTH , VSD 2(VSG VTH ) ( Deep Triode)
L
ID I SD
W 1 2
p C ox VSG VTH VSD VSD ; if VSG VTH , VSD VSG VTH (Triode)
L 2
1 W
p C ox (VSG VTH ) 2 ; if VSG VTH , VSD VSG VTH ( Saturation )
2 L
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Regions of Operation - 1
• Regions of Operation:
Cut-off, triode (linear), and saturation (active or pinch-off)
• Once the channel is pinched off, the current through the channel is
almost constant. As a result, the I-V curves have a very small slope in
the pinch-off (saturation) region, indicating the large channel
resistance.
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Regions of Operation - 2
• The following illustrates the transition from pinch-off to triode region for
NMOS and PMOS devices.
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Regions of Operation - 4
• PMOS Regions of Operation:
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Regions of Operation - 5
Example:
For the following circuit assume that VTH=0.7V.
• When is the device on?
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Transconductance - 1
• The drain current of the MOSFET in saturation region is ideally a
function of gate-overdrive voltage (effective voltage). In reality, it is also
a function of VDS.
• It makes sense to define a figure of merit that indicates how well the
device converts the voltage to current.
ID
gm
VGS VDS Const.
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Transconductance - 2
Example:
Plot the transconductance of the following circuit as a function of VDS
(assume Vb is a constant voltage).
• Transconductance in triode:
W 1 2
gm n C ox VGS VTH V DS VDS
VGS L 2 VDS Const.
W
n C ox VDS
L
• Transconductance in saturation:
1 W
gm n C ox (VGS VTH ) 2
VGS 2 L VDS Const.
W
n C ox (VGS VTH )
L
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Second-Order Effects (Body Effect)
Substrate Voltage:
• So far, we assumed that the bulk and source of the transistor are at the
same voltage (VB=VS).
• If VB >Vs, then the bulk-source PN junction will be forward biased, and
the device will not operate properly.
• If VB <Vs,
– the bulk-source PN junction will be reverse biased.
– the depletion region widens, and Qdep increases.
– VTH will be increased (Body effect or Backgate effect).
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Channel Length Modulation - 1
1 W
• The drain current is I D C
n ox (VGS VTH ) 2 where L' L- L
2 L'
1 1 1 1 1
1 L
L' L L L 1 L L L
L
1 1 L 1
• Assuming L VDS we get: 1 1 VDS
L L' L L L
1 W 1 W 2
• The drain current is I D n C ox (VGS VTH ) 2 n C ox VGS VTH 1 VDS
2 L' 2 L
• As ID actually depends on both VGS and VDS, MOS transistors are
not ideal current sources (why?).
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Channel Length Modulation - 2
• represents the relative variation in effective length of the channel for a given
increment in VDS
In Triode:
W
gm n C ox VDS
L
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Channel Length Modulation - 3
Example:
Given all other parameters constant, plot ID-VDS characteristic of an NMOS
for L=L1 and L=2L1
W 1 2
• In Triode Region: ID n Cox
L
VGS VTH VDS
2
VDS
ID W
Therefore :
VDS L
1 W
• In Saturation Region: ID nCox VGS VTH 2 1 VDS
2 L
ID 1 W
So we get : nCox VGS VTH 2
VDS 2 L
ID W W
Therefore :
VDS L L2
• Changing the length of the device from L1 to 2L1 will flatten the ID-VDS
curves (slope will be divided by two in triode and by four in saturation).
• Increasing L will make a transistor a better current source, while
degrading its current capability.
• Increasing W will improve the current capability.
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Sub-threshold Conduction
• If VGS < VTH, the drain current is not zero.
• The MOS transistors behave similar to BJTs.
VBE
VT
• In BJT: I C IS e
VGS
VT
• In MOS: I D I0 e
• In BJT devices the current drops faster (one decade for approximately
each 60mv of drop in VGS).
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CMOS Processing Technology
• Top and side views of a typical CMOS process
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CMOS Processing Technology
• Different layers comprising CMOS transistors
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Photolithography (Lithography)
• Used to transfer circuit layout information to the wafer
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Typical Fabrication Sequence
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Self-Aligned Process
• Why source and drain junctions are formed after the gate oxide
and polysilicon layers are deposited?
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Back-End Processing
• Oxide spacers and silicide
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Back-End Processing
• Contact and metal layers fabrication
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Back-End Processing
• Large contact areas should be avoided to minimize the
possibility of spiking
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MOS Layout - 1
• It is beneficial to have some insight into the layout of the MOS devices.
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MOS Layout - 2
Example:
Figures below show a circuit with a suggested layout.
• The same circuit can be laid out in different ways, producing different
electrical parameters (such as different terminal capacitances).
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Device Capacitances - 1
• The quadratic model determines the DC behavior of a MOS transistor.
• The capacitances associated with the device are important when
studying the AC behavior of that device.
• There is a capacitance between any two terminals of a MOS transistor.
So there are 6 capacitances in total.
• The Capacitance between Drain and Source is usually negligible
(CDS=0).
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Device Capacitances - 2
• The following will be used to calculate the capacitances between
terminals:
ox
1. Oxide Capacitance: C W L C , C ox
1 t ox
ox
q N sub
2. Depletion Capacitance: C2 C dep W L
4
si
4. Junction Capacitance:
Sidewall Capacitance: C jsw C j0
C jun m
VR
Bottom-plate Capacitance: Cj 1
B
C5 C6 Cj C jsw
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Device Capacitances - 3
In Cut-off:
1. CGS: is equal to the overlap capacitance. C C C GS ov 3
C DB C6
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Device Capacitances - 4
In Triode:
• The channel isolates the gate from the substrate. This means that if VG
changes, the charge of the inversion layer are supplied by the drain
and source as long as VDS is close to zero. So, C1 is divided between
gate and drain terminals, and gate and source terminals, and C2 is
divided between bulk and drain terminals, and bulk and source
terminals.
C
1. CGS: CGS C ov 21
2. CGD: CGD Cov C1
2
3. CGB: the channel isolates the gate from the substrate. CGB 0
C2
4. CSB: C SB C 5
2
5. CDB: C 2
C DB C 6
2
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Device Capacitances - 5
In Saturation:
• The channel isolates the gate from the substrate. The voltage across
the channel varies which can be accounted for by adding two
equivalent capacitances to the source. One is between source and
gate, and is equal to two thirds of C1. The other is between source and
bulk, and is equal to two thirds of C2.
2
1. CGS: C C 3 C
GS ov 1
2. CGD: C
GD C ov
4. CSB: CSBC 5
2
C 2
3
5. CDB: C
DB C 6
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Device Capacitances - 6
• In summary:
Cut-off Triode Saturation
C1 2
CGS C ov C ov C ov
3
C1
2
C1
CGD C ov C ov C ov
2
CGB C1 C 2
C GB C1 0 0
C1 C 2
C2
CSB C5 C5
2 C5
2
C2
3
C2
CDB C6 C6
2
C6
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Importance of Layout
Example (Folded Structure):
Calculate the gate resistance of the circuits shown below.
Folded structure:
• Decreases the drain capacitance
• Decreases the gate resistance
• Keeps the aspect ratio the same
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Passive Devices
• Resistors
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Passive Devices
• Capacitors:
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Passive Devices
• Capacitors
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Passive Devices
• Inductors
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Latch-Up
• Due to parasitic bipolar transistors in a CMOS process
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Small Signal Models - 1
• Small signal model is an approximation of the large-signal model
around the operation point.
• In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor
series approximation:
ID ID ID
Taylor Expansion : I D I D0 VGS VDS VBS second order terms
VGS VDS VBS
ID ID ID V DS
ID VGS VDS VBS gm VGS g mb VBS
VGS VDS VBS ro
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Small Signal Models - 2
1 W 1 W 2
• Current in Saturation: I D n C ox (VGS VTH ) 2 n C ox VGS VTH 1 VDS
2 L' 2 L
ID ID ID
• Taylor approximation: ID VGS VDS VBS
VGS VDS VBS
• Partial Derivatives:
ID W
n C ox (VGS VTH ) 1 V DS gm
VGS L
ID 1 W 1
n C ox (VGS VTH ) 2 ID
V DS 2 L ro
ID ID VTH W
n C ox (VGS VTH ) 1 V DS
V BS VTH V BS L 2 2 F VSB
gm gm g mb
2 2 F VSB
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Small Signal Models - 3
• Small-Signal Model:
v DS
iD g m vGS g mb v BS
ro
PMOS :
D
GO - 0
p
+ VSB
so
^ i t
VSB
-
1=10 B
channel
r# 0
length mod
.
body
effect
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Small Signal Models - 4
• Complete Small-Signal Model with Capacitances:
• Small signal model including all the capacitance makes the intuitive
(qualitative) analysis of even a few-transistor circuit difficult!
• For intuitive analysis we try to find a simplest model that can represent
the role of each transistor with reasonable accuracy.
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Circuit Impedance - 1
• It is often useful to determine the impedance of a circuit seen from a
specific pair of terminals.
V
R X
I
X
X
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Circuit Impedance - 2
Example:
• Find the small-signal impedance of the following current
sources.
• We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
v v
i X
g v X
r r
X m GS
o o
v
R X
r
i
X o
X
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Circuit Impedance - 3
Example:
• Find the small-signal impedance of the following circuits.
• We draw the small-signal model, which is the same for both
circuits, and connect a voltage source as shown below:
v v
i X
g v g v X
g v g v
r r
X m GS mb BS m X mb X
o o
v 1 1 1
R X
r
X
i 1 o
g g
X
g g m mb
r
m mb
o
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Circuit Impedance - 4
Example:
• Find the small-signal impedance of the following circuit. This
circuit is known as the diode-connected load, and is used
frequently in analog circuits.
r r r
X m GS m X X m
o o o
v 1 1
R X
r
X
i 1 o
g
X
g m
r
m
o
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Circuit Impedance - 5
Example:
• Find the small-signal impedance of the following circuit. This
circuit is a diode-connected load with body effect.
v v
i X
g v g v X
g v g v
r r
X m GS mb BS m X mb X
o o
1
v g g
r
X m mb
o
v 1 1 1 1
R X
r r
X
i 1 o
g g
o
g g
X
g g m mb m mb
r
m mb
o
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Short-Channel Effects
• Threshold Reduction
– Drain-induced barrier lowering (DIBL)
• Mobility degradation
• Velocity saturation
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Threshold Voltage Variation in Short Channel Devices
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Drain-Induced Barrier Lowering (DIBL)
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Effects of Velocity Saturation
• Due to drop in mobility at high electric fields
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Hot Carrier Effects
• Short channel devices may experience high lateral drain-source
electric field
• “Hot” carriers may “hit” silicon atoms at high speed and cause
impact ionization
• The resulting electron and holes are absorbed by the drain and
substrate causing extra drain-substrate current
• Really “hot” carriers may be injected into gate oxide and flow out
of gate causing gate current!
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Output Impedance Variation
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Output Impedance Variation in Short-Channel Devices
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Output Impedance Variation in Short-Channel Devices
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