Memory

By
Kriti Sundar Das
Mirafra Technnologies
Contents
• Introduction
– Complexities involving a memory.
– When is memory used in ASIC design. What type ?
• A Basic Memory Cell.
• Different Types of Memories.
• Memory Architecture w.r.t BIST.
• ATPG aspects of a Memory.
• Memory Repair
– Column redundancy
– Row redundancy
– Efuse
 Introduction
• Memory is the most dense physical structure in a SOC.
• Embedded memories begin to dominate physical die
area vs. digital logic.
• Considering the increasing density, with shrinking
technology, memory arrays are more sensitive to
defects.
• The need for Memory repair capability also arises.
• Main memory design concern in a SOC is the aspect
ratio: square, rectangle, in pieces, number of memory
modules.
• It affects routing, chip area, power dissipation etc.
• Recent trend is to have many distributed memory
arrays close to the logic they serve.
 Different types of Memory
• Semiconductor memories are characterized according
to the following properties:
– Serial or random access,
– Volatile or nonvolatile,
– Static or dynamic,
– Destructive or nondestructive readout
• Examples :
– SRAM : Cache-L1, L2.
– DRAM : DDR-2, DDR-3.
– Serial : Magnetic tapes.
– ROMs : EPROM.
– FLASH : External hard disk, SD/MMC Cards.
DRAM Memory Architecture
Memory Core Array
 Mux Factor of Memory
• It signifies the aspect ratio of the memory.
• Memory size = 1024 x 16 (For example).
• No. of Rows = word_length / Muxfactor.
• No. of Columns = Muxfactor x (no. of bits in
word).
• Muxfactor = 4 ->
– Memory Orientation = 256 x 64.
• Muxfactor = 8 ->
– Memory Orientation = 128 x 128.
• What is the deciding factor for Muxfactor
selection?
 SRAM Cell
• Volatile memory. Data remains till power supply is
applied.
• Basic flip-flop structure with 2 basic states.
• Memory cell size greater than DRAM, so lesser density.
• High Speed compared DRAM.
 DRAM Cell
• Volatile memory. Data remains till power supply is applied.
• Very Simple Cell sturcture, 6 times smaller than SRAM . High-dense
structure possible.
• DRAMs must be refreshed when their contents are read out, since a
read causes the capacitor to discharge.
• Lesser speed compared SRAM.
 Memory Core & Wrapper
Addr[A:0]
D[B:0]
WE
Functional
ME
pins
CLK
TEST1
RME Memory Row
Decoders Memory Array
RM
Qi
WEMB[B:0]
TCLK
TADR[A:0]
Control Sense Amp and Output buffers
TD[3:0] BIST mode
TWE Integrated Test (BIST Muxes, I/O Scan Flops,
Comparator and Capture Logic)
TME
BISTE Input /Output Data
Control Signals
BISTMODE
CD[3:0]
CAPT
RSCOUT
RSCIN
Redundancy
RSCRST scan pins
RSCEN
Input/Output Data,
SWT Control Signals
AWT
SE SO
SI ATPG mode
DFTMODE
 Data Flow through Memory 1

Asynchronous Bypass
Synchronous Bypass
 Data Flow through Memory 2

Asynchronous Bypass
Synchronous Bypass
 References
• http://www.ece.uc.edu/~wjone/Memory.pdf
• http://digitalelectronics.blogspot.in/2009/01/memories-
introduction-part-1.html
• http://digitalelectronics.blogspot.in/2009/01/memories-types-
part-2.html
• http://www.patentstorm.us/patents/6934213/description.html

• Mirafra Twiki Link :

• https://mail.mirafra.com/twiki/bin/view/Main/DFTReferences
Post Test
Memory Repair
 Memory Repair
• Large ASIC SOCs have many embedded memories.

• Manufacturing Yield of such big system on a chip largely

depends on correct manufacturing of these dense memories.

• Providing some repair capability for these memories, largely

increases the Yield.

• Its possible for memories to go bad over time, Having soft

repair capabilty is an added advantage.

• Memories can be repaired 2 ways :

– Hard Repair
– Soft Repair
 Column Redundancy
• 2 column redundancy
Bit0 Bit1 Bit2 Bit6 Bit7

Columns

C1

C3
C2
C1

C3
C2

C0
C1

C1
C3

C1

C3
C0

C3

RC1
C2

RC2
C2
C2
C0

C0
C0
r4

r3

r2

r1

r0

Repair Mechanism

ColMux

Q[6] Q[7]
Memory IO Q[0] Q[1] Q[2]
 Hard Repair
SOC Sub Block 1 RAM1
With
Redundancy

TOP ROM RAM2

P Clk domain 1
A
D BIST
R Sub Block 2
Controll RAM3
I er
N
G

Efuse RAM4 with

Redundancy
Controller
E-Fuses Clk domain 2

Copyright © Infineon Technologies 2009. All rights

12/08/21 Page 22
reserved.
 Hard Repair
• Bist Controller runs algorithms on the memory to find out total
number of faulty addresses.

• If no. of faulty addresses < repairable_limit, Bist engines analyses &

calculates the repair signature .

• This repair signature is programmed into E-fuse.

• When system boots up with power-on , E-fuse data is read, and

repair signature is being shifted to the faulty memories.

• Faulty Memories with the repair info, works as full functional

memory.

• But if the faulty memory again gets Bad over time, then it can’t be
repaired again.
 Soft Repair
• Bist Controller runs algorithms on the memory to find out total number of
faulty addresses.

• If no. of faulty addresses < repairable_limit, Bist engines analyses &

calculates the repair signature . Or else send a alarm that Chip is not
repairable.

• Bist Controller then send this repair signature to the faulty

memories(repair info is stored into redundant flops inside memory).
Faulty memory after repair, works fine.
• But repair info inside memory get lost , when power is Off.
• When system boots up with power-on , Bist Controller everytime have to
run algorithms again , find faulty addresses of memories, calculate repair
signature & then send the repair info to faulty memories.

• System Boot up takes a longer duration, compared to Hard repair.

• But if the chip with reapired memories again gets Bad over time, then it
can be repaired again, provided it is under the repairable limit.
Conclusion