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ch12 p2 PDF
ch12 p2 PDF
2002
General Organisation
Registers
Instruction Cycle
Pipelining
Branch Prediction
Interrupts
26.9.2002 Copyright Teemu Kerola 2002 1
30 40 20 30 40 20 30 40 20 30 40 20
T
Time for one load
a A Latency
(viive?)
s
k 1.5 hours per load
B
O 0.67 loads per hour
r Throughput
d C
e
r
D
Sequential laundry takes 6 hours for 4 loads
If they learned pipelining, how long would laundry take?
26.9.2002 Copyright Teemu Kerola 2002 9
it helps throughput of 30 40 40 40 40 20
the entire workload A
Pipeline rate limited by
B
slowest pipeline stage
C
Multiple tasks operating
simultaneously D
Potential speedup
= maximum possible speedup (nopeutus)
= Number pipe stages
26.9.2002 Copyright Teemu Kerola 2002 11
Another Possible
Instruction Execution Pipeline
FE - Fetch instruction
DI - Decode instruction
CO - Calculate operand effective addresses
FO - Fetch operands from memory
EI - Execute Instruction
WO - Write operand (result) to memory
Fig. 12.10 (Fig. 11.11 [Stal99])
= max[ i ] + d = m + d >> d
max gate delay in stage
(min) cycle time
delay in latches between stages
(= clock pulse, or clock cycle time)
gate delay in stage i
Time
pipelined:
Tk = [k + (n 1)]
Time
pipelined:
Tk = [k + (n 1)]
Speedup T1 nk nk
Sk = = =
Tk [k + (n 1)] [k + (n 1)]
with
k stages: