Tuesday, August 1, 2017 Page |

Experiment 1: Basic VHDL Codes BT15ECE021 and BT15ECE039

BASIC VHDL CODES

Objective
To implement the following codes in VHDL :

1. OR Gate
2. Half Adder
3. Full Adder
4. 2x1 MUX
5. 1x2 DEMUX

Codes

1. Code for Or Gate

entity my_or is
port (a, b: in bit;
y: out bit);
end my_or;

architecture or_arch of my_or is

begin
y<=a or b;
end or_arch;

2. Code for Half Adder

entity half_adder is
port (a, b: in bit;
s, cout: out bit);
end half_adder;

architecture half_arch of half_adder is

begin
s<=a xor b;
cout<=(a and b);
end architecture;

3. Code for Full Adder

entity full_adder is
port (a, b, cin: in bit;
s, cout: out bit);
end full_adder;

architecture full_arch of full_adder is

begin
s<=a xor b xor cin;
cout<=(a and b) or (a and cin) or (b and cin);
end architecture;
Tuesday, August 1, 2017 Page |
Experiment 1: Basic VHDL Codes BT15ECE021 and BT15ECE039

4. Code for 2x1 MUX

entity mux2x1 is
port (a, b, s: in bit;
y: out bit);
end mux2x1;

architecture mux_arch of mux2x1 is

begin
y<=((not s)and a) or (s and b);
end architecture;

5. Code for 1x2 DEMUX

entity demux1x2 is
port (a, s: in bit;
y1, y0: out bit);
end demux1x2;

architecture demux_arch of demux1x2 is

begin
y1<=(s and a);
y0<=((not s) and a);
end architecture;

Input

We force desired inputs to each of these cases to get our desired output

Output

1. OR Gate
Tuesday, August 1, 2017 Page |
Experiment 1: Basic VHDL Codes BT15ECE021 and BT15ECE039

2. Half Adder

3. Full Adder

4. 2x1 MUX
Tuesday, August 1, 2017 Page |
Experiment 1: Basic VHDL Codes BT15ECE021 and BT15ECE039

5. 1x2 DEMUX

Result

VHDL Programs were Compiled and Simulated. The waveforms obtained were in coherence
with the expected behavious from the various Logic Gates / Combinational Circuits.