SUBTRACTOR

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity subtractor is

port(x0,x1,x2,x3,y0,y1,y2,y3:in bit;

cin:in bit;

res0,res1,res2,res3:out bit;

carry:out bit);

end subtractor;

architecture Behavioral1 of subtractor is

component tsg

port(a,b,c,d:in bit;

p,q,r,s:out bit);

end component;

signal cp0,cp1,cp2,cp3,cg0,cg1,cg2,cg3,f1,f2,f3:bit;

signal g,s,s1,s2,s3,s0,rest0,rest1,rest2,rest3:bit;

begin
g<='0';

s<='1';

s0<=y0 xor s;

s1<=y1 xor s;

s2<=y2 xor s;

s3<=y3 xor s;

U1: tsg port map (x0,s0,g,cin,cp0,cg0,rest0,f1);

U2: tsg port map (x1,s1,g,f1,cp1,cg1,rest1,f2);

U3: tsg port map (x2,s2,g,f2,cp2,cg2,rest2,f3);

U4: tsg port map (x3,s3,g,f3,cp3,cg3,rest3,carry);

res0<=not(rest0);

res1<=not(rest1);

res2<=not(rest2);

res3<=not(rest3);

end Behavioral1;
TSG GATE

library ieee;

use ieee.std_logic_1164.all;

entity tsg is

port(a,b,c,d: in bit;

p,q,r,s: out bit);

end tsg;

architecture tsg1 of tsg is

signal s1,s2,s3: bit;

begin

p<=a;

q<=((not(a) and (not(c)))xor (not(b)));

s3<=(((not(a) and not (c))xor not (b))and d);

s1<=((((not(a)) and (not(c)))xor (not(b)))xor d);

s2<=((a and b)xor c);

r<=s1;

s<=s3 xor s2;

end tsg1;
ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_level is

port(x0,x1,x2,x3,y0,y1,y2,y3:in bit;

cin:in bit;

sum0,sum1,sum2,sum3:out bit;

carry:out bit);

end top_level;

architecture Behavioral of top_level is

component tsg

port(a,b,c,d:in bit;

p,q,r,s:out bit);

end component;

signal cp0,cp1,cp2,cp3,cg0,cg1,cg2,cg3,f1,f2,f3:bit;

signal g:bit;

begin
g<='0';

U1: tsg port map (x0,y0,g,cin,cp0,cg0,sum0,f1);

U2: tsg port map (x1,y1,g,f1,cp1,cg1,sum1,f2);

U3: tsg port map (x2,y2,g,f2,cp2,cg2,sum2,f3);

U4: tsg port map (x3,y3,g,f3,cp3,cg3,sum3,carry);

end Behavioral;