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0 00 1 01 0 MSB+ = LIn + MIn LSB+ = L'In + MIn Out+ = ML
reset
0 0 1 0 01 0 00 0
0 01 1 10 0
0 10 0 00 0 Notation
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K-map for P1 K-map for P0 K-map for Open

Q1Q0 Q1 Q1Q0 Q1 Q1Q0 Q1
DN 00 01 11 10 DN 00 01 11 10 DN 00 01 11 10
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11 X X X X 11 X X X X 11 X X X X
D D D
10 1 1 1 1 10 0 1 1 1 10 0 0 1 0
Q0 Q0 Q0

P1 = Q1 + D + Q0N if FFs do not have a reset pin then

A BC 83 8C <
P0 = Q0'N + Q0N' + Q1N + Q1D P1 = reset'(Q1 + D + Q0N)
A BC D
< 8 C <D8 C < 8 C 3
OPEN = Q1Q0 P0 = reset'(Q0'N + Q0N' + Q1N + Q1D)
A < BC C

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?@

:
 + *) ; " # + *) / 40
always @(in or state)

case (state) *
`define zero 0 `zero:
// last input was a zero #
`define one1 1 *
`define two1s 2 begin
if (in) next_state = `one1;
module reduce (clk, reset, in, out); else next_state = `zero;
input clk, reset, in; end
output out; . `one1: #
reg out; // we've seen one 1 # !
?@ begin
reg [2:1] state; // state variables
reg [2:1] next_state; if (in) next_state = `two1s;
else next_state = `zero;
always @(posedge clk) end
if (reset) state = `zero; `two1s: always @(state)
else state = next_state; ?@ // we've seen at least 2 ones case (state)
begin `zero: out = 0;
if (in) next_state = `two1s; `one1: out = 0;
else next_state = `zero; `two1s: out = 1;
end endcase
?@ endcase
endmodule

!+ *) ! !
module reduce (clk, reset, in, out);
module reduce (clk, reset, in, out);
input clk, reset, in;
output out;
input clk, reset, in;
reg out; output out;
reg state; // state variables reg out;
reg next_state; reg state; // state variables

always @(posedge clk) always @(posedge clk)

if (reset) state = `zero; if (reset) state = `zero;
else state = next_state; else
case (state)
always @(in or state) `zero: // last input was a zero
case (state) begin
`zero: // last input was a zero out = 0;
begin if (in) state = `one;
out = 0;
else state = `zero;
if (in) next_state = `one;
end
else next_state = `zero;
end
`one: // we've seen one 1
`one: // we've seen one 1 if (in) begin
if (in) begin state = `one; out = 1;
next_state = `one; out = 1; end else begin
end else begin state = `zero; out = 0;
next_state = `zero; out = 0; end
end endcase
endcase endmodule
endmodule