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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and

5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI
Paramjeet Singh Sahni, Suresh Chandra Joshi, Nitin Gupta, and Gangaikondan Subramani Visweswaran

Abstract A multistage continuous-time linear equalizer (CTLE)

design with a controllable transfer function is presented. The entire
frequency range of interest, from dc to gain roll-off frequency, is divided
into six regions, and the transfer function in each region is indepen-
dently matched to be the inverse of the channel transfer function.
The equalizer is used for 6-Gb/s data transfer per channel for high-
definition multimedia interface (HDMI) 2.0 receiver and 5.4-Gb/s data
transfer per channel for DisplayPort (DP) receiver designs. Fabricated in
a 28-nm ultrathin body and buried oxide fully depleted silicon-on-
insulator technology, the 0.06-mm2 CTLE consumes 30 mW to achieve
up to 28-dB peaking. The entire receiver channel occupies 0.21 mm2 ,
consumes 55 mW, and achieves a power efficiency of 9.2 pJ/bit
at 6 Gb/s. This design achieves a jitter tolerance of 0.7 unit interval (UI)
up to 10 MHz for HDMI and 0.42 UI up to 100 MHz for DP, which is Fig. 1. Proposed CTLE architecture with four digitally programmable
better than their respective specifications. HPF stages and feedback to suppress low-frequency noise.

Index Terms Adaptive equalization, analog filter, continuous-

time linear equalizer (CTLE), high-speed serial links, intersymbol
interference (ISI), jitter, SerDes, transceivers.
I. I NTRODUCTION
The demand for ultrahigh-definition TV (UHDTV), 3-D displays,
has led to an increase in color depth, frame refresh rate, and
resolution of a display panel. All these require higher data rates
to be supported over existing low-bandwidth, low-cost transmission
media and have led to the emergence of higher data-rate speci-
fications for display interfaces, such as high-definition multimedia
interface (HDMI) 2.0 and DisplayPort (DP).
Receiver equalizers have become necessary to compensate for the
high-frequency channel loss [1] and intersymbol interference (ISI)
to meet the required bit error rate (BER) in recovered data. The
advantages of continuous-time linear equalizers (CTLEs) over deci-
sion feedback equalizers (DFEs) are lower area, lower power [2], [3],
and its potential to cancel the precursor ISI [3]. The major drawback
of CTLE is noise amplification [4]. To receive high data rates
over low-bandwidth channels, DFE is used after CTLE to cancel
ISI and to adapt the equalizer to the connected channel. However,
for applications with moderate signal-to-noise ratio, the addition
of a power hungry DFE stage can be avoided if the CTLE can
adapt its transfer function to the connected channel and its varying
characteristics.
The goal of an equalizer is to realize a transfer function which can
be tuned to be the inverse of the channel transfer function [1], [5].
If properly tuned, the equalizer improves the receiver performance
parameters, such as BER and jitter tolerance. A conventional capac-
itive source-degenerated first-order CTLE [1], [6], with one zero
and two poles, provides limited capability to control the shape of
CTLE transfer function. The second-order CTLEs [4] and inductor-
based CTLEs [5], [7] offer the advantage of increased peaking gain,
Manuscript received September 20, 2015; revised December 25, 2015;
accepted January 26, 2016.
P. S. Sahni, S. C. Joshi, and N. Gupta were with STMicro-
electronics, Greater Noida 201308, India. They are now with
Synopsys, Noida 201301, India (e-mail: paramjeet.s.sahni@ieee.org;
suresh-chandra.joshiext@st.com; nitin.gupta.in@ieee.org).
G. S. Visweswaran is with the Department of Electrical Engineering,
IIT Delhi, New Delhi 110016, India (e-mail: gswaran@ee.iitd.ac.in).
Digital Object Identifier 10.1109/TVLSI.2016.2530680
1063-8210 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
but have limited control over the shape of the entire CTLE transfer
function.
In this brief, we have proposed a high-pass filter (HPF) circuit
topology with coarse and fine-tuning of the transfer function.
Furthermore, a feedback stage has been incorporated to take
advantage of transition minimized differential signaling (TMDS)
or 8-/10-bit encoding (HDMI uses TMDS data encoding [8], and
DP uses 8-/10-bit data encoding [9]) to remove low-frequency noise.
Four such HPF stages have been used to completely equalize the
channel up to 6 Gb/s, without requiring an additional DFE circuit.
Instead of using a conventional power comparison approach [1], [5]
for adaptation, we have proposed an adaptive digital control to
independently tune these four HPF stages, utilizing the advantage
of the TMDS (or 8/10 bit) encoding.
II. A RCHITECTURE
The equalization architecture shown in Fig. 1 involves a multistage
CTLE design. The first stage of the CTLE is a variable gain
amplifier (VGA) incorporating a linear (analog output)-level shifter to
shift the differential signals to 1 V domain. The VGA and three CTLE
stages following the level shifter have tunable high-pass transfer
functions, and are referred to as the HPF stages. The output of
the cascaded HPF stages is processed and fed back at the level
shifter output, to control low-frequency noise gain and remove offset.
The HPF stages are followed by an amplifier and CMOS buffers
to produce rail-to-rail output to ease slicer and CDR designs.
As the number of cascaded stages increases, the required unity-
gain-bandwidth product of each individual stage reduces until
about six stages [6], while the accumulated noise increases [7].
For a receiver with a bandwidth of 5 GHz, four or five stages
are considered best for power efficiency [6] and minimal noise
accumulation [7].
Fig. 2 shows the measured channel transfer functions for varying
cable lengths, similar to the proprietary channel transfer function
provided by HDMI and DP specifications [8], [9].
III. CTLE T RANSFER F UNCTION C ONTROLS
AND S IMULATION R ESULTS
The four HPF stages of the CTLE have a topology, as shown
in Fig. 3(a), but have different values for resistors, capacitors,
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 2. Measured channel transfer functions normalized with respect to

attenuation at 1 MHz for varying cable lengths.

Fig. 4. Combined transfer function of four HPF stages of the CTLE.

Fig. 3. (a) Schematic of one HPF circuit and (b) its differential-mode (a) DC gain controlled by programming R1 and R2 . (b) Mid-frequency
half-circuit. transfer function shape controlled by C1 programming. (c) High-frequency
transfer function shape controlled by C2 programming.

and MOS sizes. Differential-mode half-circuit of the HPF stage

is shown in Fig. 3(b). Each HPF stage of the CTLE has inde- obtained from Fig. 3(b), and along with (1) and (2), we can obtain
pendently controllable dc gain, low-frequency gain, mid-frequency the HPF-stage transfer function as
gain, high-frequency gain, peak gain, and gain-roll-off frequency.
The first two HPF stages have been sized to contribute more to the gm R L (1 + Ds + Es 2 )
H (s) = (3)
high-pass filtering and also have larger gain programmability than the (1 + C L R L s){1 + Ds + Es 2 + gm (A + Bs)}
last two HPF stages. The transfer function of an HPF stage, H (s), is
where A = R1 + R2 , B = R1 R2 C1 , D = C1 R1 + C2 R1 + C2 R2 , and
given by
E = C1 C2 R1 R2 . H (s) has two zeros and three poles, confirming
H (s) = G Meff Z L (1) the CTLE to be of second order.

where G Meff , the effective transconductance, and the effective

load Z L are given by A. DC Gain and Gain-Roll-Off Shape Control
1 RL At dc or very low-frequency Z S approaches (R1 + R2 ), which is
G Meff = , ZL = (2) more than 1/gm . From (3)
(1/gm + Z S ) (1 + sC L R L )
where gm is the transconductance of M1 and M2 , and Z S is the R L
H (0) = . (4)
source-degeneration impedance, as shown in Fig. 3(b). Z s can be (R1 + R2 )
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 5. Offset cancellation and low-frequency attenuation control.
The required gain-roll-off frequency fixes the third pole of H (s),
which is 1/(R L C L ). To control the dc gain, we program the denom-
inator of (4), R1 + R2 . As shown in Fig. 4(a), about 7 dB of dc and
low-frequency gain could be programmed.
B. Mid-Frequency Transfer Function Shape Control
The capacitor C1 is chosen, such that at medium frequencies (sMF ),
resistance R1 shown in Fig. 3(b) gets bypassed by C1 . C2 is
chosen small enough, such that R2 and R1 are not by-passed at this
frequency
Z s (sMF ) R2  1/gm
where sMF is defined by
sMF = 1/(R1 C1 ).
Using (1), (2), (5), and Z L (sMF ) R L , the mid-frequency gain
H (sMF ) is given by
R L
H (sMF ) . (7)
R2
A comparison of (4) and (7) reveals that the gain increases by
a factor (1 + R1 /R2 ) when the frequency approaches sMF . The
programmability of C1 is used to control sMF and the transfer
function at medium frequencies. As shown in Fig. 4(b), about 5 dB
of gain could be programmed at 100 MHz.
C. High-Frequency Transfer-Function Shape Control
At high frequencies, C2 by-passes R2 and C1 by-passes R1
Z s (sHF )  1/gm
where sHF is defined by
sHF = 1/(R2 C2 ).
Using (1), (2), (8), and Z L (sHF ) R L , the high-frequency
gain H (sHF ) is given by
H (sHF ) gm R L . (10)
It can be inferred from (7) and (10) that the gain increases by
a factor of gm R2 when the frequency approaches sHF . By pro-
gramming C2 , we can control sHF and the transfer function at
high frequencies. As shown in Fig. 4(c), about 6-dB gain could be
programmed at 1 GHz.
3
TABLE I
T RANSFER F UNCTION C ONTROL PARAMETERS
Fig. 6. Shape controls for each HPF stage adaptation.
D. Peak-Gain Shape Control
(5)
At a frequency close to sHF , the second-order CTLE (HPF) stage
starts behaving like a conventional first-order CTLE [6], and the
second pole and the second zero of this second-order CTLE stage
(6) are the same as the first zero and the first pole of the first-order
CTLE [6]
(1 + gm R2 ) gm 1
p2 = , z2 = . (11)
(C2 R2 ) C2 (C2 R2 )
To tune the peak gain, gm of M1 and M2 shown in Fig. 3 is tuned
by programming IBIAS .
E. Offset Cancellation, Low-Frequency Attenuation Control
The feedback stage shown in Fig. 1 cancels offset and controls
noise amplification, which is considered as an important drawback
of CTLE [4]. As shown in Fig. 5, noise amplification has been
reduced by 30 dB at frequencies much lower than the data rate
of the receiver (up to the cutoff frequency of the LPF shown
in Fig. 1).
F. Transformation of an HPF Stage to an Amplifier
(8)
For a small cable length, high-pass filtering may be detrimental.
To reduce the CTLE peaking, an HPF stage is converted to an
amplifier by turning ON the switch in Fig. 3(a), removing the source
(9) degeneration.
G. Adaptation of CTLE and Data Recovery
The proprietary cable transfer functions provided in HDMI [8] and
DP [9] specifications have both, falling ramp and falling staircaselike
transfer functions depending on the category of the cable. This
requires not only peak-gain control but also mid-frequency gain
control of the CTLE. Table I shows all the transfer function control
parameters with representative values for the second HPF stage.
Fig. 6 shows the frequency range in which each of these control
parameters impact the HPF transfer function.
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON
Fig. 7. Simulated output-referred noise of the CTLE at extreme settings.
Fig. 8. Chip micrograph. The area of the CTLE is 0.06 mm2 and that of
the receiver is 0.21 mm2 .
Every recovered word (10-bit digital data) should ideally produce
valid TMDS codes [8] for HDMI and valid 8-/10-bit codes for DP [9].
For poor transfer function tuning, some of the recovered words will
produce forbidden codes, which prompts a change in control bits.
Based on the data rate (less than 1.65, 1.653.4, and 3.46 Gb/s),
the default control parameters to begin tuning are picked from pre-
stored values. These have been obtained from the simulation results
and confirmed to be appropriate through laboratory characterization.
The four major dimensions of controlling the CTLE transfer
function are DC gain, mid-frequency gain, high-frequency gain,
and peak gain. Tuning any of the four HPF stages impacts the
CTLE transfer function in the same frequency range for any given
dimension. Consequently, tuning is done, one dimension at a time, for
all stages. Later stages are designed to provide finer tuning. Because
of the large vector size of control bits, valid codes are received for
several settings. The median of all passing settings is chosen, as it
has the largest Euclidean distance (in terms of gain margin) from all
the failing settings. This indirectly adapts the CTLE for a given data
rate and channel.
An additional dimension, low-frequency attenuation is always ON
for more than 1.65-Gb/s data rates. The HPF stages are transformed
Fig. 9. Measured jitter tolerance for DP receiver.
to amplifiers one by one when minimum peaking leads to invalid
codes.
During operation, code validity is monitored to track voltage and
temperature variations. In the case of an invalid code, the control
dimensions are retuned (one by one) by checking 1 bit on both the
sides. Typically voltage, temperature tracking is achieved by 1-bit
retuning for dc gain or mid-frequency gain only. If valid codes are
still not received, a full retuning cycle is repeated.
H. CTLE Noise Analysis
The output-referred noise of the CTLE for extreme control settings
is shown in Fig. 7. The integrated noise from 4-MHz onward is con-
verted to jitter using the worst case-voltage slope at the CTLE output.
Below 4 MHz, the CDR will track and recover data from a noisy
signal. The rms jitter contribution of CTLE comes out to be varying
from 0.9 to 2.9 ps, depending on the CTLE settings. This is acceptable
for the required data rate of 6 Gb/s [unit interval (UI) of 167 ps] for
HDMI and similarly for DP.
IV. M EASUREMENT R ESULTS
The design was implemented in a 28-nm ultrathin body and
buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI)
technology and was tested for 6-Gb/s HDMI 2.0 specifications [8]
and 5.4-Gb/s DP specifications [9]. The chip micrograph is shown
in Fig. 8 showing the CTLE and the receiver areas.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 10. (a) Measured receiver input voltage for 120 bit or 20 ns showing ISI.
(b) Measured eye diagram for receiver input (closed). (c) CTLE output with
default CTLE settings. (d) CTLE output with adapted CTLE settings based on
the algorithm described in Section III-G. All measurements were for 6-Gb/s
data rate, using Agilent E4887A-102 Category 2 HDMI cable emulator [8].
A 5.4-Gb/s 27 1 pseudorandom bit sequence (PRBS7), transmit-
ted through Agilent N4915-68702 DP ISI generator, was used for
measuring DP receiver jitter tolerance as per specifications [9]. The
jitter tolerance curve with respect to DP tolerance mask [4], [9] is
shown in Fig. 9. Fig. 9 shows the performance of the entire receiver,
including the proposed CTLE, the proposed digital adaptation, the
slicer, and the CDR circuit. The DP receiver was found to be tolerant
to more than 0.42 UI jitter at 100 MHz, while the specification
is 0.1 UI at 100 MHz.
Data from a 6-Gb/s PRBS7 generator were transmitted through
Agilent E4887A-102 Category 2 and E4887A-101 Category 1 HDMI
cable emulators. Due to the hardware limitation of the instrument,
the maximum jitter was confined to 0.7 UI. The jitter tolerance
specification for HDMI is 0.3 UI at a BER of 109 [8], [10] and is
tested up to 10 MHz as per the HDMI compliance test specifications.
Our design could tolerate 0.7 UI, which is comparable to 0.75 UI,
as reported in [10]. However, this brief has a power efficiency
of 9.2 pJ/bit as compared to 34.4 pJ/bit for [10].
To directly observe the CTLE output, it was brought out
through an on-chip auxiliary-transmitter driver. The eye diagram
was first observed with default CTLE setting and then with adapted
5
CTLE settings. Comparison of Fig. 10(d) with Fig. 10(c) confirms a
significant improvement in the eye diagram.
Table II shows a summary and a comparison of the performance of
our design with recently published work on HDMI and DP receivers.
The extensive programmability to adapt the CTLE transfer func-
tion to a given channel transfer function allowed a lower power
receiver design, achieve higher CTLE peaking, and enabled support
of two protocols, HDMI 2.0 and DP (with different input common
mode voltages). The equalizer amplifier stages required large gain and
large device lengths were used. Technology scaling did not directly
lead to area or power reduction.
V. C ONCLUSION
The proposed second-order CTLE can provide mid-frequency
gain control and high-frequency gain control, which a conventional
first-order CTLE [1], [6] cannot provide. Due to extensive
CTLE transfer function programmability and its adaptive digital
control, the CTLE output produces a wide open eye diagram. This
eases slicer and CDR circuit designs, leading to a power efficient
receiver.
Fabricated in 28-nm UTBB-FDSOI technology, each receiver chan-
nel consumes 55 mW at 6-Gb/s data rate achieving a power efficiency
of 9.2 pJ/bit. Better matching of transfer function to the inverse
of the channel transfer function allowed the equalizer to support
two different protocols, higher data rate, and still achieve higher
power efficiency than recently published works [1], [4], [10][12].
ACKNOWLEDGMENT
The authors would like to thank other teams at STMicroelectronics,
who worked on the previous versions of the receiver designs.
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