Advanced Synchronous Reference Frame Controller for three-Phase UPS
Powering Unbalanced and Nonlinear Loads
Kyung-Hwan Kim
Ehwa Technologies and Information Company
Department of Power System
272-20 Taejun, Kwangjoo, KyungKi-Do, KOREA
Email: hellokim@eti21.com
Abstract— This paper describes a high performance voltage
controller for 3-phase 4 wire UPS (Uninterruptible Power
Supply) system, and proposes a new scheme of synchronous
reference frame controller in order to compensate for the
voltage distortions due to unbalanced and nonlinear loads.
Proposed scheme in this paper is able to completely eliminate the
negative sequence voltage distortion due to unbalanced loads
and also reduce the harmonic voltage distortion due to
non-linear loads, even if the bandwidth of voltage control loop is
a very narrow. Therefore, the proposed scheme is especially
appropriate for a fully digital controlled UPS or a high power
UPS with limited voltage control bandwidth. In order to
compensate for the effects of unbalanced loads, the synchronous
reference frame controller with the positive and negative
sequence computation block is proposed, and the synchronous
frame controller with a bandpass filter is proposed to
compensate for the selected harmonic frequency of output
voltage. The effectiveness of the proposed scheme has been
investigated and verified through computer simulations and
experiments by a 30kVA UPS.
I. INTRODUCTION
With the ever-increasing use of electronic equipments in
the market, the majority of loads fed by UPS (Uninterruptible
Power Supply) are nonlinear and/or unbalanced loads. These
unbalanced and nonlinear loads create the voltage distortions
which lead to load failures as well as a reduction of inverter
MTBF on the output of UPS [1]. Therefore, the limitation of
the voltage distortions has become the main aim in designing
a high quality UPS. Since the origin of these voltage
distortions is due to the distorted voltage drop on the output
impedance of inverter output filter by the distorted load
currents, several approaches directly proposed a strategically
selected output filter with a low-impedance [1], [2].
Different approaches have been proposed in order to
reduce the voltage distortion in UPS or a 3-phae inverter.
High performance feedback control scheme using a dead-beat
control and an observer has been proposed in [3]. Although
this technique is able to ensure a fast and robust control of
output voltage, the scheme requires the current controller in
the minor loop with a fast sampling frequency and the
knowledge of the filter components.
In [4], repetitive learning controller is designed to
eliminate the periodic tracking error by nonlinear load
disturbances. Although this scheme is able to compensate the
parameter uncertainties of the output filter, it requires still the
0-7803-9033-4/05/$20.00 ©2005 IEEE. 1699
Nam-Joo Park, Dong-Seok Hyun
Hanyang University
Department of Electrical Engineering
17 Haengdang-dong, Seongdong-Gu, Seoul KOREA
Email: pnano@ihanyang.ac.kr
information of the filter components. Also a heightened
sampling frequency is needed to reduce the residue tracking
errors. In UPS control system, the phase of the reference
voltages are changed continuously for synchronization with a
voltage source of the utility or the other UPS in parallel
operation. This situation will produce a bad effect on the
performance of repetitive-based controller.
As another approach, the selected harmonic compensation
method using discrete Fourier transformation (DFT) [5] and
the synchronous reference frame controller (SRFC) [6] have
been proposed. However, the DFT method requires too much
computation, and the method by SRFC requires the
knowledge of the leading angle which compensates for the
system delay.
Unfortunately, the aforementioned approaches do not
compensate the voltage distortion due to unbalanced loads.
Also the majority of them require a wide bandwidth of the
voltage control loop, likewise a fast sampling frequency. In
[7], synchronous reference frame controller has been
proposed in order to compensate the negative sequence
component voltage distortion due to unbalanced loads.
However, with respect that PI controllers in the scheme do not
operate in pure DC domain, the heightened voltage control
bandwidth with over hundreds of Hz is needed for the zero
steady state error, and its performance depend on the delay in
measuring the output voltages.
One important point to be duly considered in designing a
voltage controller for UPS is the voltage control bandwidth.
Considering a full digitalized UPS in the market,
microprocessor or DSP (Digital Signal Processor) actually
must do so many things to increase the value of the product,
such as the serial communication for networking, the
man-machine interface, the displaying of currents, voltages
and some of parameters, the tracing some waveforms, and the
managing of fault history, etc. They limit the switching
frequency; likewise limit the voltage control bandwidth to less
than several hundred rad/sec. Generally, the commercialized
3-phase 4-wire UPS have about from 5 KHz to 10 KHz of
switching or sampling frequency, and it has an output LC
filter whose natural frequency is about from 300Hz to 500Hz.
Under these conditions, if the integral controller is used to
meet about 1% of steady state errors, the bandwidth of voltage
control loop will be limited to more and less 100Hz. This
situation is especially true for a high power UPS because of its
limited switching frequency.
This paper proposes advanced synchronous reference
frame controller (SRFC) based on [6] and [7]. The proposed
scheme can be able to compensate the voltage distortion due II. REVIEW SYNCHRONOUS FRAME CONTROLLER
to non-linear or unbalanced loads even though the voltage In a balanced and linear 3-phase system, synchronous
control bandwidth is very narrow of less than several hundred reference frame transforms both the reference values and the
rad/sec. The scheme is able to provide not only the zero feedback values into DC quantities, and SRFC shown in
steady state error but also fast transient response without any figure 1 is able to provide the zero steady state error even
knowledge of the leading angle and the value of parameters. though the bandwidth of its voltage control loop is narrow.
The effectiveness of the proposed control scheme is verified Also, in respect that it has the simple structure, and it has an
by computer simulations and an experimental UPS system inherent feature of PLL (Phase Locked Loops) through the
that has a 30kVA load power capacity. adjustment of its reference values, SRFC can be considered as
one of best control scheme for UPS. Unfortunately, the
vcd
* *
uca *
, ucb , ucc* integral terms of PI controller in synchronous reference frame
*
do not provide the effectiveness for unbalanced or non-linear
vcq
loads.
(ωt ) vPd Reference [6] and [7] has showed a feasibility of SRFC that
vPq
vca , vcb, vcc is able to eliminate the effects of both non-linear and
(ωt ) unbalanced loads if each strategy is combined. Figure 2 show
the concept of SRFC for unbalanced load compensation
Fig. 1: Conventional SRFC
which is proposed in [7]. The negative sequence controller in
the scheme compensates the negative voltage distortion due to
unbalanced load with the synchronous reference frame
rotating at the fundamental frequency in the opposite
vcd
* direction against the positive sequence. In this scheme, the
uca* , ucb* , ucc*
negative sequence components of feedback voltage vNd, vNq is
vcq
*
pulsating with the two times fundamental frequency under the
(ωt ) vcd unbalanced load and PI controllers does not operate in pure
vca, vcb, vcc
vcq DC domain. Therefore, in order to ensure the zero tracking
error in this scheme, the voltage control bandwidth over than
(ωt ) 120Hz at least and no delay in measuring the output voltages
vNd = Vm cos 2ωt
*
are required.
vNq = −Vm sin 2ωt
*
Figure 3 shows the concept of SRFC for the selected
(−ωt ) harmonic voltage compensation, which is introduced in [6].
vNd
vNq
This method proposes a synchronous reference frame rotating
at the selected harmonic frequency to be compensated in
(−ωt ) positive and negative sequence. This scheme also requires the
more heightened voltage control bandwidth in order to
Fig.2 Negative sequence voltage compensator compensate the harmonic voltage because that PI controllers
operate with a pulsating feedback value. Another drawback in
the scheme for UPS is that it requires the knowledge of the
leading angle ϕ n which compensates for the system delay. It is
*
not easy to calculate the leading angle considering the phase
vcd uca* , ucb* , ucc*
of reference voltages are changed continuously for
vcq
*
synchronization with a voltage source of the utility or the
(ωt ) vcd other UPS in parallel operation.
vcq
III. PROPOSED SYNCHRONOUS FRAME CONTROLLER
(ωt )
*
c ,c ,c
ha
*
hb
*
hc
Figure 4 shows the proposed scheme in this paper. The
negative-sequence voltage controller (NVC) compensates the
negative voltage distortion due to unbalanced loads, and
∫
* * *
vca , vcb , vcc
harmonic voltage compensator (HVC) compensates the
vca, vcb, vcc ( n ωt ) (nωt + ϕn ) harmonic voltage distortion due to non-linear loads. Compare
∫ to SRFC shown in [6] [7], the positive and the negative
(−nωt + ϕn )
sequence computation block are introduced for unbalanced
(− nωt )
load compensation, and bandpass filter is introduced for
non-linear load compensation. The main feature of the
scheme is that NVC and HVC is able to provide the
Fig.3 Harmonic voltage compensator zero-steady state error even if the bandwidth of voltage
control loop is not wide enough.

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A. Negative-sequence Voltage Compensator (NVC) s 2 − bs + c
Y ( s) = X ( s) (3)
Any unbalance output voltage can be expressed as three s 2 + bs + c
symmetrical components of positive, negative and zero
sequence components as follows, In this scheme, the negative sequence computation block
(NSC) shown in equation (3) is accomplished as figure 5. The
Vc = Vc ( + ) +V c ( − )+Vc ( 0 ) (1) positive sequence computation block can be similarly
where accomplished. Note that the NSC and PSC transform the
unbalanced output voltage into the symmetrical balanced sets,
[
Vc = [vca , vcb , vcc ]T , Vc ( + ) = vca ( + ) , vcb( + ) , vcc ( + ) T , ] then, these balanced sets are transformed into perfect DC
[
Vc ( − ) = vca ( − ) , vcb ( − ) , vcc ( − ) ]
T
, Vc (0) = [vca (0) , vcb (0) , vcc (0) ]T quantities by the Park-transformation as

Then the positive and negative component are obtained as ⎡v ⎤

⎡v ⎤ ⎡ cos θ cos(θ − 2π / 3) cos(θ − 2π / 3)
ca
2 ⎤⎢ ⎥ (4)
cd

⎢ ⎥= ⎢ − sin(θ − 2π / 3) ⎦⎥ ⎢
v
⎥
⎣ − sin θ − sin(θ − 2π / 3)
cb
⎣v ⎦ 3
⎡vca ( + ) ⎤ ⎡1 ⎤ ⎡vca ⎤ ⎡ 0 1 -1⎤ ⎡vca ⎤ ⎢⎣ v ⎥⎦
cq
-1 -1
2 2 cc

⎢ ⎥ 1 ⎢ -1 ⎥ ⎢v ⎥ - ⎢-1 0 1 ⎥ ⎢v ⎥ (2) where

⎢vcb ( + ) ⎥ = 3 ⎢ 2 1 -1 1
2
⎥ ⎢ cb ⎥ j2 3 ⎢ ⎥ ⎢ cb ⎥ vcd is d-axis voltage on synchronous reference frame.
⎢⎣ vcc ( + ) ⎦⎥ ⎢⎣ -1 2 -1
2 1 ⎥⎦ ⎢⎣ vcc ⎥⎦ ⎢⎣ 1 -1 0 ⎥⎦ ⎢⎣ vcc ⎥⎦
vcq is q-axis voltage on synchronous reference frame.

⎡vca ( − ) ⎤ ⎡ 1 −1 −1
⎤ ⎡vca ⎤ ⎡0 1 −1⎤ ⎡ vca ⎤
⎢ v ⎥ = 1 ⎢ −1
2 2
Therefore, PI controllers in NVC is operated with pure DC
1 −1 ⎥ ⎢v ⎥ + 1 ⎢ −1 0
⎢ ⎥ (3)
1 ⎥ vcb
⎢ cb ( − ) ⎥ 3 ⎢ 2 2
⎥ ⎢ cb ⎥ j2 3
⎢ ⎥⎢ ⎥ control variables, its output contribute the zero steady state
⎢⎣ vcc ( − ) ⎥⎦ ⎢⎣ −1 2 −1
2 1 ⎥⎦ ⎢⎣ vcc ⎥⎦ ⎢⎣ 1 −1 0⎥
⎦ ⎢⎣ vcc ⎥⎦ error for the compensation of a negative sequence component
voltage distortion regardless of the voltage control bandwidth
where
or phase lag due to system delay including the LC filter. The
j is 90 °phase shift. zero-sequence voltage distortion is compensated by the
The 90 ° phase shift is accomplished by all-pass filter as output transformer with Delta-Wye winding.

*
vcd
vca , vcb , vcc

*
vcq
*
vcd = 0
(ωt )
(ωt )
(± nωt )

vcd
vcq
vca (+)
vcb (+)
(ωt ) vcc (+)
* * *
cna , cnb , cnc

vca (−)
* * *
vcb (−)
cha , chb , chc (−ωt ) (−ωt ) vcc (−)

* * *
vca , vcb , vcc

(−5ωt ) (−5ωt )

(7ωt ) (7ωt )

Fig.4 Proposed control scheme for unbalanced and nonlinear load compensation

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 13
16
16
1
(vca − vcb )
1 j2 3
vca
2 3
Allpass Filter 90° Shift
1 completely eliminated. Likewise the proposed scheme is
vcb
2 3 1 able to provide the improved THD (Total Harmonic
Allpass Filter 90° Shift (vcb − vcc )
j2 3
vcc
Allpass Filter 90° Shift
13
16
16
Fig.5 Block diagram of negative sequence computation
B. Harmonic Voltage Compensator (HVC)
HVC in the proposed scheme is designed to compensate the
selected harmonic voltage distortion due to nonlinear loads.
The scheme shows an example of 5th and 7th harmonic
compensation. The symmetrical balanced harmonic
component of the output voltage can be obtained by the
dedicated bandpass filter whose characteristic frequency is
corresponding to the selected harmonic frequency that is to be
compensated. The bandpass filters in the scheme output the
symmetrical balanced sets of the 5th and 7th harmonic
components, and these symmetrical balanced sets of harmonic
components can be transformed into DC quantities by the
Park-transformation. Likewise PI controllers in HVC are
operated with pure DC control variables, and can provide the
zero steady state errors for selected harmonic frequency.
HVC in the scheme do not require the knowledge of the
system parameter, the leading angle which compensate the
system delay including the LC filter, and a fast switching
frequency.
In conclusion NVC and HVC operates as the feed-forward
controller for the compensation of voltage distortion.
IV. SIMULATION RESULT
Simulation has been performed to verify the validity of the
proposed control scheme shown in figure 4. Unbalanced
load condition, where 100% load is connected between
A-phase and neutral point and the other phase are left open
circuit, is used in the computer simulation. Figure 6 shows
3-phase output voltage waveforms, RMS values, negative
sequence components, and the control inputs (PI controller
output) respectively under the condition where the
unbalanced load is applied at 100msec from the no-load state.
Note that only peak portion of the output voltage waveforms
are shown in this figure.
It can be seen from the simulation results that the proposed
SRFC is able to completely eliminate the negative sequence
component of the output voltage within one period of the
output voltage, and the PI controllers in the proposed
scheme are operated with pure DC quantities while the PI
controllers in the conventional SRFC without any
compensation have the pulsating signals.
Figure 7 shows the simulation results under the condition
that the UPS system feeds the balanced 100% of non-linear
vca( − ) loads. It can be seen from figure 7(b) that the 5th and 7th
vcb(− ) harmonic components of the output voltage were
vcc( − )
Distortion) in the output voltage. Through these simulation
results, the feasibility of the proposed control scheme can be
verified.
V. EXPERIMENTAL RESULT
The prototype for the fully digital controlled three-phase
inverter using two DSP (TMS320C33 and
TMS320LF2407A) was built to investigate the operation
performance and to prove the feasibility of the proposed
control scheme. The major parameters of the UPS system
used in the experiments are given as follows
z Power rating: 30kVA
z Fundamental frequency : 60Hz
z Nominal line-to-line output voltage : 208V
z DC bus : 405V
z Inverter and converter switching frequency : 6kHz
z Voltage control bandwidth: about 120Hz
z Output transformer turns ratio : 1.22:1
z Output transformer parameters: %X=5%, %R=3.5%
z Selected frequencies for harmonic compensation: 5th, 7th
Figure 8 shows the q-axis voltage reference which is
pulsating with about 120Hz and the q-axis output voltage of
the test equipment. It can be seen from this figure that the
voltage control bandwidth of the prototype is about 120Hz.
Figure 9 shows 3-phase UPS output voltage waveform under
the unbalanced load. Note that the imbalance of the output
voltage has been perfectly improved to 0.19, while imbalance
of 3.57 is obtained from the conventional SRFC without any
compensation shown in figure 1. The negative sequence
component of the output voltage is also perfectly eliminated
to 0.4V from 6 V.
In order to compensate the harmonic voltage distortion due
nonlinear load, the 5th and 7th harmonic compensating strategy
proposed in this paper has been implemented on the prototype
of UPS. Figure 10 shows the output voltage and current
waveforms under the condition, where uncontrolled 3-phase
rectifier load is connected. Figure 11 shows Fourier spectra of
the voltage and current waveforms which are shown in figure
10. The upper waveform is for the current and the other is for
the output voltage. The voltage and current distortions before
and after the compensation are shown in Table I. Note that the
5th and 7th harmonic components of output voltage are
perfectly eliminated to near zero.
These experimental result shows that proposed scheme is
able to provide the zero steady state errors for the unbalanced
and nonlinear load compensation even though the bandwidth
of the voltage control loop is limited.
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 output voltages without compensation output voltages with compensation

RMS of output voltage without compensation RMS of output voltage with compensation

negative sequence components of output negative sequence components of output

voltage without compensation voltage with compensation

output of PI controllers in SFC output of PI controllers in SFC

without compensation with compensation

(a) SRFC Without any compensation (b) Proposed SRFC

Fig.6 Simulation Results: Unbalanced load compensation

output voltage and current THD of voltage and current FFT of output voltage

a) Conventional SRFC without any compensation

output voltage and current THD of voltage and current FFT of output voltage

b) Proposed Synchronous Frame Controller

Fig.7 Simulation Results: Non-linear load compensation

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 TABLE I SYSTEM PARAMETERS VI. CONCLUSION
This paper has proposed the advanced synchronous
Harmonic With Compensation Without Compensation
order
reference frame control scheme for the unbalanced and
Voltage Curren Voltage Current
(%) t(%) (%) (%) nonlinear load compensation in UPS. SRFC proposed in this
5th 0.1 28.3 2.6 26.0 paper is able to perfectly compensate for the negative voltage
7th 0.1 11.8 1.8 10.5 distortion and the selected harmonic voltage distortion
11th 1.1 7.9 2.4 5.5
created by unbalanced load and non-linear load respectively
13th 2.6 4.4 2.9 5.7
THD(%) 2.9 5.9 even if the bandwidth of voltage control loop is limited to less
than 100Hz. PI controllers in the proposed scheme operate
with pure DC values under the unbalanced and nonlinear load
144 condition, in the same as SRFC under balanced system, which
142
140 is able to provide the zero steady state error.
138
136
The proposed scheme is particularly suitable for a full
134
132
digital controlled high power UPS with limited voltage loop
130 bandwidth.
1 11 21 31 41 51 61 71 81 91 101 111 121 131 141 151 161 171 181 191

×166.7 µ sec
Fig.8 q-axis voltage reference and feedback APPENDIX
The voltage imbalance is calculated by equation shown
below

Maximum value of RMS/ Average value of RMS

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zero-output impedance UPS system” IEEE Trans. Industry
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Fig.9 3-phase voltage waveforms of proposed scheme [2] Peng Li, Bai Dan, Kang Yong, and Chen Jian, “Research on
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a)vab=203.5,Vbc=210.9,Vca=207.0 APEC 2004, CD ROM, Feb. 2004.
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[5] A.Von Jounne, P.N. Engeti and D.J. Lucas, “DSP Control of High
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[6] P.Mattavelli, and S.Fasolo, “Implementation of Synchronous Frame
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a) Conventional SRFC b) Proposed SRFC [7] P.Hsu and M. Behnke, “A Three-phase Synchronous Frame Controller
Fig.10 Voltage and load current waveforms during non-linear for Unbalanced Load,” Proceedings of the 1988 IEEE Power
load(voltage-100V/div, current-50A/div, time- 5ms/div) Electronics Specialists Conference, vol.2, pp.1369-1374.

current

voltage

1st 3rd 5th 11th 13th 1st 3rd 5th 11th 13th
a) Conventional SFC b) Proposed SFC

Fig.11 Fourier spectra of voltage and load current during

nonlinear load
(voltage-4V/div, current-4A/div, frequency- 100Hz/div)

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