Digital Electronics Sample Chapter PDF

Eighth Edition
GATE
ELECTRONICS & COMMUNICATION
Digital Electronics
Vol 6 of 10
R. K. Kanodia
Ashish Murolia
NODIA & COMPANY

GATE Electronics & Communication Vol 6, 8e
Digital Electronics
RK Kanodia & Ashish Murolia
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SYLLABUS
GATE Electronics & Communications

Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL,
TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters,
multiplexers, decoders, PROMs and PLAs. Sequential circuits : latches and flip-flops,
counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories.
Microprocessor(8085): architecture, programming, memory and I/O interfacing.
IES Electronics & Telecommunication
Transistor as a switching element ; Simplification of Boolean functions, Karnaguh map

, Boolean algebra, and applications; IC logic families : DTL, ECL, TTL, NMOS, CMOS
and PMOS gates and their comparison; Full adder , Half adder; IC Logic gates and their
characteristics; Digital comparator; Multiplexer Demultiplexer; Flip flops. J-K, R-S, T and
D flip-flops; Combinational logic Circuits; Different types of registers and counters Waveform
generators. Semiconductor memories.A/D and D/A converters. ROM an their applications.
**********
CONTENTS
CHAP 1 NUMBER SYSTEM AND CODES
1.1 INTRODUCTION 1
1.2 ANALOG AND DIGITAL SYSTEMS 1
1.2.1 Advantages of Digital System 2
1.2.2 Limitations of Digital System 2
1.3 NUMBER SYSTEMS 2
1.3.1 Decimal Number System 2
1.3.2 Binary Number System 3
1.3.3 Octal Number System 3
1.3.4 Hexadecimal Number System 4
1.4 NUMBER SYSTEM CONVERSION 5
1.4.1 Decimal-to-Binary Conversion 5
1.4.2 Decimal-to-Octal Conversion 6
1.4.3 Decimal-to-Hexadecimal Conversion 7
1.4.4 Octal-to-Binary conversion 7
1.4.5 Binary-to-Octal Conversion 7
1.4.6 Hexadecimal-to-Binary Conversion 8
1.4.7 Binary-to-Hexadecimal Conversion 8
1.4.8 Hexadecimal-to-Octal and Octal-to-Hexadecimal Conversion 8
1.5 BASIC BINARY ARITHMETIC 9
1.5.1 Binary Addition 9
1.5.2 Binary Subtraction 9
1.5.3 Binary Multiplication 9
1.5.4 Binary Division 9
1.6 COMPLEMENTS OF NUMBERS 10
1.7 NUMBER REPRESENTATION IN BINARY 11
1.7.1 Sign-Magnitude Representation 11
1.7.2 1s Complement Representation 11
1.7.3 2s Complement Representation 12
1.8 COMPLEMENT BINARY ARITHMETIC 13
1.8.1 Addition Using 1s Complement 13
1.8.2 Subtraction Using 1s Complement 13
1.8.3 Addition Using 2s Complement 14
1.8.4 Subtraction using 2s Complement 15
1.9 HEXADECIMAL ARITHMETIC 15
1.9.1 Hexadecimal Arithmetic Using 1s or 2s Complements 15
1.9.2 Hexadecimal Subtraction Using 15s or 16s Complement 15
1.10 OCTAL ARITHMETIC 16
1.10.1 Octal Arithmetic using 1s or 2s Complements 16
1.10.2 Octal Subtraction using 7s or 8s complement 16
1.11 DECIMAL ARITHMETIC 17
1.11.1 Decimal Arithmetic Using 1s or 2s Complements 17
1.11.2 Decimal Subtraction Using 9s and 10s Complement 17
1.12 BINARY CODES 18
1.13 BINARY CODED DECIMAL (BCD) CODE OR 8421 CODE 20
1.13.1 BCD-to-Binary Conversion 20
1.13.2 Binary-to-BCD Conversion 20
1.14 BCD ARITHMETIC 20
1.14.1 BCD Addition 21
1.14.2 BCD Subtraction 21
1.15 THE EXCESS-3 CODE 22
1.16 GRAY CODE 23
1.16.1 Binary-to-Gray Code Conversion 23
1.16.2 Gray-to-Binary Code Conversion 24
1.16.3 Applications of Gray Code 24
EXERCISE 1.1 25
EXERCISE 1.2 31
EXERCISE 1.3 33
SOLUTIONS 1.1 41
SOLUTIONS 1.2 53
SOLUTIONS 1.3 58
CHAPTER 2 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
2.1 INTRODUCTION 63
2.2 BOOLEAN ALGEBRA 63
2.2.1 Logic Levels 63
2.2.2 Truth Table 64
2.3 BASIC BOOLEAN OPERATIONS 64
2.3.1 Boolean Addition (Logical OR) 64
2.3.2 Boolean Multiplication (Logical AND) 65
2.3.3 Logical NOT 65
2.4 THEOREMS OF BOOLEAN ALGEBRA 66
2.4.1 Complementation Laws 66
2.4.2 AND Laws 66
2.4.3 OR Laws 66
2.4.4 Commutative Laws 67
2.4.5 Associative Laws 67
2.4.6 Distributive Law 67
2.4.7 Redundant Literal Rule 67
2.4.8 Idempotent Law 67
2.4.9 Absorption Law 67
2.4.10 Consensus Theorem 67
2.4.11 Transposition Theorem 68
2.4.12 De Morgans Theorem 68
2.4.13 Shannons Expansion Theorem 68
2.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA 68
2.5.1 Complement of Boolean Function 69
2.5.2 Principal of Duality 69
2.5.3 Relation Between Complement and Dual 69
2.6 LOGIC GATES 69
2.6.1 Logic Levels 70
2.6.2 Types of Logic Gates 70
2.7 UNIVERSAL GATE 75
2.7.1 NAND Gate as a Universal Gate 75
2.7.2 NOR Gate as a Universal Gate 77
2.8 ALTERNATE LOGIC-GATE REPRESENTATIONS 79
2.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS 80
2.9.1 Converting Boolean Expressions to Logic Diagram 80
2.9.2 Converting Logic to Boolean Expressions 81
2.10 CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC 82
2.10.1 NAND-NAND Logic 82
2.10.2 NOR-NOR Logic 83
EXERCISE 2.1 84
EXERCISE 2.2 105
EXERCISE 2.3 107
SOLUTIONS 2.1 117
SOLUTIONS 2.2 144
SOLUTIONS 2.3 148
CHAPTER 3 THE K-MAP
3.1 INTRODUCTION 155

3.2 REPRESENTATION FOR BOOLEAN FUNCTIONS 155
3.2.1 Sum-of-Products (SOP) 156
3.2.2 Product-of-Sum (POS) 156
3.3 STANDARD OR CANONICAL SUM-OF-PRODUCTS (SOP) FORM 156
3.3.1 Minterm 157
3.3.2 S Notation 157
3.3.3 Converting SOP Form to Standard SOP Form 158
3.4 STANDARD OR CANONICAL PRODUCT-OF-SUMS (POS) FORM 158
3.4.1 Maxterm 158
3.4.2 P Notation 159
3.4.3 Converting POS Form to standard POS Form 159
3.5 CONVERTING STANDARD SOP FORM TO STANDARD POS FORM 160
3.6 BOOLEAN EXPRESSIONS AND TRUTH TABLES 161
3.7 CALCULATION OF TOTAL GATE INPUTS USING SOP AND POS 162
3.8 KARNAUGH MAP (K-MAP) 162
3.8.1 Structure of K-map 163
3.8.2 Another Structure of K-map 165
3.8.3 Cell Adjacency 165
3.9 PLOTTING A K-MAP 166
3.9.1 Plotting Standard SOP on K-map 166
3.9.2 Plotting Standard POS on K-map 166
3.9.3 Plotting a Truth Table on K-map 166
3.10 GROUPING OF CELLS FOR SIMPLIFICATION 166
3.10.1 Grouping of Two adjacent Cells (Pair) 166
3.10.2 Grouping of Four Adjacent Cells (Quad) 167
3.10.3 Grouping of Eight Adjacent Cells (Octet) 168
3.10.4 Redundant Group 169
3.11 MINIMIZATION OF SOP EXPRESSIONS 169
3.12 MINIMIZATION OF POS EXPRESSIONS 170
3.13 CONVERTING SOP TO POS AND VICE-VERSA 170
3.14 DONT CARE CONDITIONS 171
3.14.1 K-map Simplification With Dont Care Conditions 171
3.14.2 Conversion of Standard SOP to Standard POS with Dont Care Conditions 171
3.15 K-MAPS FOR MULTI-OUTPUT FUNCTIONS 171
3.16 LIMITATIONS OF K-MAP 172
EXERCISE 3.1 173
EXERCISE 3.2 186
EXERCISE 3.3 188
SOLUTIONS 3.1 192
SOLUTIONS 3.2 223
SOLUTIONS 3.3 228
CHAPTER 4 COMBINATIONAL CIRCUITS

4.2 DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS 231
4.3 ADDERS 232
4.3.1 Half-Adder 232
4.3.2 Full-Adder 233
4.4 SUBTRACTORS 235
4.4.1 Half-Subtractor 235
4.4.2 Full-Subtractor 236
4.5 BINARY PARALLEL ADDER 237
4.6 CARRY LOOK-AHEAD ADDER 238
4.6.1 Carry Generation 238
4.6.2 Carry Propagation 239
4.6.3 Look Ahead Expressions 239
4.7 SERIAL ADDER 240
4.8 COMPARATOR 241
4.8.1 1-bit Magnitude Comparator 241
4.8.2 2-bit Magnitude Comparator 242
4.9 MULTIPLEXER 244
4.9.1 2-to-1 Multiplexer 245
4.9.2 4-to-1 Multiplexer 245
4.9.3 Implementation of Higher Order Multiplexers using Lower Order Multiplexers 247
4.9.4 Applications of Multiplexers 247
4.10 DEMULTIPLEXER 247
4.10.1 1-to-2 Demultiplexer 248
4.10.2 1-to-8 Demultiplexer 249
4.10.3 Applications of Demultiplexers 250
4.10.4 Comparison between Multiplexer and Demultiplexer 250
4.11 DECODER 251
4.11.1 2-to-4 Line Decoder 252
4.11.2 Applications of Decoder 253
4.12 ENCODERS 253
4.12.1 Octal-to-Binary Encoder 253
4.12.2 Decimal-to-BCD Encoder 254
4.13 PRIORITY ENCODERS 256
4.14 CODE CONVERTERS 257
4.15 PARITY GENERATOR 259
4.15.1 Even Parity Generator 260
4.15.2 Odd Parity Generator 260
EXERCISE 4.1 262
EXERCISE 4.2 281
EXERCISE 4.3 284
SOLUTIONS 4.1 291
SOLUTIONS 4.2 314
SOLUTIONS 4.3 318
CHAPTER 5 SEQUENTIAL CIRCUITS

5.2 SEQUENTIAL LOGIC CIRCUITS 323
5.3 LATCHES AND FLIP-FLOPS 324
5.3.1 General Block Diagram of a Latch or Flip-flop 324
5.3.2 Difference between Latches and Flip-flops 325
5.4 S-R LATCH 325
5.4.1 S - R Latch using NOR Gates 325
5.4.2 S - R Latch using NAND Gates 326
5.5 FLIP-FLOPS 327
5.5.1 S-R Flip-Flop 327
5.5.2 D-Flip Flop 328
5.5.3 J-K Flip-Flop 329
5.5.4 T Flip-Flop 331
5.6 TRIGGERING OF FLIP-FLOPS 332
5.6.1 Level Triggering 332
5.6.2 Edge Triggering 332
5.6.3 Edge Triggered S - R Flip Flop 334
5.6.4 Edge Triggered D Flip-Flop 336
5.6.5 Edge Triggered J - K Flip-Flop 337
5.6.6 Edge Triggered T -Flip-Flop 339
5.7 OPERATING CHARACTERISTIC OF FLIP-FLOPS 340
5.8 APPLICATION OF FLIP-FLOPS 342
5.9 REGISTER 343
5.9.1 Buffer Register 343
5.9.2 Shift Register 344
5.9.3 Applications of Shift Registers 345
5.10 COUNTER 345
5.10.1 Asynchronous and Synchronous Counter 345
5.10.2 Up-Counter and Down-Counter 346
5.10.3 MOD Number or Modulus of a Counter 348
5.11 SHIFT REGISTER COUNTERS 348
5.11.1 Ring Counter 348
5.11.2 Johnson Counter 349
EXERCISE 5.1 352
EXERCISE 5.2 369
EXERCISE 5.3 372
SOLUTIONS 5.1 383
SOLUTIONS 5.2 402
SOLUTIONS 5.3 407
CHAPTER 6 LOGIC FAMILIES

6.2 CLASSIFICATION OF DIGITAL LOGIC FAMILY 413
6.3 CHARACTERISTIC PARAMETERS OF DIGITAL LOGIC FAMILY 414
6.3.1 Speed of Operation 414
6.3.2 Power Dissipation 415
6.3.3 Voltage Parameters 415
6.3.4 Current Parameters 416
6.3.5 Noise Immunity or Noise Margin 416
6.3.6 Fan-In 417
6.3.7 Fan-out 417
6.3.8 Operating Temperature 417
6.3.9 Speed Power Product 417
6.4 RESISTOR-TRANSISTOR LOGIC (RTL) 418
6.4.1 Circuit Operation 418
6.4.2 Drawbacks of RTL Family 418
6.5 DIRECT COUPLED TRANSISTOR LOGIC (DCTL) 419
6.5.1 Circuit Operation 419
6.6 DIODE TRANSISTOR LOGIC (DTL) 419
6.7 TRANSISTOR-TRANSISTOR LOGIC (TTL) 421
6.8 TTL CIRCUIT OUTPUT CONNECTION 422
6.8.1 Totem-pole Output 422
6.8.2 Open-collector Output 423
6.8.3 Tri-state Output 423
6.9 TTL SUBFAMILIES 424
6.10 EMITTER COUPLED LOGIC (ECL) 425
6.10.1 ECL OR/NOR Gate 426
6.10.2 ECL Characteristics 427
6.10.3 Advantages and Disadvantages of ECL Family 427
6.11 INTEGRATED INJECTION LOGIC (I L) 2
428
6.11.1 Characteristic of I2L 428
6.11.2 I2L Inverter 428
6.11.3 I2L NAND Gate 428
6.11.4 I2L NOR Gate 429
6.11.5 Advantages of I2L 429
6.11.6 Disadvantages of I2L 429
6.12 METAL OXIDE SEMICONDUCTOR (MOS) LOGIC 430
6.12.1 NMOS Inverter 430
6.12.2 NMOS NAND Gate 431
6.12.3 NMOS NOR Gate 432
6.12.4 Characteristics of MOS Logic 433
6.13 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) LOGIC 433
6.13.1 CMOS Inverter 434
6.13.2 CMOS NAND Gate 434
6.13.3 CMOS NOR Gate 435
6.13.4 Characteristics of CMOS Logic 436
6.13.5 Advantages and Disadvantages of CMOS Logic 437
6.14 COMPARISON OF VARIOUS LOGIC FAMILIES 437
EXERCISE 6.1 439
EXERCISE 6.2 455
EXERCISE 6.3 458
SOLUTIONS 6.1 465
SOLUTIONS 6.2 485
SOLUTIONS 6.3 490
CHAPTER 7 INTERFACING TO ANALOG

7.2 DIGITAL TO ANALOG CONVERTER 495
7.2.1 Parameters of DAC 496
7.3 DAC CIRCUITS 496
7.3.1 R - 2R Ladder Type DAC 496
7.3.2 Weighted Resistor Type DAC 497
7.4 ANALOG-TO-DIGITAL CONVERTER 497
7.4.1 Sample-and-hold circuit 498
7.4.2 Quantization and Encoding 499
7.4.3 Parameters of ADC 499
7.5 ADC CIRCUITS 500
7.5.1 Flash Type A/D Converter 500
7.5.2 Counting A/D Converter 501
7.5.3 Dual Slope Type A/D Converter 503
7.5.4 Successive Approximation Type ADC 503
7.6 ASTABLE MULTIVIBRATOR 504
7.6.1 Astable Multivibrator Using BJT 505
7.6.2 Astable Multivibrator Using 555 Timer 507
7.6.3 Astable Multivibrator Using Op-amps 507
7.7 MONOSTABLE MULTIVIBRATOR 508
7.7.1 Monostable Multivibrator Using BJT 508
7.7.2 Monostable Multivibrator Using 555 Timer 510
7.8 SCHMITT TRIGGER 511
7.8.1 Schmitt Trigger Using BJT 512
7.8.2 Schmitt Trigger Using 555 Timer 513
EXERCISE 7.1 515
EXERCISE 7.2 532
EXERCISE 7.3 535
SOLUTIONS 7.1 541
SOLUTIONS 7.2 564
SOLUTIONS 7.3 568
CHAPTER 8 MICROPROCESSOR

8.2 MICROCOMPUTER 571
8.2.1 Memory 572
8.2.2 Input-Output Interfacing 572
8.2.3 System Bus 572
8.3 MICROPROCESSOR OPERATION 572
8.3.1 FETCH 573
8.3.2 EXECUTE 573
8.4 MICROPROCESSOR ARCHITECTURE 573
8.4.1 System Bus 573
8.4.2 Arithmetic Logic Unit (ALU) 573
8.4.3 Registers 574
8.4.4 Program Counter (PC) 574
8.4.5 Flags 574
8.4.6 Timing and Control Unit 574
8.5 PIN DIAGRAM OF 8085 MICROPROCESSOR 574
8.5.1 Address and Data Bus 575
8.5.2 Control and Status Signals 575
8.5.3 Power Supply and Clock Frequency 576
8.5.4 Interrupts and Other Operations 576
8.5.5 Serial I/O Ports 577
8.6 INSTRUCTION SET 577
8.6.1 Data Transfer Instructions 577
8.6.2 Arithmetic Instructions 579
8.6.3 Branching Instructions 581
8.6.4 Logic Instructions 584
8.6.5 Control Instructions 587
EXERCISE 8.1 589
EXERCISE 8.2 602
EXERCISE 8.3 605
SOLUTIONS 8.1 609
SOLUTIONS 8.2 621
SOLUTIONS 8.3 625
***********
GATE STUDY PACKAGE Electronics & Communication
Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)
Page 63
CHAPTER 2
Chap 2
Boolean Algebra and
Logic Simplification
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION
i. n
2.1 INTRODUCTION
o
This chapter, concerned with the basic study of Boolean algebra and
c
simplification theory, includes the following topics:

.
Introduction to Boolean algebra: logic levels, truth table.

i a
Basic Boolean operations: addition, multiplication, not operation
Various theorems of Boolean algebra

o d
Meaning of positive and negative logic
Various types of logic gates: AND, OR, NOT, NAND, NOR, XOR,

.
XNOR gates.
n
Universal logic gates; conversion of logic diagrams to universal

w w
logic gates.
Boolean analysis of logic circuits.
2.2
w
BOOLEAN ALGEBRA
Boolean algebra is mathematics of logic. It is one of the most basic

tools which is used in the analysis and synthesis of logic circuit. In
Boolean algebra, often the variables are represented by capital letters
such as A, B , C , X , Y , Z . The Boolean value of a variable is either
logic 0 or logic 1. These, 0 and 1, are known as Boolean constants.
2.2.1 Logic Levels

Boolean logic variable 0 or 1 is not used to represent actual numbers
but it is used to represent the state of voltage variable called logical
level. Commonly used representation of logic levels are shown in Table
below.
Table 2.1: Representation of Logic Levels for Boolean Variables
Logic 0 Logic 1
False True
Open switch Close switch
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Logic 0 Logic 1
Chap 2
Boolean Algebra and
Logic Simplification Low High
No Yes
OFF ON
2.2.2 Truth Table

A truth table represents the relation between all inputs and possible
outputs of any logic device or logic circuit in a tabular form. The
number of inputs may vary from one to many depending upon the
device or complexity of the circuit. Number of output also varies in this
way and may be one or more. For different digital circuits, some of the
examples of truth table are given below.
in
Table 2.2: Examples of Truth Tables for 1-input, 2-input and 3-input
Circuits
o .
. c
d ia
n o
w.
w w
2.3 BASIC BOOLEAN OPERATIONS
Boolean algebra uses only three basic operations, namely

1. OR operation
2. AND operation
3. NOT operation
2.3.1 Boolean Addition (Logical OR)

The OR operation in Boolean algebra is similar to addition in ordinary
algebra i.e., OR means logical addition operation. The logical OR
operation on A and B is denoted by

Y = A + B, where + is the OR operator Page 65

The output Y corresponding to various combinations of inputs, A Chap 2
and B , is shown in Table 2.3 below. Boolean Algebra and
Table 2.3: Truth Table for OR Operation
Input Output
A B Y = A+B
0 0 0
0 1 1
i. n
1 0 1
1 1 1
NOTE :
. c o
The minimum number of inputs for OR operation is two. The number of outputs
i a
is always one, irrespective of the number of inputs.
2.3.2
d
Boolean Multiplication (Logical AND)
o
The AND operation in Boolean algebra is similar to multiplication in
. n
ordinary algebra i.e, AND performs logical multiplication operation.
Let A and B be two Boolean variables. Then, the logical AND
w w
operation on A and B is denoted by
Y = A : B,
where : is the AND operator. The output Y corresponding to various
w combinations of inputs, A and B , is shown in Table 2.4 below.
Table 2.4: Truth table for AND operation
Input Output
A B Y = AB
0 0 0
0 1 0
1 0 0
1 1 1
NOTE :
The minimum number of inputs for AND operation is two. The number of output
is always one, irrespective of the number of inputs.
2.3.3 Logical NOT

NOT is the simplest of the three basic operations of Boolean algebra.
It is also known as inversion and complement. The NOT operation is
indicated by a bar - over the variable. If A is a variable, then NOT
of A is expressed as A . The truth Table of the NOT operation is shown
in Table 2.5.

Page 66 Table 2.5: Truth table for NOT operation

Chap 2
Boolean Algebra and Input Output
A Y=A
0 1
1 0
NOTE :
Logical NOT is the only Boolean operation which must be performed with only
one operand or one input. Note that in some texts, the NOT operation is also
presented as Al .
2.4 THEOREMS OF BOOLEAN ALGEBRA
The theorems of Boolean algebra can be used to simplify many complex
. in
Boolean expression and also to transform the given expression into a
more useful and meaningful equivalent expression. These theorems are
2.4.1
discussed as below.
Complementation Laws
. c o
d ia
The term complement implies to invert, i.e. to change 1s to 0s and 0s
to 1s. The five laws of complementation are as follows:
2.
n o
1. The complement of 0 is 1, i.e. 0 = 1
The complement of 1 is 0, i.e. 1 = 0
3.
4.
w.
If A = 0 , then A = 1
If A = 1, then A = 0
w
5.
w
The double complementation does not change the function, i.e.
A=A
2.4.2 AND Laws

The four AND laws are as follows:
1. Null Law: A : 0 = 0
2. Identity Law: A : 1 = A
3. A:A = A
4. A:A = 0
2.4.3 OR Laws
The four OR laws are as follows:
1. Null Law: A + 0 = A
2. Identity Law: A + 1 = 1
3. A+A = A
4. A+A = 1

2.4.4 Commutative Laws Page 67

Chap 2
Commutative law states that the order of the variable in OR and AND Boolean Algebra and
operations is not important. The two commutative laws are Logic Simplification
A+B = B+A
A:B = B:A
2.4.5 Associative Laws

Associative law states that the grouping of variables in AND or OR
expression does not affect the result. There are two associative laws.
A + _B + C i = _A + B i + C
A : _B : C i = _A : B i : C
i. n
2.4.6 Distributive Law
. c o
The distributive laws allow factoring or multiplying out of expressions.
There are two distributive laws
i
A _B + C i = AB + AC
a
d
A + BC = _A + B i_A + C i
o
2.4.7 Redundant Literal Rule
. n
This law states that ORing of a variable with the AND of the
w w
complement of that variable with another variable, is equal to ORing
of the two variables, i.e.
A + AB = A + B
w Another theorem based on this law is

A _A + B i = AB
2.4.8 Idempotent Law

Idempotence means the same value. There are two idempotent laws
A : A : A :g: A = A
A+A+A+g+A = A
2.4.9 Absorption Law

There are two absorption laws
A+A:B = A
A : _A + B i = A
2.4.10 Consensus Theorem

There are two consensus theorems,
AB + AC + BC = AB + AC
_A + B i_A + C i_B + C i = _A + B i_A + C i

Page 68 2.4.11 Transposition Theorem

Chap 2
Boolean Algebra and There are two transposition theorems, the first is given as
Logic Simplification AB + AC = _A + C i_A + B i
_A + B i : _A + C i = A : C + A : B
2.4.12 De Morgans Theorem

De Morgans theorem gives two of the most powerful laws in Boolean
algebra. These theorems are very useful in simplification of Boolean
expressions,
A+B = A B
AB = A + B
2.4.13 Shannons Expansion Theorem

According to this theorem, any switching expression can be decomposed
. in
with respect to a variable A into two parts, one containing A and the
other containing A . This concept is useful in decomposing complex
system into an interconnection of smaller components.
c o
f _A, B, C, ....i = A : f _1, B, C...i + A : f _0, B, C, ...i
.
f _A, B, C, ...i = 8A + f _0, B, C, ...iB : 8A + f _1, B, C, ...iB
2.5
d ia
SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN
ALGEBRA
n o
w.
In Boolean algebra, we have to reduce the Boolean expression into its
simplest form such that the hardware cost reduces efficiently. The basic
w w
rules, laws and theorems of Boolean algebra discussed in this chapter,
are used to simplify Boolean expressions. The following steps are used
to simplify a Boolean expression using Boolean algebra,
METHODOLOGY: TO SIMPLIFY A BOOLEAN EXPRESSION USING

BOOLEAN ALGEBRA
1. Remove all parentheses and multiply all variables.

2. Look for the identical terms. Only one of those terms be retained
and all others skipped. For example,
AB + AB + AB = AB
3. Look for a variable and its complement in the same term. This
term can be removed. For example,
A : BB = A : 0 = 0 ; ABCC = AB : 0 = 0
4. Look for pairs of terms that are identical except for one variable
which may be missing in one of the terms. The larger term can
be removed. For example,
ABC D + ABC = ABC _D + 1i = ABC : 1 = ABC

Page 69
5. Look for pairs of terms which have the same variables, except in Chap 2
one term a variable is complemented and in other term is it not. Boolean Algebra and
Such terms can be combined into a single terms. For example, Logic Simplification
ABC D + ABC D = ABC _D + D i = ABC : 1 = ABC
AB _C + D i + AB _C + D i = AB 7_C + D i + _C + D iA = AB : 1 = AB
6. Apply Boolean theorem and laws discussed earlier for further

simplification.
2.5.1 Complement of Boolean Function

The complement of a Boolean function is obtained in the following
steps:
i. n
. c o
METHODOLOGY: TO OBTAIN COMPLEMENT OF BOOLEAN EXPRESSION
i a
1. Change all the ANDs to ORs and all the ORs to ANDs i.e.,
change all : to + and all + to :
o d
2. Complement each of the individual variables.
3. Change all 0s to 1s and 1s to 0s.
. n
2.5.2
w
Principal of Duality
w
Duality is a very important property of Boolean algebra. The dual of a
w Boolean expression is obtained by replacing all : operations with +

operations, all + operations with : operations, and complementing
all 0s and 1s. The variables are not complemented in this process.
Dual of a function f _A, B, C, ...i is given as
7f _A, B, C,..., 0, 1, + , :iAd = f _A, B, C, ..., 1, 0, : , +i
2.5.3 Relation Between Complement and Dual

For a given Boolean expression f _A, B, C, ...i the relation between its
complement and dual expressions are given as
fc _A, B, C,....i = f _A, B, C, ...i = fd _A, B , C , ...i
fd _A, B, C,...i = f _A, B , C , ...i = fc _A, B , C , ....i
where subscript c represents the complement and subscript d
represents the dual of the given function.
NOTE :
The above relation states that the dual can be obtained by complementing all the
literals in complement function f Â, B, C, ....h .
2.6 LOGIC GATES
Logic gates are the fundamental building blocks of digital systems.

Logic gates are electronic circuits that perform the most elementary

Page 70 Boolean operations. Before understanding the logic gates, we must

Chap 2 understand the meaning of positive and negative logic.
Boolean Algebra and
2.6.1 Logic Levels
Inputs and outputs of logic gates can occur only in two levels. These
two levels are termed HIGH and LOW, or TRUE and FALSE, or ON
and OFF, or simply 1 and 0. There are two different ways to assign a
signal value to logic level such as positive logic and negative logic.
1. Positive Logic: If higher of the two voltage levels represents a logic
1 and the lower of the two levels represents a logic 0, then the
logic system is referred to as a positive logic system. Figure 2.1
shows the positive logic system.
. in
2.
Figure 2.1: Positive Logic System
. c o
Negative Logic: If the higher of the two voltage levels represents a
ia
logic 0 and the lower of the two levels represents a logic 1, then
the logic system is referred to as a negative logic system. Figure
d
2.2 shows the representation of negative logic systems.
n o
w.
w w
Figure 2.2: Negative Logic System
3. Mixed Logic: In mixed logic, the assignment of logical values to

voltage values is not fixed, and it can be decided by the logic
designers. Mixed logic provides a simplified mechanism for the
analysis and design of digital circuits. The proper use of mixed
logic notation provides logic expressions and logic diagrams that
are analogue to each other. Also, a mixed logic diagram provides
clear information as to the operation of a circuit.
2.6.2 Types of Logic Gates

Logic gates are electronic circuits with a number of inputs and one
output. There are three basic logic gates, namely
1. OR gate,
2. AND gate,
3. NOT gate

Other logic gates that are derived from these basic gates are Page 71
1. NAND gate, Chap 2
Boolean Algebra and
2. NOR gate, Logic Simplification
3. EXCLUSIVE-OR gate,
4. EXCLUSIVE-NOR gate
AND Gate
An AND gate is a logic circuit with two or more inputs and one output
that performs ANDing operation. The output of an AND gate is HIGH
only when all of its inputs are in the HIGH state. In all other cases, the
output is LOW. For a positive logic systems, it means that the output
i. n
of the AND gate is a logic 1 only when all of its inputs are in logic 1
state. In all other cases, the output is logic 0. The logic symbol and
the truth table of a two-input AND gate are shown in Figure 2.3 and
Table 2.6 respectively.
. c o
i a
o d
n
Figure 2.3: Logic Symbol of Two-input AND gate
w.
Table 2.6: Truth table of a 2-input AND gate
w w
A
0
Input
B
0
Output
Y = AB
0
0 1 0
1 0 0
1 1 1
OR Gate
An OR gate is a logic circuit with two or more inputs and one output
that performs ORing operation. The output of an OR gate is LOW
only when all of its inputs are LOW. For all other possible input
combinations, the output is HIGH. For a positive logic system, the
output of an OR gate is a logic 0 only when all of its inputs are at
logic 0. For all other possible input combinations, the output is a logic
1. The logic symbol and the truth table of a two-input OR gate are
shown in Figure 2.4 and Table 2.7 respectively.
Figure 2.4: Logic Symbol of Two-input OR gate

Page 72 Table 2.7: Truth table of a 2-input OR gate

Chap 2
Boolean Algebra and Input Output
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate
A NOT gate, also called an inverter is a one-input, one-output logic
circuit whose output is always the complement of the input. That is,
a LOW input produces a HIGH output, and vice versa. It means that
for a positive logic system, a logic 0 at the input produces a logic 1
at the output, while a logic 1 at the input produces a logic 0 output.
. in
It is also known as a complementing circuit or an inverting circuit. The
logic symbol and the truth table of an inverter are shown in Figure 2.5
and Table 2.8 respectively.
. c o
d
Figure 2.5: Symbol for a NOT gate ia
n o
Table 2.8: Truth Table of NOT Gate
w.Input Output
w w A
0
1
Y=A
1
0
NAND Gate
The term NAND implies NOT-AND. A NAND gate is equivalent to
AND gate followed by a NOT gate. The standard logic symbol for a
2-input NAND gate is shown in Figure 2.6. This symbol is same as
AND gate symbol except for a small circle (bubble) on its output. This
circle represents the NOT function.
Figure 2.6: Logic symbol of NAND gate
The truth Table 2.9 of a NAND gate is obtained from the truth
Table of an AND gate by complementing the output entries. The
output of a NAND gate is a logic 0 when all its inputs are a logic 1.

For all other input combinations, the output is a logic 1. NAND gate Page 73
operation is logically expressed as Chap 2
Boolean Algebra and
Y = A:B
Table 2.9: Truth Table of a 2-input NAND Gate
Input Output
A B Y = AB
0 0 1
0 1 1
1 0 1
1 1 0
i. n
NOR Gate
. c o
The term NOR implies NOT-OR. A NOR gate is equivalent to OR
i a
gate followed by a NOT gate. The standard logic symbol for a 2-input
NOR gate is shown in Figure 2.7. This symbol is same as OR gate
o
represents the NOT function. d
symbol except for a small circle (bubble) on its output. This circle
. n
w w
Figure 2.7: Logic symbol of NOR gate
w The truth Table 2.10 of a NOR gate is obtained from the truth
Table of an OR gate by complementing the output entries. The output
of a NOR gate is a logic 1 when all its inputs are logic 0. For all other
input combinations, the output is a logic 0. The output of a two-input
NOR gate is logically expressed as
Y = A+B
Table 2.10: Truth table of a 2-input NOR gate
Input Output
A B Y = A+B
0 0 1
0 1 0
1 0 0
1 1 0
Exclusive-OR (XOR) Gate

The Exclusive-OR gate, commonly known as EX-OR gate, is a two-
input, one-output gate. The logic symbol for the Ex-OR gate is shown
in Figure 2.8 and the truth table for a two-input EX-OR operation is
given in Table 2.11.

Page 74
Chap 2
Boolean Algebra and
Figure 2.8: Symbol for 2-input Ex-OR Gate
Table 2.11: Truth Table of a 2-input Ex-OR Gate
Input Output
A B Y = A5B
0 0 0
0 1 1
1 0 1
1 1 0
in
From the truth table it can be stated that, the output of an EX-
logic 0 when the two inputs are at the same logic.
o .
OR gate is a logic 1 when the two inputs are at different logic and a
NOTE :
1.
. c
The exclusive-OR and equivalence gates both can be extended to more than
ia
two inputs. However, multiple-input exclusive OR gates are uncommon from
the hardware standpoint.
2.
d
For a multiple output-input EX-OR logic function we can conclude that the
output of a multiple-input EX-OR logic function is a logic 1 only when an
o
odd number of input variables are 1.
. n
Exclusive-NOR (XNOR) Gate
w w
The exclusive-NOR gate, commonly known as Ex-NOR, is an Ex-OR
gate, followed by an inverter. It has two inputs and one output. The
wlogic symbol for the Ex-NOR gate is shown in Figure 2.9, and the truth
table for the two-input Ex-NOR operation is given in Table 2.12.
Figure 2.9: Symbol for 2-input Ex-NOR Gate
Table 2.12: Truth Table of a 2-input Ex-NOR Gate
Input Output
A B Y = A9B
0 0 1
0 1 0
1 0 0
1 1 1

The Boolean expression for the Ex-NOR gate is Y = A 5 B . Using Page 75

DeMorgans theorem, Chap 2
Boolean Algebra and
A 5 B = AB + AB = AB : AB Logic Simplification
= (A + B ) (A + B) = AB + A B
The output of a two-input EX-NOR gate is a logic 1 when the
inputs are same and a logic 0 when they are different.
NOTE :
1. Likewise Ex-OR gates, three or more variable Ex-NOR gates also do not exist.
Normally, multiple-input EX-NOR logic functions can be implemented using
more than one 2-input Ex-NOR gates.
2. For a multiple output-input EX-NOR logic function we can conclude that the
i. n
output of a multiple-input EX-NOR logic function is a logic 1 only when
an even number of input variables are 0. Note if all inputs are 0, then also
output will be 1.
2.7 UNIVERSAL GATE

. c o
i a
d
NAND and NOR gates are known as universal gates because any of
these two gates is capable of implementing all other gate functions.
o
2.7.1
. n
NAND Gate as a Universal Gate
w
The NAND gate can be used to implement the NOT function, AND
function, the OR function and other functions also as explained below.
w
The NOT Gate using NAND Gate
w An inverter can be made from a NAND gate by connecting all of the

inputs together and creating, in effect, a single common input, as shown
in Figure 2.10, for a two-input NAND gate. Algebraically, we may write
Y = A:B = A:A = A
Figure 2.10: NOT gate using NAND gate
The AND Gate Using NAND Gate

To construct an AND gate from NAND gates, an inverter or a NOT
gate is required to invert the output of a NAND gate. This inversion
cancels out the first inverted operation of NAND gate and the final
result will be AND function as depicted in Figure 2.11. Algebraically,
Y = AB = AB
Figure 2.11: AND Gate using NAND Gate

Page 76 The OR Gate using NAND Gate

Chap 2
To construct OR function using only NAND gates, first we transform
Boolean Algebra and
Logic Simplification the OR function as follows.
Y = A+B = A+B A=A
= A:B (De Morgans Theorem)
The above equation is implemented using only NAND gates as
shown in the Figure 2.12.
Figure 2.12: OR Gate using NAND Gate
. in
The NOR Gate Using NAND Gate
. c
We know that Boolean expression for NOR gate iso
ia
Y = A+B = A:B (De Morgans Theorem)
d
= A:B A=A
The above equation is implemented using only NAND gates, as
o
. n
w w
w
Figure 2.13: NOR Gate Using NAND Gate
The Ex-OR Gate using NAND Gate

The Boolean expression for Ex-OR gate is given by
Y = AB + AB
= AB + AB X=X

Page 77
= _AB i : _AB i (De Morgan Theorem)
Chap 2
So, five NAND gates are required to implement the Ex-OR gate
Boolean Algebra and
as shown in Figure 2.14. Logic Simplification
Figure 2.14: Ex-OR Gate using NAND Gate

i. n
Ex-NOR Gate Using NAND Gate
. c o
Ex-NOR gate can be constructed by taking complement of Ex-OR. That
i a
is, we need one more NAND gate to implement the Ex-NOR function.
Figure 2.15 shows Ex-NOR implementation using five NAND gates.
o d
. n
w w
w Figure 2.15: Ex-NOR Gate Using NAND Gate
2.7.2 NOR Gate as a Universal Gate

Just like the NAND gate, the NOR gate also may be used to implement
all other operations of Boolean algebra. These are explained in following
texts.
NOT Gate Using NOR Gate
In the same way as the NAND gate described above, an inverter can
be made from a NOR gate by connecting all of the inputs together and
creating, in effect, a single common input, as shown in Figure 2.16.
Algebraically,
Y = A+B = A+A = A
Figure 2.16: NOT Gate Using NOR Gate

Page 78 OR Gate Using NOR Gate

Chap 2
An OR gate can be created by simply inverting the output of a NOR
Boolean Algebra and
Logic Simplification gate as shown in Figure 2.17. Algebraically,
Y = A+B = A+B
Figure 2.17: AND Gate Using NOR Gate
AND Gate using NOR Gate

AND function can be generated using three NOR gates. We know that
Boolean expression for AND gate is
Y = A:B
in
= A:B A=A
= A+B
.
(DeMorgans Theorem)
o
The above equation is implemented using only NOR gates as
NAND Gate using NOR Gate
. c
d
Y = A:B ia
The Boolean expression for NAND gate is
n o
= A+B (DeMorgans Theorem)
. = A+B A=A
The above equation is implemented using only NOR gates, as
w
w w
Figure 2.18: AND Gate Using NOR Gate
Figure 2.19: NAND gate using NOR gate

The Ex-OR Gate using NOR Gate Page 79

Chap 2
XOR function may also be implemented by using NOR gates. The Ex-
Boolean Algebra and
OR operation is given by, Logic Simplification
Y = AB + BA
= AA + AB + BA + BB _AA = BB = 0i
= A _A + B i + B _A + B i = A _A + B i + B _A + B i
= _A + A + B i + _B + A + B i
= _A + A + B i + _B + A + B i _X = X i
The above expression can be realized using five NOR gates as
shown in Figure 2.20.
i. n
. c o
i a
o d
. n
Figure 2.20: Ex-OR Gate Using NOR Gate
w w
The Ex-NOR Gate using NOR Gate
To implement Ex-NOR gate using NOR gates, we just remove the last
w NOR gates from the circuit of Ex-OR gates shown in Figure 2.21.
Figure 2.21: Ex-NOR Gate using NOR Gate
2.8 ALTERNATE LOGIC-GATE REPRESENTATIONS
We have discussed the five basic logic gates (AND, OR, INVERTER,
NAND, and NOR) and the standard symbols used to represent them
in a logic circuit diagram. Most of the logic networks use standard
symbols. But in some networks an alternative set of symbols is used in
addition to the standard symbols. Table 2.13 shows the alternate set of
symbols for the five basic gates.

Page 80 Table 2.13: Alternate Logic Gate Representations

Chap 2
Boolean Algebra and Logic Normal Symbol Alternate symbol
NOT
AND
OR
NAND
NOR
. in
To convert any normal symbol to its corresponding alternate
symbol, the following steps are used:
. c o
ia
METHODOLOGY: TO CONVERT STANDARD SYMBOL TO ALTERNATE
SYMBOL
Step 1:
d
Add bubbles (indication of inversion) at those input or
o
output points where it is not present.
Step 2:
. n Remove all pre-existing bubbles of the normal symbol, if

there is any at the point (only NOT, NAND and NOR
w w
Step 3:
gates)
If the existing normal logic symbol is AND, change it to
OR, Similarly, if it is OR, then change it to AND. There
w is no change for the triangular symbol of NOT gate.
2.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS
A Boolean function may be transformed from an algebraic expression

into a logic diagram using AND, OR and NOT gates. This is also
referred to as AOI logic. Conversely, a logic circuit can be transformed
into Boolean expressions for the analysis.
2.9.1 Converting Boolean Expressions to Logic Diagram

The simplest way to convert a Boolean expression to a logic circuit
is to start with the output and work towards the input. Assume that
the expression Y = AB + AC + ABC is to be realized using AOI logic.
Start with the final expression AB + AC + ABC , we go through
following steps:

Page 81
METHODOLOGY: TO CONVERT BOOLEAN EXPRESSION TO LOGIC
DIAGRAM Chap 2
Boolean Algebra and
Step 1: The expression Y = AB + AC + ABC contains three Logic Simplification
terms (AB , AC , ABC ) which are ORed together. So,
draw an OR gate with three inputs as shown below.
Step 2: AB must be the output of an AND gate whose inputs are
i. n
A and B and AC must be output of an AND gate whose
inputs are A and C . Similarly, ABC must be output of a
3-input AND gate with inputs A , B and C . We introduce
. c o
these three AND gates as shown below.
i a
o d
. n
w w
w Step 3: Now, C must be the output of an inverter whose input is
C and similarly, A will be the output of an inverter whose
input is A. So we put two inverters as shown below.
This is the complete logic diagram of given function
2.9.2 Converting Logic to Boolean Expressions

Any logic circuit, no matter how complex it is, can be described using
Boolean expressions. To derive the Boolean expression for a given
logic circuit, start from the left-most input and work toward the final
output, writing output for each gate. As an example, consider the logic

Page 82 diagram shown in Figure 2.22. We go through the following steps to get
Chap 2 the Boolean expression.
Boolean Algebra and
Figure 2.22: Logic diagram for which Boolean expression to be determined

METHODOLOGY: TO CONVERT LOGIC DIAGRAM TO BOOLEAN
EXPRESSION
Step 1: In the logic diagram shown in Figure 2.22, the output of

left-most OR gate with inputs A and B is _A + B i .
in
Step 2: The output of left-most AND gate with inputs C and D
is CD .
Step 3:
.
The outputs of the OR gate and AND gate are the inputs
o
of right-most AND gate. Therefore, the expression for
. c
this AND gate is _A + B i : CD , which is the final output
expression for the entire circuit.
d ia
2.10
o
CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC
n
w.
Since, NAND logic and NOR logic are universal logic system, digital
circuits which are first computed and converted to AOI logic may then
w w
be converted to either NAND logic or NOR logic depending on the
choice.
2.10.1 NAND-NAND Logic

A logic network can be converted into NAND-NAND gate network by
going through following steps:
METHODOLOGY: TO OBTAIN NAND-NAND GATE NETWORK
Step 1: First draw the circuit in AOI logic i.e., using AND, OR
and NOT gates.
Step 2: Add a circle (bubble) at the output of each AND gate and
at the inputs to all the OR gates.
Step 3: Add an inverter on each line that received only one circle
in steps 2, so that the polarity of signals on those lines
remains unchanged from that of the original diagram.
Step 4: Replace bubbled OR by NAND and each inverter by its
NAND equivalent.

2.10.2 NOR-NOR Logic Page 83

Chap 2
The procedure of converting an AOI logic to NOR-NOR logic is same Boolean Algebra and
as above except steps 2 and 4. Logic Simplification
METHODOLOGY: TO OBTAIN NOR-NOR GATE NETWORK
Step 1: First draw the circuit in AOI logic i.e., using AND, OR
and NOT gates.
Step 2: Add a circle (bubble) at the output of each OR gate and
at the inputs to all the AND gates.
Step 3:
i. n
Add an inverter on each line that received only one circle
in steps 2, so that the polarity of signals on those lines
Step 4: o
remains unchanged from that of the original diagram.
c
Replace bubbled AND by NOR and each inverter by its
NOR equivalent.
.
i a
o d
***********
. n
w w
w

Page 84
Chap 2
Boolean Algebra and
EXERCISE 2.1
MCQ 2.1.1 In the following circuit the output Z is
(A) (A + B ) (C + D ) (E + F)
(B) AB + CD + EF
. in
(C) (A + B) (C + D) (E + F)
(D) AB + CD + EF
. c o
d ia
MCQ 2.1.2
o
In the following circuit, the output X is
n
w.
w w
(A) MNQ (B) N (Q + M )
(C) M (Q + N ) (D) Q (M + N )
MCQ 2.1.3 In the following circuit, the output Z is
(A) AB + (C + D) E (B) AB (C + D) E
(C) AB + CD + E (D) AB + CDE

MCQ 2.1.4 The Boolean expression (X + Y) (X + Y ) (X + Y) is equivalent to Page 85

(A) XY (B) XY Chap 2
Boolean Algebra and
(C) XY (D) XY Logic Simplification
MCQ 2.1.5 In the following circuit, the output Z is
i. n
(A) A + B + C
. c o
(B) ABC
(C) AB + BC + AC
i a (D) Above all
o d
MCQ 2.1.6
.
is equivalent to
n
Given that AB + AC + BC = AB + AC , then (A + C ) (B + C ) (A + B)
w
(A) (A + B ) (A + C )
(C) (A + B ) (A + C )
w
(B) (A + B) (A + C )
(D) (A + B ) (A + C )
MCQ 2.1.7
w In the following circuit the output X is
(A) AB (B) AB
(C) AB (D) 0
MCQ 2.1.8 In the following circuit the output Y is
(A) AB + AB + C (B) AB + AB + C
(C) AB + AB + C (D) AB + AB + C

Page 86 MCQ 2.1.9 In the following circuit the output Z is

Chap 2
Boolean Algebra and
(A) ABC (B) ABC

(C) ABC (D) 0
(A) ABC
. in
(B) AB (C + B)
(C) ABC
. c o
(D) AB (C + B)
MCQ 2.1.11
d ia
In the following circuit the output Z is
n o
w.
w
(A) ABC
(C) 0
w (B) ABC
(D) ABC
MCQ 2.1.12 The truth table of a circuit is shown below.
A B C X
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
The expression for X is

(A) AB + BC + AC + BC (B) BC + ABC
(C) BC (D) ABC

MCQ 2.1.13 A + BC is equivalent to Page 87

(A) (A + B) (A + C ) (B) A + B Chap 2
Boolean Algebra and
(C) A + C (D) (A + B ) (A + C ) Logic Simplification
MCQ 2.1.14 The truth table of a circuit is shown below.
A B C Z
0 0 0 1
0 0 1 0
0
0
1
1
0
1
1
1
i. n
1
1
0
0
0
1
1
1
. c o
i
The Boolean expression for Z is
a
(A) (A + B ) (B + C )
(C) (A + B) (B + C )
o d (B) (A + B ) (B + C )
(D) Above all
. n
MCQ 2.1.15
A
w
The Boolean expression for the truth table shown is
w B C f
w 0
0
0
0
0
1
0
0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
(A) B (A + C) (A + C ) (B) B (A + C ) (A + C )
(C) B (A + C ) (A + C ) (D) B (A + C ) (A + C )
MCQ 2.1.16 The Boolean expression AC + BC is equivalent to

(A) AC + BC + AC
(B) BC + AC + BC + ACB
(C) AC + BC + BC + ABC
(D) ABC + ABC + ABC + ABC

Page 88 MCQ 2.1.17 Expression A + AB + A BC + ABC D + A B C DE would be simplified

Chap 2 to
Boolean Algebra and (A) A + AB + CD + E
(B) A + B + CDE
(C) A + BC + CD + DE
(D) A + B + C + D + E
MCQ 2.1.18 The simplified form of a logic function Y = A (B + C (AB + AC )) is

(A) A B (B) AB
(C) AB (D) AB
MCQ 2.1.19 The reduced form of the Boolean expression of Y = (AB ) : (AB ) is
(A) A + B
(B) A + B
. in
(C) AB + AB
(D) A B + AB
. c o
MCQ 2.1.20
d ia
If XY + XY = Z then XZ + X Z is equal to
(A) Y
n o (B) Y
(C) 0
w. (D) 1
MCQ 2.1.21
w w
If XY = 0 then X 5 Y is equal to
(A) X + Y (B) X + Y
(C) XY (D) XY
MCQ 2.1.22 If A = 0 in logic expression Z = [A + EF + BC + D] [A + DE + BC + DE ]

, then
(A) Z = 0 (B) Z = 1
(C) Z = BC (D) Z = BC
MCQ 2.1.23 From a four-input OR gate the number of input condition, that will
produce HIGH output are
(A) 1 (B) 3
(C) 15 (D) 0

MCQ 2.1.24 In the following circuit, for which of the following input combination Page 89
output will be 1 ? Chap 2
Boolean Algebra and
(A) A = 0, B = 0
(B) A = 1, B = 0
(C) A = 0, B = 1
i. n
(D) Either A = 1 or B = 1
MCQ 2.1.25
. c o
A logic circuit control the passage of a signal according to the following
requirements:
i a
1. Output X will equal A when control input B and C are the same.
2.
d
X will remain HIGH when B and C are different.
o
The logic circuit would be
. n
w w
w
MCQ 2.1.26 The output of logic circuit is HIGH whenever A and B are both HIGH
as long as C and D are either both LOW or both HIGH. The logic
circuit is

Page 90 MCQ 2.1.27 Consider the statements below.

Chap 2 1. If the output waveform from an OR gate is the same as the
Boolean Algebra and waveform at one of its inputs, the other input is being held
permanently LOW.
2. If the output waveform from an OR gate is always HIGH, one of
its input is being held permanently HIGH.
The statement, which is always true, is
(A) Both 1 and 2
(B) Only 1
(C) 2
(D) None of the above
Common Data For Q. 28 and 29 :

A Boolean function Z = ABC is to be implemented using NAND and
in
NOR gate. Each gate has unit cost. Only A, B , and C are available.
o .
MCQ 2.1.28
. c
If both gates are available then minimum cost is
ia
(A) 2 units (B) 3 units
(C) 4 units (D) 6 units
od
MCQ 2.1.29
. n
If only NAND gates are available, then minimum cost is
(A) 2 units (B) 3 units
w w
(C) 4 units (D) 6 units
MCQ 2.1.30
wIn the circuit shown below the LED emits light when
(A) both switches are closed

(B) both switches are open
(C) only one switch is closed
(D) LED does not emit light irrespective of the switch positions

MCQ 2.1.31 If the input to the digital circuit shown below consisting of a cascade of Page 91
20 XOR gates is X , then the output Y is equal to Chap 2
Boolean Algebra and
(A) X (B) X
(C) 0 (D) 1
MCQ 2.1.32 In the network shown below F can be written as

i. n
. c o
i a
o d
(A) X0 X1 X3 X5 + X2 X4 X5 ...Xn - 1 + ...Xn - 1 Xn
(B) X0 X1 X3 X5 + X2 X3 X4 ...Xn + ...Xn - 1 Xn
. n
(C) X0 X1 X3 X5 ...Xn + X2 X3 X5 ...Xn + ... + Xn - 1 Xn
w
(D) X0 X1 X3 X5 ...Xn - 1 + X2 X3 X5 ...Xn + ... + Xn - 1 Xn - 2 + Xn
w
w
MCQ 2.1.33 The gate G1 and G2 in figure shown below have propagation delays of
10 ns and 20 ns respectively.
If the input Vi makes an abrupt change from logic 0 to 1 at t = t0 then

the output waveform Vo is
[t1 = t0 + 10 ns, t2 = t1 + 10 ns, t3 = t2 + 10 ns]

Page 92 MCQ 2.1.34 Which of the following Boolean expressions correctly represents the
Chap 2 relation between P, Q, R and M1
Boolean Algebra and
(A) M1 = (P OR Q) XOR R (B) M1 = (P AND Q) XOR R

(C) M1 = (P NOR Q) XOR R (D) M1 = (P XOR Q) XOR R
MCQ 2.1.35 If the X and Y logic inputs are available and their complements X
in
and Y are not available, the minimum number of two-input NAND
required to implement X 5 Y is
(A) 4 (B) 5
o .
c
(C) 6 (D) 7
ia .
MCQ 2.1.36
d
In the negative logic system,
(A) The more negative of the two logic levels represents a logic 1
state
o
. n
(B) The more negative of the two logic levels represents a logic 0
w w
state
(C) All input and output voltage levels are negative
(D) The output is always complement of the intended logic function
w
MCQ 2.1.37 Positive logic in a logic circuit is one in which
IES EE 1992 (A) logic 0 and 1 are represented by 0 and positive voltage respectively
(B) logic 0 and 1 are represented by negative and positive voltages
respectively
(C) logic 0 voltage level is higher than logic 1 voltage level
(D) logic 0 voltage level is lower than logic 1 voltage level
MCQ 2.1.38 How is inversion achieved using Ex-OR gate ?

IES EC 2002 (A) Giving input signal to the two input lines of the gate tied together
(B) Giving input to one input line and logic zero to the other line
(C) Giving input to one input line and logic one to the other line
(D) Inversion cannot be achieved using Ex-OR gate

MCQ 2.1.39 Match List-I with List-II and select the correct answer using the codes Page 93
given below the lists. Chap 2
Boolean Algebra and
List - I List - II
a. A5B = 0 1. A=
YB
b. A+B = 0 2. A=B
c. A:B = 0 3. A = 1 or B = 1
d. A5B = 1 4. A = 1 or B = 0
i. n
Codes :
a b c d
(A) 3 2 1 4
(B)
(C)
2
3
3
2
4
4
1
1
. c o
(D) 2 3 1 4
i a
MCQ 2.1.40
o d
Consider the following statements:
IES EE 1999
. n
(1) A NAND gate is equivalent to an OR gate with its inputs inverted.
(2) A NOR gate is equivalent to an AND gate with its inputs inverted.
w w
(3) A NAND gate is equivalent to an OR gate with its output inverted.
(4) A NOR gate is equivalent to an AND gate with its output inverted.
w
Which of these statements are correct?
(A) 1 and 2 (B) 2 and 3
(C) 3 and 4 (D) 1 and 4
MCQ 2.1.41 The output (X ) waveform for the combination circuit shown below for
the inputs at A and B (waveform shown in the figure) will be

Page 94
Chap 2
Boolean Algebra and
. in
. c o
MCQ 2.1.42
d ia
Which of the following represents the correct waveform for X in the
given circuit diagram.
n o
w.
w w

MCQ 2.1.43 A logic circuit and input waveform to it shown below. Page 95
Chap 2
Boolean Algebra and
i. n
The output waveform is represented by
. c o
i a
o d
. n
w w
w
MCQ 2.1.44 In a natural food restaurant, fruit is offered for desert but only in
certain combination. One choice is either orange or apple or both.
Another choice is either mango and apple or neither. A third choice
is orange, but if you choose orange, then you must also take banana.
If the fruits are represented by their first alphabet of the name, then
the logical expression that specifies the fruit available for desert in the
simplified form is
(A) A + B (B) M + O
(C) A + O (D) M + B
MCQ 2.1.45 The open collector wired circuit shown below functions as
(A) Ex-NOR (B) AND

(C) Ex-OR (D) NOR

Page 96 MCQ 2.1.46 The simplified form of the expression (w + x) (w l + x + yz l ) (w + y l ) is

Chap 2 (A) w l xy l + wx l + w l yz (B) w l xy l + wx
Boolean Algebra and
(C) xy l + wx + wyz l (D) xy l + wx + w l yz
MCQ 2.1.47 The elevator door should open if the elevator is stopped, it is level with
the floor, and the timer has not expired, or if the elevator is stopped,
it is level with the floor, and a button is pressed. If
D " Elevator door opens ; S " Elevator is stopped ;
F " Level with floor ; T " Timer expired ; B " Button pressed
Which of the following Boolean expression represents the above
condition ?
(A) D = SFT l + SFB (B) D = SFT l B
(C) D = SF + T l B (D) D = (S + F ) T l B
MCQ 2.1.48
. in
The logic circuit shown in the given figure can be minimized to
. c o
d ia
n o
w.
w w
(A) AD (B + C ) + A D (B) AD (B 5 C ) + A D
(C) AD (B 5 C ) + A D (D) A D (B 5 C ) + AD

MCQ 2.1.50 What does the expression AD + ABCD + ACD + AB + AC D + A B on Page 97

minimization result into ? Chap 2
(A) A + D Boolean Algebra and
(B) AD + A
(C) AD
(D) A + D
MCQ 2.1.51 Which one of the following logical operations is performed by the digital
circuit shown below ?
i. n
. c o
i a
(A) NOR
o d (B) NAND
.
(C) Ex-OR
n (D) OR
MCQ 2.1.52
w w
The switching circuit given in the figure an be expressed in binary logic
IES EE 1995
w notation as
(A) L = (A + B) (C + D) E
(B) L = AB + CD + E
(C) L = E + (A + B) (C + D)
(D) L = (AB + CD) E
MCQ 2.1.53 Which of the following statements is not correct ?

IES EE 2005 (A) X + XY = X
(B) X (X + Y) = XY
(C) X + XY = X
(D) ZX + ZXY = ZX + ZY

Page 98 MCQ 2.1.54 Consider the given circuit diagram of switching of light from two
Chap 2 different switches.
Boolean Algebra and
The input conditions needed to turn on LED is

(A) A = B = 1 (B) A = B = 0
(C) A = 1; B = 0 (D) Both (A) and (B)
. in
MCQ 2.1.55
IES EC 1996
c o
Which one of the following is the dual-form of the Boolean identity
given below ?
.
ia
AB + AC = (A + C) (A + B)
(A) AB + AC = AC + AB
d
(B) (A + B) + (A + C) = (A + C) (A + B)
o
. n
(C) (A + B) (A + C) = AC + AB
(D) AB + AC = AB + AC + BC
w w
MCQ 2.1.56
w
What is dual of A + [B + (AC )] + D ?
(A) A + [B (A + C)] + D
(C) A + [B _A + C i] D
(B) A 7B + AC A D
(D) A [B _A + C i] D
MCQ 2.1.57 If x and y are Boolean variables, which one of the following is the
IES EE 2004 equivalent of x 5 y 5 xy ?
(A) x + y (B) x + y
(C) 0 (D) 1
MCQ 2.1.58 The minimized form of _X + W i_Y 5 Z i + XW l is

(A) (X + W ) (YZ l + Y l Z ) + XW l
(B) (XYZ l + XY l Z + WYZ l + WY l Z )
(C) WYZ l + WY l Z + XW l
(D) WYZ l + WY l Z

MCQ 2.1.59 Which of the following logic diagrams represents the original and Page 99
simplified expression of the function, F = (x + y) (x + y l ) ? Chap 2
Boolean Algebra and
i. n
. c o
i a
o d
. n
w w
MCQ 2.1.60
IES EC 1992
w A copy machine generate a stop sign S , to stop the machine operation
and energize and indicates light if according to either of the following
conditions exists:
(1) There is no paper in the paper feeder tray.
(2) The two micro switch in the paper path are activated, indicating
a jam in the paper path.
The presence of paper in the feeder tray is indicated by a high at logic
signal P as shown in figure.

Page 100 Which of the following represents the correct logic circuit so as to get
Chap 2 HIGH output at S ?
Boolean Algebra and
MCQ 2.1.61 In the following circuit, the motor will turn on when DRIVE = 1
. in
. c o
d ia
n o
w.
Which of the following give correct values of A0, A1, A2, A3, A4, A5, A6,
w w
A7, A8 , and A9 in order to move motor ?
(A) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = A9 = 1
(B) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A9 = 1; A7 = A8 = 0;
(C) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = 1 ; A8 = A9 = 0
(D) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = 1 ; A9 = 0
MCQ 2.1.62 When two gates with open collector outputs are tied together as shown
in the figure, the output obtained will be
(A) A + B + C + D (B) A + B + C + D
(C) (A + B ) + (C + D ) (D) (A + B) + (C + D)

MCQ 2.1.63 The output of a two level AND-OR gate network is F . What is the Page 101
output when all the gates are replaced by NOR gates ? Chap 2
(A) F Boolean Algebra and
(B) F
(C) F D
D
(D) F
where F D is the dual function of F
Which one of the gates labelled 1,2,3, and 4 in the network shown in
the figure is redundant ?
i. n
. c o
i a
(A) 1
o d
n
(B) 2
(C) 3
(D) 4
w.
MCQ 2.1.64
w w
For the circuit shown in Figure, the Boolean expression for the output
GATE EE 2002 Y in terms of inputs P , Q , R , and S is
(A) P + Q + R + S
(B) P + Q + R + S
(C) (P + Q ) (R + S )
(D) (P + Q) (R + S)
MCQ 2.1.65 Which of the following circuit implement the Boolean expression
X = AB + CD ?

Page 102
Chap 2
Boolean Algebra and
. in
. c o
d ia
n o
w.
w w
(D) None of the above.
MCQ 2.1.66 Consider the logic circuit shown below.
Using NOR gates only, the circuit can be realised as

Page 103
Chap 2
Boolean Algebra and
i. n
. c o
i a
o d
. n
w w
w
MCQ 2.1.67 Which of the following represent the correct realization of the given
circuit using NAND gate only ?

Page 104
Chap 2
Boolean Algebra and
. in
. c o
d ia
n o
MCQ 2.1.68
.
The logic operations of two combinational circuits given in Figure - I
and Figure - II are
w
w w
(A) Entirely different (B) Identical
(C) Complementary (D) Dual
***********

EXERCISE 2.2 Page 105

Chap 2
Boolean Algebra and
QUES 2.2.1 The minimum number of NAND gates required to implement the
IES EC 2003 Boolean function A + AB + ABC is _____
QUES 2.2.2
i. n
The Boolean expression Y (A, B, C ) = A + BC is to be realized using
IES EC 2006
for the realization is _____
. c o
2-input gates of only one type. The minimum number of gates required
i a
QUES 2.2.3
d
The number of different sets of input conditions that produces a high
o
output from a five-input OR gate is _____
. n
QUES 2.2.4
w w
A Boolean function of two variables X and Y is defined as follows :
F (0, 0) = F (0, 1) = F (1, 1) = 1; F (1, 0) = 0
Assuming complements of X and Y are not available, a minimum cost
w solution for realizing F using 2-input NOR gates and 2-input OR gates
(each having unit cost) would have a total cost of _____ unit.
QUES 2.2.5 To implement Y = ABCD using only two-input NAND gates, minimum
number of requirement of NAND gates is _____
QUES 2.2.6 In circuit shown below, for what input at the terminal A the output
is X = 1 ?
QUES 2.2.7 If X = 1 in logic equation [A + Z {Y + (Z + XY )}][{X + Z (X + Y)} = 1

then Z is _____

Page 106 QUES 2.2.8 The minimum number of NOR gates required to implement
Chap 2 A (A + B ) (A + B + C ) is equal to ______
Boolean Algebra and
QUES 2.2.9 In the following circuit the output Z is _____
QUES 2.2.10 The number of distinct Boolean expressions of 4 variables is _____
QUES 2.2.11
. in
The number of duals of distinct Boolean expressions of 4 variables is
_____
. c o
QUES 2.2.12
d ia
To implement Y = ABCD using two-input NAND gates and NOR
gates, minimum number of requirement of gates is _____
n o
***********
w.
w w

EXERCISE 2.3 Page 107

Chap 2
Boolean Algebra and
MCQ 2.3.1 The NAND gate can perform the invert function if the inputs are
K (A) Connected together (B) Left open
SHASHIDHAR
(C) Either (A) or (B) (D) None of these
i. n
214/12
MCQ 2.3.2
K switches for the input ?
. c o
Which of the following gate corresponds to the action of parallel
SHASHIDHAR
214/13
(A) AND
(C) OR
i a
(B) NAND
(D) NOR
o d
MCQ 2.3.3
. n
Which of the following gate corresponds to the action of series switches
for the input ?
w
K
SHASHIDHAR (A) AND (B) NAND
w
214/14
(C) OR (D) NOR
MCQ 2.3.4
w Which of the following gate is called universal gate ?
K (A) AND (B) OR
SHASHIDHAR
214/15
(C) XOR (D) NAND
MCQ 2.3.5 In positive logic,

K (A) a HIGH = 1, a LOW = 0
SHASHIDHAR
214/16
(B) a LOW = 1, a HIGH = 0
(C) Only HIGHs are present
(D) Only LOWs are present
MCQ 2.3.6 The output of an AND gate is LOW

K (A) All the time
SHASHIDHAR
214/17
(B) When any input is LOW
(C) When any input is HIGH
(D) When all inputs are HIGH

Page 108 MCQ 2.3.7 The output of an OR gate is LOW when

Chap 2 K (A) All inputs are LOW
Boolean Algebra and SHASHIDHAR
Logic Simplification 214/18
(B) Any INPUT is LOW
(C) Any input is HIGH
(D) All inputs are HIGH
MCQ 2.3.8 If a three-input AND gate has eight input possibilities, how many of
K those possibilities will result in a HIGH output?
SHASHIDHAR (A) 1 (B) 2
214/19
(C) 7 (D) 8
MCQ 2.3.9 If a three-input OR gate has eight input possibilities, how many of
in
SHASHIDHAR
214/20
(A) 1
(C) 7
(B) 2
(D) 8
o .
. c
MCQ 2.3.10
K (A) the input is LOW
d ia
The output of NOT gate is HIGH when
SHASHIDHAR
214/21
(B) the input is HIGH
n o
.
(C) power is applied to the gates IC
(D) power is removed from the gates IC
w
MCQ 2.3.11
w w
The output of an AND gate with three inputs, A, B , and C , is HIGH
K when
SHASHIDHAR (A) A = 1, B = 1, C = 0
214/22
(B) A = 0 , B = 0 , C = 0
(C) A = 1, B = 1, C = 1
(D) A = 1, B = 0 , C = 1
MCQ 2.3.12 The output of an OR gate with three inputs, A, B, and C , is LOW
K when
SHASHIDHAR (A) A = 0 , B = 0 , C = 0
214/23
(B) A = 0 , B = 0 , C = 1
(C) A = 0 , B = 1, C = 1
(D) All of the above

MCQ 2.3.13 If a three-input NAND gate has eight input possibilities, how many of Page 109
K those possibilities will result in a HIGH output? Chap 2
SHASHIDHAR (A) 1 (B) 2 Boolean Algebra and
215/25 Logic Simplification
(C) 7 (D) 8
MCQ 2.3.14 If a three-input XOR gate has eight input possibilities, how many of
SHASHIDHAR (A) 2
215/27
(B) 4
(C) 6
(D) 8 i. n
. c o
MCQ 2.3.15
i a
A two-input NOR gate is equivalent to a
K
SHASHIDHAR
215/32
(A)
(B)
negative-OR gate
o
negative-AND gate d
(C)
(D)
. n
negative-NAND gate
none of the above
w w
K
w
MCQ 2.3.16
SHASHIDHAR
215/34
The exclusive-OR gates output is HIGH if
(A) All inputs are low
(B) all inputs are HIGH
(C) the inputs are different
(D) none of the above
MCQ 2.3.17 The exclusive-NOR gates output is HIGH if

K (A) the inputs are the same
SHASHIDHAR
216/35 (B) one input is High, and the other input is LOW
(C) the inputs are different
(D) none of the above
MCQ 2.3.18 How many two-input NOR gates does it take to produce a two-
K input NAND gate ?
SHASHIDHAR
216/38
(A) 1 (B) 2
(C) 3 (D) 4

Page 110 MCQ 2.3.19 Boolean algebra can be used to

Chap 2 V K PURI (A) Simplify any algebraic expressions
Boolean Algebra and 94/1
Logic Simplification (B) Minimize the number of switches in a circuits
(C) Solve the mathematical problems
(D) Perform arithmetic calculations.
MCQ 2.3.20 De Morgans theorems state that

V K PURI (A) A + B = A.B and A.B = A.B
.
(B) A + B = A + B and A B = A.B
95/13
.
(C) A + B = A.B and A B = A + B
(D) A + B = A + B and A.B = A + B
MCQ 2.3.21 The gate ideally suited for bit comparison is a

. in
V K PURI
95/16
(A) Two input Exclusive NOR gate
(B) Two input Exclusive OR gate
. c o
ia
(C) Two input NAND gate
(D) Two input NOR gate
od
MCQ 2.3.22
. n
A buffer is
B.R. GUPTA
73/521
w w
(A) always non-inverting
(B) always inverting
w(C) inverting or non-inverting

(D) none of above
MCQ 2.3.23 Symbol in figure given below is IEEE symbol for

B.R. GUPTA
83/522
(A) AND (B) OR

(C) NAND (D) NOR
MCQ 2.3.24 As per Boolean Algebra, inputs can be interchanged in

B.R. GUPTA (A) OR gates (B) AND gates
85/522
(C) both OR and AND gates (D) none of above

MCQ 2.3.25 In which function is each term known as minterm Page 111
B.R. GUPTA (A) SOP (B) POS Chap 2
94/522 Boolean Algebra and
(C) Hybrid (D) both SOP and POS Logic Simplification
MCQ 2.3.26 For a certain two-input logic gate, the output is 1 for like inputs and
MAINI 0 for unlike inputs. The logic gate is
1/102 (A) Ex-OR (B) NAND
(C) NOR (D) Ex-NOR
MCQ 2.3.27
i. n
In general, logic gates whose all output entries are logic 1 except for
MAINI
4/103
one entry that is logic 0 are
(A) AND, OR
(B) NAND, NOR
. c o
(C) NAND, OR
i a
(D) NOR, AND
o d
MCQ 2.3.28
. n
A logic gate with four inputs can have
MAINI
8/103
w w
(A) 16 possible input combinations
(B) 4 possible input combinations
w
(C) 8 possible input combinations
(D) None of these
MCQ 2.3.29 The dual of a Boolean expression is A + B . The expression is

MAINI (A) A : B (B) Al : B l
4/200
(C) Al + B l (D) A + B
MCQ 2.3.30 Complement of complement of Al : B + A : B l is

MAINI (A) A : B + Al : B l
5/200
(B) _Al + B i : _A + B li
(C) Al : B + A : B l
(D) None of these
MCQ 2.3.31 The operation A : A =

(A) A 2 (B) 2A
(C) 1 (D) A

Page 112 MCQ 2.3.32 The operation A + A =

Chap 2 Chakravorty (A) A 2 (B) 2A
Boolean Algebra and M4.10/111
(C) 0 (D) A
MCQ 2.3.33 The operation A + A =

Chakravorty (A) 1 (B) A
M4.11/111
(C) 0 (D) A
MCQ 2.3.34 The operation A : A =

Chakravorty (A) 1 (B) A
M4.12/111
(C) 0 (A) A
MCQ 2.3.35 The AND, OR, and NOT gates are called
. in
Chakravorty
M6.1/170
(A) universal gates
(B) basic gates
. c o
ia
(C) hexadecimal gates
(D) decimal number gates
od
MCQ 2.3.36
. n
The gate shown in Fig. is an alternative symbol of
Chakravorty
M6.6/171
w w
w(A) AND gate (B) OR gate
(C) NAND gate (D) NOR gate
MCQ 2.3.37 The gate shown in Fig. is an alternative symbol of

Chakravorty
M6.7/171
(A) AND gate

(B) OR gate
(C) NAND gate
(D) NOR gate

MCQ 2.3.38 The gate shown in below is an alternative symbol of Page 113
Chakravorty Chap 2
M6.8/171 Boolean Algebra and
(A) AND gate (B) OR gate

(C) NAND gate (D) NOR gate
MCQ 2.3.39 The gate shown below is an alternative symbol of
i. n
Chakravorty
M6.9/171
(A) AND gate

. c o
(B) OR gate
i a
(C) NAND gate
(D) NOR gate
o d
. n
MCQ 2.3.40
MANDAL
1/72
w
In a positive logic circuit,
w
(A) Logic 0 and 1 represented 0 V (ground) and positive voltage
_+ VCC i respectively
w (B) Logic 0 and 1 represented by negative and positive voltages

respectively
(C) Logic 0 voltage level is higher than logic 1 voltage level
(D) Logic 0 voltage level is lower than logic 1 voltage level
MCQ 2.3.41 In negative logic, the logic 1 state corresponds to

MANDAL (A) Ground level
2/72
(B) High voltage level
(C) Negative voltage level
(D) Low voltage level
MCQ 2.3.42 A NAND gate is called a universal logic element because

MANDAL (A) All digital computers use NAND gates
3/72
(B) All the minimisation techniques are applicable for optimum NAND
gate realisation
(C) Every body use this gate
(D) Any logic function can be realised by NAND gates alone

Page 114 MCQ 2.3.43 Boolean algebra is different from ordinary algebra in which way ?
Chap 2 MANDAL (A) Boolean algebra can represent more than 1 discrete level between
Boolean Algebra and 17/73 0 and 1.
(B) Boolean algebra have only 2 discrete levels : 0 and 1
(C) Boolean algebra can describe up to levels of logic levels
(D) They are actually the same
MCQ 2.3.44 The voltage levels for positive logic system

ANAND KU- (A) must necessarily be positive
MAR
10/21
(B) must necessarily be negative
(C) may be positive or negative
(D) must necessarily be 0 V and 5 V
MCQ 2.3.45
. in
Knowledge of binary number system is required for the designers of
ANAND KU-
MAR
1/65
computers and other digital systems because
c
(A) it is easy to learn binary number system
.
(B) it is easy to learn Boolean algebra
o
d ia
(C) it is easy to use binary codes
(D) the devices used in these systems operate in binary
n o
MCQ 2.3.46
w.
Which of the following statements is true ?
(A) OR and NOT gates are necessary and sufficient for realization of
w
ANAND KU-
MAR any logic function.
w
51/136
(B) AND and NOT gates are necessary and sufficient for realization of
any logic function.
(C) NAND gates are not sufficient to realize any logic function.
(D) NOR gates are sufficient to realize any logic function.
MCQ 2.3.47 For the gate shown in the figure, the output will be HIGH
(A) if and only if both inputs are HIGH

(B) if and only if both the inputs are LOW
(C) if one of the inputs is LOW
(D) if one of the inputs is HIGH

MCQ 2.3.48 In a digital computer binary subtraction is performed Page 115

ANAND KU- (A) in the same way as we perform subtraction in decimal number Chap 2
MAR system Boolean Algebra and
25/67 Logic Simplification
(B) using 2s complement method
(C) using 9s complement method
(D) using 10s complement method
MCQ 2.3.49 The most suitable gate to check whether the number of 1s in a digital
ANAND KU- word is even or odd is
i. n
MAR (A) X-OR (B) NAND
63/137
(C) NOR (D) AND, OR, and NOT
. c o
a
MCQ 2.3.50 Which of the following operations is commutative but not associative ?
ANAND KU-
MAR
65/138
(A) AND
(C) OR
d i (B) NOR
(D) X-OR
n o
MCQ 2.3.51
ANAND KU- (A) 1
w.
A + AB + ABC + ABCD + ABCDE + ... =
(B) A
w
MAR
1/192
(C) A + AB (D) AB
MCQ 2.3.52
wA + AB + A BC + A B C D + .... =
ANAND KU- (A) A + B + C + ... (B) A + B + C + D + ...
MAR
2/192
(C) 1 (D) 0
MCQ 2.3.53 The number of table entries needed for a five input logic circuit is
(A) 4 (B) 8
(C) 16 (D) 32
MCQ 2.3.54 The dual of a Boolean expression is obtained by

ANAND KU- (A) interchanging all 0s and 1s
MAR
15/192
(B) interchanging all 0s and 1s, all + and :signs
(C) interchanging all 0s and 1s, all + and : signs and complementing
all the variables
(D) interchanging all + and : signs and complementing all the
variables

Page 116 MCQ 2.3.55 The complement of a Boolean expression is obtained by

Chap 2 ANAND KU- (A) interchanging all 0s and 1s
Boolean Algebra and MAR
Logic Simplification 16/192
(B) interchanging all 0s and 1s, all + and : signs
(C) interchanging all 0s and 1s, all + and : signs and complementing
all the variables
(D) interchanging all + and : signs and complementing all the
variables
MCQ 2.3.56 All Boolean expressions can be implemented with

SEDHA (A) NAND gates only
7/118
(B) NOR gates only
(C) combinations of NAND and NOR gates
(D) Any of these
. in
MCQ 2.3.57
o
Which of the following logic gates will have an output of 1 ?
. c
d ia
n o
w.
MCQ 2.3.58
SEDHA w w
Boolean algebra is essentially based on
(A) symbols (B) logic
1/183
(C) truth (D) numbers
MCQ 2.3.59 X + XY is reduced to

SEDHA (A) X (B) X + Y
15/184
(C) X + Y (D) X + Y
MCQ 2.3.60 A carry look ahead adder is frequently used for addition, because it
KHARATE (A) is faster (B) is more accurate
7/197
(C) uses fewer gates (D) costs less
***********

SOLUTIONS 2.1 Page 117

Chap 2
Boolean Algebra and
SOL 2.1.1 Correct option is (B).

From the Boolean properties, we know that
i. n
So, its equivalent logic will be
. c o
i a
i.e.
o d
AND-Invert = Invert-OR
. n
By converting AND Invert logic to equivalent Invert-OR logic in the
given circuit diagram, we get
w w
w
So, the output Z is
Z = AB + CD + EF
ALTERNATIVE METHOD :
Expression of output can be directly obtained from given circuit as
Z = _AB i_CD i_EF i
Using De-Morgans theorem, we have
Z = AB + CD + EF
SOL 2.1.2 Correct option is (D).

From the Boolean properties, we know that

Page 118
Chap 2
Boolean Algebra and
So, its equivalent logic will be
i.e. AND-Invert = Invert-OR

Applying the property, we have the modified logic circuit as
. in
. c o
So, the output X is
d ia
n o
X = MNQ + MNQ + M NQ
w. = MQ _N + N i + M NQ
= MQ + M NQ
= Q _M + M N i
w w = Q _M + N i
SOL 2.1.3 Correct option is (A).

We convert the AND-Invert logic to equivalent Invert-OR logic as
or

Page 119
Chap 2
Boolean Algebra and
So, the output Z is given as

Z = AB + E _C + D i
i. n
SOL 2.1.4 Correct option is (C).
expression as
. c o
By using the Boolean properties, we minimize the given Boolean
i a
_X + Y i_X + Y i_X + Y i = _X + Y i_X : X + XY + X Y + Y : Y i
= _X + Y i_XY + X Y i
o d = XY + XY
n
= XY
w.
w
From the given logic diagram, expression of the output can be written
w as
Z = A + _AB + BC i + C
= A+A+B+B+C+C
= A+B+C
4
= ABC
From the above logic function, we can observe that options (A) and (B)
are matched. Now, we check the expression given in option (C).
Z = AB + BC + AC
= A+B+B+C+A+C
= A+B+C
Hence, all the options are same, and equal to the output Z of the given
logic circuit.

Given that
From Consensus Theorem, when a particular variable is associated
with some variable and its complement is associated with another
variable and next term is formed by the leftover variables, then the last
term becomes redundant.

Page 120 AB + AC + BC
S
= AB + AC
Chap 2 redundant
term
Boolean Algebra and Its dual also exists. Taking dual of the expression, we get
_A + B i_A + C i_B + C i = _A + B i_A + C i
Hence, _A + C i_B + C i_A + B i = _A + B i_A + C i

Expression of output for the circuit is given by
X = _A 5 B i : _A + B i
= _AB + AB i_AB i
= AB
in
Y = _A 5 B i : C
o .
Expression of the output for the circuit is given by
= _AB + AB i : C
= _AB + AB i + C
. c {Using De Morgans theorem}
= _AB + A B i + C
= A B + AB + C
d ia
{A 9 B = A 5 B or A 5 B = A 9 B }
n o
SOL 2.1.9
.
Correct option is (C).
w
Expression of the output Z for the circuit is given by
w w Z = A : _A + A i : B : C
= ABC {A + A = 1}

Expression of the output Z for the circuit is given by
Z = _A : B i : _B + C i
= A : B : B + ABC
= ABC {B : B = 0 }

The expression of the output Z for the circuit is given by
Z = _A + B i : BC
= AB : BC {Using De-Morgans theorem}
= ABC

SOL 2.1.12 Correct option is (C). Page 121

Expression for X from given table is obtained by writing logic for X Chap 2
corresponding to 0 output. i.e. Boolean Algebra and
X = A BC + ABC
= _A + Ai BC {A + A = 1}
= BC

Given expression is A + BC . Using distributive law, we have
A + BC = _A + B i_A + C i
i. n
This law states that ANDing of several variables and ORing the result
with a single variable is equivalent to ORing that single variable with
verified from the table below.
. c o
each of the several variables and then ANDing the sums. It can be
A B C A+B
i A+C
a _A + B i_A + C i A + BC
0
0
0
0
0
1
o
0
0 d 0
1
0
0
0
0
0
0
.1
1
0
1 n 1
1
0
1
0
1
0
1
1
w
1
w 0
0
0
1
1
1
1
1
1
1
1
1
w 1
1
1
1
0
1
1
1
1
1
1
1
1
1

The expression of Z from given truth table can be written for logic
1 or indirectly we can solve for Z and then take complement. The
expression for Z is given by , writing logic expression for 0 output as,
Z = A BC
Taking complement, we get
Z = Z = A BC {Using De-Morgans theorem}
or Z = A+B+C
Now, we check the result for the given options. From expression given
in option (B), we get same minimized result.
_A + B i_B + C i = _A + B i + _B + C i
= A+B+C

Page 122 SOL 2.1.15 Correct option is (A).

Chap 2 From truth table, the expression of the function f is given by
Boolean Algebra and
f = ABC + ABC
= B _AC + AC i
= B _A + C i_A + C i

The given Boolean expression is rewritten as
AC + BC = AC _B + B i + BC _A + A i
or AC + BC = ABC + ABC + ABC + ABC
in
The given expression is
A + AB + A BC + A B C D + A B C DE
.
On simplification of the expression using Boolean algebra, we get
o
. c
= A + A 8B + B #C + C _D + DE i-B
a
...(1)
i
Using redundant literal rule, we have
A + AB = A + B
or
o d
A + A _B + C i = A + B + C
Applying this rule in equation (1), we get
. n
= A + A 7B + B #C + C _D + E i-A
w w = A + A #B + B _C + D + E i-
= A + A _B + C + D + E i
w = A+B+C+D+E

Given logic function is
Y = A #B + C _AB + AC i-
On simplification, we get
Y = AB + AC 7_A + B i_A + C iA
= AB + AC _A + A C + A B + B C i
= AB

Given logic expression is
Y = _AB i : _AB i
On simplification by using Boolean algebra, we get

Y = _AB i : _AB i (Using De-Morgans theorem) Page 123
= _A + B i_A + B i
Chap 2
Boolean Algebra and
= _AA + A B + AB + BB i Logic Simplification
= A B + AB

Given that Z = XY + XY
So, we simplify the given function as
XZ + X Z = X _XY + XY i + X _XY + XY i
= X _XY + X Y i + XY
= XY + XY
i. n
= Y _X + X i
=Y
. c o
i a
Given that
oXY = 0 d
. n
Since, we know that
X 5 Y = XY + XY
w w X5Y = X9Y
So, by using the given condition, we get
X 5 Y = XY + XY = _XY + X Y i
w
or X5Y = X Y = X+Y (XY = 0 )

Rearranging the given expression, we get
Z = 7A + EF + BC + DA7A + D E + BC + D F A
= 7A + BC + EF + DA7A + BC + D _E + F iA
= 7_A + BC i + _EF + D iA7_A + BC i + _D + EF iA
Let A + BC = X
and EF + D = Y
So, we may write Z = _X + Y i_X + Y i
= X + XY + XY
= X 71 + Y + Y A
=X
= A + BC
Given that A = 0 , then
Z = BC

Page 124 SOL 2.1.23 Correct option is (C).

Chap 2 There are Four inputs (let A, B , C , D ) to a OR gate. So, we have
Boolean Algebra and
Total no. of input conditions = 2 4 = 16
Now, the output of OR gate is given by
Z = A+B+C+D
i.e. the output is High, if any one out of 4 input is high; and output
will Low, only for one condition (0 0 0 0). Thus, output will high for
15 input conditions.

The expression for the output of given circuit is
F = 7_A + B i + A + _A + B iA : 7_A + B i + A A
Let A + B = X and A + _A + B i = Y
So, the expression for output can be minimized as
F = _Y + X i Y
= Y + XY = Y _1 + X i = Y
. in
= A + _A + B i
= A : _A + B i
. c o
ia
= AA + AB
= AB
od
Thus, we may conclude that
F = 1 for A = 0 and B = 1
. n
SOL 2.1.25
w w
Correct option is (A).
We check the given requirements for the circuits given in the options.
wConsider the circuit of option (A).
1. For B = C :
P = B5C = 0
and X = A+0 = A
i.e. Output X will equal A when control input B and C are the same.
2. For B ! C :
P = B5C = 1
and X = A+1 = 1
i.e. X will remain HIGH when B and C are different.
Hence, the circuit satisfies both the requirements.

SOL 2.1.26 Correct option is (A). Page 125

We check the circuits in given option for the required condition. The Chap 2
output of the logic circuit will be high only when both inputs of last Boolean Algebra and
AND are high. Now, we have the two conditions:
1. Given that A and B are both High. For A and B as logic High,
one input of last AND gate is high for the circuits given in options
(A) and (B).
2. Given that C and D are either both LOW or both HIGH. For the
circuit given in option (A), if C and D inputs are either both high
or both low, i.e. C = D applied to XNOR gate then
C 9 D = 1 for C = D
i. n
i.e. another input of last AND gate will be High.
Thus, the circuit given in option (A) is HIGH whenever A and B are
. c o
both HIGH as long as C and D are either both LOW or both HIGH.

i a
d
Consider a 2-input OR gate shown below.
o
. n
w
Now, we check the correctness of the given two statements.
1. Given that output waveform _X i is same as the any one input
w
(let A). For this condition, we may have the following two state
w diagrams.
From the above state diagram, we may observe that it is not

necessary that B should be permanently Low to satisfy the
required condition. Therefore, statement-1 is False.
2. Given that output wave form _X i is always high. Again, we may
draw the state diagram for the condition.

Page 126 From the above state diagram, we observe that it is not necessary
Chap 2 that any one input should be permanently high. Therefore,
Boolean Algebra and statement-2 is False.

Given Boolean function is
Z = ABC
To obtain the Boolean expression in form of NAND gate output and
NOR gate output, we rewrite the expression as
Z = ABC = ACB = AC + B
Let AC = D
then Z = D+B
Therefore, one NAND gate and one NOR gate is required to implement
in
the Boolean function as shown below.
o .
. c
ia
Hence, the minimum cost for the implementation is 2 units.
d
SOL 2.1.29
n
Correct option is (C). o
w.
Given Boolean function,
Z = ABC
w w
To implement the function using using only NAND gates, we draw the
logic circuit as
Now, we convert each gate to its NAND implementation.
Thus, the minimum cost for implementation of the function using

NAND gate will be 5 units.

SOL 2.1.30 Correct option is (D). Page 127

For the LED circuit, we know the following points: Chap 2
1. Output of NAND gate must be Low for LED to emit light. Boolean Algebra and
2. Both inputs to NAND must be High for Low output.
3. If any one of the switches is closed, output of AND gate will be
Low.
4. If Both switches are open, output of XOR gate will be Low.
So there can not be both input High to NAND. Therefore, LED does
not emit light irrespective of the switch positions.

For the given circuit, we have i. n
Output of 1 st XOR = X : 1 + X : 1 = X
Output of 2 nd XOR = X 5 X
. c o
Output of 3 XOR = 1 5 X
i a
= X X + XX = 1
d
rd
= X:1+X:1 = X and so on.
o
Hence, after 2, 4, 6, 8, .......20 XOR (i.e. even number of XOR gates),
n
.
output will be 1.
w
SOL 2.1.32
w w
For the given network, we obtain
Output of gate 1 = X0 X1
Output of gate 2 = X0 X1 + X2
Output of gate 3 = _X0 X1 + X2i X3
= X0 X1 X3 + X2 X3
Similarly, we may deduce
Output of gate 4 = X0 X1 X3 + X2 X3 + X4
Output of gate 5 = _X0 X1 X3 + X2 X3 + X4i X5
= X0 X1 X3 X5 + X2 X3 X5 + X4 X5
Hence, the output of gate n would be
F = X0 X1 X3 X5 .........Xn + X2 X3 X5 .........Xn + X4 X5 X7 ..........Xn + ........ + Xn - 1 Xn

Given that G1 has delay of 10 ns and G2 has delay of 20 ns. Let output
of G1 is X . So, we get the output waveform for the given circuit as
shown below.

Page 128
Chap 2
Boolean Algebra and

From the circuit diagram, we have
X = PQ
. in
and
Y = P+Q
c
Z = X : Y = _PQ i_P + Q i
.
= _P + Q i_P + Q i
o
and
d
M1 = Z 5 R ia
= PQ + PQ = P 5 Q
Hence,
n o
M1 = _P 5 Q i 5 R
M1 = _P XOR Q i XOR R
w.
SOL 2.1.35
w w
XOR logic using 2-input NAND gates is implemented as
Now, we may prove that the above logic circuit implements an XOR
gate
Z = $_XY i X . : $_XY i Y .
= _XY i X + _XY i Y
= _X + Y i X + _X + Y i Y
= XY + XY = X 5 Y
Thus, 4 NAND gates are required


In negative logic system, Low-level or more negative represent the logic Chap 2
1 and HIGH level or less negative represent the logic 0, as illustrated Boolean Algebra and
in figure below.

i. n
c o
In positive logic system Low-level or more negative represents the logic
0 and HIGH level or less negative represents the logic 1.
.
i a
o d
. n
SOL 2.1.38
w w
Ex-OR gate output is given by
w Y = A5B
= AB + AB
(A and B are inputs)
To make inversion of a input using XOR gate, we consider one input,

let A. So, we must have the output
Y =A
For the required output, we should take another input at logic 1 (High). i.e.
Y = A:1+A:1 = A

We know that, XOR output is logic 1 when both inputs are not equal
and logic 0 when both inputs are same. Hence, we have
A 5 B = 0 for A = B
A 5 B = 1 for A ! B i.e. (a " 2 ) and _d " 1i
Again, XNOR output become logic 0, if any one input of XNOR is logic
1 (high), i.e.
A + B = 0 for A = 1 or B = 1 or A = B = 1 i.e. _b " 3i
Also, we have
A : B = 0 for A = 1 or B = 0 i.e. _c " 4i
Therefore, the correct match in the list is
(a " 2 ), _b " 3i , _c " 4i , _d " 1i


Chap 2 A NAND gate output can be expressed as
Boolean Algebra and
Y = A : B = A + B = A OR B
So, NAND gate is equivalent to an OR gate with its inverted inputs.
Again, the NOR gate output can be expressed as

Y = A + B = A : B = A _ANDi B
Hence, NOR gate is equivalent to an AND gate with its inverted input.
Therefore, statements (1) and (2) are correct.
. in
. c o
ia
For given logic circuit, expression for output X is
X = _A + B i : B = _A + B i + B
od
= Â + B h + B = A + B
Output waveform for the given input waveforms is
. n
w w
w

SOL 2.1.42 Correct option is (C). Page 131

The expression of the output for the given logic circuit is Chap 2
Boolean Algebra and
X = AB + A B = A 9 B Logic Simplification
So, we may conclude that
X = A 9 B = 1 for A = B
= 0 for A ! B
Therefore, we obtain the output waveform for the given input waveforms
as
i. n
. c o
i a
o d
. n
w w
SOL 2.1.43
w
Correct option is (D).
The expression of the output for the given logic circuit is
X = _A + B i + B
= _A + B i : B
= _A : B i : B
=0
Hence, the output for the circuit will remain zero irrespective of the
input.

According to the given problem, we represent the fruits as
A = apple; B = banana; M = Mango; O = orange
So, the logical expression that specifies the fruit available for desert is
f _A, B, M, O i = _1st Choicei + _2nd Choicei + _3rd Choicei
= _O + A + OAi + _MAi + _OB i
= _A + O i + MA + BO
= A _1 + M i + O _1 + B i
= A+O


Chap 2 The wired AND in open-collector is given by
Boolean Algebra and
Since, for the given circuit, we have

C = A and D = B
Hence, the output of the circuit is given as
F = AB : A B = AB + AB
= A 5 B = A _XOR i B

. in
Given Boolean expression is
c
_w + x i_w l + x + yz li_w + y li
On simplification, we obtain
. o
d ia
_w + x i_w l + x + yz li_w + y li = _w l + x + yz li_w + xy li
= ww l + w l xy l + xw + xxy l + yz l w + yz l xy l
n o= w l xy l + xy l + xw + yz l w
= _w l + 1i xy l + w _x + yz li
w. = xy l + wx + wyz l
SOL 2.1.47
w w
The elevator door will open in the following two cases.
Case 1: If the elevator is stopped, it is level with the floor, and the
timer has not expired.
Since, we have the representations
Elevator is stopped = S ;
Level with the floor = F ;
Time has not expired = T l
So, the given condition is expressed as
X1 = SFT l
Case 2: If the elevator is stopped, it is level with the floor, and a button
is pressed.
Again, we have the representations
Elevator is stopped = S
and Level with the floor = F
and Button is pressed = B
So, the given condition is expressed as

X2 = SFB Page 133

Since, the door will be open is case-1 or case-2. Therefore, we may Chap 2
express the condition for elevator door to be open as Boolean Algebra and
D = X1 OR X2
or D = SFT l + SFB

Given logic circuit is
i. n
. c o
So, the output Z is given by
i a
Z = X + X + Y = X : X + Y = X : _X + Y i
o d
= X + XY = X _1 + Y i = X = X
In option (D), the circuit provides the output X as shown below.
. n
w w
Hence, the circuit given in option (D) is minimized form of the logic
w
circuit.

We redraw the given logic circuit as
Output Z of the logic circuit is

Z = AB C D + ABCD + A D

Page 134 = AD ^B C + BC h + A D
Chap 2
= AD _B 9 C i + A D
Boolean Algebra and
Logic Simplification = AD _B 5 C i + A D

Given Boolean expression is
AD + ABCD + ACD + AB + AC D + A B
On minimization using Boolean algebra, we get
AD + ABCD + ACD + AB + AC D + A B
= AD _1 + BC + C + C i + AB + A B
= AD + AB + A B
= AD + A _B + B i = AD + A
= _A + A i_D + A i = A + D
in
NOTE :
.
Here, it must be noted that, we got first the expression ÂD + A h , and this is also
given in option (B). At first glance it seems to be Answer but it is not. It can be
minimized further into Â + D h .
o
. c
d
We redraw the given digital circuit asia
n o
w.
w w
Output Y is given by
Y = AB + AB = A 5 B = A _XOR i B

We have the switching circuit as

Now, we consider the parallel switches as shown below. Page 135

Chap 2
Boolean Algebra and
The logic expression for parallel switches is obtained as

L = A+B
i. n
Again, we consider the series connected switches
. c o
i a
o d
The logic expression for series connected switches is
. n L = A:B
Hence, the logic expression for given circuit is
w w L = _A + B i : _C + D i : E
SOL 2.1.53
w
We have to check the correctness of each options.
Option (A)
On minimizing L.H.S. of the equation, we have
X + XY = _X + X i_X + Y i = X + Y ! X
or X + XY ! X
Option (B)
X _X + Y i = XX + XY = XY
or X _X + Y i = XY
Option (C)
X + XY = X _1 + Y i = X
or X + XY = X
Option (D)
ZX + ZXY = Z _X + XY i = Z _X + Y i = ZX + ZY
or ZX + ZXY = ZX + ZY

Page 136 SOL 2.1.54 Correct option is (D).

Chap 2 We have the switching circuit diagram as
Boolean Algebra and
in
From the circuit diagram, we deduce that LED will glow when
o .
Z = Low _ 0 i , and Z will be low only when X or Y or both will be
High. Now, we consider the different input conditions as
1. For A = B = 1,
. c
X = 1 and Y = 0 & Z = 0 ; LED glows
2.
3.
For A = B = 0 ,
For A = 0 , B = 1;
d ia
X = 0 and Y = 1 & Z = 0 ; LED glows
n o
X = 0 and Y = 0 & Z = 1; LED doesnt glow
4.
w.
For A = 1, B = 0 ;
X = 0 and Y = 0 ( Z = 1; LED doesnt glow
SOL 2.1.55 w w
We have the Boolean identity
AB + AC = _A + C i_A + B i
Dual form of any identity can be found by replacing all AND function
to OR and vice-versa. Hence, dual form of the expression is given as
_A + B i : _A + C i = _A : C i + _A : B i

Dual form of any identity can be found by replacing all AND functions
to OR functions and vice-versa. Now, we have the Boolean expression
as
A + 7B + _AC iA + D
So, the dual form of the expression is given as
A : 7B : _A + C iA : D
or A 7B _A + C iA : D

SOL 2.1.57 Correct option is (B). Page 137

We have the Boolean expression as Chap 2
Boolean Algebra and
Z = x 5 y 5 xy Logic Simplification
On minimizing the expression, we have
Z = x 5 7y 5 xyA
= x 5 7yxy + yxyA
= x 5 7y _x + y i + 0A
= x 5 7yx + 0A
= x : yx + x : yx
= x _y + x i + xy = x + xy + xy
= x _1 + y i + xy = x + xy
= x+y
i. n
. c o
We have the Boolean expression as
i a
_X + W i_Y 5 Z i + XW l
o d
On simplification and minimization of the Boolean expression, we get
_X + W i_Y 5 Z i + XW l = _X + W i_YZ l + Y l Z i + XW l
. n = XYZ l + XY l Z + WYZ l + WY l Z + XW l
w w
From consensus theorem, we have
So, eliminating the redundant term in the expression, we get
w
i.e. the minimized expression of _X + W i_Y 5 Z i + XW l is
WY l Z + XW l + WYZ l

We have the Boolean expression
F = _x + y i_x + y li ...(1)
On simplification, we get the expression
Fsimplified = x + xy l + xy + yy l
= x _1 + y l + y i
=x ...(2)
Hence, the logic diagram for the expression (1) and (2) is shown below.

Page 138
Chap 2
Boolean Algebra and

To get output at High state, i.e. to stop the Machine operation; either
path). Hence, logic expression for output S is

. in
P is low (no paper in paper feeder) or Q and R are high (jam in paper
S = P+Q:R
. c o
So, the logic circuit for the given condition is drawn as
d ia
n o
w.
SOL 2.1.61
w w
Correct option is (B).
We redraw the given logic circuit as
DRIVE is active-HIGH, and it will go high only when

X =Y=0
X will be LOW only when either A8 and A9 is HIGH.

Y will be LOW only when W = 0 and A7 = 0 Page 139

W will be LOW only when A0 through A6 are all HIGH. Chap 2
Putting this all together, we have the condition for DRIVE to be high Boolean Algebra and
as
A0 = A1 = A2 = A3 = A4 = A5 = A6 = 1
A7 = 0
and either A8 or A9 or both are 1
i. n
We have the wired-OR logic circuit as shown below.
. c o
i a
o d
For the logic circuit, the output is
. n Y = _A + B i + _C + D i
SOL 2.1.63
w w
w
We have the two level AND-OR gate as shown below.
Now, all the gates are replaced by NOR gate. So, we get the modified
circuit as
Hence, the output of the modified network is

Z = _A + B i + _C + D i
= _A + B i : _C + D i
= dual of F = F D


Chap 2 The output function for the given circuit is
Boolean Algebra and
f = xyz + wyz + wxz
Let y = A; x = B ; w = C
then f = Z _AB + AC + BC i
Using consensus theorem, we conclude that BC term is redundant. So,
we have
f = Z _AB + AC i
or f = xyz + wyz
Hence, gate 3 is redundant.

We have the logic circuit as shown below
. in
. c o
d ia
n o
w.
From the Boolean algebra, we have
w w
By using the above conversion, we redraw the given logic circuit as
Hence, the output of the logic circuit is

Y = P+Q+R+S


All the given circuit in the options include NOR gate. So, we implement Chap 2
the given expression using NOR gate as Boolean Algebra and
X = AB + CD = (A + B ) (C + D )
= (A + B ) + (C + D )
i. n
. c o
i a
o d
SOL 2.1.67
. n
In order to convert the given circuit into all NOR, we apply the bubbles
w
at the input terminals of gates as shown below.
w
w
and
Therefore, by using the above conversion, we get the logic circuit with
NOR gates.


Chap 2 In order to convert the given circuit using only NAND gate, we apply
Boolean Algebra and bubbles at the input terminal of each gates as shown below.
and
. in
c o
Therefore, by using the above conversion, we get the logic circuit with
NAND gates as
.
d ia
n o
w.
w w
Figure I
We have the combinational circuit in Figure - I as
So, the output of the circuit is

F1 = X + (X + Y ) = X (X + Y )
= X X + XY = XY
Figure II
We have the combinational circuit in Figure - II as

Page 143
Chap 2
Boolean Algebra and
So, the output of the circuit is
F2 = X $ Y
Hence, we have
F1 ! F2
i.e. the output of the given two circuits are entirely different.
***********
i. n
. c o
i a
o d
. n
w w
w

Page 144
Chap 2
Boolean Algebra and
SOLUTIONS 2.2
SOL 2.2.1 Correct answer is 0.

Given Boolean function is
F = A + AB + ABC = A _1 + B + BC i = A
Therefore, no gate is required to implement this function.
in
As the given expression is to be realized using one type of 2-input gates.
o .
So, we may use universal gates (NAND, NOR) for realization. Now, we
implement the given function using NAND and NOR gates.
given expression
. c
1. NAND Implementation: For NAND implementation, we rewrite the
ia
Y = A + BC = A + BC = _A i : _BC i
So, the logic circuit can be implemented as
d
n o
w.
w w
2. NOR Implementation: For NOR implementation, we rewrite the
given expression as
Y = A + BC = _A + B i_A + C i ; [Distributive
property]
or Y = _A + B i_A + C i
= _A + B i + _A + C i
Thus, to implement given circuit, minimum 3 gates are required.

SOL 2.2.3 Correct answer is 31. Page 145

We know that, if any one input of the OR gate becomes high logic (1), Chap 2
OR gate gives the high logic (1) output. The output is High only for Boolean Algebra and
the case when all the inputs are at Low logic (0). Now, for 5-inputs,
we have
Total number of input conditions = 2 5 = 32
Out of the 32 conditions, all inputs are zero (0) for only one condition.
i.e. for only one condition the output is low.
Hence, 31 input conditions produce the high output from a five-input
OR gate.

i. n
o
The Boolean function of two variables x and y are defined as
c
f _0, 0i = f _0, 1i = f _1, 1i = 1 and f _1, 0i = 0
.
For the Boolean function, we obtain the truth table as
x y f
i a
0
0
0
1
1
1
o d
1
. 0
n0
w
1
w 1 1
From the truth table, we define the function f as
f = xy
w So, f = xy = x + y
Hence, the function _ f i can be implemented using 2 input NOR and
2-input OR gate as shown below.
Thus, the total cost for the logic circuit will be 2 units.

The circuit is as follows

Page 146 SOL 2.2.6 Correct answer is 011.

Chap 2 For given logic circuit, output X = 1, if all inputs to AND gate are
Boolean Algebra and High. The output for the circuit can be expressed as
X = _A 5 B i : _B 9 C i : C
Also, we have
A 5 B = 1 if A ! B
and B 9 C = 1 if B = C
Hence, for X = 1, the required conditions are
C must be High
B =C=1
A =0 (since A ! B )

Given the logic equation,
and
7X + Z #Y + _Z + XY i-A#X + Z _X + Y i- = 1
X =1
. in
. c o
So, by substituting X = 1 and X = 0 in the logic equation, we get
71 + Z #Y + _Z + 1Y i-A : 80 + Z _1 + Y iB = 1
ia
or 71A8Z _ 1 iB = 1
Hence, we have Z = 1 or Z = 0
od
SOL 2.2.8
. n
Correct answer is 0.
w w
Given logic expression is
A _A + B i_A + B + C i
On solving the expression, we have
w A _A + B i_A + B + C i = _AA + AB i_A + B + C i

= _A + AB i_A + B + C i
= A + AB + A : AB + A : B : B + AC + ABC
= A + AB + AC + ABC
= A _1 + B + C + BC i = A
Therefore, no gate is required to implement this function.

From the given circuit, we can observe that input to last XNOR gate is
same. So, the XNOR output is given by (Let input is X )
Z = X:X+X:X = X+X = 1
i.e. the output will be High (logic 1), irrespective of the inputs A and
B.

SOL 2.2.10 Correct answer is 65536. Page 147

The number of distinct Boolean expressions of n variables is 2 2 . Since,
n
Chap 2
we have Boolean Algebra and
n =4
Hence, the number of distinct Boolean expressions is
2 2 = 2 2 = 2 16 = 65536
n 4

The number of duals of distinct boolean expressions of n variables
is 2 2 . Since, we have n = 4 . Hence, the number of duals of distinct
n-1
Boolean expressions is
22
n-1
= 2 2 = 2 2 = 2 8 = 256
4-1 3
i. n
. c o
i a
To implement the given function using NAND and NOR gates, we
rewrite the given function as
o d
Y = ABCD = ABCD = AB + CD
. n
So, the equivalent circuit for the Boolean function is
w w
w
Therefore, two NAND gates and one NOR gate is required to implement
the function Y = ABCD .
***********

Page 148
Chap 2
Boolean Algebra and
SOLUTIONS 2.3

NAND gate output Y = A : B
Where, A and B are inputs, if inputs are connected together, i.e. A = B
Y = A:A = A
. in
. c o
d ia
n o
SOL 2.3.5
.
w
SOL 2.3.6
w w

AND gate output Y = A : B : C
If any one of the inputs is LOW then output becomes LOW. Output
will HIGH only when all the inputs are HIGH.
For 3-inputs, 8 input possibilities are there, out of which only one case
has all inputs high.

OR gate output Y = A+B+C
If any one input is HIGH, output will be HIGH. Output will be LOW

only when all three inputs become LOW. Page 149

Out of 8 input possibilities, seven cases have one or more inputs high Chap 2
results in HIGH. Boolean Algebra and

i. n
. c o
SOL 2.3.13 Correct option is (C)
i a
SOL 2.3.14
o
d
. n
SOL 2.3.15
w w
Output of two input _A, B i NOR gate, Y = A+B
w
Using Demorgan theorem,
AND gate
Y = A:B = negative-

Two-input NAND gate using two-input NOR gate is realized
as :


Chap 2
Boolean Algebra and

The Ex-NOR gate output is HIGH only when both input bits of it are
equal.
Hence, Ex-NOR gate is suitable for bit comparison.

. in
. c o
ia
AND : Y = A : B = B : A
d
OR : Y = A + B = B + A
o
. n
SOL 2.3.25
w
w
SOL 2.3.26
wCorrect option is (D).
The truth table for Ex-NOR gate is,
Inputs Output
A B Y = A9B
0 0 1
0 1 0
1 0 0
1 1 1
The output is 1 for like inputs and 0 for unlike inputs.

The truth table for NAND and OR is,

Page 151
Inputs Outputs
Chap 2
A B X = A:B Y = A+B Boolean Algebra and
0 0 1 0
0 1 1 1
1 0 1 1
1 1 0 1
For both NAND and OR gates, all output entries are logic 1 except
for one entry.

i. n
. c o
i a
o d
. n
Taking of two times complement results the original function.
Y = AB + AB
w w
Complement of Y = Y = AB + AB
Complement of Y = Y = Y = AB + AB = AB + AB
SOL 2.3.31
w
Correct option is (D).

Y = A + B = A $ B = NAND gate logic


Chap 2 Y = A.B = A + B = NOR gate logic
Boolean Algebra and

Y = A.B = A + B = A + B = OR gate logic

Y = A + B = A $ B = AND gate logic
. in
. c o
d ia
SOL 2.3.43
n
Correct option is (B). o
w.
SOL 2.3.44
w w

NAND and NOR gates are universal gates. Any logic function can be
realized using only NAND or only NOR gates.
So, AND, OR and NOT gates are not necessary to realize any logic
function.

X = A.B = A + B = NOR gate logic
Hence, output will be HIGH if and only if both the inputs are low.

SOL 2.3.48 Correct option is (B). Page 153

Chap 2
Boolean Algebra and
When the no. of inputs in the XOR gate is even then output is 0 and
when the no. of inputs is odd then output is 1.

NAND and NOR gates do not follow the associative property.
i. n
Now check for NOR gate, (A + B ) + C is equal to or not equal to
A + (B + C ) .
or
or
. c o
(A + B ) + C ! A + (B + C )
(A + B ) + C ! A + (B + C )
i a
o d
A + AB + ABC + ABCD + ABCDE + ....
. n
= A (1 + B + BC + BCD + BCDE + ...)
= A (1 + X) = A
w w
w
A + AB + A BC + A B C D + ... = A + A (B + BC + BC D + ...)
= A + A (X ) = (A + A) (A + X )
= A+X
= A + B + BC + B C D + ... and so on.
= A + B + C + ...

The number of combinations for five inputs is = 2 5 = 32 .


Chap 2 Output of each option is
Boolean Algebra and (A) Y = 0.1 = 0 (B) Y = 0 + 1 = 1 = 0
(C) Y = 0 $ 1 = 0 = 1 (D) Y = 0 9 1 = 0
***********
. in
. c o
d ia
n o
w.
w w


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GATE Electronics & Communications

IES Electronics & Telecommunication

Transistor as a switching element ; Simplification of Boolean functions, Karnaguh map

CHAP 1 NUMBER SYSTEM AND CODES

CHAPTER 2 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

CHAPTER 3 THE K-MAP

3.1 INTRODUCTION 155

CHAPTER 4 COMBINATIONAL CIRCUITS

4.1 INTRODUCTION 231

CHAPTER 5 SEQUENTIAL CIRCUITS

5.1 INTRODUCTION 323

CHAPTER 6 LOGIC FAMILIES

6.1 INTRODUCTION 413

CHAPTER 7 INTERFACING TO ANALOG

7.1 INTRODUCTION 495

8.1 INTRODUCTION 571

Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)

BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Boolean algebra is mathematics of logic. It is one of the most basic

2.2.1 Logic Levels

Table 2.1: Representation of Logic Levels for Boolean Variables

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2.2.2 Truth Table

2.3 BASIC BOOLEAN OPERATIONS

Boolean algebra uses only three basic operations, namely

2.3.1 Boolean Addition (Logical OR)

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Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)

Y = A + B, where + is the OR operator Page 65

w combinations of inputs, A and B , is shown in Table 2.4 below.

Table 2.4: Truth table for AND operation

2.3.3 Logical NOT

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Page 66 Table 2.5: Truth table for NOT operation

2.4 THEOREMS OF BOOLEAN ALGEBRA

The theorems of Boolean algebra can be used to simplify many complex

2.4.2 AND Laws

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Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)

2.4.4 Commutative Laws Page 67

2.4.5 Associative Laws

w Another theorem based on this law is

2.4.8 Idempotent Law

2.4.9 Absorption Law

2.4.10 Consensus Theorem

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Page 68 2.4.11 Transposition Theorem

2.4.12 De Morgans Theorem

2.4.13 Shannons Expansion Theorem

METHODOLOGY: TO SIMPLIFY A BOOLEAN EXPRESSION USING

1. Remove all parentheses and multiply all variables.

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Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)

6. Apply Boolean theorem and laws discussed earlier for further

2.5.1 Complement of Boolean Function

w Boolean expression is obtained by replacing all : operations with +

2.5.3 Relation Between Complement and Dual