3/16/22, 11:10 PM Emulate CMOS Inverter with Cadence Virtuoso IC617 - Programmer Sought

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Emulation of CMOS Inverter with Cadence Virtuoso IC61

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foreword
This article is my own study notes. It is the fourth article in the Cadence Virtuoso series and also the article in
the introductory series. The software version used is Cadence Virtuoso IC617. For other articles, please click
above to see the content of the Cadence Virtuoso column I produced.

This paper mainly records how to simulate a CMOS inverter with the Cadence Virtuoso IC617, which will help
learners to understand Cadence simulation more deeply. This paper involves time domain simulation and
multi-curve simulation.

Input and output characteristics when W and L are fixed

Schematic
Using the SMIC 0.18um process mentioned in the first article as the process used for the schematic diagram,
the following schematic diagram is established to measure the curve of the output voltage as a function of the
input voltage. VDD is controlled by V2, set a fixed value of 3V, and the input is controlled by V1, set to variable
vin. Here, the W and L of the MOS are set as fixed values, which are 220nm and 180nm respectively.

Error 1: This schematic is a CMOS inverter, which consists of an N-MOS and a P-MOS.

Error 2: The B pole of N-MOS is connected to GND, and the B pole of P-MOS is connected to VDD.

In order to avoid too long, and most of the simulation settings have been discussed in the previous articles, so
here is a summary of the simulation settings. By default, anyone reading this article has read the previous article
on Simulating VI Characteristic Curves.

If you haven't seen it, please click the link below and jump to **"Set Single Variable Simulation"** in the directory,
which will explain all the options mentioned below in detail.

Simulation of VI characteristic curve with Cadence Virtuoso IC617

Set Simulation Variables

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Select Launch in the menu and select the first item ADE L.

Select Copy From Cellview in the pop-up window to import the variable vin in the schematic.

At the same time, set the initial value of the variable, here the initial value is set to 0.

Set up simulation analysis

Set the scan type. Select the icon on the right in the AED L window.

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Set the DC simulation here, the simulation variable is vin, the range is 0-3V, click OK to confirm.

Eventually, the setup prompt will be displayed in the window.

Set simulation output

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Click the icon on the right to set the simulation output.

In the pop-up window, it is not recommended to enter the node name directly, it is more recommended to
directly click From Design.

We need to simulate the voltage, not the current in the simulation VI characteristic curve, so we choose the wire,
not the node of the device. The selected wires are marked with colors, where the input is marked green and the
output is marked red.

Returning to the original window, it can be seen that the output is a voltage type, named "net XXX", and the
current type mentioned above is "NM0 / X". Click OK to confirm the modification.

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Eventually, the setup prompt will be displayed in the window.

final simulation result

After the above three steps, it can be concluded that there are data in the three sub-windows in the emulator.
Click the start icon on the right to get the simulation results.

A simulation curve is obtained. The red one is the input voltage curve, and the green one is the output voltage
curve. At this W and L, the point of vin=vout is at about 1.16V, or 38.7% VDD.

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Influence of sweep W on input and output characteristics

In the previous section, the input and output characteristics were introduced when the W and L of the MOS were
fixed. In order to visually observe the circuit behavior under different transistor sizes, we need to simulate the
circuit by sweeping variables.

Schematic
Change the schematic to the following figure. That is, the W of the MOS is changed to a variable. Only the
process of scanning W is recorded here, and the process of scanning L is the same, and will not be repeated
here.

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The specific settings are as follows, and the change is Total Width.

Simulation settings
In the left window, after adding all variables and setting initial values, select Parametric Analysis in Tools.

Add two variables, both start scanning at 220nm, and the scanning step is 110nm. You can switch the scanned
variables by ticking the Sweep option box. Click the green button to start the simulation.

Simulation results
Set the W for scanning N-MOS, and the result is as follows. It can be seen that as W becomes larger, the output
curve shifts to the left, that is, the point where vin=vout shifts to the left.

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Set the W to scan the P-MOS, and the result is as follows. It can be seen that as W becomes larger, the output
curve shifts to the right, that is, the point where vin=vout shifts to the right.

Input and output characteristics when the input is a square wave

The previous records are all input voltage as a variable for DC DC analysis. Now change the input to a square
wave for time domain analysis.

Schematic
On the basis of the previous schematic diagram, the input voltage source V1 is changed to a square wave input.
The details are as follows, select the vpulse in the device library and add it to the schematic diagram.

The parameters of the square wave signal are set as follows. Here, the peak range is mainly set to 0-3V, the
period is 2ns, and the pulse width is 1ns, and finally a square wave with a 50% duty cycle is obtained.

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The schematic diagram of the setup is as follows. Note that the W of MOS is changed back to a constant.

Simulation settings

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Select Launch in the menu and select the first item ADE L.

Since it is a time domain analysis, there is no need to set variables and directly set the scan type.

Set it to the first item, time domain analysis, and set the sweep time to 10ns, that is, 5 cycles.

Set output.

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In the pop-up window, it is not recommended to enter the node name directly, it is more recommended to
directly click From Design.

We need to simulate the voltage, not the current in the simulation VI characteristic curve, so we choose the wire,
not the node of the device. The selected wires are marked with colors, where the input is marked green and the
output is marked red.

Returning to the original window, it can be seen that the output is a voltage type, named "net XXX", and the
current type mentioned above is "NM0 / X". Click OK to confirm the modification.

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Eventually, the setup prompt will be displayed in the window.

Simulation results
After the above three steps, it can be concluded that there are data in the three sub-windows in the emulator.
Click the start icon on the right to get the simulation results.

Result graph. It can be seen that the inversion effect has been achieved.

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Drag the timeline handle to pull apart the curve and select the time to observe the rising and falling edges.

Experience summary
In the design, we generally make the balance point of vin=vout at 0.5*VDD. At this time, the Ids of the two
transistors are equal, but since the process parameters of P-MOS and N-MOS are not equal, we need to The
W/L of the two transistors are designed.

generally
In general, the following relationship can be derived. Among them, K is preferably slightly larger than 2, so the
effect is better.

W W
( ) =K( )
L p L n
​ ​ ​ ​

W
K ≈2, ( ) ⩾3
L n
​ ​

For example, the following dimensions are designed to satisfy the above-mentioned relationship.

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At this time, the equilibrium point of vin=vout is located at about 1.40V, which is 46.7% VDD.

size restrictions
If the design is limited, W cannot accept too long dimensions, and the K value can only be increased to meet the
requirements. becomes the following formula.

W W
( ) =K( )
L p L n
​ ​ ​ ​

K>2

For example, design the following dimensions, at this time K=3.

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At this time, the equilibrium point of vin=vout is located at about 1.44V, which is 48% VDD.

Analysis principle
Start with the VI characteristic formula of MOS. There is the following relationship, their currents are equal, and
the expressions on both sides are expanded at the same time.

ID S n = ID Sp _​ ​

1 W
Kn ( ) ( VG S − VT n )2 ( 1 + λn VD S )
2 L n
​ ​ ​ ​ ​ ​ ​ ​

=
1 W
Kp ( ) ( VG S − VT p )2 ( 1 + λp VD S )
2 L p
​ ​ ​ ​ ​ ​ ​ ​

The process parameters here are the SMIC 0.18um process library parameters, which have been calculated in
my previous article. Click below to view.

Simulation of process library parameters with Cadence Virtuoso IC617

In the relationship, VGS = VDS = 0.5*VDD, while ignoring the right part of the equation that has little effect, the
following relationship is obtained.

( VG S − VT n )2 ( 1 + λn VD S ) = 1 . 8 5 5
​ ​ ​ ​

( VG S − VT p )2 ( 1 + λp VD S ) = 1 . 8 1 9
​ ​ ​ ​

∵1.855≈1.819

W W
∴ ID S n = ID Sp _ ⟹ Kn (
​ ​
) = Kp ( ) ​ ​ ​ ​ ​

L n L p

That is to say, the last relationship is related to the process parameters Kn and Kp, as well as the transistor size
ratio we design. Transform the expression into the form of a ratio.

(W )
L Kn
​ ​

p
= = K ≈ 2.4 _ _
​

Kp
​ ​

(W
L ​ ) ​
​

This result is consistent with the previous result, K needs to be slightly larger than 2, and the effect is best at this
time.

Of course, with different processes (especially more advanced ones), and when VDD changes, there will be
some slight changes in this K value.

At the same time, for analog circuits, many of our designs are based on "experience" and "estimation", and the
experience recorded here can apply to some cases, but not all cases. The title of this section also summarizes it
as "experience" rather than "theorem".

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content

foreword

Input and output characteristics when …

Schematic

Set Simulation Variables

Set up simulation analysis

Set simulation output

final simulation result

Influence of sweep W on input and outp…

Schematic

Simulation settings

Simulation results

Input and output characteristics when th…

Schematic

Simulation settings

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