3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

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Designing a Low Dropout (LDO) Linear Regulator with t

he Cadence Virtuoso IC617
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foreword
This article is my own study notes, which belong to the advanced part of the Cadence Virtuoso series. The
software version used is Cadence Virtuoso IC617. For other articles, please click above to see the content of
the Cadence Virtuoso column I produced.

While the previous articles have studied bandgap references, which are commonly used in circuits such as
linear regulators and ADCs, this article will look at low-dropout (LDO) linear regulators, using a standard
CMOS process.

Linear Regulator
Theoretical principles
In circuit application, how can we reduce 5V to 2.5V? The easiest way is to divide the voltage by resistance. In
many cases, we use the circuit shown in the figure below, such as the voltage divider before ADC sampling.

But the problem is, the voltage reducer we are designing now needs to carry a load, that is, it needs to be used
as a power supply, then the situation in the following picture will appear. In the case of using a constant
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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

resistance divider, we cannot get what we want. voltage.

What can we do to solve this problem? We can replace R1 with an adjustable resistor, then when the load
changes, adjust R1 to get the desired voltage.

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circuit principle
The linear regulator uses the principle mentioned above, except that the adjustable resistor R1 is replaced by a
transistor, and the effect of output voltage regulation is achieved by dynamically adjusting the conduction state
of the transistor. The optional transistors are listed in the table below.

This paper mainly studies the CMOS process, so P-MOS is selected. Compared with the triode, it has the
following characteristics.

The minimum input and output voltage difference supported is small, generally 0.1V-0.4V, and the triode will
reach more than 1V

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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

The maximum output current is small, generally not more than 500mA, and the triode can reach more than
1A

Small quiescent current, suitable for low power consumption

Then, a linear regulator using a P-MOS transistor as a power regulator can be called a low dropout (LDO) linear
regulator because it supports a small minimum input-output voltage drop. For example, when the minimum
voltage difference is 0.3V, to output 1.8V, the input only needs to be greater than or equal to 2.1V, while the
linear regulator using triode needs to input more than 2.8V (when the minimum voltage difference is 1V).

The schematic diagram of the circuit using the P-MOS transistor is as follows. One end of the operational
amplifier collects the output voltage, and then compares it with Vref. The output signal passes through a buffer
to control the P-MOS.

designing process
The MOS used in this design is all 3.3V withstand voltage devices, and the previous ones are 1.8V withstand
voltage devices, so the curve of gmoverid needs to be re-obtained, and it can be changed in the original
schematic diagram, this is relatively simple .

op amp design
In the previous design of the bandgap reference, a folded cascode circuit structure with P-MOS as the input
tube was used. In this design, an N-MOS folded cascode circuit structure will be used as the input tube to
reduce the dependence on the power supply voltage.

The branch current is also designed to be 5uA. Since the efficiency of the 3.3V device is low, the gain of the op
amp is the most important indicator, so the gm/id=16 of the input tube and the gm/id=8 of the current mirror are
designed.

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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

Under the load of 3pF, the performance parameters of the designed op amp.

Buffer Design
Because the operational amplifier directly drives the power transistor, it needs to consume a large chip area and
current, so adding a buffer to let the buffer drive the power transistor can increase the transient response
performance at the same time.

Buffers are implemented using source followers. Of course, P-MOS is used this time, not N-MOS in the picture.

Power tube design

For the power tube, if it wants to flow a larger current, its W will become larger. When designing a power tube, L
can take the minimum value, while W needs to take a large value. The designed current is 100mA. After

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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

simulation, the obtained power tube size is, L=300nm, W=100um, Multiplier=12.

Dynamic adjustment tube design

The schematic diagram below. The P-MOS and resistor on the left constitute a buffer, and the P-MOS on the
right is a power tube. A diode-connected P-MOS is added in the middle, and the size does not need to be too
large, which acts as a dynamic adjustment.

Simulation results
Vref is 1.2V, and the voltage dividing resistor is set to a 1:2 relationship. It is planned to obtain an output voltage
of 1.8V and a maximum output current of 100mA. Set the output capacitor to 4.7uF.

DC simulation
First test the relationship between power supply voltage and output. When the output current is 10mA, when the
power supply voltage reaches 2.1V, the voltage of 1.8V can be output normally, that is, the voltage difference is

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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

0.3V. And when the output current is 100mA, the voltage drop reaches 1.1V. At 50mA, linear regulation is 0.3%.

In the 1.8V output state, the maximum output current is 110mA, leaving a margin of 10mA. The resulting load
regulation is 0.2%.

Transient Simulation

load adjustment response

Test the load adjustment response, replace the DC source load on the left with the pulse load on the right, set
the current and period, and do a transient simulation.

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3/16/22, 11:19 PM Designing a Low Dropout (LDO) Linear Regulator with the Cadence Virtuoso IC617

When the circuit jumps from 0 current to 50mA, the voltage regulation time is about 5us.

Linear adjustment response

To test the linear adjustment response, add a voltage pulse source to the VDD voltage source, set the current
and period, and do a transient simulation. The power supply voltage jumps from 5V to 3V, observe the
undershoot of the output, and the stabilization time is about 5us.

AC simulation
Add an AC amplitude to the DC source of VDD and observe the power supply rejection ratio. It can be seen that
the performance deteriorates as the output current increases.

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content

foreword

Linear Regulator

Theoretical principles

circuit principle

designing process

op amp design

Buffer Design

Power tube design

Dynamic adjustment tube design

Simulation results

DC simulation

Transient Simulation

load adjustment response

Linear adjustment response

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