BioElex - Chopper Amplifier - Lectures1-7

‫تقويت كننده هاي چاپر‬
Chopper Amplifier
1 ‫ دانشگاه تهران‬،‫اميد شعاعي‬
Omid Shoaei
College of Engineering / School of Electrical and Computer Engineering
Department of Electronics
https://ece.ut.ac.ir/en/~oshoaei
OFFSET/FLICKER NOISE CANCELLATION
 Trimming (only offset)
 Auto-zeroing
 Chopping
Auto-zeroing
Omid Shoaei, University of Tehran

2
CHOPPER AMPLIFIER Chopper Switches
o A polarity reversing switch (+1 or -1)

o CMOS -> near-ideal square-wave modulator
• DC input modulated twice -> remain the same

frequency
• Offset modulated once -> ripple at ƒch -> LPF
• Non-50% duty-cycle -> residual offset
• LPF -> bandwidth loss
• Non-ideal LPF -> residual ripple
• Effective amplifier gain

3
CHOPPER AMPLIFIER
o Offset and 1/ƒ noise -> modulated

o CMOS -> near-ideal square-wave modulator
o 1/ƒ noise can be completely removed
o Ƒch > 1/ƒ corner frequency

4
CHOPPER AMPLIFIER
 Chopping usually does not introduce

extra noise, especially when the choppers
are positioned at low impedance nodes.
 In the situation of the Figure, for instance,
the main noise source is the on-resistance of
the input chopper.
 Thus, by making this low enough, its noise
contribution can be made negligible.

5
CHOPPER AMPLIFIER
 The effective DC gain of the opamp is

equal to the gain of Gm1 at fchop, which is
usually much lower than its gain at DC.
 Thus, to ensure sufficient gain, multiple gain
stages are often employed.
 In a two-stage opamp, for instance, the (a)
output chopper (CHout) can be located at

the input of the second stage, as shown in
Figure (b).
 The amplifier’s effective DC gain is then the
gain of Gm1 at fchop multiplied by the DC
gain of Gm2.
(b) Schematic of a two-stage chopper opamp

6
ANOTHER PROBLEM: LARGE DC COMMON-MODE SIGNAL
 In many measurement situations, the signal of interest is small,

possibly in the range of tens of microvolts, and is superimposed on a
much larger DC common-mode (CM) signal, possibly in the range of
several volts.
 Coping with such a large CM signal and at the same time accurately
measuring such small signals is a big challenge for interface circuits.
 A good example of such a measurement is in high-side current sensing
[85], as shown in Fig. 1.1, where the load current of a battery is
monitored by inserting a small sensing resistor Rsense in series with the
battery.
Fig. 1.1 of [86]: A simplified schematic of a
 This requires a readout amplifier with low offset and low 1/f noise. high-side current-sensing readout circuit.
Moreover, Vsense is accompanied by a large CM voltage, which can be
as large as 30V in the case of a laptop battery.
 This is far beyond the supply voltages of normal CMOS circuitry.  Also, recall the monopolar
 Thus, novel circuit techniques to reject this large CM voltage and stimulation example of ours
accurately measure Vsense must be found. produced a CM voltage of
 This problem becomes more challenging as CMOS technology 665mV at the recording
advances, since this has historically been accompanied by a steady electrode inputs!
decrease in supply voltages.
[86]

7
LARGE DC COMMON-MODE SIGNAL  TRADITIONAL
SOLUTIONS (1)
 Readout system employing magnetic coupling shown in Fig. 1.2

consists of an input and output modulator, a transformer, and a
readout amplifier.
 In this case, the modulators are implemented as choppers, i.e.,
polarity-reversing switches driven by a digital clock signal with a fixed
frequency (fchop).
 The choppers are also driven via an isolating transformer. The input
chopper converts the DC differential voltage Vsense into a square wave,
and the output chopper converts the amplified square wave back to
DC. Fig. 1.2 of [86]: A schematic of magnetic
isolation readout circuit for current
 In this way, the differential signal is first modulated to high frequency
sensing application.
by the input chopper and so can be coupled to the input of the readout
amplifier via a transformer.
 The DC CM voltage, however, will not be modulated and thus
will not be coupled to the readout amplifier. Note: the DC CM
input doesn’t induce any current at the transformer primary,  A big disadvantage of this approach,
whereas the differential DC does! however, is that transformers are
 Furthermore, the offset and 1/f noise of the readout amplifier will be difficult to integrate on chip.
up-modulated by the output chopper and so can be filtered out. [86]

8
SOLUTIONS (2)
 A second approach involves isolating the DC CM voltage

optically, e.g., with an opto-isolator. Although there are many
types of opto-isolator, the most common type simply consists
of an LED and a photodiode as shown in Fig. 1.3.
 The LED is connected to the input signal and converts it into
an optical signal, which is then picked up and converted back
to an electrical signal by the photodiode and a readout
amplifier.
 In this way, the input CM voltage is completely isolated from Fig. 1.3 of [86]: Schematic of CM
isolation with opto-isolator.
the readout amplifier.
 The main disadvantage of this approach, however, is its lack
of accuracy. The signal transfer function between the LED
and the photodiode depends on several parameters such as
the voltage-to-light transfer function of the LED, the intensity
of the light picked up by the photodiode, and the light-to-
voltage transfer function of the photodiode.
 Thus, the accuracy of the measurement, especially the [86]
system’s overall gain, is not well defined.

9
SOLUTIONS (3)
 A third approach, which is the most commonly

used, is to isolate the CM voltage electrically. A
simple way to do this is to use the basic
differential pair shown in Fig. 1.4.
 Neglecting circuit non-idealities, the input
differential pair acts as an ideal voltage to
current converter, which floats between the tail Fig. 1.4 of [86]: CM isolation with
basic differential pair.
current source and a potential close to ground.
Since it is only sensitive to the input differential  A big disadvantage of
signal, the CM signal is completely isolated this approach, however,
from the rest of the circuit (assuming ideal tail is that handling a large
CM voltage requires a
current source and perfect matching). large supply voltage and,
 In reality, however, circuit non-idealities such consequently, high-
as mismatch will significantly decrease the voltage input transistors [86]
measurement accuracy. in the input stage.
10
SOLUTIONS (4)
 To improve this, the chopping technique can again be

applied as shown in Fig. 1.5.
 Since the input chopper only modulates the differential
input signal, its contribution to the output voltage is
separated from that of the CM signal in the frequency
domain.
 The offset and 1/f noise are also up-modulated and so are
removed from the base band.
Fig. 1.5 of [86]: CM isolation with
 However, the maximum CM voltage that can be handled is chopper differential pair.
determined by the differential pair’s supply. So handling a
large CM voltage requires a large supply voltage and,
consequently, high-voltage input transistors in the input
stage. This increases the power consumption considerably.
 Moreover, the limited output impedance of the input
transistors will reduce the circuit’s CM immunity, while their
offset and 1/f noise will reduce its DC precision. Finally, the
common-mode voltage range (CMVR) of the circuit shown in [86]
Fig. 1.5 will not cover both the negative and positive rails.

11
SOLUTIONS (5)
 Another approach to isolate the input CM voltage is

to use a so-called flying capacitor [87] to sample and
hold the input signal, as shown in Fig. 1.6.
 The CM voltage at the input of the succeeding
amplifier is set by a feedback resistor network
and so it can be realized with low-voltage
circuitry.
Fig. 1.6 of [86]: Schematic of CM isolation
 However, the kT/C noise associated with the sample- with the flying capacitor.
and-hold action of the flying capacitor increases the
total input-referred noise.
 Moreover, continuous-time operation is not possible.
Last but not least, the input switches must once
more be able to handle the large CM signal.
 From the above introduction, it seems that none of
these approaches is very satisfactory. Thus, a new [86]
approach is required.
12
A PROMISING SOLUTION: CAPACITIVELY COUPLED
CHOPPER AMPLIFIER (1)
 An intuitively appealing solution to the

Rb1
problem of CM isolation is the use of
capacitive coupling.
 Capacitors are widely available in most standard
CMOS process and exhibit a natural ability to block Rb2
DC signals without any extra power consumption.
 Thus, a capacitively coupled amplifier will Fig. 1.7 of [86]: Schematic of a
perfectly reject DC CM voltages, as long as they capacitively coupled amplifier.
are smaller than the breakdown voltage of the
coupling capacitors (Fig. 1.7). Although the
breakdown voltages of on-chip capacitors is usually
less than 100 V, this is still sufficient for many
applications.
 However, it is also obvious that the DC input
signal is also blocked due to the high-pass [86]
filtering made with Cin1,2 and Rb1,2.
13
CHOPPER AMPLIFIER (1, CONT’D)
 Recall the differential capacitively coupled

amplifier shown in Figure (a) has a natural (a)
large CM rejection ratio figure.
 However, it amplifies the differential signal well
(not the DC input as it is high-pass filtered).
 This is true even w/o Rf in its feedback i.e. the Figure: Schematic of a fully differential
circuit shown in Figure (b). capacitively coupled amplifier.
 Note: the capacitive coupled amp of Figure

(b) also amplifies the differential DC signal
𝒔𝑪𝒊𝒏 (b)
as its transfer function is .
𝒔𝑪𝒇
Although in simulation due to difficulty to bias
the virtual grounds it could be hard to observe it. [86]

14
 One solution to unblock the DC input in the

capacitive coupling is to use the chopping
technique described in the previous sections to up-
modulate the input signal. This has the added
advantage of suppressing the offset and low 1/f noise
of the input stage.
 However, the concept of capacitively coupled chopper Fig. 1.8 of [86]: Schematic of a
amplifiers is not new! As early as 1940, the classic capacitively coupled amplifier.
capacitively coupled chopper amplifier shown in Fig.
1.8 was invented [88].
 The input signal is up-modulated by the input  Note: its is assumed
chopper, amplified, and finally de-modulated by the
output chopper.
that Vs is composed
 However, the CM voltage is also modulated of both differential
and so no CM isolation can be obtained. and DC CM signals. [86]

15
 The differential structure, as shown in Fig. 1.9, changes the story
completely.
 The input chopper modulates the DC differential signal to high
frequencies, which can then travel through the input
capacitors.
 The DC CM signal, however, is blocked.
 As a result, the input CM level of the succeeding amplifier can be fixed
arbitrarily via biasing resistors R1,2 and so the amplifier can be
Fig. 1.9 of [86]: Schematic of a classic
implemented with low-voltage circuitry.
fully differential capacitively coupled
 At the amplifier’s output, an output chopper demodulates the signal chopper amplifier.
back to the base band. The offset and 1/f noise of this amplifier,
however, are blocked/filtered by the output capacitors.
 Note: the input current paths to
 To prevent its output from saturating, the gain of the amp inputs are through chopper
(transconductance) amplifier is limited by the output resistors Rout1,2.
However, the amplifier cannot be used as an operational amplifier switches, Cin1,2, Rin1,2, Vref
(opamp) due to its low gain or an instrumentation amplifier (IA) due to voltage source to ground.
its inaccurate gain (Gm1*Rout1,2).  Note: it is assumed that Vinp &
Vinn inputs are composed of both
differential and DC CM signals. [86]

16
REGULAR OR CHOPPER CAPACITIVELY COUPLED
AMPLIFIERS RESPONSE TO EOV
 Recall for neural recording EOV
(electrode offset voltage), so called (a)
electrode polarization is in order

of 50mV, whereas the neural signal
in order of 1mV or smaller.
 Note: EOV is a differential DC
input (not CM DC)!
 It should be noted either the (b)
regular capacitively coupled
amplifier shown in Fig. (a), or
the chopper capacitively coupled
amplifier shown in Fig. (b),
amplifies the EOV offset.
 Creating a high-pass pole for the
regular capacitively coupled (c)
amplifier shown in Fig. (c), by
placing Rf in its feedback, the
EOV is rejected! [86]

17
 In 2007, the first capacitively coupled chopper
instrumentation amplifier (CCIA) was described by
Timothy Denison [56]. It is shown in Fig. 1.10.
 This work represents a great improvement on Fig.
1.9 topology. By eliminating the need for Rout1,2 and
Cout1,2, the open-loop gain of the amplifier can be
quite large.
 A chopped capacitor feedback path ensures that the
gain of the IA is accurately defined as Cin1,2/Cfb1,2.
 Since the amplifier was intended for biomedical
applications, a DC servo loop was employed (an SC
integrator and Chp1,2) to give it a high-pass
characteristic.
 The up-modulated offset and 1/f noise of Gm1 was Fig. 1.10 of [86]: Block diagram of the first
suppressed by a second stage (not shown) which CCIA: from Timothy Denison [56].
acts as a low-pass filter.
 Although not designed for high input CM voltages,
this CCIA demonstrated the feasibility of realizing
on-chip capacitively coupled precision IAs.
[86]

18
OPEN-LOOP CHOPPER AMPLIFIER DRAWBACKS
 The primary issue in Open-loop Chopper Amplifier is the

finite bandwidth of the signal chain creating signal errors:
distortion (even harmonics at the chop frequency) and so
sensitivity errors.
 The sensitivity (precision) of a chopper amplifier with ideal gain 𝐴
is reduced to an effective gain of 𝐴 (1 − ) (to be proved later),
where 𝜏 is the time constant of the amplifier and 𝑇 is the chopper
period.
 This issue can be particularly bad in micropower

amplifiers, where the amplifier has a limited bandwidth
product compared with the lower limit dictated by the 1/f
noise corner frequency.
 Meaning the amp BW has to be high enough (greater than
FCH + Signal BW/2) in order to pass/amplify the modulated
(upconverted) baseband signal to FCH. Fig. 4 of [56]
[56]
(T. Dension, JSSC’07)

19
 Robust open-loop (referred to not having a global feedback

to be introduced shortly, and not to the local feedback for
the A0 itself) chopper architectures can require a gain
bandwidth product approximately 10 times greater
than the signal BW (NFP for example) application
demands
o The excessive power burden to implement chopper stabilization then
makes it impractical
 With the open-loop architecture offsets is amplified

prior to chopping and low-pass filtering so the
headroom requirement is in conflict with low supply
designs
o The amplified offset signal at VA’ requires limiting
the front-end gain to avoid saturation, which can
undermine performance by making second-stage noise [56]
contribution significant.
20
Recall C1=Cin, C2=Cf , R2=Rf
 Effect of opamp limited bandwidth on the f f
total gain for a DC input (note of the ideal

DC gain being 𝑨𝒐𝒑𝒂𝒎𝒑):
𝐴
𝐴 𝑠 =
1 + 𝑠𝜏
Note: as shown in the figure 𝐴 =𝐴 = Effect of opamp limited bandwidth on the total gain
of the chopper amplifier, in time domain [64].
(passband gain), and
𝜏= = = ( ),
𝜏 is the amp signal bandwidth so the signal excursion

at the output of the opamp is limited to ±𝑉 and its
value is (b)
Output curve of the chopper amplifier shown
in Fig. 3.10 after (a) the opamp (red curve) and
(a) (b) after the output choppers (blue curve) and [64]
𝑉 =𝐴 𝑉 the low-pass filter (brown curve) [64].

21
Recall C1=Cin, C2=Cf , R2=Rf
 To calculate the filtered signal, the DC content of f f
the demodulated curve should be calculated

(through integration in TM/2 period):
𝑉 𝐴 4 4
𝑉 = (𝑇 + 𝑒 𝜏− 𝜏)
𝑇
1+𝑒 1+𝑒
Given 𝟐𝝉 ≪ 𝑻𝑴 one can obtain:
Effect of opamp limited bandwidth on the total gain
𝟒𝝉 𝟒𝝉 of the chopper amplifier, in time domain [64].
𝑮𝒂𝒊𝒏𝒄𝒉𝒐𝒑𝒑𝒆𝒓 = 𝑨𝒐𝒑𝒂𝒎𝒑 (𝟏 − )  error=
𝑻𝑴 𝑻𝑴
 For error0.01 (1 percent) then: 𝑓 ≥ , for 𝑓

= 400kHz, : 𝑓 ≥ 255kHz (also recall for LFP, the signal BW
is only 100Hz, and UGBW=10kHz for 𝐴 =𝐴 =

(b)
= 100). Output curve of the chopper amplifier shown
in Fig. 3.10 after (a) the opamp (red curve) and
 The excessive power burden to implement (a) (b) after the output choppers (blue curve) and [64]
the low-pass filter (brown curve) [64].
chopper stabilization then makes it impractical
22
for neural recording applications!
[56]
 As proven before and seen in

the Figure, the effective gain of
the open-loop chopper amp is
𝟒𝝉
𝟎 instead of 𝟎.
𝑻𝑴
 There is also a finite ripple at

the output.
Fig. 4. of [56]: Distortion and headroom problems encountered with an
open-loop low-power chopper-amplifier architecture, assuming a dc input.
Note that, to simplify the figure, the ac offset signal at VB is not shown.

23
CLOSED-LOOP CAPACITIVELY-COUPLED CHOPPER
AMPLIFIER DESIGN
 The proposed chopper architecture circumvents the
major issues of low power designs by using closed-
loop feedback with specific timing constraints. A0
 To illustrate this concept, the proposed signal flow

graph for an amplifier responding to a step is
illustrated in the Figure.
Fig. 5. of [56]: Feedback of up-modulated signal significantly
 Feedback is a well-known technique to suppress suppresses distortion and increases headroom.
distortion and increase precision in circuits.

 The implementation of feedback in this
micropower application, however, required two
design paradigms, explained in the following
slides.
[56]

24
CLOSED-LOOP CHOPPER AMPLIFIER DESIGN PARADIGMS
1) Input and feedback paths around the amplifier are

ac signals (capacitively-coupled) and up-modulated
to the chopper modulation frequency. A0
o The ac feedback (meaning the output signal modulated or

upconverted) ensures that all signals passing through the
front-end of the amplifier are well above the 1/f corner for the
transistors.
o Using ac modulation (modulation done with cross switching
Fig. 5 of [56]
the caps) also allows for input and feedback signal chain
scaling to be achieved with low-noise, on-chip capacitors as
opposed to resistors that potentially draw excess power and
add noise to the signal chain;
o Fig. 5 of [56] applies this ratio by the scaling factor 1/𝐴 (as
an example where the UGBW of the loop is normalized to 1,
in actuality the loop gain can be arbitrary designed) in the
feedback path.
[56]

25
CLOSED-LOOP CHOPPER AMPLIFIER DESIGN PARADIGMS
2) Chopper modulation throughout the signal chain is

designed such that switching dynamics are much
faster than the chopper period. A0
o At the input and feedback nodes Vin and Vout, the effective
time constant of chopper settling is constrained to be orders
of magnitude smaller than the chopper period.
o Within the forward amplifier path, fast modulation is
performed by steering currents within the transconductance (T. Dension, JSSC’07)
stage prior to integration and loop compensation (to be shown
later).
o By partitioning the forward path such that modulation
occurs prior to integration, the steady-state signal is
minimized which helps further suppress distortion.
o Chopping the amplifier is possible at higher frequencies (e.g.,

4 kHz in [56]), being substantially above the gain-bandwidth
[56]
product for the overall feedback loop.

26
CLOSED-LOOP CHOPPER AMPLIFIER DESIGN  MORE
IMPROVEMENTS OVER OPEN-LOOP: SMALLER NODE DYNAMICS
 As shown the signal dynamics at different nodes of the

feedback loop i.e. VA, VA’, and VB are reduced
compared to open-loop scheme improving linearity.
 The net sensitivity error is set to first-order by differences in
the settling time constants in the input and feedback paths:
𝜀= , where 𝑇 is the chopper clock period and 𝜏 , 𝜏 are

the settling times of the input and feedback switching paths.
 At the output, the residual ac offset signal is reduced to
𝑉 , where 𝒇𝟑𝒅𝑩 is the low-pass corner of the
feedback loop, 𝐴 is the net gain, and 𝑓 is the chop Fig. 5. of [56]: Feedback of up-modulated signal significantly
suppresses distortion and increases headroom.
frequency. In [56] implementation example these values are
0.25 Hz, 20 V/V, and 4 kHz, respectively, resulting in offset [56]
ripple of 0.002 × 𝑉 .
27
AMPLIFIER DESIGN An integrator is drawn by error in the
original block diagram in Fig. 6 of [56].
 The amplifier summing node VA receives a

differential signal input scaled by the capacitor
Cin, which is balanced by two feedback networks.
 The path through Cfb sets the midband gain for
the amplifier.
 The path through the feedback integrator and Chp
sets the high-pass corner for the amplifier.
 Note that these feedback paths are always
negative; when the polarity around the
amplifier shifts, the internal chopper
modulation within the trans-conductor also
[56]
changes sign to maintain loop stability. (T. Dension, JSSC’07)

28
AMPLIFIER ADVANTAGES
 Perhaps the greatest advantage of this design is the use
of ac modulation in the input and feedback paths,
which allows for the front-end gain to be set with on-
chip capacitor ratios with excellent noise and
linearity properties, instead of requiring high-value
on-chip resistors.
 Making use of the global feedback to a summing node
(for LP filtering):
 The forward path’s transconductor and integrator can run
with low supply overhead to aid in minimizing power
without sacrificing noise performance.
 Allows for larger front-end gain by filtering the up-
modulated offset with a first-order low-pass filter.
 The need to suppress electrode polarization, however, sets [56]
a practical upper limit on the front-end gain.
29
AMPLIFIER DESIGN - EXAMPLE
 The values of the design in [56]:
o Cin=15pF & with fchop=4kHz  (Rin_diff=1/(2fch*Cin),
shown later) > 8M to avoid loading the electrodes!
o The midband gain of the chopper amplifier is then
determined by the ratio of the feedback capacitors
Cin, to Cfb i.e. Cin/ Cfb. 
o G1=20  Cfb=750fF, and for
o G1=60  Cfb=250fF.
 To set the single-ended amplifier output voltage,

the voltage to Cfb is switched between the
amplifier output and a reference potential Vref. [56]

30
AMPLIFIER  HIGHPASS FILTER CAP
 A highpass filter function can be implemented
by making use of a lowpass filter (integrator) in
the feedback loop as shown in the figure:
𝐻 𝑠 = where 𝐿(𝑠) is the loop gain.

( )
 Since 𝐿(𝑠) is a low-pass filer (integrator here)

and its gain at low frequencies is high (very high
for integrator) makes 𝐻(𝑠) small there. And since
𝐿(𝑠) is small at high frequencies 𝐻(𝑠) approaches
to there. Thereby this feedback loop creates a
high-pass frequency response! [56]


31
AMPLIFIER  HIGHPASS FILTER CAP
 Several design constraints must be considered in
the high-pass design.
 The first constraint is the scaling of the capacitor Chp,
which is dictated by the dc polarization headroom
that must be blocked by the amplifier. In the steady
state, the charge induced on VA from the input
modulation through must be countered by the feedback
capacitor Chp. This constrains the available headroom
/
with a single-ended feedback to 𝑉 , =± or
actually writing the charge equation:

𝐶 𝑉 , =𝐶 (±𝑉 /2).
 Therefore, to ensure 50mV (from dc polarization of
PtIr electrodes in that example) of headroom with
a 2V nominal supply, the value of Chp must be greater
than or equal to 750fF for single-ended feedback paths.
[56]

32
CCIA – GAIN REVERSAL & Phases
Cfb1 CH3
Vinp
Cin1 Vop Voutp
CH1
CH2
Vinn
CH2
CH1 Von Voutn
Vinp Cin2
CH3
Cfb2
𝑉 −𝑉 𝐶 𝑉 −𝑉 𝐶
𝐺𝑎𝑖𝑛 = =− 𝐺𝑎𝑖𝑛 = =+
𝑉 −𝑉 𝐶 𝑉 −𝑉 𝐶

33
ANALYSIS USING THE CHARGE CONSERVATION – ASSUMING IDEAL OTA
 Assuming fully differential balance case with identical CM voltages at

the input, virtual ground, and the amplifier output,
 And assuming ideal OTA (gain and BW of infinity) so the virtual

grounds are ideal,
 As shown in the figure below switching Cin between Vinp=Vcm+Vi and

Vinn=Vcm-Vi, and assuming the initial charge in the closed Gaussian
surface in blue is zero, results in the following output voltages at
phases 1 and 2 as follows:
𝐶 𝑉
𝑉 , =𝑉 −
𝐶
𝐶 𝑉
𝑉 , =𝑉 +
𝐶

34
CCIA – DRAWBACKS: FINITE INPUT IMPEDANCE
Low input impedance!
=>
 Assuming ideal virtual ground for OTA, and for DC input (or held input during a chopping period):
Phase 1 (@ t=T/2): 𝑄 , = 𝐶 (𝑉 − 𝑉 ), 𝑄 , = 𝐶 (𝑉 − 𝑉 )
Phase 2 (@ t=T): 𝑄 , = 𝐶 (𝑉 − 𝑉 ), 𝑄 , = 𝐶 (𝑉 − 𝑉 )
 Therefore: there is an average current from 𝑉 to 𝑉 during a chopping period for each 𝐶 , branch as follows (note that
assumed 𝑉 and 𝑉 are not changed from phase 1 to phase 2):
, , ( )
𝐼 , = = =𝑓 𝐶 (𝑉 −𝑉 ) (1) resulting in 𝑅 = =
,
 Equation (1) and the left figure indicate that there is an equivalent resistor between 𝑉 to 𝑉 due to both 𝐶 and 𝐶
being in parallel resulting in the overall resistance between 𝑉 to 𝑉 as follows: 𝑅 =𝑅 𝑅 =

35
ANALYSIS OF THE CHOPPER SWITCHES PRECEDING CAP
 It can be proved that the Laplace transform of a periodic signal

is:
()
 is the Laplace transform of the first period of the time
function . The eqn. () represents the periodicity property of
the Laplace transform. The corresponding signals for the input
chopper switched cap are shown below:

36
(CONT’D)
 The first period of the time function shown in (a)
red is as follows:
 Therefore: , and
consequently: (b)
 From which the first period of the time function (c)

shown in blue is derived:
 Repeating with period of T gives .

 The factor 2 in is for being fully differential! (d)

37
(CONT’D)
(a)
 Obviously there is a current from either
input nodes Vinp (or Vinn) into (or from)
the amplifier virtual ground.
 These currents has a very high frequency
behavior which in the ideal case is Dirac
function. (b)
 The current to/from the OTA virtual ground

goes through the feedback network changing (c)
the amplifier output voltage accordingly.
(d)

38
(CONT’D)
(a)
 Although the currents ideally have high frequency
behavior, one can obtain the average DC (low) frequency
equivalent for them:
1 2𝐶 𝑉
𝐼 , = 2𝐶 𝑉 𝛿 𝑡 − 𝑛 − 1 𝑡 . 𝑑𝑡 =
𝑇 𝑇
Note: 𝑉 = 𝑉 + 𝑉 and assumed the OTA virtual ground at
𝑉 .
(b)
 Therefore, an equivalent DC (low) frequency resistor
between 𝑽𝒊𝒏𝒑 and the OTA virtual ground can be
found as: (c)
𝑽𝒊𝒏𝒑 − 𝑽𝒄𝒎 𝑽𝒊 𝟏
𝑹𝒑,𝒂𝒗𝒈 = = =
𝑰𝒑,𝒂𝒗𝒈 𝟐𝑪𝒊𝒏 𝑽𝒊 𝟐𝒇𝒄𝒉 𝑪𝒊𝒏
𝑻
 Similarly there is an equal average current from the OTA
virtual ground to 𝑉 (opposite direction), and as a result
an equal equivalent DC (low) frequency resistor between (d)
𝑉 and the OTA virtual ground, respectively.
39
(CONT’D)
 It should be noted that this
Cfb1 CH3
equivalent resistor is a model only & Phases
for DC (low) frequency, and as Cin1

Vinp CH1 Vop Voutp
such it can not be used to obtain
CH2
the transfer functions.
CH2
Vinn
CH1 Von Voutn
Cin2
 However, for simple DC (low)
frequency calculations this Cfb2
CH3
resistive model indeed works and
simplifies the analysis.

40
(CONT’D)
 The spike currents: (a)
1) 𝐼 : the decomposed spike currents of 𝑖(𝑡) shown in
green in Figs. (b) & (c), drawn from 𝑉 to the OTA
virtual ground. (c)
2) 𝐼 : the decomposed spike currents of −𝑖(𝑡) shown in
brown in Figs. (b) & (c), to 𝑉 from the OTA virtual 𝐼 = −𝑖 (𝑡)
ground.
 Note that the current spikes 𝐼 & 𝐼 occur at (b)
different times. Therefore, one can not substitute them
with an equivalent spike current from 𝑉 to 𝑉 .
 However, their equivalent averages i.e. 𝐼 , and 𝐼 = −𝑖 (𝑡)
𝐼 , can be modeled with DC (low) frequency
currents as shown in the figs. (d) & (e). Average currents
(e) Vinp
 Having used this model is like that there is an
2𝐶 𝑉
Iinp,avg
average current 𝑰𝒊𝒏,𝒂𝒗𝒈 from 𝑽𝒊𝒏𝒑 to 𝑽𝒊𝒏𝒏 as shown 𝐼 , =
𝑇
in the figure (d) instead:
𝟐𝑪𝒊𝒏 𝑽𝒊
Iin,avg Vcm (d)
𝑰𝒊𝒏,𝒂𝒗𝒈 = 𝑰𝒊𝒏𝒑,𝒂𝒗𝒈 = 𝑰𝒊𝒏𝒏,𝒂𝒗𝒈 = 𝐼 =−

2𝐶 𝑉
𝑻 ,
𝑇
Vinn Iinn,avg
41
(CONT’D)
 Therefore, an equivalent resistor between (a)
and can be defined as follows:
 In a fully differential amplifiers there are

two caps, , connected to and
inputs.
 Thereby, there are two in parallel Average currents
Vinp
between and resulting in a total Iinp,avg
input DC (low) frequency impedance of 2𝐶 𝑉
𝟏 𝐼 = Iin,avg Vcm (d)
due to chopper capacitively ,
𝑇
𝟐𝒇𝒄𝒉 𝑪𝒊𝒏
coupling amplifier. Vinn Iinn,avg
42
(CONT’D)
 Solving this, now considering the switches non-zero (a)
resistance ( ) gives for the filter made by

and (note that the filtering effect of the OTA
is much more limiting), and so the waveform
swing between and : (b)
 Obtain and i.e. the first period of the

time functions for the voltage at the input cap top
plate and the input cap current, respectively. From
which can be readily derived.
 As seen the real spike currents are still high (c)
frequency but the DC (low) frequency resistance
model used for the ideal Dirac function are still
valid for low frequency modeling purpose.

43
CCIA – DRAWBACKS: FINITE INPUT IMPEDANCE
 Charge and discharge the input capacitor => Switch-cap impedance

Zin=1/ƒch(2Cin)=1/(2ƒch2Cin)
 Note in the previous diff case as shown below the overall input cap is assumed 2Cin.
 However, if each branch cap is assumed 2Cin, meaning the diff cap is 4Cin, then the
equivalent input impedance is Req=1/[fch*(4Cin)]=1/(4fch*Cin).

44
AMPLIFIER  OVERALL LOOP UGBW
 The overall loop gain can be obtained by breaking
the loop from the output of the integrator (here
made by a switched-cap circuit with their Csamp and
Cint shown in the Figure):
𝐶 1 𝐶 1
𝐿 𝑠 = =
𝐶 𝑠𝑅 𝐶 𝐶 𝑇 Overall Capacitively-coupled Chopper Amplifier
𝑠 𝐶 𝐶
𝐶 𝑓 𝐶
=
𝐶 𝑠𝐶
 Thereby the unity frequency of the overall loop
transfer function approximately is:
Switched-cap integrator for HP filter
𝐶 𝑓
𝑓 = ( 𝐶 ) [56]
𝐶 2𝜋𝐶 (T. Dension, JSSC’07)

45
AMPLIFIER  OVERALL LOOP UGBW
 Although the sampled-data switched-cap
filter/integrator is subject to aliasing and kT/C
noise, by sampling after the front-end’s low-
pass filtering that aliasing is suppressed (note
that transfer function from any amp inputs to
Overall Capacitively-coupled Chopper Amplifier
the output of the amp is low-pass filtered).
 The sampling of the high-pass loop is

performed at twice the chopper frequency to
cancel out the up-modulated offset ripple from Switched-cap integrator for HP filter
the chopper amplifier by averaging the two [56]
phases of the ac ripple.
46
AMPLIFIER  NET TRANSFER FUNCTION
 The net signal transfer function of the chopper amplifier is
(assuming ideal opamp):
𝐶 𝐶 𝐶
𝐶 𝐶 𝐶
𝐻 𝑠 = = = 𝜔
1 + 𝐿(𝑠) 𝐶 𝑓 𝐶 1 +
1+ 𝑠
𝐶 𝑠𝐶 Overall Capacitively-coupled Chopper Amplifier
The above expression shows a 1st order HPF that can also be
expressed as: 𝐻 𝑠 = , where 𝜔 = .
 Thereby the highpass corner frequency is:
𝑓 = --> Note: this is the same as the unity

frequency of the overall loop transfer function i.e. the frequency Switched-cap integrator for HP filter
at which the 1/gain of the amp Chp path is equal to that of the [56]
integrator.
47
AMPLIFIER  NET TRANSFER FUNCTION
 See the design example and practical challenges/issues:
 With chopper amp gain of 40dB ( = 100V/V, 𝐶
= 15pF, and 𝐶 = 150fF) to make a pole at 0.05Hz: for =5
and 𝑓 = 4kHz, the ratio for must be 64000! This

requires 𝐶 = 1nF and 𝐶 = 15fF which has poor yield and
unacceptable sensitivity to process variation as well as large Overall Capacitively-coupled Chopper Amplifier
area for 𝐶 cap.
 With chopper amp gain of 20 ( = 20V/V, 𝐶 = 15pF, and 𝐶

= 750fF) to make a pole at 0.05Hz: and 𝑓 = 4kHz, the ratio
for must be 12,800. For which the following values
chosen in [56]: 𝐶 = 768𝑝F and 𝐶 = 60fF. Still small cap
of 𝐶 could be an implementation issue which is Switched-cap integrator for HP filter
equivalent with a resistor value of 4.2G! (see
implementation details in [56]). [56]

48
[56]
AMPLIFIER  REMAINED CHALLENGING ISSUES
 Advantages:
 Improved CMVR (Common-mode Voltage Range)
 The opamp inputs don’t see the input CM swing!
 High DC precision Overall Capacitively-

coupled Chopper Amplifier
 Challenges:
1) Input chopper (switches) must handle the high CM voltage present before the input capacitors.
2) The input impedance of the amplifier is also an issue. Since the input capacitors are constantly switched
between Vin+ and Vin−, they are constantly being charged and discharged, which requires a certain amount
of input current.
 Thus, techniques to boost the input impedance are required.
3) The input DC CM voltage is blocked. So the DC CM level of the amplifier’s input stage must be fixed by
something else. Note: input SC circuit blocks the DC voltage at opamp virtual ground from that of input.
 The amplifier’s input stage DC voltage can be set using biasing resistors. However, as will be shown later, these
resistors introduce noise, and so must be rather large (hundreds of megaohms).
 Thus, another challenge is that of realizing such large resistors in an area-efficient and relatively accurate manner.
4) The amplifier’s offset will be up-modulated by the output chopper and results in ripple.
49
CCIA- TRANSFER FUNCTION Cfb
Cin
 Replacing the SC choppers in Figure (a) with their equivalent circuit in Figure (b) Vin
at a given phase and assuming the first-order pole model for the OTA:
A0/(1+s )
Vout
+ = 0 where 𝜏 =
,
Writing for the input-output transfer function: (a)

𝑉 𝐴 1
=− Cfb
𝑉 𝐶 𝐶
1+ (1 + 𝐴 ) 𝑠𝜏(1 + )
𝐶 𝐶
1+ 𝐶
1+ (1 + 𝐴 ) Cin
𝐶 Vin
For 1+𝐴 ≫ 1, and for 1 + ≈ 1 (note that = 0.01 for the passband gain of 100),
we have:
A0/(1+s )
Vout
=− =− =−
× , (b)
,
where 𝜔 , =𝐴 ×𝜔 ,
 Therefore, the input-output low-pass frequency is: 𝑓 = 𝑓, which is the

upper corner frequency.

50
CCIA- BIASING
Cfb
 Amplifier virtual ground is not defined at DC
Cfb
(T. Denison, JSSC’07)
Vin Vout
Vin Vout A
A Cin
Cin  To reduce the HP cut-off frequency  Giga ohm resistor for Rb
Rb  Low noise  Giga ohm Resistor for Rb
Vref  High impedance node  Common mode settling (see Q. Fan Book p. 32)
1) Recall: there is a high-pass filter due to Cin and Rb(pole at 𝑓 = ):
, ( , , )
• As was shown before for the without chopping case, for instance for Cin=20pF and Cpin=1pF, to achieve fHP 1Hz 
Rb  8G.
• However, with chopper at the input since the input stage is chopped, it handles signals at the chopping frequency fchop.
And so the high-pass corner of Gmin should be designed well below fchop (say 10x smaller, for example for fchop=3kHz
at 300Hz), so that the effective input transconductance will be roughly equal to Gm1 (the input transconductance).
Therefore, compared to w/o chopper case, the requirement for Rb is much more relaxed, in this example by 300x to
27M!
51
CCIA- BIASING
Cfb
 Amplifier virtual ground is not defined at DC
Cfb
(T. Denison, JSSC’07)
Vin Vout
Vin Vout A
A Cin
Cin  To reduce the HP cut-off frequency  Giga ohm resistor for Rb
Rb  Low noise  Giga ohm Resistor for Rb
Vref  High impedance node  Common mode settling (see Q. Fan Book p. 32)
2) For low thermal noise contribution of Rb, say resulting in less than 10nV/Hz input-referred noise, for Cin=20pF,
and fchop=10kHz then: Rchop = 1/(2*Cin*fchop) = 2.5M  The current noise model for 𝑅 is that, when referred
back to the input through the input capacitors impedance at the chop frequency, yields the net noise:
𝑉 =𝑖 , 𝑅 , = , (in other word this 𝑉 input noise creates the same amount of current noise at
×
, . × . ×
the amplifier input node). Therefore, for 𝑉 ≤ 10nV/Hz  𝑅 ≥ = = 1𝐺Ω.
×
52
CAPACITIVELY-COUPLED CHOPPER INSTRUMENTATION
AMPLIFIER (CCIA)
 Capacitively-Coupled Chopper IA (CCIA)
 DC->AC then AC->DC

 Low offset
Cfb
 1/f noise
 CMRR Vin Vout
A
Cin
[56]

53
CCIA – DRAWBACKS: RESIDUAL OFFSET
 Charge injection and clock feedthrough -> input spikes

 A residual offset of a few µV typically remains as a result of charge
injection by the modulator switches which, when demodulated,
contains a DC term
 Since injected error charge is constant per chopping clock period,
residual offset is proportional to chopper frequency.
 Residual offset ∝ ƒch => So what should we do?

54
GENERAL CHOPPER AMPLIFIER CHALLENGES
o Residual offset
o Finite input impedance
o Output ripple

55
CCIAS (CAPACITIVELY-COUPLED CHOPPER
INSTRUMENTATION AMPLIFIER) WITH DC SERVER LOOP
CDS
 Plotting the SC choppers in Figure (a) with the circuit
in Figure (b) at a given phase and assuming an ideal Cfb
OTA with gain of infinity:
Cin
(a)
𝑠𝐶 𝑉 + 𝑠𝐶 𝑉 + 𝑉 × 𝐾/𝑠 × 𝑠𝐶 = 0 where 𝐾 = 𝜔 , Vin
From which the ideal transfer function is as follows: A0

Vout
=− where 𝑓 = 𝑓,
( ) ,
CDS
K/s
 Obtain the transfer function for A s = where Cfb
𝜏= (for simplification once can use A s = ,

) (b)
, Cin
Vin
 It will be shown for a very low HP corner A0
𝑪 Vout
frequency of less than 1Hz, since 𝑫𝑺 is about 1 or
𝑪𝒇𝒃
2, 𝒇𝟎,𝒊𝒏𝒕 has to be less than 1Hz!

56
 DC servo loop (DSL) creates a high-pass characteristic that Cfb

effectively blocks electrode offset (10s of mV).
𝐶 CDS Vin Vout
𝑓 = 𝑓, , ∫
𝐶 A
𝐶 Cfb Cin
𝑉 _ _ = 𝑉
𝐶
Vin Vout
A First time by (T. Dension, JSSC’07): [56]
Also later by (Q. Fan, ASSCC’10): [68]
Cin
 Where 𝑓 , , is the unity-gain frequency of the integrator in the DSL. 𝑓 is set to
0.5Hz for bio-signals such as ECG/EEG signals.
 The values of 𝐶 (or 𝐶 ) is determined by the equation above (proved later) for
𝑉 _ _ , where 𝑉 is the maximum expected electrode offset and 𝑉 _ _ is the
maximum output voltage of the DSL integrator and in the case in [56] equals to the
supply voltage 1V.

57
Cfb
 DC servo loop (DSL) creates a high-pass characteristic that
effectively blocks electrode offset (10s of mV).
𝐶 CDS Vin Vout
𝑓 = 𝑓, , ∫ A
𝐶
Cfb Cin
𝐶
𝑉 _ _ = 𝑉
𝐶 𝐶
𝑓 = 𝑓
Vin Vout 𝐶
A
Also later by (Q. Fan, ASSCC’10): [68]
Cin First time by (T. Dension, JSSC’07): [56]
 For summation of the CDS feedback loop and feedforward current to be

cancelled at the max swing at virtual ground of the Opamp: .
Therefore: _ _ . At extreme, the max CDS current happens
at the Max integrator output at VDD, meaning _ _ .
58
 DC servo loop (DSL) is employed to implement a high-
pass corner in the frequency response of the chopper
amplifier as shown in Fig. (a).
 For an ideal integrator in DSL loop, the highpass corner
is 𝑓 = 𝑓 where 𝑓 is the unity-gain frequency
of the integrator in the DSL.
 Figs. (b) and (c) illustrate the effect of DSL on the overall
frequency response of the amplifier, where in actuality a
lossy integrator or a lowpass filter is used instead of an (a) (b)
ideal integrator.
 Note: 𝑓 is the BW of the amplifier (closed-loop). For
instance for the passband gain i.e. A=100V/V, and the
OTA open-loop UGF of 5kHz × 100 = 500kHz, with the
signal BW i.e. 𝑓 at 5kHz.
 As shown in Fig. (c), DSL introduces a high-pass corner
at the frequency of fhp=(1+AB)fDSL in which fDSL is the
bandwidth of the integrator used in the DSL. (Prove
this and general shape of Figure (c)).
 For a lossy integrator in which its DC gain is limited to
B, then the highpass gain at DC is down to 1/B (and not
to zero!). Ex. A=100, B=1, for fDSL=0.01Hz we have
fhp=(1+AB)fDSL1Hz. (c)

59
CAPACITIVELY CHOPPER AMPLIFIER
 AC-coupled chopper amplifiers bring new issues which

require new techniques to solve them.
 A common architecture for implementing a capacitively Use
chopper amplifier is shown in the Figure.
either
 Chopper switches are placed before the AC-coupling
capacitors. one!
 The DC value of the signal is modulated to higher
frequency and the AC-coupling capacitors are not
able to filter it.
 In order to filter the DC component of the input
signal, a DC servo-loop is used in this circuit.
 Furthermore, chopper switches in conjunction
with AC-coupling capacitors reduces the input
impedance of the amplifier.
 To enhance the input impedance of the amplifier,
an impedance boosting circuit should be used in
the architecture of the chopper amplifier.
 Another issue of this circuit is the ripples
introduced to the signal path by chopper switches.
 This issue is addressed by using a ripple reduction
circuit in the architecture of chopper amplifier.
AC-coupled (capacitively-coupled) chopper amplifier architectures
[64]

60
[59-60]
 Another architecture for employing a

chopper amplifier is shown in this Figure.
 In this architecture the chopper switches
are placed after the AC-coupling capacitors
in the signal path.
 Hence, this architecture does not

require a DC-servo loop to block the
DC component of the input signal.
 Also the input impedance is not limited
by the switched-capacitor impedance
formed by the input choppers and the
input capacitors.
 Note: the switches tie virtual grounds

of opamp to the bottom-plate of input
(not preferred!)
caps both being at the same potential,
so not causing any charge transfer! [64]

61
[59-60]
 An important drawback to
performing input modulation at the
op-amp virtual ground node is
degraded common-mode rejection
ratio (CMRR). (Prove this).
 This is due to voltage division
between Cin and Cinp (the amp i/p
cap).
 Mismatch in the input capacitors can
convert common-mode input signals
to differential-mode noise.
 Chopping before the input capacitors
(as in [Denison’2007]) mitigates the
effect of their mismatch [Yazicioglu
PhD dissertation’2008]. Hence, in (not preferred!)
this design CMRR is compromised in
favor of higher input-impedance and [64]
low-voltage operation.
62
[59-60]
 Chopper stabilized LNA with chopper at the OTA virtual ground

implementation in [60].
[60]
 The first benefit of this is that
it allows the DC offset of the
electrodes to be truly
decoupled.
 Very large EOV (Electrode
Offset Voltage) can be rejected
passively and does not have to
be processed by the amplifier.
 The second benefit is that the
input modulator does not put a
resistive load the input Fig. 6. of [60]: Chopper stabilized LNA (a) core topology and (b) complete
topology with IOS,CHOP cancelling servo-loop (CIN and CINT are off-chip).
electrodes.
63
[59-60]
 One issue with input modulation at the virtual ground node is that the
parasitic switched-capacitor resistance of the modulator introduces a
current path between the IN+ and IN- nodes in Fig. 6(a). [60]
 The input modulator does
combine with the op-amp’s
input capacitance, CINP, to
introduce a parasitic
switched-capacitor resistance ,
as shown (RMOD) in Fig. 7.
Fig. 6. of [60]: Chopper stabilized LNA (a) core topology and (b) complete
topology with IOS,CHOP cancelling servo-loop (CIN and CINT are off-chip).
Fig. 7. of [60]: Parasitic switched-capacitor resistance
(RMOD) introduced by chopper modulator..
64
[59-60]
 Any offset at the op-amp input passes through this, giving rise to an
offset current IOS,CHOP that can saturate the amplifier through the large
feedback resistor RHP. [60]
 Accordingly, to cancel the offset-
current, a GM-C servo-loop is used
as shown in Fig. 6(b) in order to
integrate the amplifier’s output
error and provide the offset current
to the input modulator.
 It is worth noting that although
the servo-loop provides a high-
pass characteristic, RHP is still
required in order to cancel a
zero in the feedback path which
is introduced as a result of the
parallel GM-C and CFB feedback Fig. 6. of [60]: Chopper stabilized LNA (a) core topology and (b) complete
branches. (Prove this). topology with IOS,CHOP cancelling servo-loop (CIN and CINT are off-chip).

65
CAPACITIVELY CHOPPER AMPLIFIER [59-60]
 The op-amp used in the CS-LNA

is shown in Fig. 9 of [60]. It is
composed of two gain stages with
Miller compensation, and similar
to the design in [Denison’2007],
output demodulation is performed
before the dominant pole (at node
A).
 As a result, chopper stabilization
does not limit the required
bandwidth. Fig. 9. of [60]: Two-stage op-amp with embedded chopper-modulators
 A third current-buffer stage is used in Chopper Stabilized low-noise amplifier (CS-LNA).
also included to reliably drive

resistive loads. [64]

66
 Model of Figure 6 of [60] is shown in Figure 10

of [60].
 However, putting the chopper switches after
the AC coupling capacitors will shape the OTA
thermal noise with 1/f characteristic when
referred to the input of the neural amplifier
[59, 60].  Prove the noise and signal
transfer functions in [60] as bonus!
 Hence, this architecture requires a very high
value of Cin (in order of 300-500pF) to degrade Fig. 10 of [60]: Equivalent
this effect. circuit model for CS-LNA (a)
shown with noise sources
 In [60], AC-coupling capacitors are
implemented by off-chip capacitors. and (b) shown in block-
diagram form.
 In [60] a clever block diagram approach to simplify

the analyze the voltage-sampling current-mixing
feedback loop is introduced by inserting 𝒁𝒂 in front
of the voltage-to-voltage amplifier gain 𝑨(𝒔).
𝟏 𝑻𝑴𝑶𝑫 𝟏
 Where 𝒁𝒂 = (eqn. 1 in [60]). Also note that 𝑹𝑴𝑶𝑫 = =
𝑮𝑴𝑶𝑫 𝑮𝑰𝑵𝑻 𝑮𝑯𝑷 𝒔𝑪𝑰𝑵 𝒔𝑪𝑭𝑩 𝑪𝑰𝑵𝑷 𝒇𝑴𝑶𝑫 𝑪𝑰𝑵𝑷
(eqn. 3 in [60]). The latter eqn. (3 in [60]) is given incorrectly there!
67
 One may use the method

introduced in Elec II course
for feedback theory.
 Find the input impedance of
the feedback and Fig. 10 of [60]: Equivalent
feedforward branches for the circuit model for CS-LNA (a)
shown with noise sources
voltage-sampling current- and (b) shown in block-
diagram form.
mixing feedback amplifier
here.
 Compare the Elec II
method result with the
one given in [60].
68
MODIFIED CAPACITIVE COUPLED AMPLIFIER  SUMMARY
1) Instead of the DC-cap coupling  Chopper amplifier employed to

mitigate the flicker (1/f) noise of the Opamp.
2) Instead of making use of Pseudoresistors (which their values

varying by a factor of 100 by PVT, nonlinear, prone to bulk
leakage)  DSL (DC Server Loop) employed to set the
required LPF to reject the DC offset of the polarized
electrode-tissue.
[70]

69
CCIAS WITH MODIFIED DC SERVER LOOP
 To achieve a sub-hertz high-pass corner frequency, a

very-low bandwidth integrator is necessary in the
servo-loop.
 For frequencies beyond the unity-gain
bandwidth (UGB) of the servo-loop, the servo-
loop is effectively broken.
 Hence, since the signal band of interest lies beyond the
servo-loop UGB (in [70] design fHP and the servo-loop
unity-gain bandwidth are 1Hz and 0.5Hz respectively,
the typical values are even smaller), the output noise of
the servo-loop integrator in the signal band will be
amplified by C3/C2 (CDSL/Cfb) and appears at Vout. 𝐶 =𝐶
 The capacitor CDSL (denoted C3 here) is kept small to 𝐶 =𝐶
reduce the in-band noise contribution of the servo loop 𝐶 =𝐶
integrator and gm.
 Note: the transfer function from the integrator output to
the amp output is not limited to the servo-loop UGB and is
the same as that of the signal, so smaller CDSL the lower
[70]
integrator noise gain is.
70
 The overall loop transfer function with DSL is:

𝐾
𝐿 𝑠 = 𝑠𝐶 + 𝑠𝐶 𝑍 (𝑠) 𝐴(𝑠)
𝑠
𝟏
where 𝐾 = 𝜔 , , and 𝒁𝒂 𝒔 = [60, 89] (recall the Elec II method in
𝒔(𝑪𝒊𝒏 𝑪𝒇𝒃 𝑪𝑫𝑺 )
finding the input/output impedances due to the feedback network), and as a result:
𝐿(𝑠) = 𝐴(𝑠) = 𝐴(𝑠)

( ) ( )
 Therefore, the net input to output transfer function is:

𝑠𝐶 𝑍 𝑠 𝐴 𝑠 𝐶 𝐴 𝑠
𝐻 𝑠 =− =−
1+𝐿 𝑠 𝐶 +𝐶 +𝐶 𝑠𝐶 + 𝐾𝐶
1+ 𝐴 𝑠
𝑠(𝐶 + 𝐶 +𝐶 )
Therefore, for 𝐴 𝑠 = ∞:
𝐻 𝑠 =−
𝐶 𝐶 +𝐶 +𝐶
=−
𝐶 1 𝐶 =𝐶
𝐶 +𝐶 +𝐶 𝐾𝐶 𝐶 𝐾𝐶
𝐶 +
𝑠 𝐶
𝐶 =𝐶
1+
𝑠 𝐶 =𝐶
 Therefore, it is obtained that: 𝜔 =𝐾 =𝜔 , ,
[60, 89]

71
 The minimum value of CDSL is limited by the

maximum electrode offset that needs to be
attenuated. In [70] CDSL is chosen to be Cin/10,
which is sufficient to attenuate differential
electrode offsets up to ±50 mV, recall:
𝐶 = 𝑉 .
_ _
 For a high-pass corner frequency of fHP in the

signal transfer function Vout/Vin, the unity-
gain bandwidth of the servo-loop integrator is
given by fugb,DSL,int=fHP(Cfb/CDSL). 𝐶 =𝐶
 Hence for fHP of 1Hz, the servo-loop 𝐶 =𝐶
unity-gain bandwidth should be 0.5Hz (in 𝐶 =𝐶
𝑪𝒊𝒏
[70] design example, where 𝑪𝑫𝑺𝑳 = 𝟏𝟎 , 𝑪𝒇𝒃
𝑪𝒊𝒏 𝑪𝑫𝑺𝑳
= and = 𝟐). [70]
𝟐𝟎 𝑪𝒇𝒃

72
 Realizing an integrator (for DSL) with very low

frequency (sub-hertz) unity gain frequency
requires a very high resistor.
 Pseudoresistors are not viable in a closed-loop
neural recording application.
 To realize such low corner frequencies in a
reasonable chip area, switched-capacitor
techniques [31] have been used in the prior work.
However, switched-capacitor integrators
significantly increase the noise of the recording
front end. The wideband noise of the Opamp and
switches used in the switched-capacitor integrator
gets aliased down to baseband, which results in a
large in-band noise contribution from the servo-
loop integrator. Hence, switched capacitor integrators,
though an effective way to realize low frequency corners
in a small chip area, prove to be detrimental to the noise [70]
performance of the recording front end.
73
 The duty-cycled resistors (DCR) is used to realize

such low-bandwidth integrators.
 The DCR consists of a passive resistor R in series
with a switch as shown in Figure (a). (a)
 When the switch (shown in Figure (b) is driven by a
clock with a duty-cycle factor of D, the average
resistance is amplified by 1/D.
 This can be shown by analyzing the circuit in Figure
(c). If G(t) is the time-varying conductance of the
duty-cycled resistor, then using KVL the behavior of
the circuit in Figure (c) can be written [70] and
consequently the following transfer function is
derived (Prove this): (b) (c)
𝑗𝜔 =
 This equation shows that if RC >> DT and 𝑉 is a

low frequency signal, then the circuit in Figure 8(b)
is identical to a low-pass filter formed by a capacitor Fig. 8 of [70] [70]
C and an equivalent resistor R/D.
74
 With a pulse width of a few

nanoseconds, and for a
(a)
sampling clock frequency of
25kHz, it is possible to achieve
duty-cycle factors of 1/20000.
 Such small duty-cycle factors
also ensure that the
assumption of RC >> DT is (b) (c)
satisfied. Hence, a 1-M poly-
resistor can be boosted to
20G= . [70]

75
[61-63]
 In contrast to AC-coupled
amplifiers, DC-coupled amplifiers
use a low-pass filter to block the
DC component of the input signal
as shown in Figure.
 Several methods are introduced
in literature to implement a DC-
coupled amplifier.
 The low-pass filter used in the
structure of a DC-coupled
amplifier can be implemented in General architecture of DC-coupled amplifiers
analog [61], digital [62] or a

combination of them [63].
[64]

76
CAPACITIVELY CHOPPER IA IMPLEMENTATIONS
 A generic CCIA is shown in the Figure

comprising an Opamp (A) and a capacitive
feedback network (Cin and Cfb), an input
chopper CHin, a feed back chopper CHfb
and a third chopper CHout.
 The gain is defined by Cin/Cfb, and the
offset and 1/f noise of the Opamp is
upmodulated and removed, provided 1/f
noise corner frequency of Opmap is lower
the fchop.
 Taking into account the open-loop gain of
the Opamp , the gain of the CCIA is
given by:
( )
(1) (Prove this) [69]
( )
77
 Assuming 1st-order pole for 𝐴 𝑠 , and

 Noting from the eqn. (1):
𝐶
𝐿 𝑠 = (1 + 𝐴 𝑠 )
𝐶
(a)
 The unity gain frequency of the loop 𝜔 which is
almost equal to the corner frequency of the closed
loop gain 𝐺 𝑗𝜔 (i.e. the overall feedback amplifier |A(j )|
A0
gain) is where:
|G(j )| Cin/Cfb
(1 + 𝐴 𝑗𝜔 ) = 1 (2)
 For the closed-loop Bode plot where 𝐴 𝑗𝜔 ≫ 1,
then from eqn. (2) we have 𝐴 𝑗𝜔 ≈ which is
ta
(b)
the gain |𝐺| up to the closed-loop corner frequency
that is also the same as 𝜔 for the feedback [69]
amplifier with the well-compensated OTA.
78
 A two-stage Opamp for high enough

was chosen. ex., for gain precision
better than 0.1%, and for a gain of 100
(i.e. ), one can (a)
conclude . (Prove this).
 A two-stage Opamp comprising an
input Gm1 and output Miller-
compensated Gm2 is used to increase
the overall Opamp DC gain to ensure
the gain accuracy.
 Note that in any chopping phase
the overall negative feedback for [69]
(b)
Cfb branches are held.
79
CAPACITIVELY CHOPPER IA IMPLEMENTATIONS  W/ GM
CELLS
 The DC level at the opamp’s input is properly biased to a reference voltage Vref by high-resistance
resistors implemented as MOS transistors operated in their sub-threshold region.
 The action of the choppers will produce spikes since the bridge capacitors Cin1,2 and Cfb1,2 are
constantly being charged and discharged by the input and output signal voltages.
 Due to the Opamp’s finite output impedance, the output spikes associated with Cfb1,2 will be fed to a
succeeding ADC and could cause error.
 To reduce the duration of these spikes, the CCIA

Opamp’s output stage must be able to provide
currents much larger than the average DC
current required to drive the capacitive bridge.
 To reduce the amplitude of the spikes, smaller
feedback capacitors can be chosen at the expense
of lower capacitance matching.
 A low-pass filter can be used after the CCIA to
suppress the spikes; however, this is at the
expense of extra power consumption and chip
area.
 A better solution is to ensure that the succeeding
ADC only samples the CCIA’s output after it has
fully settled. (b) [69]

80
CELLS (AN EXAMPLE)
 The OTA used is shown in the Figure. For
high DC gain, Gm1 is implemented as a
folded-cascode OTA, while for large output
swing, Gm2 is implemented as a class-A
output stage.
 Due to noise considerations, the resistance of
the bias resistors Rb1,2 of 10G (to obtain an
input noise density of about10 nV/Hz) is
chosen. So 50pA of gate leakage from the two
PMOS input transistors is more than enough
to cause the input voltage to clip
(50pA× 10G=0.5V).
 The simulated DC gain of the two-stage
Miller-compensated CCIA Opamp is 130dB,
which corresponds to a gain errors 0.01% for [69]
G=100.
81
CELLS (AN EXAMPLE)
 Since the overall gain is mainly determined by Cin/Cfb,
the final gain inaccuracy will be determined by the
process spread and variation (including matching) of
Cin/Cfb, which is expected to be around 0.1%.
 The CCIA’s noise is dominated by the noise of the input
stage of Gm1. To achieve high power efficiency, the input
PMOS differential pair is biased in weak inversion.
 It consumes 61% of the total supply current and
consequently, a 55nV/Hz simulated noise voltage
density Vnopamp of the input stage is obtained. With
Cin/Cfb100, the CCIA’s input-referred noise is
essentially equal to Vn,opamp.
 The Miller capacitor (MOM fringe capacitor) are chosen
to be 30pF, and so the unity-gain frequency of the CCIA
is 70kHz.
 The bias current of the class-A output stage is chosen to
be 250nA which is sufficient to drive the capacitive
bridge with a 1Vpp output signal. [69]

82
CCIA  MODIFICATIONS: POSITIVE FEEDBACK LOOP (PFL)
Cfb
 Capacitively-Coupled Chopper IA
× Finite Input Impedance
Vin Vout
 Add the shown positive feedback loop (PFL): A
 Inject a current to the top-plate of the input cap equal Cin
to the current previously supplied by the input. Zin
 This current is supplied by a positive feedback from 1/(ƒchop×Cin)
the output voltage.
 Therefore, the supplied current from the input source
Iin is zero!
Spike currents
Vinp
Iinp
Iin Vcm
Vinn Iinn
[69]
(Q. Fan, JSSC’11)

83
CCIA  MODIFICATIONS: POSITIVE FEEDBACK LOOP (PFL),
(CONT’D)
Phase 1
 Make Ipf,p=Iinp  Iin=0 & 𝒁𝒊𝒏 = ∞

 Also note obviously Iinp=Ifb,n
Phase 2
 Make Ipf,n=Iinn  Iin=0 & 𝒁𝒊𝒏 = ∞ [69]

 Also note obviously Iinn=Ifb,p
84
Cfb
× Input Impedance
Vin Vout
 Ipf=ICin=Ifb => Infinitive input impedance A
Cin
 Stability issue Zin
1/(ƒchop×Cin) (for one path)
 Solution: Positive Feedback Loop (PFL)
Cpf
𝑰𝒊𝒏 = 𝑰𝑪𝒊𝒏 −𝑰𝒑𝒇 = 𝑰𝒇𝒃 − 𝑰𝒑𝒇
Cfb Making 𝑰𝒑𝒇 = 𝑰𝑪𝒊𝒏 or for that matter
Ifb Making 𝑰𝒑𝒇 = 𝑰𝒇𝒃 results in 𝑰𝒊𝒏 = 𝟎 and
Ipf
𝒁𝒊𝒏 = ∞
Vin Vout
A
Cin (Q. Fan, JSSC’11)
Iin [69]
ICin
85
Representing the two-stage Opamp as shown in the Figure,

the previous derivation can be rewritten and verified:
Writing eqns. for the upper half path in phase 1:
𝐼 = 𝑠𝐶 𝑉 −𝑉
which should be equal to 𝐼 drawn from 𝑉 when there was no
PFL:
𝐼 = 𝐼 = 𝑠𝐶 𝑉 
𝑠𝐶 𝑉 −𝑉 = 𝑠𝐶 𝑉 
𝑉 𝐶 =𝑉 (𝐶 + 𝐶 )
and knowing 𝐺 ≜ :
𝑪𝒊𝒏
𝐺 = 1+ ⇒ 𝑪𝒑𝒇 = ()
𝑮 𝟏
 Similar derivation for the lower half path in phase 1 can be [69]
written.
86
𝑪𝒊𝒏
 So, it was obtained that: 𝑪𝒑𝒇 = ()
𝑮 𝟏
𝑪𝒊𝒏
 Also we have: 𝐼 =𝐼 , thereby: 𝑠𝐶 𝑉 = −𝑠𝐶 𝑉 = 𝑠𝐶 𝑉 ⇒𝐺= or 𝑪𝒇𝒃 = (II)
𝑮
 Also as shown in the Figure: 𝐼 =𝐼 =𝐼 , rewriting 𝐼 =𝐼 , results in:
𝑠𝐶 𝑉 −𝑉 = −𝑠𝐶 𝑉 = 𝑠𝐶 𝑉 ⇒𝑉 𝐶 −𝐶 =𝐶 𝑉 ⇒ 𝐺= (III)
 Note: eqn. (III) can actually be

obtained from eqns. (I) and (II)
and is not independent.
 Having assumed and 𝒊𝒏 ,

then 𝒑𝒇 and 𝒇𝒃 are readily
obtained from (I) and (II),
respectively. [69]

87
 Note: all of the equations could have been written for the equivalent DC (low) frequency current to obtain the
boosted input equivalent resistance:
𝐼 = 2𝑓 𝐶 𝑉 −𝑉 &𝐼 =𝐼 = 2𝑓 𝐶 𝑉  2𝑓 𝐶 𝑉 −𝑉 = 2𝑓 𝐶 𝑉 giving the
same equation:
𝑪𝒊𝒏
𝑉 𝐶 =𝑉 (𝐶 +𝐶 ) and so resulting in the same result: 𝐺 = 1 + ⇒ 𝑪𝒑𝒇 = ()
𝑮 𝟏
 Also similarly we have:

𝐼 = 𝐼 , thereby:
2𝑓 𝐶 𝑉 = −2𝑓 𝐶 𝑉 = 2𝑓 𝐶 𝑉 ⇒
𝑪𝒊𝒏
𝐺= or 𝑪𝒇𝒃 = (II)
𝑮
 It is worth noting that the original

reference [69] and the ones later used this
equivalent DC (low) frequency current model to
write their equations to derive the boosted input [69]
impedance.
88
 From (I) for 𝐺 ≫ 1: 𝐶 = = ≈ 1+ =𝐶 1+
( )
 With 𝐺 = 100, 𝐶 , = 12pF  𝐶 , = = 120fF, 𝐶 , = has to be 121.21fF to reach an infinite input impedance! As
approximated above 𝐶 ≈𝐶 1+ = 120fF × 1.01 = 121.20fF.
 This can be challenging in layout and thus in the work in [69], 𝐶 , are chosen to be equal to 𝐶 , i.e. the actual
value of 𝐶 , chose to be about (0.01 here) smaller than its ideal value.
 This means that the currents of the positive feedback
branch fed back to the signal source (𝑉 and 𝑉 )
𝟏
nodes, are also 0.01 i.e. smaller than its ideal value.
𝑮
𝟏
 Therefore, (0.01 here) of the original current of that
𝑮
before the PFL is supplied by the input source.
 In other words, the compromised boosted input
impedance of the CCIA i.e. 𝑍 , is 𝑮 times (100
here) of its original input impedance i.e. 𝑍 :
𝑉 𝑉 𝑉
𝑍 , = = =𝐺
𝐼 , 𝐼 , 𝐼 ,
( ) [69]
𝐺
= = 𝐺𝑍 = (100𝑍 here)
89
Writing the general KCL eqn., i.e.: 

Note: 𝐼 =−𝑉 , 2𝑓 𝐶 = (𝑉 , ) 2𝑓 𝐶
()
Substituting (I) i.e. , we have:
For practical implementation issues

choosing then:
[69]
where .
90
 Parasitic Effects: In practice, the parasitic capacitance Cp1,2 located between Cin1,2’s bottom-plate and ground shown
in Figure will further limit the input impedance.
 CHin and 𝐶 , act as an equivalent parasitic resistor with a resistance of ( ). The current
,
drawn by this equivalent resistor is not compensated by a PFL dimensioned. As a result, this
parasitic resistor limits the maximum input impedance.
 In a standard CMOS process, Cp1,2 ranges between

10% to 40% of Cin1,2. This means that a PFL
dimensioned according to (I) will only boost the
input impedance by a factor of 2.5 to 10.
 To overcome this, the PFL can be designed to also
compensate for the extra current flowing through
the parasitic resistor Ip1,2.
 Another critical problem with this technique is
that the positive feedback loop is driven by the
output Vout. Any practical neural recording front
end would attenuate the dc signal at the output
Vout (like with DSL). Thus, the positive feedback [69]
loop is rendered inoperative at dc, where it is most
needed [70]. 91
, _ , _ , , 
(IV)
, ,
, _
Note: 𝑰𝒇𝒃𝟐,𝟏 is the same as the original 𝑰𝑪𝒊𝒏𝟏,𝟐.
where , _ is the modified
compensating current provided by
the PFL, and , _ is the
optimal value for , .
 In practice, however, the exact
value of , will be uncertain,
and so , can be made
adjustable in order to obtain
maximum input impedance.
 However, stability is issue.
[69]

92
CCIA  MODIFICATIONS: AUXILIARY PATH FOR
BOOSTING INPUT IMPEDANCE Cfb
× Input Impedance Vin Vout
A
 Ipf=Ifb => Infinitive input impedance Cin
Zin
 Stability issue 1/(ƒchop×Cin) (for one path)
 Solution: Auxiliary Precharge Path
Cfb
B
Φ1,2
Vin Vout
A
ƒclk1,2 Cin
Zin (H. Chandrakumar, JSSC’17)

93
BOOSTING INPUT IMPEDANCE
 Figure (a) shows the input branch of the chopper amplifier.
 Figure (b) shows the waveform of the current Iin provided by a dc input Vin in (a).
 The charge supplied in one period of

the chopping clock fclk is Q = 2CinVin.
Hence, the dc input impedance is (a)
given by Z0 = 1/(2Cin fclk), (proven

before making use of SC
equivalence resistance concept). Step response of an
RC circuit.
 The input voltage source Vin (b)
provides charge in a narrow region
[70]
of time, labeled as t.
94
 If an alternate reservoir of charge could be used to supply charge to the input
capacitors Cin for the duration t, then the dc current provided by Vin is reduced to
zero, boosting the dc input impedance to infinity.
 At the beginning of every chopping
phase, denoted as the pre-charge phase
ϕ1,2, the input capacitors are pre-
charged to the input voltage Vin through
buffers in an auxiliary path.
 At the end of the pre-charge phase, the
input capacitors are reconnected back to
the input port.
 Since the capacitors Cin have been
charged to Vin, there is no charge flow
when the capacitors are reconnected to
the input port. Thus, the dc current (a) (b)
provided by Vin is reduced to zero, [70]
boosting the dc input impedance to
infinity. 95
 However, due to finite gain and finite bandwidth of the auxiliary buffer, a nonzero error is made
during the pre-charge phase.
 If the auxiliary buffer bandwidth is 𝜏 rad/sec, and the pre-charge duration is 𝑇1 sec,
then the error made in the pre-charge phase 𝑉 is given by (proved later):
 Hence, at the end of the pre-

charge phase, due to the error  ,
the input 𝑖𝑛 has to provide some
residual charge required by 𝑖𝑛.
 As such the input impedance is
now given by (proved later):
,
. (a) (b)
,
[70]

96
EXERCISE Cfb
B
Φ1,2
Vin Vout
A(s) A
Vout ƒclk1,2 Cin
Vin Zin
Buffer
Transfer function of this circuit is 𝐻 𝑠 = = ≈ .
Where 𝜏1, 𝐴𝐷𝐶 , and 𝜏𝑏 are the open-loop time constant, open-loop gain, and closed-loop time constant of the buffer. So,
𝑉 (𝑡) for an input dc voltage can be calculated as 𝑉 (𝑡) = 𝑉 , 1− . (1 − 𝑒 ).
Therefore, the error made in the pre-charge phase is given by ∆𝑉 = 𝑉 , −𝑉 𝑇 ≈𝑉 , .( +𝑒 ).
Then, the transferred charge to the input capacitor can be calculated as 𝑄 = 2. 𝑐 . ∆𝑉 = 2. 𝐶 . 𝑉 , .( +𝑒 ):

𝑉 , 1 1
𝑅 , = = ( )
𝐼 , 2. 𝐺𝑎𝑖𝑛. 𝐶 . 𝑓 1
+𝑒
𝐴
97
CCIA  MODIFICATIONS: RIPPLE REDUCTION
Cfb
Vin Vout
× Amplified offset -> ripple A
Cin
Auto-zeroing
Cfb  SRST switches are closed during

a brief reset phase to store the
offset of the Gm on Cin,
Vin Vout minimizing chopper ripple and
A aiding in rapid recovery by
Cin clearing the memory of the
(R. Muller, VLSI’17) previous sample.

98
CCIA  MODIFICATIONS: RIPPLE REDUCTION LOOP
 First describing the ripple problem:

 The up-modulated Gm1’s offset and noise create a ripple at the output of the CCIA.
 The chopped offset of the input stage is filtered by the main Miller
compensation capacitor and appears as a triangular waveform at the output.
The peak-to-peak amplitude of the ripple can then be approximated as:
𝑉 , = =
 With 10 mV offset of Gm1, Gm1=13 S, and

Cm1,2=30 pF, the ripple at the output is
approximately: 𝑉 , = 433 mV.
 This would take excessive headroom from a
1 V supply and must be suppressed.
 Decreasing Gm1 leads to more noise, while
increasing fchop and Cm1,2 results in larger residual
offset and more chip area respectively.
[69]

99
 An AC coupled continuous-time ripple reduction loop (RRL) is employed. A block diagram

of the RRL is shown in Figure.
 It consists of sensing capacitors Cs1,2, a demodulating chopper CHRRL, an integrator and a
compensation transconductor Gm4.
 The output ripple is down-converted and used as an input to an integrator. The output of the
integrator is summed up with the output current of Gm1, thus creating a negative feedback loop,
which nulls the output ripple.
 Cs1,2 sense and convert the large ripple
voltage at the amplifier’s output into an AC
current; the AC current is then integrated
by the integrator into a voltage; this voltage
is then converted by Gm4 into a current,
which compensates for Gm1’s offset current.
 The RRL creates a notch at fchop with a
width determined by flexible design
parameters such as Cs1,2, and Gm4.
 The main drawback of this method is that
Cs1,2 loads the amplifier’s output, and thus [69, 58]
should be kept small.
100
 We must obtain the loop transfer function of the RRL.

 Note: Despite the input signal chopper in which fch >> Signal BW, CHRRL
chopper input during 1 sees a full cycle ripple, and continuously
differentiates Vout to create the current into Gm3 virtual ground.
 To obtain the Loop Gain and RRL
reduction, we start from 𝐼 and then
back to it.
 Transfer function from the input current to
𝑽𝒐𝒖𝒕 𝟏
CHout to Vout is an integrator: = . (I)
𝑰𝒊𝒏 𝑪𝑯𝒐𝒖𝒕 𝒔𝑪𝒎
 Transfer function from Vout to the current CS
which goes into the RRL integrator (Gm3 virtual
ground) which is chopped again by CHRRL is a
𝑰
differentiator: 𝑪𝒔 = 𝒔𝑪𝒔 . (II)
𝑽𝒐𝒖𝒕
 Hence the operations of the two choppers CHout
and CHRRL around the integrator Cm and the
differentiator Cs respectively, cancel each other.
[69, 58]

101
[86]
Fig. 2.9 of [86]: Block diagram of the AC-coupled ripple-reduction loop

102
 Note 1: Despite the input signal of the main chopper amplifier in which fch >> Signal BW, CHRRL
chopper input during 1 sees a full cycle ripple, and continuously differentiates Vout to create the
current into Gm3 virtual ground.
 Note 2: From Vout that is directly connected to Cs1,2 the seen impedance is not switched-capacitor but
actually the real capacitor Cs1,2 which its other side is switched between positive and negative virtual
grounds of Gm3.
 Let be the transfer function of the integrator (a)
built around Gm3 and Cint (Figure (a)). If Gm3 has
a finite DC voltage gain of A03, Gm3 input node is
no longer an ideal virtual ground, and then:
 Since Cs is chopped by CHRRL, the switched-
capacitor impedance 𝑍 looking into the chopper
output from the integrator’s non-ideal virtual
𝟏
ground is given by: 𝒁𝑪𝒔 = .
𝒇𝒄𝒉 𝑪𝒔
(b)
 where 𝑓 is the chopping frequency of CHRRL and the
output Vout is assumed to be a virtual ground. The
action of Cs and CHRRL can then be modeled by the
[69, 58]
Norton equivalent circuit shown in Figure (b).
103
(a)
 We must obtain the loop transfer function of
the RRL (cont’d).
 From Figure (b), the input Vi voltage can be
derived as
𝑉 =𝐼 𝑍 + 𝑉 , − 𝑉 s𝐶 𝑍
 Also we have: 𝑉 , = −𝐴 𝑉 , where 𝐴 is the finite
DC voltage gain of Gm3 OTA:
− ,
= 𝐼 𝑍 + (𝑉 , + ,
)s𝐶 𝑍 , and
(b)
,
=− (III), therefore:
( )
𝐼 𝑉 , 𝐼 𝑉
𝐿 𝑠 =
𝑉 , 𝐼 𝑉 𝐼
𝑍 𝐴 1 [69, 58]
=𝐺 (− ) 𝑠𝐶
1 + s𝑍 (1 + 𝐴 )𝐶 𝑠𝐶
104
(a)
 𝐿(𝑠) = − 𝐺 
( )
𝑪𝒔 𝑨𝟎𝟑 𝑮𝒎𝟒
 𝑳 𝟎 = −𝑮𝒎𝟒 𝒁 𝑨 =− (Recall: 𝑍 = )
𝑪𝒎 𝑪𝒔 𝟎𝟑 𝑪𝒎 𝒇𝒄𝒉
&
𝑮𝒎𝟒 𝑪𝒔
 𝒇𝟎,𝑹𝑹𝑳 =
𝟐𝝅𝑪𝒎 𝑪𝒊𝒏𝒕
Note: for unity gain frequency of the loop we have:
𝐿(𝑗𝜔 =1= 𝐺 .
( )
 In [58] example, it is stated: with the CCIA’s (b)

bandwidth equal to 700 Hz and 𝒇𝒄𝒉𝒐𝒑 equal to 5 kHz,
𝒇𝟎,𝑹𝑹𝑳 should be smaller than 4.3 kHz to maintain
CCIA’s signal bandwidth.
 Also the ripple is attenuated by
𝑳 𝟎 =
𝑨𝟎𝟑 𝑮𝒎𝟒
=
𝟐𝟓𝟐𝐕/𝐕×𝟎.𝟔𝟓𝛍𝐀/𝐕
= 𝟏𝟎𝟗𝟎 (w/o dimension). [69, 58]
𝑪𝒎 𝒇𝒄𝒉 𝟑𝟎𝐩𝐅×𝟓𝐤𝐇𝐳

105
CCIA  MODIFICATIONS: RIPPLE ANALYSIS RECAP
 All the designs discussed for RR use elaborate feedback loops with large
capacitors or switched-capacitor filters in the signal path that can
complicate the compensation of the amplifier.
 It was observed that the primary
cause of chopper ripple is the offset
current generated by gm1.
 Note that the current produced by
the input signal is also flowing from
gm1 into the second amplifier stage;
however, this current has power
around the chopping frequency.
 If the offset current is selectively
blocked from flowing into the second
amplifier stage, then the output
ripple can be reduced. Conventional two-stage chopper-stabilized amplifier [72]

106
 The output current from the first stage due to the dc offset is gm1Voff.
 This current is chopped by the mixer MX3 and flows into node X. The transfer
function Vout/I (where I is the chopped current) for ω ≈ 𝜔 is given by:
𝑉 𝑠 =− ( ), where 𝜔 is the nondominant pole frequency given by gm2/CL.
 For stability, 𝜔 is a factor of 3–5

higher than the closed-loop
bandwidth. Moreover, it is typical to
choose 𝑓 that is a factor of 5–10
higher than the closed-loop
bandwidth.
 Therefore, 𝑓 could be close to 𝑓 .
 Thus, Vout/I is not an ideal integrator.
Conventional two-stage chopper-stabilized amplifier [72]

107
 The output ripple can be approximated by

considering only the fundamental
component of chopping current I, as:
4
𝜔 𝐴 1
𝜋
𝑉 , ≈ 2𝑉
𝜔
𝜔
1+
𝜔
where 𝐴 is the closed-loop gain given by
Cin/Cf, and 𝜔 is the closed-loop bandwidth.
(Prove this).
 For an input offset of 5mV, a closed-loop
gain of 100, and 𝜔 = 𝜔 = 5𝜔 , the
output ripple amplitude is 180mVpp.
 Given that the output signal of interest is
about 100mV, such a large ripple is
unacceptable and needs to be attenuated
before digitization. Conventional two-stage chopper-stabilized amplifier [72]

108
CCIA  MODIFICATIONS: A SIMPLER RIPPLE REJECTION
TECHNIQUE
 A far simpler technique to reduce chopper ripples without any RR
feedback is presented in [72].
 A chopper-stabilized capacitive feedback amplifier, modified for
ripple rejection, is shown in the Figure.
 To reduce the offset current, a
parallel-RC impedance is added
immediately after gm1.
 This impedance acts as an open
circuit to gm1 at low frequencies if
R is larger than Zo1 (the output
impedance of gm1).
 At the chopper frequency, the
parallel-RC impedance acts similar
to a short circuit if the impedance
of capacitor C (at fclk) is smaller [72]
than Zo1.
109
TECHNIQUE
 To reduce the gain seen by the offset and flicker noise from gm1, a large resistor Rf is placed in
feedback across gm1.
 For signals around dc flowing in the first stage, gm1 along with Rf feedback appears as a unity-
feedback voltage buffer, as the feedback from the capacitor divider formed by Cin and Cf is broken for
dc signals. Thus, the offset voltage at the output of gm1 is Voff.
 This offset voltage will produce a current through resistor R, and this current gets chopped and
integrated onto CC to produce the output ripple.
 The amplitude of the ripple is given by:
4
2𝑉 (𝜋)𝜔 𝐴 1
𝑉 , ≈
𝑔 𝑅 𝜔
(1 + 𝜔 /𝜔 )
 where 𝐴 is the closed-loop gain given by Cin/Cf, and 𝜔 is the closed-
loop bandwidth.
 The attenuation of the output ripple arising from the dc
offset is given by 𝒈𝒎𝟏 𝑹.
 Resistance R can be implemented by a leaky switch that is off, with
R ≈ 1 GΩ. With gm1≈10μA/V (typical for biosignal amplifiers), the
output ripple can be easily attenuated by 80dB.
 In later works [70, 71] there is no path for dc current to flow from
gm1 to gm2, the resistance R is infinite. Thus, the expected
attenuation of ripples caused by the dc offset of gm1 is infinite.
[72]

110
TECHNIQUE
 The circuit presented in
[72] for gm1, gm2, and the
RR technique.
 Note each gm has its
individual CMFB loops.
 Also note the Rf1,2 are
made of leaky switches in
[72] where its resistance
varied from 350 MΩ to 35
GΩ over process and
temperature. Hence the
worst-case results must be
considered.
 Also in [72] it is shown
that the proposed
architecture is immune to
large variations in the
resistors.
[72]

111
TECHNIQUE
Q. Fan 2011 I. Akita 2013 R. Burt 2006
 To verify the effectiveness of the RR

technique in [72] in reducing output ripple
due to flicker noise, the transfer function
from vn(f) to Vout(f) is simulated and plotted
in Fig. 7(a) of [72], along with the theoretical
estimate as given by (4) of [72].
 The chopper amplifier with RR is compared
with published state-of-the-art designs in
Table II. The overall performance of the
amplifier is on par or better than the other
designs. The ripple-rejection performance
comparison shows that the RR technique
presented here achieves larger ripple
reduction for a nominal area increase and
consumes no additional power.
[72]

112
CAPACITIVELY COUPLED (CC) CHOPPER AMPLIFIER CM
RESPONSE
 Chopping is implemented using passive mixers at the
input and feedback arms of the capacitive-feedback
network.
 The demodulation mixer is placed within the Opamp gm,
usually in-between the first and second stages of a two-
stage Opamp. The signals appearing at the electrode (a)
inputs, as discussed before, consist of a differential signal
with amplitudes <100 mV, and a CM signal with
amplitudes around 500 mV.
(b)
 Figure (a) shows the core of a CC with CM inputs.
 Figure (b) shows Equivalent circuit of the chopper
amplifier for CM signals.
 Figure (c) shows the transfer function from the CM input
at the electrode ECM to the Opamp input Vin,CM:
,
= where 𝑅 is a large resistor to set (c)
( )
the CM dc voltage at the input of Opamp.
[71]

113
CAPACITIVELY COUPLED (CC) CHOPPER AMPLIFIER CM
RESPONSE
 The transfer function from the CM input at the electrode ECM to
the Opamp input Vin,CM is a first-order high-pass filter, with the
corner frequency set by the capacitance Cin+Cf and the resistor
RB.
 To ensure proper functioning of the chopper amplifier, this
corner frequency is usually set to <10 Hz.
(a)
 Hence, CM signals beyond 10-Hz pass unattenuated to the
input of the Opamp, which could cause the differential response
of a power optimized amplifier to show significant departures
from the expected response.
(b)
 It must be noted that these CM interferers are not “slow”
signals. This is because the CM interferers have the same
bandwidth (BW) as the differential signals of interest, large CM
swings at the input of Opamps could lead to distortion.
 This is particularly significant when the Opamp is designed for
low-noise and low-power operation, i.e., the input devices (and
possibly others) are biased in weak inversion, where they are (c)
most nonlinear.
[71]

114
CAPACITIVELY COUPLED (CC) CHOPPER AMPLIFIER WITH
FEED-FORWARD CM CANCELLATION (CMC)
 A feed-forward CM cancellation (CMC) path to attenuate the
CM swings at Vin,CM which would restore the linear operation of
the front-end for differential signals is presented in [71].
 The concept of the CMC path is shown in the Figure.
 The CM signal at the electrodes is sensed and amplified by the
Opamp gma and capacitors Ca and Cb.
 This amplified CM signal is then subtracted from Vin,CM through
capacitors Ccm. The gain in the CMC path is set by the capacitor
ratio Acm=2Ca/Cb.
 If Ccm is sized to be Cin/Acm, then the CM signals at the input of
the Opamp Vin,CM are ideally cancelled to zero.
 Any mismatches in the ratio of Cin/Ccm would lead to residual
CM swings at Vin,CM.
 However, the presence of the capacitors Ccm leads to an increase
in the input-referred noise of the front-end, as shown by the
following equation: 𝑣 , = 𝑣 (1 + ), where, 𝑣 is the
input-referred noise of the opamp gm. [71]
 Also note the CMC path differential gain is zero.
115
CCIA  EXAMPLE
[70]

116
CCIA  EXAMPLE
[71]

117
CCIAS FOR EEG APPLICATIONS
(M. Zamani, JSSCL’21)

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‫تقويت كننده هاي چاپر‬

Omid Shoaei, University of Tehran

o A polarity reversing switch (+1 or -1)

• DC input modulated twice -> remain the same

Omid Shoaei, University of Tehran

o Offset and 1/ƒ noise -> modulated

Omid Shoaei, University of Tehran

 Chopping usually does not introduce

Omid Shoaei, University of Tehran

 The effective DC gain of the opamp is

output chopper (CHout) can be located at

Omid Shoaei, University of Tehran

 In many measurement situations, the signal of interest is small,

Omid Shoaei, University of Tehran

 Readout system employing magnetic coupling shown in Fig. 1.2

Omid Shoaei, University of Tehran

 A second approach involves isolating the DC CM voltage

Omid Shoaei, University of Tehran

 A third approach, which is the most commonly

 To improve this, the chopping technique can again be

Omid Shoaei, University of Tehran

 Another approach to isolate the input CM voltage is

 An intuitively appealing solution to the

 Recall the differential capacitively coupled

 Note: the capacitive coupled amp of Figure

Omid Shoaei, University of Tehran

 One solution to unblock the DC input in the

Omid Shoaei, University of Tehran

Omid Shoaei, University of Tehran

electrode polarization is in order

Omid Shoaei, University of Tehran

Omid Shoaei, University of Tehran

 The primary issue in Open-loop Chopper Amplifier is the

 This issue can be particularly bad in micropower

Omid Shoaei, University of Tehran

 Robust open-loop (referred to not having a global feedback

 With the open-loop architecture offsets is amplified

 Effect of opamp limited bandwidth on the f f

total gain for a DC input (note of the ideal

𝜏 is the amp signal bandwidth so the signal excursion

Omid Shoaei, University of Tehran

 To calculate the filtered signal, the DC content of f f

the demodulated curve should be calculated

 For error0.01 (1 percent) then: 𝑓 ≥ , for 𝑓

is only 100Hz, and UGBW=10kHz for 𝐴 =𝐴 =

 As proven before and seen in

 There is also a finite ripple at

Omid Shoaei, University of Tehran

 To illustrate this concept, the proposed signal flow

distortion and increase precision in circuits.

Omid Shoaei, University of Tehran

1) Input and feedback paths around the amplifier are

o The ac feedback (meaning the output signal modulated or

Omid Shoaei, University of Tehran

2) Chopper modulation throughout the signal chain is

o Chopping the amplifier is possible at higher frequencies (e.g.,

Omid Shoaei, University of Tehran

 As shown the signal dynamics at different nodes of the

𝜀= , where 𝑇 is the chopper clock period and 𝜏 , 𝜏 are

 At the output, the residual ac offset signal is reduced to

𝑉 , where 𝒇𝟑𝒅𝑩 is the low-pass corner of the

 The amplifier summing node VA receives a

Omid Shoaei, University of Tehran