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VLSI Design Spring 2022
COMSATS University Islamabad
COURSE DESCRIPTION FILE
CPE434 VLSI Design
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
COMSATS University Islamabad
COURSE DESCRIPTION FILE
CPE434 VLSI Design
DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
VLSI Design
Course code:
CPE434 (3+1)
Prerequisites:
Digital Logic Design (CPE241), Electronics II (EEE232)
Co‐requisites
None
Course Catalog Description:
This is an introductory course which covers basic theories and techniques of digital VLSI design in CMOS
technology. In this course, we will study the fundamental concepts and structures of designing digital VLSI
systems include CMOS devices and circuits, standard CMOS fabrication processes, CMOS design rules,
static and dynamic logic structures interconnect analysis, CMOS chip layout, simulation and testing, low
power techniques, design tools and methodologies, VLSI architecture.
This course provides an introduction to the design and implementation of VLSI circuits for complex digital
systems. The focus is on CMOS technology. Issues to be covered include deep submicron design, clocking,
power dissipation, CAD tools and algorithms, simulation, verification, testing, and design methodology.
The course includes a laboratory component in which students will design and layout some basic digital
circuits.
This course provides the necessary background to design circuits and systems for VLSI. These circuits are
required to provide very high performance while working under size, area and power constraints. The
design of such electronic circuits is also complex owing to the high clock speeds, high logic density and
problems in layout, simulation and fabrication. The course covers different design and architecture
approaches for CMOS digital VLSI while also giving hands‐on experience of design, verification and
simulation of an integrated circuit using state‐of‐the‐art CAD tools.
Text Book:
1. Introduction to VLSI Circuits & Systems, 1st Edition – John P. Uyemura
Reference Books:
1. VLSI Design, 1st Edition – Debaprasad Das
2. CMOS VLSI Design, 4th Edition – Neil H.E Weste and David Money Harris
Course Learning Objectives:
The course is designed to give the student an in‐depth understanding of the different design steps
required to carry out a complete digital VLSI (Very‐Large‐Scale Integration) design in silicon. The design
steps starting from behavioral‐level modeling to physical layout.
Course Learning Outcomes (CLOs):
After successfully completing this course, the students will be able to:
1. Understand and explain the importance of VLSI, design hierarchy, design metrics, IC fabrication
materials, IC fabrication processes and reliability of ICs. (C2‐PLO1)
2. Implement and analyze complex logic circuits and layout (physical design) using static CMOS logic and
transmission gates and advanced techniques in CMOS logic circuits. (C4‐PLO2)
3. Design complete circuits electrically and geometrically using individual MOSFETs, interconnects and
other layers as well as logic gates, modules. (C4‐PLO3)
4. Investigate advanced techniques in CMOS logic circuits to develop solutions for given a set a
constraints and specifications. (C5‐PLO4)
5. Use CAD tools to implement and verify behavioral, RTL, circuit and layout level designs. (A3‐PLO5)
6. Present and analyze data with effective report writing skills. (A2‐PLO10)
Course Schedule:
3 credit hours/week
One laboratory session/week (3 hours/session)
Topics Covered
Week 01 Introduction and design metrics
Week 02 Logic design using MOSFETs
Week 03 Physical structure of CMOS ICs
Week 04 CMOS layers, designing MOSFET arrays (logic gates) in layout
Week 05 Fabrication process of CMOS ICs, lithography and design rules
Week 06 Elements of physical design
Week 07 Electrical characteristics of MOSFETs
Week 08 Electronic analysis of CMOS Logic Gates
Week 09 Advances techniques CMOS logic circuits
Week 10 System specifications using VHDL or Verilog
Week 11 General VLSI system components (multiplexors, latches and registers etc.)
Week 12 Arithmetic circuits in CMOS VLSI (Adders and multipliers etc.)
Week 13 Memories architectures and core design
Week 14 System level physical design (delays, crosstalk, scaling & power consumption)
Week 15 Reliability, testing and Design for Test (DFT)
Week 16 Revision
Assessment Plan:
Theory Quizzes (4) 15%
Homework assignments 10%
Mid‐term exam (in class, 60‐80 minutes) 25%
Terminal exam (3 hours) 50%
Total (theory) 100%
Lab work Lab reports (12) 25%
Lab Mid‐term exam 25%
Lab project and terminal exam 50%
Total (lab) 100%
Final marks Theory marks * 0.75 + Lab marks * 0.25
Assessment plan (Tentative):
Sr. # Course Learning Outcomes Assessment
1. Quiz 1
2. Quiz 2
3. Quiz 3
4. Quiz 4
5. Assignment 1
6. Assignment 2
7. Assignment 3
8. Assignment 4
9. Mid‐term Exam
10. Terminal Exam
Table 1: Assessment plan for course learning objectives
**CLO 5 will be covered and assessed during the laboratory sessions.
Computer Resources
Microwind and DSCH
Tanner EDA tools
ModelSim
Mapping Course Learning Outcomes (CLOs) to Program Learning Outcomes (PLOs):
PLO 1 Engineering Knowledge: An ability to apply knowledge of mathematics, science, engineering
fundamentals and an engineering specialization to the solution of complex engineering
problems.
PLO 2 Problem Analysis: An ability to identify, formulate, research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences and engineering sciences.
PLO 3 Design/Development of Solutions: An ability to design solutions for complex engineering
problems and design systems, components or processes that meet specified needs with
appropriate consideration for public health and safety, cultural, societal, and environmental
considerations.
PLO 4 Investigation: An ability to investigate complex engineering problems in a methodical way
including literature survey, design and conduct of experiments, analysis and interpretation of
experimental data, and synthesis of information to derive valid conclusions.
PLO 5 Modern Tool Usage: An ability to create, select and apply appropriate techniques, resources,
and modern engineering and IT tools, including prediction and modeling, to complex
engineering activities, with an understanding of the limitations.
PLO 6 The Engineer and Society: An ability to apply reasoning informed by contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to professional engineering practice and solution to complex engineering problems.
PLO 7 Environment and Sustainability: An ability to understand the impact of professional
engineering solutions in societal and environmental contexts and demonstrate knowledge of
and need for sustainable development.
PLO 8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of engineering practice.
PLO 9 Individual and Team Work: An ability to work effectively, as an individual or in a team, on
multifaceted and /or multidisciplinary settings.
PLO 10 Communication: An ability to communicate effectively, orally as well as in writing, on complex
engineering activities with the engineering community and with society at large, such as being
able to comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
PLO 11 Project Management: An ability to demonstrate management skills and apply engineering
principles to one’s own work, as a member and/or leader in a team, to manage projects in a
multidisciplinary environment.
PLO 12 Lifelong Learning: An ability to recognize importance of, and pursue lifelong learning in the
broader context of innovation and technological developments.
PLOs
PLO10
PLO11
PL012
PLO 9
PLO1
PLO2
PLO3
PLO4
PLO5
PLO6
PLO7
PLO8
CLOs
CLO1 C2
CLO2 C4
CLO3 C4
CLO4 C5
CLO5 A3
CLO6 A2
Table 2: Mapping CLOs to PLOs
PLO Coverage Explanation
PLO 1 – Engineering Knowledge
The quizzes, assignments, exams require direct application of mathematics, scientific, and engineering
knowledge to successfully complete the course. This includes elementary integral, differential calculus,
Boolean algebra, component calculations, circuit analysis, computer modeling.
PLO 2 – Problem Analysis
Students become eligible to analyze and design different digital CMOS circuits onto the silicon (physical
design). They will be able to cope with different design constraints at RTL, transistor and physical level like
circuit layouts, area, performance and other physical phenomena like latch up, crosstalk and dynamic
power dissipation.
PLO 3‐ Design/Development of Solutions:
The course shows the value of theory, by making it possible for the students to solve relevant engineering
problems, which form the basis of more complex problems in electronics and digital design (High
relevance to course).
PLO 4‐ Investigation:
The foundational aspects of this course are noted with pointers to the many directions that can be
pursued, with an emphasis on the need for continuing formal education and pursuing practical experience
(High relevance to course). Using the concepts and knowledge covered in this, students are encouraged
to explore and develop solutions to meet a given set of constraints (area, power and performance) and
specifications.
PLO 5 – Modern Tool Usage
The course introduces the state of the art simulation and circuit designing tools like Tanner EDA (or DSCH
and MicroWind) and ModelSim which can help students to design different complex digital integrated
circuits to solve relevant engineering problems. Tanner EDA (or MicroWind) tools will also provide them
in depth understanding of physical design by designing layouts of digital circuits.
PLO 10‐ An ability to Communication:
In the lab setup, the students are asked to perform the experiment and take the data. This collected data
is analyzed by the student and finally the conclusion comprehended by the student is required in the
report format. The students are also given chance to present some new finding in the presentation format
also. (High relevance to course)
PLO 4, 6 – 9, 11, 12: These PLOs are not directly addressed in this course.
List of Experiments
Lab No. Details
1 Introduction and AND‐Gate Implementation using Tanner S‐Edit
2 Designing Complex Logic Circuits using CMOS and Transmission Gates
3 Design and Simulation of Basic Logical Operations in ModelSim
4 Design and Simulation of 4‐bit ALU using HDL Architecture
5 Introduction to Layout Design and Simulation of Inverter using Tanner L‐Edit
6 Layout of Basic Logic Gates using 0.25‐micron Technology in Tanner L‐Edit
7 Layout of Complex Logic Function using 0.25‐micron Technology
8 Layout Design and Simulation of Full Adder in Tanner L‐Edit using Cell Concept
9 Design and Implementation of Static RAM Cell Layout
10 Controlling Rise and Fall Time of Complex Function in Layout Design
11 Designing a Chip in Tanner L‐Edit
12 Designing Clocked CMOS (C2MOS) and Dual Rail Logic Networks
13 ‐14 Lab Project / Viva
Version Applicable From
Version 1 Fall 2016
Version 2 Spring 2017
Version 3 Fall 2017
Version 4 Fall 2018
Version 5 Fall 2021
Version 6 Spring 2022