Starting: 2nd Sep 2021

DEPARTMENT OF ELECTRONIC ENGINEERING

UET ABBOTTABAD CAMPUS

Course Description File

ELE-210 Digital Logic Design (Theory 3cr. hrs)
Semester: 3rd Fall 2021
Instructor: Muhammad Fayaz Khan
ELE-210 DIGITAL LOGIC DESIGN
Credit Hours Contact Hours Pre-requisite(s)

3 3 hrs. /week x 15 weeks= 45 hrs. _

COURSE OBJECTIVES:

The objective of this course is to introduce the concepts required for the design of digital circuits and
systems using combinational and sequential logic.

COURSE LEARNING OUTCOMES (CLOS):

Upon successful completion of the course, the student must be able to:
Taxonomy
No. Statement of CLO Domain PLO
Level

CLO-1 Understand different numbering systems , codes, Cognitive C2 1

logic gates, Boolean algebra and circuit minimization

CLO-2 Apply the acquired knowledge to implement Cognitive C3 3

combinational logic circuits

CLO-3 Apply the acquired knowledge to implement Cognitive C3 3

sequential logic circuits
RELEVANT PROGRAM LEARNING OUTCOMES (PLOS):
The course is designed so that students will achieve the following PLOs:
1 Engineering Knowledge  7 Environment and Sustainability

2 Problem Analysis 8 Ethics

3 Design/Development of Solutions  9 Individual and Team Work

4 Investigation 10 Communication

5 Modern Tool Usage 11 Project Management

6 The Engineer and Society 12 Lifelong Learning

RECOMMENDED BOOKS:
1. Digital Design, 5th Ed, by M morris Mano and Michael D. Ciletti

2. Digital Computer Electronics, by Malvino Brown

3.
COURSE CONTENTS:

Digital systems and information

• Information representation
• Number systems, Arithmetic operations, decimal codes
Combinational logic circuits
• Binary logic and gates, Boolean algebra, standard forms
• Two-level circuit optimization, map manipulation
• Exclusive-OR operator and gates, other gate types, high impedance outputs
Combinational logic design
• Design procedure, hierarchical design, technology mapping
• Decoding, Encoding, Multiplexing
• Combinational circuits design based on decoders, multiplexors
Arithmetic functions
• Binary adders, binary subtractors, complements, binary adder-subtractors, signed binary
numbers, overflow
Sequential circuits and design
• Sequential circuit definitions, latches, flip flops
• Sequential circuit analysis and design
• JK and T flip flops, flip-flop characteristics and excitation tables
Registers and register transfers
• Registers and load enable, shift registers
• Register design with parallel load
Counters
• Counters, types of counters
• Counter design
Simple as possible computer -1(SAP-1)
• SAP-1 Architecture
• SAP-1 assembly language programming
 Assessment Plan:

Theory Quizzes 10%

Homework assignments 10%
Midterm exam ( 2hours) 20%
Final Term exam(3 hours) 60%
Total (theory) 100%

Course Learning Outcomes Assessment Plan (Tentative):

Sr. # Course Learning Cognitive levels Assessment Assessment

Outcomes %marks
Assignment 1,2,3 30
Quizzes 1,2 20
CLO1 C2
1. MTEQ#1,2,3,4,5 50

Assignment 4,5,6 30
Quiz 3,4,6 20
FTEQ#1,2,3,4,5 50
6. CLO2 C3

3. CLO3 C3

Assessment Plan for Course Learning Outcomes (Theory)