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8086 Processors PDF
8086 Processors PDF
)
It is a 16 bit p.
8086 has a 20 bit address bus can access upto 220 memory
locations ( 1 MB) .
It can support upto 64K I/O ports.
It provides 14, 16-bit registers.
It has multiplexed address and data bus AD0- AD15
and A16 A19.
TEMPORARY REGISTERS 6
CONTROL
LOGIC B
U
S
EU
ALU CONTROL INSTRUCTION QUEUE
SYSTEM Q BUS
1 2 3 4 5 6
8 BIT
FLAGS
BUS INTERFACE UNIT ( BIU)
EXECUTION UNIT ( EU )
Fig:
M. Krishna Kumar MM/M1/LU3/V1/2004 4
Pin Diagram of 8086
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16 / S3
AD12 4 37 A17 / S4
AD11 5 36 A18 / S5
AD10 6 35 A19/S6 _____
AD4
30 RQ / GT
___1
( HLDA)
12 _______
29 ____
AD3 LOCK (WR) ____
13
28 ___
___ S2 (M / IO )
AD2
14 27 S 1
___
(DT
_____
/ R)
AD1 15 26 S0 (DEN)
AD0 25 ________ QS0 (ALE)
16
NMI 24 QS1 (INTA)
17
______
INTR 18 23
TEST
CLK 19 22
READY
GND 20 21
RESET
INTR
_____
TEST INTERFACE
D0 - D15
MEMORY M / IO __
I/O DT / R
HOLD DMA ____
CONTROLS RD
HLDA INTERFACE _____
WR
VCC _____
DEN
MODE
____
SELECT READY
MN / MX
CLK
M. Krishna Kumar MM/M1/LU3/V1/2004 6
Internal Architecture of 8086
Output,
S2 S0 Bus Cycle Status 3- State
QS1, QS0 Instruction Queue Status Output
INTR
A0-A15,A16/S3 A19/S6
INTA
Interrupt Address / data bus
interface
TEST
D0 D15
NMI
8086
ALE
RESET MPU
BHE / S7
M / IO Memory
HOLD I/O controls
DMA DT / R
interface
HLDA RD
WR
Vcc
DEN
Mode select
READY
MN / MX
CLK clock
S4 S3 Segment Register
0 0 Extra
0 1 Stack
1 0 Code / none
1 1 Data
0 0 1 I / O read
1 0 I/O write
0
1 0 1 Memory read
1 1 0 Memory write
ALE
RD
DEN
DT / R
Clk
ALE
BHE S7 S3
ADD / STATUS A19 A16
WR
DEN
DT / R
HOLD
HLDA
They also serve the same purpose, but are activated one
clock cycle earlier than the IOWC and MWTC signals
respectively.
The maximum mode system timing diagrams are divided
in two portions as read (input) and write (output) timing
diagrams.
The address/data and address/status timings are similar to
the minimum mode.
ALE is asserted in T1, just like minimum mode. The only
difference lies in the status signal used and the available
control and advanced command signals.
8086
CLK
AD6-AD15 A/D Address bus
A16-A19 Latches
Add bus
DT/R
BHE A0
DIR
Data CS0H CS0L RD CS WR RD
buffer WR
DEN G Memory Peripherals
Data bus
Clk
AL
E
S2 S0 Active Inactive Active
MRDC
DT / R
DEN
Clk
ALE
ADD/STATUS BHE S7 S3
DT / R high
DEN
Clk
RQ / GT