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Ch10: Digital CMOS Logic Circuits

Tai-Cheng Lee
Electrical Engineering/GIEE, NTU

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1 Fall 2009

Introduction
• Why CMOS?

• CMOS circuit types:

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2 Fall 2009
Digital IC Technologies-(I)
• IC-Logic Family

• Interface problem

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3 Fall 2009

Digital IC Technologies-(II)
• How to choose digital IC?

• The advantage of CMOS logic family

SSI:
MSI:

Bipolar:

BiCMOS

GaAs
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4 Fall 2009
Logic-Circuit Characterization
• Voltage-transfer curve (VTC)

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5 Fall 2009

Propagation Delay
• Low-to-high propagation delay (tPLH)
• High-to-low propagation delay (tPHL)

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6 Fall 2009
CMOS Power Dissipation
• Static/Dynamic Power

• Silicon Area

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7 Fall 2009

CMOS Inverter (I)


• CMOS inverter operation principle

• Static operation

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8 Fall 2009
CMOS Inverter (II)
• Switching voltage

• What happens if NMOS/PMOS becomes larger?

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9 Fall 2009

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10 Fall 2009
CMOS Inverter (III)
• Dynamic operation (how fast!!)

• Parasitic capacitance: what happens?

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11 Fall 2009

CMOS Inverter (IV)


• Parasitic cap equations

• Average current

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12 Fall 2009
CMOS Inverter Design Strategy
(1)

(2)

(3)

(4)

(5)

• Dynamic power dissipation

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13 Fall 2009

CMOS Logic Gate Circuits


• Basic structure

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14 Fall 2009
AND/OR Structure-(I)
• Practical DAC implementation
Parallel Æ Series Æ

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15 Fall 2009

AND/OR Structure-(II)

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16 Fall 2009
Logic Representation for MOS
• Logic representation for MOS

• Two-input NOR Gate Two-input NAND Gate

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17 Fall 2009

CMOS Logic Gate-(I)


• Complex gate

Y = A( B + CD )

• Dual network

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18 Fall 2009
CMOS Logic Gate-(II)
• Exclusive OR function

Y = AB + B A

• Synthesis method

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19 Fall 2009

Transistor Sizing
• The basic rules: size transistors such that the worst-case pull-
up/down current is equal to those of inverters.

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20 Fall 2009
Fan-in/Fan-out
• Effects of fan-in/fan-out on propagation delay

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21 Fall 2009

Pseudo-NMOS Logic Circuits


• Pseudo-NMOS Inverters

• Enhancement MOSFET load

• Depletion MOSFET load

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22 Fall 2009
Pseudo-NMOS Inverter I-V
• Static characteristics

• How to obtain VTC?

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23 Fall 2009

Pseudo-NMOS Inverter VTC-(I)


• Operation region:
• Region I

• Region II

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24 Fall 2009
Pseudo-NMOS Inverter VTC-(II)
• Region III

• Region IV

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25 Fall 2009

Pseudo-NMOS Inverter Dynamic Operation


• Propagation delay

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26 Fall 2009
Pseudo-NMOS Inverter Design
• Sizing on pseudo-NMOS inverter

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27 Fall 2009

Pass-Transistor Logic Circuits


• Pass-transistor logic operation (PTL):

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28 Fall 2009
Pass-Transistor Logic Design Requirement
• Design example

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29 Fall 2009

Pass-Transistor Logic Delay-(I)


• Operation with NMOS transistor as a switch

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30 Fall 2009
Pass-Transistor Logic Delay-(II)
• Operation with NMOS transistor as a switch

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31 Fall 2009

Pass-Transistor Logic Design Issue


• Non rail-to-rail operation:
“Bad 1” (signal-level loss)

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32 Fall 2009
Transmission Gate –(I)
• Input changes from 0 to 1

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33 Fall 2009

Transmission Gate –(II)


• Input changes from 1 to 0

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34 Fall 2009
Pass-Transistor Logic Circuit
• Pass-transistor logic circuit design

• We can also use low or zero threshold MOS to construct


different logic function.

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35 Fall 2009

Dynamic Logic Circuits


• Definition of Static

• Dynamic circuits

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36 Fall 2009
Dynamic Logic Principle
• Two-phase operation

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37 Fall 2009

Dynamic Logic Example


• Sizing

• Noise margin

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38 Fall 2009
Charge sharing problem
• What’s wrong with the dynamic circuits??

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39 Fall 2009

Cascading Dynamic Logic Gates


• What’s wrong in the cascading dynamic logic gates?

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40 Fall 2009
Domino CMOS Logic –(I)
• Non-inverting dynamic gates

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41 Fall 2009

Domino CMOS Logic –(II)


• Domino logic timing analysis

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42 Fall 2009