Ch10: Digital CMOS Logic Circuits

Tai-Cheng Lee
Electrical Engineering/GIEE, NTU

Tai-Cheng Lee
1 Fall 2009

Introduction
• Why CMOS?

• CMOS circuit types:

Tai-Cheng Lee
2 Fall 2009
 Digital IC Technologies-(I)
• IC-Logic Family

• Interface problem

Tai-Cheng Lee
3 Fall 2009

Digital IC Technologies-(II)
• How to choose digital IC?

• The advantage of CMOS logic family

SSI:
MSI:

Bipolar:

BiCMOS

GaAs
Tai-Cheng Lee
4 Fall 2009
 Logic-Circuit Characterization
• Voltage-transfer curve (VTC)

Tai-Cheng Lee
5 Fall 2009

Propagation Delay
• Low-to-high propagation delay (tPLH)
• High-to-low propagation delay (tPHL)

Tai-Cheng Lee
6 Fall 2009
 CMOS Power Dissipation
• Static/Dynamic Power

• Silicon Area

Tai-Cheng Lee
7 Fall 2009

CMOS Inverter (I)

• CMOS inverter operation principle

• Static operation

Tai-Cheng Lee
8 Fall 2009
 CMOS Inverter (II)
• Switching voltage

• What happens if NMOS/PMOS becomes larger?

Tai-Cheng Lee
9 Fall 2009

Tai-Cheng Lee
10 Fall 2009
 CMOS Inverter (III)
• Dynamic operation (how fast!!)

• Parasitic capacitance: what happens?

Tai-Cheng Lee
11 Fall 2009

CMOS Inverter (IV)

• Parasitic cap equations

• Average current

Tai-Cheng Lee
12 Fall 2009
 CMOS Inverter Design Strategy
(1)

(2)

(3)

(4)

(5)

• Dynamic power dissipation

Tai-Cheng Lee
13 Fall 2009

CMOS Logic Gate Circuits

• Basic structure

Tai-Cheng Lee
14 Fall 2009
 AND/OR Structure-(I)
• Practical DAC implementation
Parallel Æ Series Æ

Tai-Cheng Lee
15 Fall 2009

AND/OR Structure-(II)

Tai-Cheng Lee
16 Fall 2009
 Logic Representation for MOS
• Logic representation for MOS

• Two-input NOR Gate Two-input NAND Gate

Tai-Cheng Lee
17 Fall 2009

CMOS Logic Gate-(I)

• Complex gate

Y = A( B + CD )

• Dual network

Tai-Cheng Lee
18 Fall 2009
 CMOS Logic Gate-(II)
• Exclusive OR function

Y = AB + B A

• Synthesis method

Tai-Cheng Lee
19 Fall 2009

Transistor Sizing
• The basic rules: size transistors such that the worst-case pull-
up/down current is equal to those of inverters.

Tai-Cheng Lee
20 Fall 2009
 Fan-in/Fan-out
• Effects of fan-in/fan-out on propagation delay

Tai-Cheng Lee
21 Fall 2009

Pseudo-NMOS Logic Circuits

• Pseudo-NMOS Inverters

• Enhancement MOSFET load

• Depletion MOSFET load

Tai-Cheng Lee
22 Fall 2009
 Pseudo-NMOS Inverter I-V
• Static characteristics

• How to obtain VTC?

Tai-Cheng Lee
23 Fall 2009

Pseudo-NMOS Inverter VTC-(I)

• Operation region:
• Region I

• Region II

Tai-Cheng Lee
24 Fall 2009
 Pseudo-NMOS Inverter VTC-(II)
• Region III

• Region IV

Tai-Cheng Lee
25 Fall 2009

Pseudo-NMOS Inverter Dynamic Operation

• Propagation delay

Tai-Cheng Lee
26 Fall 2009
 Pseudo-NMOS Inverter Design
• Sizing on pseudo-NMOS inverter

Tai-Cheng Lee
27 Fall 2009

Pass-Transistor Logic Circuits

• Pass-transistor logic operation (PTL):

Tai-Cheng Lee
28 Fall 2009
 Pass-Transistor Logic Design Requirement
• Design example

Tai-Cheng Lee
29 Fall 2009

Pass-Transistor Logic Delay-(I)

• Operation with NMOS transistor as a switch

Tai-Cheng Lee
30 Fall 2009
 Pass-Transistor Logic Delay-(II)
• Operation with NMOS transistor as a switch

Tai-Cheng Lee
31 Fall 2009

Pass-Transistor Logic Design Issue

• Non rail-to-rail operation:
“Bad 1” (signal-level loss)

Tai-Cheng Lee
32 Fall 2009
 Transmission Gate –(I)
• Input changes from 0 to 1

Tai-Cheng Lee
33 Fall 2009

Transmission Gate –(II)

• Input changes from 1 to 0

Tai-Cheng Lee
34 Fall 2009
 Pass-Transistor Logic Circuit
• Pass-transistor logic circuit design

• We can also use low or zero threshold MOS to construct

different logic function.

Tai-Cheng Lee
35 Fall 2009

Dynamic Logic Circuits

• Definition of Static

• Dynamic circuits

Tai-Cheng Lee
36 Fall 2009
 Dynamic Logic Principle
• Two-phase operation

Tai-Cheng Lee
37 Fall 2009

Dynamic Logic Example

• Sizing

• Noise margin

Tai-Cheng Lee
38 Fall 2009
 Charge sharing problem
• What’s wrong with the dynamic circuits??

Tai-Cheng Lee
39 Fall 2009

Cascading Dynamic Logic Gates

• What’s wrong in the cascading dynamic logic gates?

Tai-Cheng Lee
40 Fall 2009
 Domino CMOS Logic –(I)
• Non-inverting dynamic gates

Tai-Cheng Lee
41 Fall 2009

Domino CMOS Logic –(II)

• Domino logic timing analysis

Tai-Cheng Lee
42 Fall 2009