HW 6

For each of the following sequencing styles, determine the maximum logic
propagation delay available within a 500 ps clock cycle. Assume there is zero clock
skew and no time borrowing takes place. (Use the timing parameters in Table 1.)
(a) Flip-flops
(b) Two-phase transparent latches
(c) Pulsed latches with 80 ps pulse width

a)
Flip-Flops

From the Figure

Here
tpd 500- (65+50) ps
Propagation delay should be less than or equal to 385 ps.
(b) Two-phase transparent latches
From the below figure

In this case
tpd 500-80 ps
tpd 420ps

c) Pulsed latches with 80 ps pulse width

From the Figure
Here
tpw = 80 ps
tsetup = 25 ps
clearly tpw>tsetup

In this case
tpd Tc-tpdq
tpd 500 -40 ps
tpd 460ps