Pole-Zero Analysis of Multi-Stage

Amplifiers: A Tutorial Overview

Punith R. Surkanti, Annajirao Garimella and Paul M. Furth
Klipsch School of Electrical and Computer Engineering,
New Mexico State University, Las Cruces, NM 88003, USA
Email: punith@nmsu.edu, garimella@ieee.org, pfurth@nmsu.edu

Abstract- Analyzing pole-zero locations of an amplifier is

essential to 1) understand the characteristics of a circuit in
the frequency domain, and 2) choose appropriate frequency
compensation techniques to guarantee the stability of a circuit
over a specified range of load resistance and capacitance. The
objective of this paper is to provide tutorial treatment of the
steps for analyzing poles and zeros in multi-stage amplifiers.
These techuiques can be equally applied for the analysis of power
management circuits such as low-dropout voltage regulators
(LDOs) and controllers for DC-DC converters.

I. INTRODUCTION Fig. 1. Schematic of two-stage amplifier with cascode compensation [I].

Finding the analytical equations of poles and zeros is often adapted from Fig. 3 of [1]. The first stage is a PMOS
essential to 1) choose appropriate frequency compensation folded cascode differential amplifier and the second stage
techniques to stabilize an amplifier and 2) understand which is a PMOS common-source amplifier. The transconductance,
parameters have more impact than others, aiding in tuning output resistance and lumped parasitic capacitance of the first
the circuit for desired frequency response. In this tutorial, we and second stage are represented by gmb gm2, R1, ROUT,
explain the process of performing small-signal analysis and C1 and COUT respectively. The first stage is inverting so as
deriving the equations of poles and zeros in two-stage and to ensure that the overall gain from VI N + to VOUT is non­
three-stage amplifiers. Section II outlines the steps for finding inverting. Equations for the small-signal parameters of the
poles and zeros. Section III illustrates pole/zero analysis in amplifier are given in Table I and the small-signal model is
a two-stage folded-cascode op-amp. Section IV shows an shown in Fig. 2.
example of analyzing poles and zeros for a more complex
three-stage amplifier. SPICE simulations are performed to
compare hand-computed pole/zero locations with AC analysis.

II. STEPS FOR FINDING POLES/ZEROS

The steps for obtaining the DC gain, poles and zeros:

1) Draw the small-signal model
2) Apply Kirchhoff's Current Law (KCL) at each node
Fig. 2. Small-signal model of two-stage amplifier with cascode compensation.
3) Solve the KCL equations using symbolic manipulation
software to obtain the transfer function
The first-stage is represented with voltage-controlled current
4) Set 8=0 to find the DC gain of the amplifier source (VCCS) gMIVS, where Vs is the differential input volt­
5) Factor and solve the numerator to obtain zeros age, given by Vs == VI N + VI N
- _. The output of the first-stage
6) Applying the assumption of widely-separated poles, VI .
is The second-stage is represented with VCCS gM2Vl.
solve the denominator to obtain the poles, OR applying
The output of the second-stage is VOUT. The compensation
the assumption of widely-separated poles with complex
capacitor Cc and resistor Rc are connected between VOUT
pole pair, solve the denominator to obtain the poles
and vx, where Vx is the source node of the common-gate

III. POLE-ZERO ANALYSIS OF TWO-STAGE AMPLIFIER transistor M6. Transistor M6 acts as a positive current buffer
between Vx and VI represented with VCCS gmBvx. Transistor
Compensation networks such as Miller compensation [2]­
M6, resistor Rc and compensation capacitance Cc form the
[4], cascode compensation [1], [5]-[8], nested Miller compen­
cascode compensation. The impedance looking into the source
sation (NMC) [9], [10], and reverse NMC (RNMC) [6], [11]
terminal of M6 is
1/ gmB, connected between nodes Vx and
are widely used techniques to stabilize multi-stage amplifiers.
ground. Resistor Rc can be used to increase the impedance
The transistor-level schematic of a two-stage op-amp using 1
looking into the source to __ + Rc, as illustrated in [6], [7].
cascode compensation is shown in Fig. 1. This circuit is 9",B

978-1-61284-857-0/11/$26.00 <92011 IEEE

 TABLE I
Assuming widely separated poles «: «: (WPI WP2 WP3), the
SMALL-SIGNAL PARAMETERS OF TWO-STAGE AMPLIFIER (FIG. 2) 2 3
coefficients of s,
s and s can be approximated as
9m1 9m of MbM2
R1 ro4119m6ro6{rosllro2) _1_ ::::}
b1 1
*
� WPI� -b 1
wPl
G1 Gad4 + Gad6 + Gas9 1_ ::::}
9m2 9m of M9 b2 �
WPlwP2
__
WP2 � �b 2 (7)

. .
RouT ro9lirolOIIRL b3 �
�
1 ��
::::} WP3 �
* b3
GOUT Gqd9 + GqdlO + GL WPlWP2WP3
9mB 9m of M6
. . 3) One Real Pole & Two Complex Poles: The generic
* OmItting bulk capacitances for simplicity
transfer function with one real pole WPI.
one complex pole
A. Applying Kirchhoff's current la w (KCL) pair WP2with a quality factor Q and a real zero is WZI

) ( sJ )
In order to obtain the transfer function of the amplifier
ADe 1+w�
shown in (1), we apply KCL at every node in Fig. 2. Let G(s) = (8)
(1+ (1+ +
2
ic be the current flowing through the compensation network 8
wPl QWP2 �
8
'
from node VOUT to node vx. The set of KCL equations are

- -
The coefficients for s, S2 3
and s in the expanded denominator
9mBVX 9mlVS + "*" + vlsGl
=
of (8) are given by

:!!.QJl.X...
(V OUT - V X )
t. c - Rc ..,....::!.X..­
(2) _1_ _1 _
+(l/sCc) 119m B b1 -
- WPI + QWP2
o = ic + 9m2 Vl + RV OUT + VOUTSGOUT b2 - 1
- QWPIWP2 +�
1
(9)
B. Transfer Function b3 =�
WPIWp 2
Solve the equations in (2) so as to eliminate
VI , Vx and ic
to obtain the transfer function G(s) == VOUT(S)jvS(s) shown
Assuming widely separated poles «: (WPI WP2 ), the coeffi­

in (1) using symbolic manipulation software. The transfer

cient of s, S23
and s can be approximated as

function of a two-stage amplifier with three left-half-plane

(LHP) poles and one LHP zero has a general form given by
(10)
ADC (1 + als)
G(s) - (3)
(1 + bls + b2 s2 + b3s3)
1) DC Gain: ADc is the DC gain of the amplifier, given
C. Calculating Pole Locations
by the product of the gains of the two stages as
The two-stage amplifier in Fig. 2 has three real poles if
(4)
the output capacitor GOUT is very large; otherwise, it has a
2) Three Real Poles: The generic transfer function with complex pole pair.
three real LHP poles WPI . WP2 , WP3 and single LHP zero 1) Three Real Poles: Assuming real and widely separated
WZI is poles, the equation for the dominant pole is given by WPI
1
WPI= = - 1(
/ RouTCe+ReCe+ROUTCOUT
(5) b1
+Ce/ gmb +R1 C1 +RICegm2RoUT) (11)
2 3
The coefficients for s,
s and s in the expanded denominator In order to simplify this expression, we make the following
of the transfer function in (5) are compared with those of the assumptions concerning small-signal parameters
transfer function in (3) as shown below:
__1_ +_1_ +_1_ R1 , RouT » Re and gm1 Rl , gm2ROUT » 1 (12)
b1 -
WPI wp2 WP3
b2 = w w 1_ + 1_ + 1_ Applying (12), that is, neglecting smaller terms,
Pl
__

p2 wp 2 w
__

p3 wp3wPI
__
(6)
b3 - 1
- wPlwp2wp3 WPI� - 1/RICegm2RouT . (13)

( )
"

"-.R' :::
ROUT 1+S (aa[
RO
: .�J)
� ��
G(s) = - �[ - - - - - -
-------+-8 - - - - -+- c- - g- � -- - - - - - -- - - - - - - - - - - � ' ------� (1)
1 ROUTCC + R CC c C �k + ROUTC OUT + RIC l + RlCC g m 2Ro uTl+

bl
82 R
[ C CC ROUTC OUT + RIC IROUTCC + RIC IRC CC + ROUTC OUT9�k CC + RIC IROUTC OUT + RIC 1
9�kCCI +

b2
3 + RIC IROUTC OUT g �kCCl
. [RI C IROUTC OUTRC CC

b3
 TABLE II
Substituting the inWPI (7), the equation of first non-dominant
POLE/ZERO EQUATIONS OF FIG I AND THEIR ApPROXIMATE VALUES
pole WP2 is given by
Parameter Equation ValuelFrequency
WP
WP2 = b;1 = -(9m2RoUT9mBR 1 Cc)/(R 1 C 1 CC +
ADC 9m 1 R 1 9m2 ROUT 50dB
ROUTCOUTCC +ROUTCOUT9mBRc Cc + WP 1 - 1 40kHz
R, Ceo a ? RnlTT
••

R 1 C1 9mBRoUTCC +R 1 C 1 9mBRc Cc + 9mB9", 2

WP2
V CICOUT
28MHz
R 1 C 1 9mBRoUTCOUT). (14) CCOUT . 9rn 2CQlJT

Applying the assumptions in (12), WP2 is approximated as

Q (CC+C ) V 9m BCl
0.78

WZ 1 - Cc 1 24MHz
1 / 9",B)
( Rc+
1 14MHz
WP2 ::::;- . (15) WGBW 9mI/CC
(119m2 )C 1 1+ ( cg�?) E. Bandwith and Phase Margin
Observe the equations of the dominant pole WPI in (13) The gain-bandwidth product is given by
and first non-dominant pole WP2 in (15). As the value of
gml
compensation capacitor Cc increases, the dominant pole WPI WCBW::::; ADC WPI = . (19)
Cc
moves to lower frequencies, whereas the non-dominant pole
The phase margin for a system with three real poles and
WP2 moves to higher frequencies.
Substituting WPI
and in (7), the high frequency pole
WP2 single zero is computed using the equation given by
WP3 is given by

Cc +COUT
tan- 1
PM::::;900-tan- 1 ( a2 ) -tan- 1 ( a3 ) + ( WGBW
WZ 1
) , (20)
WP3 = - -:::---::--=--,=-....::....::....:..,-
----,-
- (16)
CCCOUT(Rc +119mB) where == i:¥2 and WCBW/WP2
== If there exist i:¥3 WCBW/WP3'
In a design example, when we input realistic values for small­ a complex pole pair, the phase margin becomes
signal parameters of Table I, we found that the calculated val­
ues for WP2 and WP3 were very close to each other, violating
PM::::;90° -tan- 1 ( a2
Q(1- a� )
tan- 1
+ ) ( WGBW
WZ 1
) . (21)
the assumption that the real poles are widely separated. Hence,
Fig_ 4 shows the AC analysis simulated result of two-stage
we anticipate the existence of a complex pole pair.
amplifier shown in Fig. 1. The hand-calculated gain and pole­
2) One Real Pole and One Complex Pole Pair: For
zero locations of Table II are very close to the simulated
moderately-sized CouT,the two non-dominant poles converge
values.
and form a single complex pole pair. The dominant pole WPI
is unchanged and is given by (13).
" F=======:::::-r--"""""---"-"""'----=1
Applying the assumptions from (12), the non-dominant
complex pole WP2
and quality factor Q are given by "

9mB9m2 Gain=.51.OdB
WP2 ::::; (17) -2S GBP=II.6r..·IHz
, .

C 1 COUT
,

PM=.59 . .52° ,
"

Cc 9m2 COUT
Q ::::;
( Cc +COUT) 9mB C 1
D. One Real Zero
The equation of the LHP zero is given by

1
WZ 1 = - . (18)
Cc(Rc +119mB)
-180 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ., -

' ' J � ' ' ' '

Table II summarizes the derived equations of the poles and 10 10 10 10
Frtqlltu('�'(Hl)
10 10 10 10

zeros. The third column in the table represents the hand­

calculated values. Fig. 3 illustrates the pole/zero locations Fig. 4. Simulated loop gain and phase response of the two-stage amplifier
with the theoretical pole and zero locations indicated.
before and after compensation.

Two-stage op-amp
Uncompensated
IV. POLE-ZERO ANALYSIS OF THREE-STAGE AMPLIFIER

The three-stage pseudo class-AB amplifier shown in Fig. 5

is the NMOS version of the circuit in [12]. The first stage is a
Two-Stage Cascode
�)2 Compensation
differential amplifier and the next two stages are common­
source amplifiers. The PMOS transistor MlO, which is an
COZ]
inverting common-source amplifier, creates a feed-forward
&�)2
Complex path gmF from the intermediate node to the output node. The
pole-pair
last stage of the amplifier is a non-inverting common-source
Fig. 3. Diagram illustrating pole/zero locations (not to scale). amplifier. It comprises an NMOS current mirror formed by
Mg and M11 of dimensions in I:K ratio, as shown in Fig. 5.
 by proper placement of the two LHP zeros created by RNMC.
The fourth pole is at very high frequency. As a result, the
overall amplifier response can be designed to behave as a two­
pole system with widely-separated poles.
As a design example, the simulated frequency response of
the three-stage amplifier is shown in Fig. 7.

100 I I

== 50
2-
=

t3 0 ....... . . . . . . . . . . . . . . . • .1 . . ... . ....... .......

.. . .
I
I
Fig. 5. Schematic of three-stage amplifier based on [12).
-50 I I

RNMC with nulling resistor is adopted to stabilize the ' ' ' ' ' ' '
10 10 10i 10 10 10 10 I 10
I FrE'qut'u(y (Hz) I
amplifier for a wide range of capacitive loads. The small-signal I I
I I

model of this three-stage amplifier is shown in Fig. 6

�
-45
CCI
.....,...
�
-90
ICI 8
�
v,

£ -135
vOUT

[PI
8
-1 0

R, C, ' ' ' ' ' '

10 10 10 10 10 10
Frt"qu('ufY (Hz)

Fig. 7. Simulated loop gain and phase response of the three-stage amplifier
with the theoretical pole and zero locations indicated.
Fig. 6. Small-signal model of three-stage amplifier shown in Fig. 5.

Using notations similar to the previous example, iC I and

REFERENCES
iC2 are the currents flowing through the compensation network
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from node VOUT to node VI and from node V2 to node VI,
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set of equations: 1984.
[2) P. R. Gray and R. G. Meyer, "MOS Operational Amplifier Design-A
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=
Tutorial Overview," IEEE J. Solid-State Circuits, vol. 17, no. 6, pp.
iC I + iC2 V ��V ! =
969-982, Dec 1982.
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tC 2 �I/SCC2=
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=
Stage Operational Amplifiers," IEEE Trans. Circuits Syst. I, Reg. Papers,
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= V
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WPI - 122Hz
RlCCI9=2R29=3ROUT 2011.
W P2 - 2TTti,lcCJ 2.1MHz
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1
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The amplifier has four poles. CC I creates the dominant pole.
on Circuits and Sys. II, vol. 50, no. 5, pp. 227-233, May 2003.
The effect of the next two non-dominant poles can be nullified