Part A

Figure 3: Buffer module’s gain control is about middle of

its travel.
Figure 1: Buffer module’s input and output.

Figure 4: Buffer module’s gain control is fully anti clock

wise.
Figure 2: Buffer module’s gain is in attenuation or
loss state.

Figure 5: Buffer module’s gain control is fully clock wise.

Part B

Figure 6: Adder module’s G control varying from left to Figure 9: Fully clock wise Adder module’s g control.
right.

Figure 7: Fully clock wise Adder module’s G control.

Figure 10: Fully anti clock wise Adder module’s g control.

Figure 8: Fully anti clock wise Adder module’s G control.

Figure 11: Fully clock wise for both Adder module’s gain
control.
Part C

Figure 12: Phase Adjust control varying left and right at Figure 15: Minimum DCV voltage.
0deg position.

Figure 16: Maximum DCV voltage.

Figure 13: Phase Adjust control varying left and right at
180deg position.

Part D Part E

Figure 14: Peak-to-peak amplitude of the VCO module’s Figure 17: Out of phase signals to each other when Phase
sine output. Change control is set to 180deg.