Professional Documents
Culture Documents
Single Phase On-Line UPS Using MC9S12E128: Designer Reference Manual
Single Phase On-Line UPS Using MC9S12E128: Designer Reference Manual
HCS12
Microcontrollers
DRM064
Rev. 0
09/2004
freescale.com
Single Phase On-Line UPS Using MC9S12E128
Designer Reference Manual
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Revision Page
Date Description
Level Number(s)
Freescale Semiconductor 3
Single Phase On-Line UPS Using MC9S12E128
4 Freescale Semiconductor
Contents
Chapter 1
Introduction
1.1 Application Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 The UPS Topologies and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.1 Passive Standby UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2.2 Line-Interactive UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2.3 On-Line UPS Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3 MC9S12E128 Advantages and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2
System Description
2.1 System Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 3
UPS Control
3.1 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Battery Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 Power Factor Correction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.3 dc/dc Step-Up Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.4 Output Inverter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.5 PI and PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.6 Phase-Locked Loop (PLL) Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 4
Hardware Design
4.1 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.2 Battery Charger Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.3 Flyback Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.4 Design of Flyback Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.5 Voltage and Current Sensing, Current Limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.6 Main Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.7 Battery Charger Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Auxiliary Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.1 Auxiliary SMPS Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 dc/dc Step-Up Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.1 dc/dc Converter Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.2 dc/dc Converter Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Power Factor Correction and Output Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Freescale Semiconductor 5
Contents
Chapter 5
Software Design
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.1 Software Variables and Defined Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2.2 Process PLL Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.3 Process RMS Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.4 Process Mains Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.5 Process Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.6 Process Sine Wave Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.7 Process Button Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.8 Process LED Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.9 Process Application State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2.10 Process PFC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.11 Process Sine Wave Reference (PFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.12 Process dc Bus Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.13 Process dc/dc Step-Up Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.14 Process Inverter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2.15 Process Battery Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Main Software Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.1 Initialization of Peripherals and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.2 Periodic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.3 Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.4 Interrupt Time Execution and MCU Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4 Software Constant Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.4.1 PI and PID Controller Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 6
Tests and Measurements
6.1 Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2 Load Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.1 Overall Efficiency at Linear Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.2 Overall Efficiency at Non-linear Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.3 Output Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.4 Output Voltage THD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.5 Power Factor Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.6 Response on Step Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6 Freescale Semiconductor
Chapter 7
System Set-Up and Operation
7.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1.1 Setting of Mains Line System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 Software Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.1 Application Software Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.2 Application PC Master Software Control Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.3 Application Build. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.4 Programming the MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3 Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.1 On-line Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.2 Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3.3 Remote Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix A. Schematics
A.1 Schematics of Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.2 Schematics of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
A.3 Schematics of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.4 Parts List of UPS Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5 Parts List of User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
A.6 Parts List of Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix B. References
Appendix C. Glossary
Freescale Semiconductor 7
Contents
8 Freescale Semiconductor
Figures
Freescale Semiconductor 9
Figures
10 Freescale Semiconductor
Tables
Freescale Semiconductor 13
Introduction
LINE FILTER
BATTERY
CHARGER
AC AC SWITCH
~ = = ~
DC DC
INVERTER
+ - Normal operation
Backup operation
BATTERY
Figure 1-1. Passive Standby UPS Topology
During normal operation, while the mains line (the power cord for the ac line) is available, the load is
directly connected to the mains. The battery is charged by the charger, if necessary. If a power failure
occurs, the switch switches to the opposite position, and the load is powered from the batteries. An
inverter converts the battery dc voltage level to an ac mains level. The inverter generates a square wave
output.
The advantage of passive standby topology is its low cost and high efficiency. The disadvantage is limited
protection against power failures. Because the load is connected to the mains line through the filter only,
the load is saved against short sags and surges.
14 Freescale Semiconductor
UPS Topologies and Features
BYPASS
BATTERY
CHARGER
AC AC SWITCH
~ = = ~
DC DC
INVERTER
+ - Normal operation
Backup operation
BATTERY
Figure 1-2. Line-Interactive UPS Topology
Freescale Semiconductor 15
Introduction
BYPASS
RECTIFIER PFC
IN
DC
OUT
BATTERY
= ~
CHARGER AC
AC DC INVERTER
~ = = =
DC DC
DC-DC
CONVERTER
+ - Normal operation
Backup operation
BATTERY
Figure 1-3. On-Line UPS Topology
As can be seen, the complexity of the on-line UPS is much greater than the other two topologies
described in this section. This means that the cost is higher, and the efficiency is lower due to double
conversion.
However, the on-line UPS brings a much higher quality of delivered energy. The UPS generates a pure
sine wave output with tight limits (typically ±2%). Besides the power failures eliminated by previous
topologies, the on-line UPS avoids all the failures relating to frequency disturbance, such as frequency
variation, harmonic distortion, line noise, or other shape distortions.
16 Freescale Semiconductor
MC9S12E128 Advantages and Features
Freescale Semiconductor 17
Introduction
18 Freescale Semiconductor
Chapter 2
System Description
DC-AC
PFC
L1
D1
D2
KBU8J Q1 D3
IN - + + C1
Q2
IN
C2 + D4
Q3
GND
OUT
D5
Filter
OUT
DC-DC Converter
D6
D7 L2
Q4
T1
GND
Q5
D8 L3
Charger
(Flyback
Converter) BT1 D9
GND
GND
Freescale Semiconductor 19
System Description
The battery BT1 supplies a load during the backup mode. There are two 12-V batteries connected in
serial. The battery voltage level 24-V is converted to ±390-V by the dc/dc step-up converter (Q4, Q5,
D6-D9, L2, L3, and T1) using a push-pull topology fully controlled by the MCU.
The last part of a UPS is a battery charger. The battery charger maintains a fully charged battery. It uses
a flyback topology controlled by a mixed approach. The flyback converter is controlled by a dedicated
circuit and the required output voltage and current limit are set by the MCU. A dedicated circuit is used
due to the lower cost compared to direct MCU control. Where a different battery charger topology is used,
there is still enough MCU power to provide digital control.
20 Freescale Semiconductor
System Concept
Figure 2-4 shows the user interface PCB. It includes two buttons (ON/OFF, BYPASS), four status LEDs
(on-line, on-battery, bypass, and error), and six LEDs indicating output power or remaining battery
capacity. There are also two serial RS232 ports, which can used for communication with the PC. The user
interface provides an extension of the serial ports, which are implemented on the MC9S12E128 controller
board.
Freescale Semiconductor 21
System Description
Figure 2-5 shows a controller board for the MC9S12E128. The MC9S12E128 controller board is designed
as a versatile development card for developing real-time software and hardware products to support a
new generation of applications in UPS, servo and motor control, and many others.
The power of the 16-bit MC9S12E128, combined with Hall-effect/quadrature encoder interface, circuitry
for automatic current profiling, over-current logic and over-voltage logic, and two isolated RS232
interfaces, makes the MC9S12E128 controller board ideal for developing and implementing many motor
controlling algorithms, UPS, SMPS, as well as for learning the architecture and instruction set of the
MC9S12E128 processor.
For more detailed information on the MC9S12E128 controller board, see [33].
An overall view of the assembled UPS is shown in Figure 2-6.
22 Freescale Semiconductor
System Specification
Architecture and Concept The UPS should be a regenerative 1-phase online type UPS with an automatic bypass
feature when self check fails or is overloaded. The UPS is controlled manually from a front
panel switch and from PC application software.
On-line: If the input power is available, the UPS supplies a load and eliminates all possible
defects on the line (online double conversion)
Battery: If the input power is not available, the UPS supplies a load from batteries. The
backup time is given by battery capacity.
Functional Modes Bypass: The UPS directly connects its output and input, so the load is directly connected to
the input line. The transition to this mode is set manually or automatically during overload or
fault
Fault: If any fault is detected, the UPS signals fault, and if it is possible, the bypass is
activated.
45 to 65 Hz Operating Frequency Range
120 V (at 25% of load) — 280 V Operating Voltage Range for nominal mains 230 V
Input 85 V to 135 V Operating Voltage Range for nominal mains 110 V
Power factor at input > 0.95 at nominal voltage
Conversion efficiency > 85% at nominal output power
Number of output ports 6 in 2 segments
Output voltage selectable 110/120/200/220/230/240 V
Output power 725 – 750 VA at 230 V mains input voltage
Output Output power 325 – 350 VA at 110 V mains input voltage
Output waveform: true sine wave < 5% THD
Output frequency 50/60 Hz +/-0.3%
Output load regulation +/-2% (at steady state and linear load)
Battery 2*12 V
Battery
Battery 7.2 Ah
2x RS232 port for communication with host PC with opto-isolation implemented on
Communication
MC9S12E128 Controller Board
4 LED indicators (on-line, battery, bypass, fault)
Visual Interface battery level gauge 6 levels (<5/20/40/60/80/100%)
load level gauge 6 levels (20/40/60/80/100/>100%)
Control Interface 2x buttons for user control (on/off, bypass)
Fault
Overload
Audible warning
low battery
lasts 5 minute
Coding in C language according to ANSI C standard for software running on MCUs
Implementation
Coding in assembler if needed for software running on MCUs
Freescale Semiconductor 23
System Description
24 Freescale Semiconductor
Chapter 3
UPS Control
Freescale Semiconductor 25
UPS Control
MC9S12E128
Output Voltage
PU7
no
Bulk mode
Set HV level
yes
IBAT > 0.05C
no
Absorption mode
Set HV level
Float mode
Set LV level
Battery Voltage
AN03
26 Freescale Semiconductor
Control Techniques
MC9S12E128
PFC ENABLE
PU8
SIN REFERENCE
DA0
UREQ +
PI Controller
-
SINUS +
GENERATION
Top DC Overvoltage
FAULT1
Bottom Overvoltage
FAULT0
Freescale Semiconductor 27
UPS Control
Hysteresis Sine
Levels Reference
Input current
PWM 4
PWM 3
28 Freescale Semiconductor
Control Techniques
The control algorithm is depicted in Figure 3-5. Both dc bus voltages pass the digital filter, and their sum
is compared with the required value of the dc bus voltage. Based on the error, the PI controller sets the
desired duty cycle of the switching transistors.
During mains line operation, the required value of the dc bus is set to 720 V (2 x 360 V). Because the dc
bus is kept by the PFC at 780 V (2 x 390 V), the dc/dc converter is automatically switched off. In case of
mains failure, the dc bus voltage will start to fall. As soon as the voltage reaches the value 720 V, the
dc/dc converter is activated. At 720 V, there is still 20 V reserve in amplitude to generate a maximum
output voltage of 240 V RMS. As soon as the operation from batteries is recognized, the required value
of the dc bus voltage is increased back to 780 V.
The PI controller maintains the constant voltage on the dc bus independent of the load until the mains is
restored or the battery is fully discharged. If the battery is discharged, the UPS output is deactivated and
UPS stays in STANDBY ON BATTERY mode. After 1 minute, the UPS is switched off.
The PI controller constants were experimentally tuned in the same way as the PFC. The constants are
P = 39 and TI = 0.0033 s. The control loop is calculated every 1 ms.
MC9S12E128
PMF3
Output Transistors
UREQ + PMF4
PI Controller
-
Top DC Overvoltage
FAULT1
Bottom DC Overvoltage
FAULT0
Freescale Semiconductor 29
UPS Control
+DCBUS
-DCBUS
Figure 3-6. Sine Wave Modulation
The control algorithm can be seen in Figure 3-7. The main control loop comprises of the PID controller
and a feed forward control technique. The required value entering the PID controller is generated by a
sine wave generator, optionally synchronized with input voltage. The same value is added directly to the
output of the PID controller. It is called the feed forward technique, and it improves the responds of control
loop. The amplitude of the sine wave reference is corrected by RMS correction, which keeps the RMS
value of the output voltage independent of any load. The RMS correction uses the PI controller. The PI
constants were experimentally tuned, and set to P = 0 and TI = 0.00936.
The PID controller was tuned using simulation in MATLAB. The results of the simulation can be seen in
Figure 3-8 and Figure 3-9, with P = 0.6, TI = 0, TD = 0.00071 s, and N = 31. The value N represents the
filter level of D portion EQ 3-5.
The result of the PID controller, including feed forward, is scaled relative to actual dc bus voltage. Then
the exact duty cycle is set to the PMF module.
30 Freescale Semiconductor
Control Techniques
Freescale Semiconductor 31
UPS Control
1
u ( s ) = K e ( s ) + -------- e ( s ) (EQ 3-3)
sT I
1
u ( s ) = K e ( s ) + -------- e ( s ) + sT D e ( s ) (EQ 3-4)
sT I
To improve the response of the PID controller to noisy signals, the derivative portion is often replaced by
a derivative portion with filter:
sT D
sTD ≈ ------------------- (EQ 3-5)
sT
1 + --------D-
N
For implementation of algorithms on MCU the equations EQ 3-3 and EQ 3-4 have to be expressed in
discrete time domain like:
u ( kh ) = P ( kh ) + I ( kh ) + D ( kh ) (EQ 3-6)
32 Freescale Semiconductor
Control Techniques
where
P ( kh ) = K ⋅ e ( kh ) (EQ 3-7)
Kh
I ( kh ) = I ( kh – h ) + ------- e ( kh ) (EQ 3-8)
TI
TD KT D N
D ( kh ) = --------------------- D ( kh – h ) – --------------------- e ( kh – h ) (EQ 3-9)
T D + Nh T D + Nh
e ( kh ) = w ( kh ) – m ( kh ) (EQ 3-10)
and
Freescale Semiconductor 33
UPS Control
The PLL algorithm measures a period from last two zero crossing signals. Because calculation of the
phase increment to the sine wave table requires a division instruction EQ 3-11, the phase over one-half
period is calculated instead:
T
Phase Increment = 32767 ----------------- (EQ 3-11)
Period
where
If phase increment just corresponds to the measured period we should get a phase of 180º. If there is
some difference, the phase increment must be adjusted (see Figure 3-10). Based on the sign of the phase
difference, the phase increment is incremented or decremented by the value which is equal to the phase
difference multiplied by the PLL constant.
If the phase difference falls below some limit for last 20 periods, the PLL is locked to the line frequency
and a frequency locked status bit is set.
Actual Period
Zerocrossing
Signal
Actual
Phase
0º 180º
Actual Phase
Increment Phase
Difference
34 Freescale Semiconductor
Chapter 4
Hardware Design
Freescale Semiconductor 35
Hardware Design
J101
J104 J100 PSH02_02P
J102 J103
1
2
Auxiliary Power Supplies
+VBAT
F101 /POWER_EN
POWER_EN
1 3
2 4
+15V_BOT
+15V_TOP
+15V_PFC
GND_BOT
GND_TOP
GND_PFC
+5V_REF
-5V_BOT
-5V_TOP
FUSE AUTO 40A
+5V_D
+5V_A
GNDA
+15V
GND
+VBAT
Battery Charger
L J105 L +VBAT
N +VBAT -VBAT
F102 +15V +15V_TOP
-VBAT
+5V_A +5V_A +5V_D
GNDA /POWER_ON +5V_A -5V_TOP
6.3A/fast GND_TOP
GND
+15V_BOT
GNDA GND GND
F100 HV_BAT_LEVEL -5V_BOT
GND_BOT
IBAT_CONTROL
+15V_PFC
2A/fast GNDA
VBAT
N J106 IBAT
+5V_REF GND_PFC
PFC+Inverter
+5V_REF
-5V_BOT
GND_BOT
+15V_BOT
GND
+5V_D
GND_PFC
+15V_PFC
GNDA
+5V_A
+15V
-5V_TOP
GND_TOP
+15V_TOP
L1
L2
N
PE MH100 PE
PE CONNECTION
PWM_TOP
PWM_BOT J107
Control Board Interface
GNDA J108
GNDA PWM10 FAN_PWM
GND PWM12
+5V_D
UNI-3 PFC_EN
GND +5V_D TIM14 RLY_IN OUT1
V_DCB_BOT
V_DCB_TOP
V_OUT_BOT
+5V_A
V_OUT_TOP
+5V_A TIM15 RLY_BYPASS OUT2 J109
DCB_NEG
+15V
DCB_POS
+15V TIM16 RLY_OUT1 N_OUT
PFC_ZC
FAULT0
FAULT1
TIM17 RLY_OUT2
I_OUT
TEMP
FAN+
V_IN
DIV1
DIV2
DA0
DA1
I_IN
J110
AD2 FAN-
AD3 1
2
AD1 PSH02_02P
AD4 UNI-3_PWM2 J111
AD5 UNI-3_PWM3
AD6 UNI-3_PWM4 1
UNI-3 PHAIS UNI-3_PWM5 2
UNI-3 PHCIS PSH02_02P
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
UNI-3 BEMFZCA
UNI-3 BEMFZCC
UNI-3 BEMFZCB
UNI-3 PFC_ZC DC-DC Step Up
DA0
Fault1
Fault0
DA1 GND
GND GNDA
GNDA +VBAT DCB_POS
-VBAT +VBAT DCB_NEG
-VBAT
PWM4
PWM5
36 Freescale Semiconductor
Battery Charger
Output voltage
High voltage level 29.4 V
Low voltage level 27.4 V
Output current
Max. value 1.8 A
Absorption - float threshold 0.36 A
NOTE
The output values are set to the values recommended by the battery
manufacturer. The current limits can be set to any value by SW.
Freescale Semiconductor 37
TP300
D301 Vbat
D302 C302 BYW29E-200 29.4V @ Q4 ON
D303 T300 L300
B250R 220uF/450V P6KE200 27.4V @ Q4 OFF
1 13 +VBAT
47uH
+
C301 LINE_OK
R301
4.7nF 68k R302 R303
L
+
1M 9 24k
D304
R304
7 39k
-
1N4148 C303
6 5 R305
D305 R306 220uF/50V 1k8
TR02/MC145 100nF 220uF/50V
N BYV26C 1M R307
+ + 100u/50 +
620
sense
sense
C
ISO300 GND_CH MMBF0201NLT1 GND
CONTROL
1 SFH615A-2
4 1
F X R329 IBAT1 IBAT2
R313
TOP249Y 27R 1K
4 5 3 GNDA
3 2 R314
HV_BAT_LEVEL
100
C316
R315 +
7.5k 100n C307 R308
47uF/10V 3K6
R331
100
R316 R317
220 33K +5V_A D309
100nF 5V1
C300
C309 C308
470nF GND_CH GND
8
1
R319 Q300 220n
1k6 MC33502 3
U301B + R318
IBAT1 6 - R320 1 BC847 8
7 2 - 100k
IBAT2 5 U301A U302
100K
+ 6
MC33502 TL431ACD
R321
4
1k6 R322
220 GND
C314 R323 R324
N/P GND_CH 1k 1k C312 D307
IBAT_CONTROL R327 R328
LINE_OK /POWER_ON
R325 R326
C311 560 68K
33K C310 10nF/100V BAV103 D
3k9
470nF 470nF C313
D308 R330
GND 10k G
BAV103
100nF/100V
4.875V @ 2.34A
IBAT GND Q302 S
MMBF0201NLT1
GND
GND_TR GND
The calculated parameters of the flyback transformer are specified in Table 4-3. The measured values on
the manufactured sample are listed in Table 4-4. To decrease leakage inductance, the interleaved
winding layout is used for the primary winding. The complete transformer winding layout is shown in
Figure 4-4.
Freescale Semiconductor 39
Hardware Design
14 8
L3
Core ETD29/16/10 N87 B66358-G-X187 1pcs
ETD29/16/10 N87 B66358-G500-X187 1pcs
Coil former B66359-J1014-T1 1pcs
Yoke B66359-A2000 2pcs L1 L4 L2
(EPCOS components)
1 7
40 Freescale Semiconductor
Battery Charger
Freescale Semiconductor 41
Hardware Design
As the name of algorithm suggests, charging consists of three stages. The charging starts with the current
limit 0.25 of battery capacity. The battery charger works in current mode until the battery voltage reaches
the high level voltage (2.45 V/cell). This stage is called bulk charging. As soon as the battery voltage
reaches the high level, the current starts to fall, and the absorption stage begins. Once the battery current
falls under 0.05 of battery capacity, the battery charge voltage is set to the low level (2.28 V/cell). The last
stage is called the float stage.
NOTE
The voltage levels and current thresholds come from the battery
manufacturer. The values may also vary with the temperature if
temperature measurement is implemented.
+VBAT U202
LM2575-5
TP204 +5V_D
R212 4
1 +5V_D
33k
L202
2
470uH
1
/POWER_EN
R200
3
D210 + 510
+ 1N5819
C215
2
D C216 220uF/10V
22uF/50V D211
KA3528LSGT
R213 G
POWER_EN
100
Q200 S
MMBF0201NLT1
GND GND GND GND GND GND
U200
LM2575-15
TP200 +15V
4
1 +15V
L203
2
1
680uH
1
R214
R215 2.4k
3
D213 20K
+ 1N5819
2
+
12
C218
22uF/50V R216 C217 D214
1.8K 220uF/10V KA3528LSGT
2
TP207 TP208
U203 +5V_A Vref
L205 MC78L05ACP +5V_A L200 +5V_REF
+15V 3 VIN VO 1
10uH 10uH
+
GND
+ C221 C200
100nF C220
C219 100nF 22u/20V
22u/20V
2
42 Freescale Semiconductor
Auxiliary Power Supplies
Supply voltages for the microcontroller and other digital circuits (+5V_D) are generated by U202. U200 is
used to stabilize +15V for the flyback converter, relays, dc/dc MOSFETs drivers, and cooling fans and it
is used as a down-converter for U203 in order to lower the power loss dissipated by U203. The IC supplies
5 V for op amps, comparators, and the heatsink temperature sensor. The output voltage is further filtered
and used as a reference for the signal and control circuits. In order to switch-on and switch-off all the
control and signal circuits, U200 and U202 are controllable by POWER_EN and /POWER_EN signals.
POWER_EN signal is driven by the microcontroller to control the switch-off process. /POWER_EN signal
is grounded when the “ON” button is depressed. All the power supplies are put into an operational state,
the micro starts to execute the program, and the POWER_EN signal is then put into the active state to
hold the supplies operational even when the button is released.
Figure 4-7 shows the isolated flyback converter schematic that provides the inverter and PFC drivers with
a power supply. MOSFET Q201 is driven by UC3843 in a classic current-mode configuration without the
feedback loop. The supply is designed to deliver constant power to the output while access power is
dissipated in zener diodes D202-D203, D206-D207, and D209 in case of drivers-in-standby. Respective
zener diodes are used specifically to split the secondary voltage to 5-V and 15-V levels.
Freescale Semiconductor 43
C201
R201 TP201
+15V_TOP
220
T1 100pF D201 +15V_TOP
12
LL4448 TP209
D202 GND_TOP
+ C202
8z. 220uF/25V BZV55/15V
+15V 1 11
C204 8 +
D203 GND_TOP TP210
C203 -5V_TOP
L201 BZV55/5V1
47nF 100uF/10V
330u 5z. 8z.
7
R202 GND -5V_TOP
2
D204 6 C205
R203 15k R205 TP202
R204 +15V_BOT
U201 D D1
15k
1 8 MMBD914LT1
220 6z. 100pF D205
220
+15V_BOT
R206 COMP VREF
8.2k 2 VFB VCC 7 R207 5
1
3 6 G
ISENSE OUT Q201 TP211
+ C206 4 5 33 LL4448 D206
RT/CT GND S NTF3055 C208 TR01/MC145 + C207 GND_BOT
330uF BZV55/15V
UC3843 220uF/25V
R209
2
+ TP213
C214 D209
GND_PFC
220uF/25V BZV55/15V
GND_PFC GND_PFC
t ON ⋅ I P
Q = ∫ i dt = ----------------
- (EQ 4-2)
2
Because the voltage is equal, the equality of these charges also provides equal energies. When we
compare both equations, we get
P IN t ON ⋅ I 1P
- ⋅ T = -------------------
-------- (EQ 4-3)
V IN 2
The peak secondary current for a 20-V output is calculated using EQ 4-6 (all the output power is
considered), and the secondary winding inductance L2 is then given by EQ 4-7.
V IN 15
L 1 = --------- dt = ------------- ⋅ 1.5µ = 38µH (EQ 4-5)
di 0.586
V OU T 20
L 2 = ------------- dt = ------------- ⋅ 1.8µ = 123µH (EQ 4-7)
di 0.293
Freescale Semiconductor 45
Hardware Design
Let’s choose a RM8 core made from N97 ferrite material, with Ae = 64mm 2 and AL = 3300 nH. Respective
winding turns are as follows:
L 38µ
N1 = ------P- = --------------- = 3.4 ≈ 4t (EQ 4-8)
AL 3300n
L 123µ
N2 = ------S- = --------------- = 6.1 ≈ 6t (EQ 4-9)
AL 3300n
For supplying the PFC driver, 15-V supply voltage is necessary and the turns ratio between both
secondaries is used to calculate the number of turns for the PFC driver.
15 15
N 4 = ------ ⋅ N 2 = ------ ⋅ 6 = 4.5t (EQ 4-11)
20 20
Rounding the number up or down would cause large unbalanced secondary voltages. Secondary turns
are then scaled to obtain appropriate secondary-to-secondary ratio. Afterwards, primary turns are also
altered. In this case, N2 = 8t gives exact value of N 4 = 6t as follows:
15 15
N 4 = ------ ⋅ N 2 = ------ ⋅ 8 = 6t (EQ 4-12)
20 20
To maintain a discontinued conduction mode, the switching frequency has to be also altered to the value
of 200 kHz. And the maximum flux has to be checked - simulation shows flux of amplitude 160 mT.
Figure 4-8 shows the layout of the windings on the transformer bobbin.
46 Freescale Semiconductor
dc/dc Step-Up Converter
5T Cu f 0.25mm
Freescale Semiconductor 47
L501
-OUT
DCB_NEG
650u/1A
D501
680u/50V 680u/50V 680u/50V +Bat 1 2 C501
+VBAT 22n/400V
MUR180
R501
1
C502 + C503 + C504 + C505 + C512 + C513 + 1k/5W
1 2
R502
2
2
FFPF05U120STU 1k/5W
-VBAT FFPF05U120STU 1 2
680u/50V 680u/50V 680u/50V D500 D502
GND_BAT MUR180
1 2 C506
22n/400V
D504 D505 D503 L502
+OUT
DCB_POS
650u/1A
FFPF05U120STU GND FFPF05U120STU
+15V +15V
13
15
10 18
T500
TR03/MC145
L503 1 9 L500
330u 330u
R503
4
6
100R/1W
1 2
100R/1W
1
47uF R504 47uF
C509 C508 C510
2 1 1n
1 2 1 2
+
+
GND_BAT GND_BAT
2
2
GND_BAT GND_BAT
GND_BAT
Q501 Q500 Q502 Q503
NTP45N06 NTP45N06 NTP45N06 NTP45N06
6
6
U500 MC33152D U501 MC33152D
1 NC VCC NC 8 D D D D 8 NC VCC NC 1
TP501
PWM_4 TP502
R505 R500
2 InA OutA 7 1 2 G G G G1 2 7 OutA InA 2 PWM_5
10 10
PWM4 S S S S
R506 R507 PWM5
1
1
4 InB OutB 5 1 2 1 2 5 OutB InB 4
R508 R509
10 10
10k 10k
GND GND
2
2
GND_BAT
GND_BAT GND_BAT
GND_BAT GND_BAT
9.98m 1 1 2k V4
K K1 22n R28
K_Linear 390 524meg
COUPLING = 1
1
0
1 2 1 2 2
2 1 390
30.8u 30.8u
2 L6 R29
L3 L1 L2 L4 2 2 R23 C8 V5 524meg
L15 9.98m
26.7n 26.7n L11 L12
15n 2k
L8 R4 C10 22n R6
1 20n 20n 10p
1 2 50m
1 2 D8 R19
1 1 2 10u 0.5 2
R16 R17
L21 L18 1 1 L14
1000
2n 2n 4700 4700 20n
mur2100e/ON
Inverter Model 2u V1 2u D3 C6 D4
23.2 C3 10p L17 R9
2 1 1
1 2
560u 0.3
R1 R2 10p mur2100e/ON mur2100e/ON
5m R14 R7 R15 5m
20m
100 100
Implementation = 1 R10 M1 M3 C1 C2 M2 M4 R12 Implementation = 2
Current Sensing
1n 1n
20
V2 20 V3
S S K K2 D1N4149
R11 NTP45N06 NTP45N06 NTP45N06 NTP45N06 R13 D12
K_Linear
COUPLING = 1
0 20 20 0
L20 R25 R27
1 2 D6
0 1 1.6m 3 220
D1N4149
L19 C11 D9
5p R24
80u D1N4149 22
80m R26 C12
1k
2 10n
D10
D1N4149
D11 0
D1N4149
The inverter is supplied by a set of a low-ESR capacitors, C502-C505 and C512-C513, to lower the
battery bus ripple current and hence the EMI signature of the converter input. Inverter MOSFETs
Q500-Q503 are driven by MC33152 drivers. MOSFETs drain voltage ringing is damped by RC cells
R504-C507 and R503-C508. Because of the voltage source character of the inverter, the rectifier has to
be a current type, which is why smoothing chokes L501 and L502 are used. Over voltage spikes across
the rectifier diodes, due to the diodes reverse-recovery and transformer leakage, are clamped by RCD
snubbers consisting of a R501- C501- D501 for the positive side, and R502 - C506 - D503 for the negative
side.
ui = induced voltage
ψ = linkage flux in the core
N = number of turns
Φ = flux in the core
Β = flux density in the core
u i dt = N ⋅ S ⋅ ∆B (EQ 4-15)
∫
where
50 Freescale Semiconductor
dc/dc Step-Up Converter
Initially, the magnetic charge has to be calculated. Since the induced voltage during an active part of the
converter operational cycle is constant and it equals the input voltage, the magnetic charge in the core is
given by EQ 4-16.
∫
u i dt = V IN ⋅ δ ⋅ T (EQ 4-16)
where
–6
u i dt = 24 ⋅ 0.45 ⋅ 20 ×10 = 216 µVs (EQ 4-17)
∫
Simulation results can also be used to obtain the magnetic charge. Figure 4-11 shows simulated
magnetizing voltage and magnetic charge. Magnetic charge is obtained by the time integral of the
magnetizing voltage. Peak-to-peak reading of the magnetic charge is 218 µV.
Rearranging EQ 4-15, the number of primary turns can be calculated:
u dt –6
∫ i 216 ×10
N1 = --------------- = ----------------------------------
- = 3.12 t (EQ 4-18)
S ⋅ ∆B 173 ×10–6 ⋅ 0.4
40V 100u
1 2
20V 0
0V -100u
-20V -200u
>>
-40V -300u
15us 20us 25us 30us 35us 40us 45us
1 V(L1:1,L1:2) 2 S(V(L1:1,L1:2))
Time
Freescale Semiconductor 51
Hardware Design
Let’s choose 3 turns. However, the flux density travel ∆B has to be checked:
u dt –6
∫ i 216 ×10
∆B = -------------- = -----------------------------
- = 416 mT (EQ 4-19)
S ⋅ N 1 173 ×10–6 ⋅ 3
From EPCOS Siferit N97 specification (FAL0625-W @60°C), the core power loss is 10 W, indicating a
good core utilization. However, forced convection should be considered. The negative loss temperature
coefficient of the N97 material is advantageous since it contributes to a temperature stability of the core
(FAL0624-N).
Now, the number of turns of the secondaries can be calculated. For primary to secondary ratio and a
forward type of converter, equation EQ 4-20 is valid:
V OU T
p = ----------------------------------
- (EQ 4-20)
V IN ⋅ η ⋅ δ MA X
For efficiency η = 0.93 and maximum duty δ(MAX) = 0.98, EQ 4-20 yields
V OUT 350
p = ----------------------------------- = ------------------------------------ = 18.47 (EQ 4-21)
V IN ⋅ η ⋅ δ MAX 21 ⋅ 0.93 ⋅ 0.97
Primary to secondary ratio is rounded to 18, and the secondary winding number of turns yields
N 2 = p ⋅ N 1 = 18 ⋅ 3 = 54t (EQ 4-22)
Once the winding turns are determined, the cross sectional area of a winding can be calculated. For the
ETD44 core, winding current density can be selected in the range 5-10A/mm 2. Let J = 8A/mm2. Primary
cross-sectional area is given by EQ 4-23
I 19.1 2
S 1 = ----1 = ---------- = 2.39 mm (EQ 4-23)
J 8
where
Ι1 = nominal primary winding current obtained by integrating the square of the simulated
winding current (Figure 4-12).
52 Freescale Semiconductor
dc/dc Step-Up Converter
60A 915m
1 2
40A 910m
20A 905m
0A 900m
>>
-20A 895m
2.2965ms 2.3000ms 2.3040ms 2.3080ms 2.3120ms 2.3160ms 2.3200ms 2.3240ms 2.3280ms
1 -I(R1) 2 S(I(R1)*I(R1))
Time
where
Ι2 = nominal secondary winding current obtained by integrating the square of the simulated
winding current (Figure 4-13).
Freescale Semiconductor 53
Hardware Design
1.5A 1.300m
1 2
1.0A 1.296m
0.5A 1.292m
-0.0A 1.288m
-0.5A 1.284m
-1.0A 1.280m
>>
-1.5A 1.276m
2.2965ms 2.3000ms 2.3040ms 2.3080ms 2.3120ms 2.3160ms 2.3200ms 2.3240ms 2.3280ms
1 -I(R3) 2 S(I(R3)*I(R3))
Time
In this case the best solution for the primary is the use of a copper foil. An ETD44 bobbin has a width of
30 mm. Because of the necessary creepage, the foil width is set to 25 mm. Based on the result of
EQ 4-23, the foil thickness yields 100 µm and has excellent skin performance when compared with skin
depth at the current switching frequency.
From the result of EQ 4-24, the secondary winding wire diameter yields 0.338 mm. The nearest wire
diameter in production is 0.315mm. A wire with a larger diameter is not helpful any more because of the
increased ac resistance due to the skin effect.
The primary winding of the push-pull converter transformer uses a center-tapped windings as well as the
secondary windings. As the power transformer is a part of the push-pull converter, there are some
restrictions required, especially with respect to the leakage inductance. With inverter transistor turn-off,
the drain voltage in push-pull is not clamped by the circuit topology itself. For ideal case (zero leakage),
the drain voltage is clamped through the transformer coupling when the rectifier diodes are re-opened.
54 Freescale Semiconductor
dc/dc Step-Up Converter
60V
40V
20V
0V
Freescale Semiconductor 55
Hardware Design
18 10
56 Freescale Semiconductor
dc/dc Step-Up Converter
The primary factor for chip selection are the effective drain current and the switching frequency. Then a
suitable device is selected. Power loss components are calculated and compared with the designed
maximum power loss per package.
Simulation results (Figure 4-12) show a value of 19.1 A (transistor and primary winding currents are the
same). Dynamically, a current level as high as 50 to 60 A is observed when a load transient occurs and
the regulator attempts to hold the output voltage level. Of course the transistor has to withstand such
conditions for a number of milliseconds.
A couple of ON Semi’s twin NTP45N06 could be a solution. RDS(ON) for the transistor is 26 mΩ. If a single
NTP45N06 switches the current with an effective value of 19.1 A, conduction losses are as high as 9.5 W.
To lower the conduction losses and to ensure the transistor switching robustness in dynamic conditions,
let’s consider the twin NTP45N06 which decrease overall conduction losses to the half (power loss per
package decreases to a quarter - 2.4 W). However, the switching and the capacitance losses have to be
considered, due to the increased overall chip area, and hence the overall chip capacitance.
Switching losses are given by EQ 4-26 (ref. [2]).
I SW
P SW = V D S ⋅ ( Q G D + Q GS2 ) ⋅ f SW ⋅ -------- (EQ 4-26)
IG
3 30
P SW = 24 ⋅ ( 3nC + 15nC ) ⋅ 50 ×10 ⋅ ------
- = 0.72 W (EQ 4-27)
0.9
where
Note that VDS can reach a level close to 60V as depending on the particular duty cycle, input voltage, and
output load conditions. The same is true for ISW parameter, and the loss value can be impacted.
CAUTION
If the output load conditions or large transformer leakage cause over
voltage spikes at the drain and the maximum drain voltage is reached, the
voltage is clamped by MOSFET internal avalanche process (see
Figure 4-14 — fourth wave oscillation on green waveform). If the energy of
the spikes is high enough, chip temperature will exceed the maximum limit
and the semiconductor structure is destroyed. Please always observe the
drain-to-source voltage when testing the prototype. If this is the case,
increase the MOSFET voltage class or redesign the power transformer in
order to decrease the leakage.
Freescale Semiconductor 57
Hardware Design
Turn-on capacitance losses PCAP for the NTP45N06 are given by EQ 4-28.
1 2
P CAP = f SW ⋅ W CAP = f SW ⋅ --- ⋅ C OSS ( EFF ) ⋅ V D S (EQ 4-28)
2
3 1 – 12 2
P CAP = 50 ×10 × --- ⋅ 380 ×10 ⋅ 60 = 34 mW (EQ 4-29)
2
where
The sum of the switching and the capacitance losses is less than 0.8W per transistor at nominal
conditions, resulting in 1.6 W for the single NTP45N06 solution and 3.2W for the twin solution. When all
the loss contributions are compared, prevalence of the conduction losses is clear. The twin NTP45N06
solution results in an overall loss of 3.2W per package (the conduction component is 2.4 W, the switching
component 0.8W). Therefore, the twin solution doesn’t contribute significantly to lower a converter
efficiency. Power loss 3.2 W per package means moderate package utilization for TO220, with a good
power loss margin.
The power losses can also be calculated by simulation of the model. Figure 4-16 shows the MOSFET
instantaneous power and energy obtained by instantaneous power integration. The average power is
then calculated by the definition of the power - the energy loss referred to the switching period.
400W 8.04m
1 2
200W 8.00m
0W 7.96m
>>
-200W 7.92m
2.208ms 2.212ms 2.216ms 2.220ms 2.224ms 2.228ms 2.232ms
1 W(M3) 2 S(W(M3))
Time
58 Freescale Semiconductor
dc/dc Step-Up Converter
The use of a single transistor with a higher rated drain current is also possible, however, the copper lead
utilization is rather high even though manufacturers define the value around 75 A as a limit for TO220
package leads.
0.5KV 1.5A
1 2
1.0A
0V
0.5A
-0.5KV
0A
>>
-1.0KV -0.5A
2.3075ms 2.3100ms 2.3150ms 2.3200ms 2.3250ms 2.3300ms
1 V(D1:1,D1:2) 2 I(D1)
Time
Freescale Semiconductor 59
Hardware Design
–6
0.98 ⋅ 10 ×10
L = [ ( 24 – 1.6 ) ⋅ 18 – 390 ] ⋅ ----------------------------------- = 583 µH (EQ 4-31)
0.3 ⋅ 0.74
where
Filter choke performance is analyzed by simulation, and the results (Figure 4-18) verified a good design
procedure. Choke PCV2-564-02 from Coilcraft, with 560 µH inductance and 2 A saturation current, is
chosen.
60 Freescale Semiconductor
Power Factor Correction and Output Inverter
800mA 1.0KV
1 2
400mA 0.5KV
0A 0V
-400mA -0.5KV
>>
-800mA -1.0KV
1.900ms 1.905ms 1.910ms 1.915ms 1.920ms 1.925ms 1.930ms 1.935ms 1.940ms
1 I(L16) I(L17) 2 V(R3:2,R4:2)
Time
Freescale Semiconductor 61
Hardware Design
I_IN1 I_IN2
7
CT1
1:100
L505
D604
L1 DCB_POS
2
2.5mH
RHRP8120
D606
KBPC606
- +
C602
C603 +
Q606 MKP10/22nF/630VDC
IRG4IBC20W 330uF/450V
GATE_PFC
GND_PFC
N N
GND
C607
+ C608
MKP10/22nF/630VDC 330uF/450V
D608
DCB_NEG
RHRP8120
62 Freescale Semiconductor
+5V_A
+5V_A
R657
33 +5V_D +5V_D
C627
3
GNDA 10k 10k R661 100n
U606A 10k 470
R662
R663 4 - V+ 2 470
DA1 5 + V-
3
LM339M D GND
100
U606B
12
C629 R664 6 - V+ G
100n 1.6k 1
7 + V-
GNDA Q609 S
GNDA LM339M MMBF0201NLT1
R665
R666
12
DA0
0
3
100
C630 R667 U606C R669 R670 TP611
GND
R668 100n 8 - V+ 10k 10k
PFC_CTRL
PWM_PFC
14
0
I_IN 9 + V-
C631
LM339M +5V_D
100 100n
12
GNDA GNDA R671
GNDA 4.7k
D
UNI-3 PFC_EN G
Q610 S
MMBF0201NLT1
60%
R673 R674 R675
All On 55%
3.3k
75%
10k
85%
9.1k GND
D D
DIV1 G DIV2 G
Q611 S Q612 S
MMBF0201NLT1 MMBF0201NLT1
1 8 D609
R606
C609 GATE_PFC
PWM_PFC 2 7 100nF 10
BAT42
R607 D628
3 6
15V
100
4 5
GND
GND_PFC
HCPL3150
GND_PFC
If we know the input current maximum value we can calculate a current ripple. We chose the current ripple
to be 15% of the input peak current. For the given peak current value it is:
∆I = I in max ⋅ 0.15 = 0.645A (EQ 4-33)
When the PFC switch is turned on, the following equation has to be met:
∆I
L 1 ⋅ -------- = V in (EQ 4-34)
T on
where
∆I ⋅ L
T on = ---------------1- (EQ 4-35)
V in
When the PFC switch is turned off, the following equation has to be met:
– ∆I
L 1 ⋅ --------- = V in – V out (EQ 4-36)
T off
where
64 Freescale Semiconductor
Power Factor Correction and Output Inverter
– ∆I ⋅ L 1
T off = -----------------------
- (EQ 4-37)
V i n – V out
Frequency is an inverse value of the period. The switching frequency of the PFC is then given by the
formula:
2
1 V out ⋅ V i n – V in
f sw = --- = ------------------------------------
- (EQ 4-39)
T ∆I ⋅ L 1 ⋅ V out
Switching losses of the IGBT transistor are proportional to the switching frequency. To maintain switching
losses within acceptable limits we have to design the input inductor L1 with respect to a maximum
switching frequency. From EQ 4-39, we can calculate the level of input voltage (Vin) when the switching
frequency reaches its maximum value. We get the maximum switching frequency at
V out
V in = ---------
- (EQ 4-40)
2
If we substitute EQ 4-40 for EQ 4-39 we can solve the equation and find the value of the required input
inductance value for the given ripple current (∆I), output voltage (Vout) and maximum switching frequency
(fmax):
V out
L 1 = --------------------------
- (EQ 4-41)
4 ⋅ ∆I ⋅ f max
Freescale Semiconductor 65
Hardware Design
:
Table 4-8. PFC Inductor Parameters
MAXIMUM CURRENT 5 A
FREQUENCY 60 kHz
TEMPERATURE 55 °C
We ran the calculation and got a list of suitable cores, that met our selection criteria. From the list we
selected core: T175-8/90. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-9. Design Parameters for Core P/N: T175-8/90
Al 48 nH
TURNS 287 -
WIRE 1.00 mm
FILL 38.9 %
Rdc 0.4971 Ω
Cu Loss 6.21 W
The core T175-8/90 meets all of our criteria, is an acceptable size, with moderate losses and good
linearity.
66 Freescale Semiconductor
Power Factor Correction and Output Inverter
The dc-bus capacitor is a storage of energy for output power factor circuit and feeds an output inverter.
The dc-bus voltage should be set above the peak at maximum r.m.s. input voltage. For input RMS voltage
Vin = 270 V, the peak voltage is Vin peak max = 381 V. To achieve good regulation of the dc-bus voltage,
the dc-bus voltage should be at least 10% above the peak at nominal r.m.s. input voltage, i.e. for
Vin nom = 230 V RMS: Vdc-bus min = 1.1x1.41x230 = 356 V. Having Vin peak max and Vdc-bus min, we can
determine the dc-bus nominal voltage. We chose Vdc-bus nom = 390 V.
The dc-bus capacitor voltage should at least be rated at 450 V dc.
If ac input is lost, it is desired that the dc-bus capacitor is large enough to hold up the dc-bus voltage at
value Vdc-bus hup, allowing the output inverter voltage to remain within specifications for a time T hup.
The maximum nominal output voltage is Vout nom = 230 V RMS. The dc-bus voltage has to be higher than
the output voltage peak value Vout peak = 325 V. The hold-up time we define as a half-period of the output
ac voltage frequency Thup = 10ms. The minimum dc-bus capacitor value can calculated:
I av ⋅ T hup
C 0 = ----------------------------------------------------- (EQ 4-43)
V dc – busnom – V outpeak
where
Iav is the average capacitor current during the drop from Vdc-bus nom to Vout peak.
The Iav current can be calculated according to the formula:
2P out
I a v = -------------------------------------------------------------- (EQ 4-44)
η ( V dc – busnom + V outpeak )
where
Pout is the inverter output power
η is the inverter efficiency
We can enumerate equation EQ 4-44 and obtain:
2 ⋅ 525
I a v = ---------------------------------------- = 1.728A (EQ 4-45)
0.85 ( 390 + 325 )
The minimum output capacitor value can be calculated if we enumerate formula EQ 4-43:
–3
1.728 ⋅ 10 ⋅ 10 –6
C 0 = --------------------------------------- = 266 ⋅ 10 F (EQ 4-46)
390 – 325
The minimum output capacitance of the dc-bus capacitor is 266µF.
The next parameter we need to know for selecting the output capacitor is the ripple current rating. The
dc-bus capacitor current consists of a dc-component plus an ac-component (100/120 Hz). The
dc-component flows to the load, ac-component flows into the capacitor C0. The ripple current amplitude
is equal to the peak load current. The ripple current can be then calculated:
I load
I ri ppl e = ---------
- (EQ 4-47)
2
The peak load current Iload is:
Pout 525
I l oad = ------------------------------------------
- = ------------------------------- = 0.792A (EQ 4-48)
2 ⋅ V dc – busnom ⋅ η 2 ⋅ 390 ⋅ 0.85
Freescale Semiconductor 67
Hardware Design
1. Nominal output apparent power for nominal output voltage 230 V r.m.s.
68 Freescale Semiconductor
RE1
MZPA001
5 o
o 4 OUT1
3 o
+15V 1 2
RE2
MZPA001
D602
5 o
D
o 4
BAT42
L2 3 o R602
G
RLY_OUT1
100 Q602 S
+15V 1 2 MMBF0201NLT1
GND
D603 RE3
MZPA001
BAT42 D
5 o
R603 o 4 OUT2
RLY_BYPASS G
100 3 o
Q603 S
MMBF0201NLT1
GND +15V 1 2
DCB_POS
D605
BAT42 D
R604 G
RLY_OUT2
100
Q604 S
MMBF0201NLT1
Q605 GND
GATE_TOP
C602
+ HGTG10N120BND
V_OUT
GND_TOP L506
330uF/450V
5mH C604
C605 2 L507 1 PE
6.8uF/400V 4 3 4.7nF/Y1 C606
TL34P 4.7nF/Y1
N
N_OUT
1
2
3
4
CT2
GND
CS2106
8
5
I_OUT2 I_OUT1
Q608
GATE_BOT
+ C608
330uF/450V HGTG10N120BND
GND_BOT
DCB_NEG
The power IGBTs Q605 and Q608 switch in a complementary manner (if Q605 is on, Q608 is off, and vice
versa). Using the power IGBTs, the dc-bus voltage is pulse-width modulated at 20kHz switching
frequency to obtain an output voltage with a low frequency a.c. component (50/60 Hz). The junction of
C602 and C608 is a zero-volts reference for the generated output waveform. The junction of the
capacitors is galvanically connected to the mains N-terminal and is labelled as system ground.
Switching pulses to gates Q605 and Q608 are generated by the dual IGBT gate opto-drive HCPL-315J
(U615). The opto-drive provides the circuitry with galvanic isolation between the MCU and each of the
IGBTs. Its topology is shown in the Figure 4-22. The IGBT gates are floating during the inverter operation
in a voltage range +/- 430 V dc. Each channel of the dual opto-drive IC is supplied from a galvanically
isolated voltage supply of +15V dc.
GATE_TOP
D611 +15V_TOP
D624
D610 15V
R609
BAT42
C610
R608 100nF 33
BAT42 D625
PWM_TOP R610 5V
330
100
GND_TOP
U615
D613 1 16
N/C VCC1 C632
2 15 GND_TOP
ANODE1 VO1 100nF
3 CATHODE1 VEE1 14
BAT42
R611
PWM_BOT 6 11 -5V_TOP
ANODE2 VCC2
330 7 CATHODE2 VO2 10 GATE_BOT
8 N/C VEE2 9
+15V_BOT
HCPL-315J D626
D612 15V
R612
C611
100nF 33
GND BAT42 D627
R613 5V
100
GND_BOT
C633
100nF
GND_BOT
-5V_BOT
70 Freescale Semiconductor
Power Factor Correction and Output Inverter
Capacitance 6.8 µF
Freescale Semiconductor 71
Hardware Design
Frequency 20 kHz
Temperature 55 °C
NOTE
Note that we swapped the input and output peak voltage values in the
design parameters. In a real inverter, the dc voltage is the input parameter
and the ac voltage is the output parameter. To make an analogy with PFC,
we have to swap these parameters in the input table.
We ran the calculation and got a list of suitable cores that met our selection criteria. From the list we
selected core: T200-30B. The software calculates all important data (number of turns, wire diameter,
losses, Rdc, Al, dimensions, etc.). For the selected core, the parameters are as follows:
Table 4-14. Design Parameters for Core P/N: T175-8/90
Al 51 nH
Turns 388 -
Fill 38.5 %
Cu loss 9.38 W
The core T200-30B meets all of our criteria, is an acceptable size, with moderate losses and low price.
72 Freescale Semiconductor
Chapter 5
Software Design
5.1 Introduction
This section describes the design of the software blocks for the UPS. The software is described in terms
of:
• Data flow
• Main software flowchart
• State diagram
For more information on the control technique used, see Chapter 3 UPS Control.
Freescale Semiconductor 73
counter_actual
Button
v_out_rms Processing
PLL
Algorithm
Mains Line buttonStatus
RMS Detection
Correction
phase_pfc phase_out
Application State
phase_pfc_inc phase_out_inc amplitude_correction amplitude_ref v_out_freq_detect v_dcb[] Machine
Ramp
v_sin_ref v_out PWM_to_DCB_scale LED
Processing
v_dcb[] v_dcb_req_rmp v_dcdc_req
Inverter
Control
PFC Control V_bat I_bat
Ramp
PWMB_duty_cycle
i_n_ref Battery Charge
v_dcdc_req_rmp v_dcdc_sum Control
Sine Wave
Reference DC/DC Step Up
Control BatState
pfc_ref_h
PWMC_duty_cycle
Type: S8 = signed 8-bit, U8 = unsigned 8-bit, S16 = signed 16-bit, U16 = unsigned 16-bit.
Freescale Semiconductor 75
Software Design
76 Freescale Semiconductor
Data Flow
• Run on line
• Run on bypass
• Error
• UPS off
After RESET, the state machine enters into the Standby on battery state if the mains line is available.
Then if the user pushes the ON/OFF button, the state machine continues on to the Run on line state.
During mains line failure, the state machine goes to the Run on battery state. The state machine stays
there until the batteries are discharged, the user switches the UPS off, or the main line is restored. If the
batteries are discharged the state machine goes to the Standby on battery state. If the state machine
stays in this state one minute, the UPS is switched off (UPS state) to avoid total discharge of the batteries.
In the case of some fault, the state machine goes into the Error state.
If the state machine goes from one to another state, a respective transition function is called.
CPU RESET
INIT
RUN BYPASS
UPS OFF
The PFC control process consists of the PI controller, which controls the dc bus voltage
v_dcb[] to the required value v_dcb_req (v_dcb_req_rmp). The result defines the
amplitude of the input current (i_n_ref).
Freescale Semiconductor 77
Software Design
78 Freescale Semiconductor
Main Software Flowchart
• Pulse-width modulator
• Voltage regulator
Subsequently, the communication with the PC is initialized, and the program variables are set to default
values.
Then the program enters the never-ending loop providing the application state machine (see main
function listing below).
void main ()
{
InitPeripherals();
PCMaster_Config();
EnableInterrupts; /* enable interrupts to make this routine
interruptible
(defined int PCMaster-S12.h) */
PCMasterInit(); // init PCMaster functions
InitVariables();
while(1)
{
appStateFcn[appState]();
FanControl();
}
}
The structure of the background loop can also be seen in Figure 5-3.
RESET
Background loop
END
of Background loop
Freescale Semiconductor 79
Software Design
Read samples
of slow ATD Conversion
Lost detection
of Line Zero Crossing
END
of Interrupt Service Routine
80 Freescale Semiconductor
Main Software Flowchart
While the fast ATD conversion is running the following tasks are performed:
• Detection of missing zero crossing on the input line
• Detection of input voltage polarity
• RMS value calculation and output power calculation (multiplication and addition)
• Generation of rectified sine waveform for the PFC
• Generation of sine wave reference for the output inverter
The execution time for these tasks is shorter than the conversion time in a fast ATD conversion.
END
of Interrupt Service Routine
Freescale Semiconductor 81
Software Design
TIM 0 ch 4 IC Interrupt
(Line Zero Crossing)
END
of Interrupt Service Routine
TIM 0 ch 5 OC Interrupt
(1 ms)
RMS correction
END
of Interrupt Service Routine
82 Freescale Semiconductor
Main Software Flowchart
TIM 0 ch 6 OC Interrupt
(50 ms)
Software timers
Battery charging
END
of Interrupt Service Routine
Freescale Semiconductor 83
Software Design
Trace
PMF Reload Interrupt
Trace
ATD Complete Interrupt
Trace
1 ms Interrupt
Trace
50 ms
Execution Execution
Name
Period Time
FLASH 10087
RAM 2502
Stack 512
84 Freescale Semiconductor
Software Constant Calculations
where
TI = Integral time constant
h = Sampling time
K = Controller gain
TD
kd1 = --------------------
-
T D + Nh (EQ 5-3)
KT D N (EQ 5-4)
kd2 = --------------------
-
T D + Nh
Freescale Semiconductor 85
Software Design
where
h = Sampling time
N = Filter constant
NOTE
The proportional constant of the output inverter controller is called q1 in the
software.
Example:
Let’s have constants for the PFC controller. The PFC uses the PI controller, where the controller gain
K(P) = 100 and Integral time constant TI = 0.0016 s. The controller is calculated every 1 ms.
–3
100 ⋅ 1 ⋅ 10
From EQ 5-2 we can calculate integral constant as: ------------------------------
- = 6.25 .
0.0016
Since the scale is common for both constants, we choose SCALE = 8. Then we get a proportional gain
100 . 2(16-8) = 25600 and an integral gain 6.25 . 2(16-8) = 1600. In the source code we can see:
86 Freescale Semiconductor
Chapter 6
Tests and Measurements
D1 D3
Rs
2.8 + P1
C1 160
937 uF
D2 D4
Freescale Semiconductor 87
Tests and Measurements
88 Freescale Semiconductor
6.3.2 Overall Efficiency at Non-linear Load
The total efficiency at a non-linear load is 90%. See Figure 6-4.
Freescale Semiconductor 89
Tests and Measurements
90 Freescale Semiconductor
Test Results
Freescale Semiconductor 91
Tests and Measurements
92 Freescale Semiconductor
Test Results
Freescale Semiconductor 93
Tests and Measurements
94 Freescale Semiconductor
Test Results
6.3.7 Summary
All measured parameters are summarized in Table 6-1
Table 6-1. Summary of Measured Parameters
Load
Parameter
Linear Non-linear
Freescale Semiconductor 95
Tests and Measurements
96 Freescale Semiconductor
Chapter 7
System Set-Up and Operation
WARNING
This application operates in an environment that includes dangerous
voltages. The application includes batteries and dangerous voltage
may appear even if the application is not connected to the mains line.
An isolating transformer should be used during debugging. If an
isolating transformer is not used, power stage grounds and
oscilloscope grounds will be at different potentials, unless the
oscilloscope is floating. Note that probe grounds, such as in the case
of a floating oscilloscope, are subject to dangerous voltages. Take
note of the following points and recommendations
Freescale Semiconductor 97
System Set-Up and Operation
98 Freescale Semiconductor
MAINS LINE OUTPUT
SWITCH SECTION 2
OUTPUT
SECTION 1
MAIN LINE
INPUT
Freescale Semiconductor 99
System Set-Up and Operation
ON/OFF Status
Button LEDs
LED Bargraph
Bypass
Button
J101
J104 J100 PSH02_02P
J102 J103
1
2
Auxiliary Power Supplies
+VBAT
D D
F101 /POWER_EN
POWER_EN
1 3
2 4
+15V_TOP
+15V_BOT
+15V_PFC
GND_TOP
GND_BOT
GND_PFC
+5V_REF
-5V_TOP
-5V_BOT
FUSE AUTO 40A
+5V_D
+5V_A
GNDA
+15V
GND
+VBAT
Battery Charger
L J105 L +VBAT
N +VBAT -VBAT
F102 +15V +15V_TOP
-VBAT
+5V_A +5V_A +5V_D
GNDA /POWER_ON +5V_A -5V_TOP
6.3A/fast GND_TOP
GND
+15V_BOT
GNDA GND GND
F100 HV_BAT_LEVEL -5V_BOT
GND_BOT
IBAT_CONTROL
+15V_PFC
2A/fast GNDA
VBAT
N J106 IBAT
+5V_REF GND_PFC
PFC+Inverter
GNDA
GND
+5V_D
GND_PFC
+5V_A
+15V
+15V_PFC
-5V_TOP
GND_TOP
+15V_TOP
+5V_REF
-5V_BOT
GND_BOT
+15V_BOT
L1
C L2 C
N
PE MH100 PE
PE CONNECTION
PWM_TOP
PWM_BOT J107
Control Board Interface
GNDA J108
GNDA PWM10 FAN_PWM
GND PWM12
+5V_D
UNI-3 PFC_EN
GND +5V_D TIM14 RLY_IN OUT1
V_DCB_TOP
V_OUT_TOP
V_DCB_BOT
V_OUT_BOT
+5V_A +5V_A TIM15 RLY_BYPASS OUT2 J109
DCB_NEG
+15V
DCB_POS
+15V TIM16 RLY_OUT1 N_OUT
PFC_ZC
FAULT0
FAULT1
TIM17 RLY_OUT2
I_OUT
TEMP
FAN+
DIV1
DIV2
V_IN
DA0
DA1
J110
I_IN
AD2 FAN-
AD3 1
2
AD1
PSH02_02P
AD4 UNI-3_PWM2
J111
AD5 UNI-3_PWM3
AD6 UNI-3_PWM4 1
UNI-3 PHAIS UNI-3_PWM5 2
UNI-3 PHCIS
PSH02_02P
UNI-3 DCBI UNI-3 PFC_EN
UNI-3 DCBV UNI-3 SERIAL
UNI-3 BEMFZCA
B UNI-3 BEMFZCC B
UNI-3 BEMFZCB
UNI-3 PFC_ZC DC-DC Step Up
DA0
Fault1
Fault0
DA1 GND
GND GNDA
GNDA +VBAT DCB_POS
-VBAT +VBAT DCB_NEG
-VBAT
PWM4
PWM5
A A
12
LL4448 TP209
D202 GND_TOP
+ C202
8z. 100uF/16V BZV55/15V
+15V 1 11
C204 8 +
D203 GND_TOP TP210
C203 -5V_TOP
L201 BZV55/5V1
47nF 100uF/16V
330u 5z. 8z.
7
R202 GND -5V_TOP
2
D204 6 C205
R203 15k R205 TP202
R204 +15V_BOT
U201 D D1
510R
1 8 MMBD914LT1
220 6z. 100pF D205
220
+15V_BOT
R206 COMP VREF
16K 2 VFB VCC 7 R207 5
1
3 6 G
ISENSE OUT Q201 TP211
+ C206 4 5 33 LL4448 D206
RT/CT GND S NTF3055 C208 TR01/MC145 + C207 GND_BOT
330uF/35V BZV55/15V
UC3843 100uF/16V
R209
2
R208 C209 100pF
N/P 1k
100nF + C210 GND_BOT TP212
C211 R210 D207
C212 100uF/16V -5V_BOT
100pF 1.8 BZV55/5V1
100pF
LL4448
+ TP213
C214 D209
GND_PFC
100uF/16V BZV55/15V
GND_PFC GND_PFC
+VBAT U202
LM2575-5
TP204 +5V_D
R212 4
1 +5V_D
33k
L202
2
470uH
1
/POWER_EN TP206
R200
5
+ 510 GND
D210 +15V_TOP +15V_TOP
+ MBRA140
C215
2
Q200 C216 220uF/35V GND_TOP
BC846 22uF/50V D211 GND
KA3528LSGT GND_TOP
R213
+5V_A +5V_A POWER_EN -5V_TOP -5V_TOP
100
1
GND 680uH 1u +15V_PFC +15V_PFC
1
R214
GNDA R215 2.4k
3
D213 20K
GND_PFC
GNDA + MBRA140
2
+ GND GNDA GND_PFC
12
C218
22uF/50V R216 C217 D214 GROUND CONNECTION
1.8K 220uF/35V KA3528LSGT
2
GND GND GND GND GND
GND
TP207 TP208
U203 +5V_A Vref
L205 MC78L05ACP +5V_A L200 +5V_REF
+15V 3 VIN VO 1
220uH 220uH
+
GND
+ C221 C200
100nF C220
C219 100nF 22u/20V
22u/20V
2
D D
TP300
D301 Vbat
D302 C302 BYW29E-200 29.4V @ Q4 ON
D303 T300 L300
B250R 220uF/450V P6KE200 27.4V @ Q4 OFF
1 13 +VBAT
47uH
+
C301 LINE_OK
R301
4.7nF 68k R302 R303
L
+
1M 9 24k
D304
R304
7 39k
-
1N4148 C303
6 5 R305
D305 R306 220uF/50V 1k8
TR02/MC145 100nF 220uF/50V
N BYV26C 1M R307
+ + 100u/50 +
620
sense
sense
C
ISO300 GND_CH MMBF0201NLT1 GND
CONTROL
1 SFH615A-2
4 1
F X R329 IBAT1 IBAT2
R313
TOP249Y 27R 1K
4 5 3 GNDA
3 2 R314
HV_BAT_LEVEL
100
C316
R315 +
7.5k 100n C307 R308
47uF/10V 3K6
R331
100
R316 R317
220 33K +5V_A D309
100nF 5V1
C300
C309 C308
470nF GND_CH GND
1
R319 Q300 220n
1k6 MC33502 3
B U301B + R318 B
IBAT1 6 -
R320 1 BC847 8
7 2 - 100k
IBAT2 5 U301A U302
100K
+
6
MC33502 TL431ACD
R321 4
1k6 R322
220 GND
C314 R323 R324
N/P GND_CH 1k 1k
IBAT_CONTROL
R325
33K C310 C311
470nF 470nF
GND
4.875V @ 2.34A
IBAT GND
GND
GND
J401
GND
GNDA 1 2
D
3 4 D
UNI-3_PWM2 5 6 GND
GNDA 7 8
UNI-3_PWM3
UNI-3_PWM4 9 10
+5V_A +5V_A UNI-3_PWM5 11 12
GND 13 14 +5V_D
+5V_D 15 16
+5V_D +5V_D GNDA 17 18 GNDA
+15V 19 20
UNI-3 DCBV 21 22 UNI-3 DCBI
+15V +15V UNI-3 PHAIS 23 24
UNI-3 PHCIS 25 26
27 28 GNDA
29 30 UNI-3 SERIAL
31 32 UNI-3 PFC_EN
UNI-3 PFC_ZC 33 34 UNI-3 BEMFZCA
UNI-3 BEMFZCB 35 36 UNI-3 BEMFZCC
GNDA 37 38
C 39 40 C
J402
2 1 UNI-3
Fault0
4 3 Fault1
6 5
8 7
10 9 J400
GND +5V
J403
2 1
4 3
6 5 PWM10
8 7
10 9 PWM12
12 11
14 13
16 15
18 17 TIM14 Motorola MCSL Roznov
20 19 TIM15 1. maje 1009
22 21 TIM16
A 24 23
756 61 Roznov p. R., Czech Republic, Europe A
TIM17 Title
GND 26 25 750 VA UPS Power Stage
+5V
Author: Pavel Grasblum
PWM and Timer HEADER Size Schematic Name: Control Board Interface Rev
A 01
Design File Name:
Modify Date: Wednesday, October 01, 2003 Sheet 5 of 10
Copyright Motorola 2003 POPI Status: Motorola General Business
5 4 3 2 1
1
C502 + C503 + C504 + C505 + C512 + C513 + 1k/5W
1 2
R502
2
FFPF05U120STU 1k/5W
-VBAT FFPF05U120STU 1 2
680u/50V 680u/50V 680u/50V D500 D502
GND_BAT MUR180
1 2 C506
22n/400V
D504 D505 D503 L502
+OUT
DCB_POS
650u/1A
FFPF05U120STU GND FFPF05U120STU
+15V +15V
13
15
10 18
T500
TR03/MC145
L503 1 9 L500
330u 330u
R503
4
6
100R/1W
1 2
100R/1W
1
47uF R504 47uF
C509 C508 C510
2 1 1n
1 2 1 2
+
+
GND_BAT GND_BAT
2
2
100n C507 GND_BAT 100n
C511 1n C500
1
GND_BAT GND_BAT
GND_BAT
Q501 Q500 Q502 Q503
NTP45N06 NTP45N06 NTP45N06 NTP45N06
6
6
U500 MC33152D U501 MC33152D
1 NC VCC NC 8 D D D D 8 NC VCC NC 1
TP501
PWM_4 TP502
R505 R500
2 InA OutA 7 1 2 G G G G1 2 7 OutA InA 2 PWM_5
10 10
PWM4 S S S S
R506 R507 PWM5
1
1
4 InB OutB 5 1 2 1 2 5 OutB InB 4
R508 R509
10 10
10k 10k
GND GND
2
2
GND_BAT
GND_BAT GND_BAT
GND_BAT GND_BAT
GND
GND
GNDA
GND_BAT GND
GNDA GNDA
130R
I_IN
R615
100k TP600
4
D614 D615 GNDA I_OUT
D616 D617
MBR0540 MBR0540 2
BZV55/5V1 BZV55/5V1
-
I_IN1 5 + 1 I_OUT
R616 R678 R679 7 1 2 3 +
I_IN2 6 MC33502D
180 180 180 - R600
D U604B U604A D
10
8
C612 R617 MC33502D
D618 D619 10n 100k C613
MBR0540 MBR0540
100n
1
+ C614 GNDA
GNDA GNDA 22uF
2
V_INP GNDA +5V_A
DCB_POS GNDA
+5V_REF +5V_REF
D600
1N4007 C616
R619 100n
300k TP602
R620 TP601 R621
-DCB_DIV GNDA 11k V_OUT_NEG
R618 11k
330k R623 R624
V_DCB_BOT_DIV 1 2 1 2
V_DCB_BOT V_OUT_BOT
R625 1K 0R
300k R626 D620
R627
1
R622 330k C617 330k BZV55/3V6
33n R672
470k
11K
C TP603 C
TP604 R628 R629 R630
2
R631 +DCB_DIV GNDA
V_IN 330k 300k 300k
130k R632
V_DCB_TOP_DIV 1 2 V_DCB_TOP
GNDA GNDA
V_IN 1K
R633 R634 R635
R636 11k C620 300k 300k
33K + C619 33n
10uF/10V V_OUT
R637
GNDA
R638
680k 300k
GNDA DCB_NEG +5V_D
GNDA
GNDA
R639
R640
300k
+5V_D R641 R642 10k
V_DCB_TOP_DIV 5 +
7 FAULT1
10k 10k 6 - TP605
C600 U605B
R643 V_OUT_POS
TP606 LM393D
330k
3
R644 100n
PFC_ZC R645
R646 R647 R648 U606D 10k 1 2 V_OUT_TOP
GNDA
V_INP 10 - V+ 1K
330k 330k 330k 13 PFC_ZC R649 D621
B B
D622 D623 C621 11 + V- 11k BAT42 C622
+5V_REF 33n
BAT42 BAT42 15n
LM339M
12
3
TP607 GNDA GNDA
GNDA R650 REF_POS
10K 2 GNDA
+5V_A +5V_A
+5V_A
1
R651 +5V_D +5V_D
GNDA
+5V_REF
680k
TP608 +15V +15V
R680
Q600 TEMP 33 +5V_D
LM35CA
R652 +5V_REF +5V_REF
+5V_A 3 2 1 2
+Vs +Vout TEMP
3
1K C623
TP609
GND
8
GND
33n 10K R655 10k
100n 2 3 GNDA
+ GNDA
1
10k 1 FAULT0
2 -
1
U605A GNDA
GNDA GNDA GNDA LM393D
4
A A
GNDA
R656 Motorola MCSL Roznov
V_DCB_BOT_DIV
1. maje 1009
10k
C626 756 61 Roznov p. R., Czech Republic, Europe
GNDA Title
100n 750 VA UPS Power Stage
Author: Pavel Grasblum
Size Schematic Name: Analog_Sensing Rev
A3 Design File Name: 01
GNDA Modify Date: Monday, March 08, 2004 Sheet 7 of 10
Copyright Motorola 2003 POPI Status: Motorola General Business
5 4 3 2 1
D D
U601 +15V_PFC
+15V_TOP +15V_TOP
1 8 D609
R606
C609 GATE_PFC
PWM_PFC 2 7 100nF 10 GND_TOP
MBR0540
R607 D628 GND_TOP
3 6
15V
100 -5V_TOP -5V_TOP
4 5
GND
GND_PFC +15V_BOT +15V_BOT
HCPL3150
GND_PFC
GND_BOT
GATE_TOP GND_BOT
C633
100nF
GND_BOT
-5V_BOT
RE1
MZPA001
5 o
MBRS130 o 4 OUT1
+15V FAN+
3 o
D601 + C601
FAN-
L504 10u/15V +15V 1 2
D 330u RE2 D
D D1 MZPA001
D602
5 o
R601
FAN_PWM G
o 4
68 Q601 BAT42
S NTF3055
L2 3 o R602
Q602
RLY_OUT1
BC846
4K7
GND +15V 1 2
GND
D603 RE3
I_IN1 I_IN2 MZPA001
BAT42
5 o
R603 o 4 OUT2
7
RLY_BYPASS Q603
CT1 4K7 BC846
3 o
1:100
DCB_POS DCB_POS
V_INP L505 GND +15V 1 2
D604
L1
2
2.5mH
RHRP8120 D605
D606
KBPC606
C BAT42 C
+15V - +
R604 Q604
RLY_OUT2
4K7 BC846
RE4
1
MZPA002 GND
o
Q605
D607 GATE_TOP
BAT42 C602
C603 + HGTG10N120BND
o
V_OUT
2
GND
RLY_IN N N_OUT
1
2
3
4
CT2
GND GND
B B
CS2106
5
I_OUT2 I_OUT1
Q608
C607 GATE_BOT
+ C608
MKP10/22nF/630VDC 330uF/450V HGTG10N120BND
GND_BOT
D608
+15V +15V
RHRP8120
DCB_NEG DCB_NEG
GND
GND
A A
+5V_A
+5V_A
R657
33 +5V_D +5V_D
C627
3
GNDA 10k 10k R661 100n
U606A 10k 470
R663 4 - R662
100 V+ 2 470
DA1 5 + V-
3
LM339M D GND
U606B
12
C629 R664 6 - V+ G
10n 1.6k 1
7 + V-
GNDA Q609 S
R665 GNDA LM339M MMBF0201NLT1
N/P R666
12
DA0
N/P
3
C630 R667 U606C R669 R670 TP611
R668 N/P 8 - 10k 10k GND PWM_PFC
C 100 V+ 14 PFC_CTRL C
0 9
I_IN + V-
C631
LM339M +5V_D
10n
12
GNDA GNDA R671
GNDA 4.7k
D
MMBF0201NLT1 MMBF0201NLT1
60% 75% 85%
3.3K 10k 9.1k
UNI-3 PFC_EN G
Q610 S
MMBF0201NLT1
R673 R674 R675
N/P N/P N/P GND
B B
All On 55% D D
DIV1 G DIV2 G
Q611 S Q612 S
N/P N/P
+5V_D
R1
LED_FAULT
SW1
R2 1300
10k D1
L53LID
D BT_BYPASS D
J1
GND
2 1 BEEP
LED_LEV5 4 3 LED_LEV6 R3
LED_LEV3 6 5 LED_LEV4 Switch/P-0SYB LED_ON
LED_LEV1 8 7 LED_LEV2 +5V_D J2
J3 1300
10 9 5
BT_BYPASS 12 11 BT_ON/OFF 9 D2
LED_BAT 14 13 LED_BYPASS 1 2 4 L53LGD
LED_FAULT 16 15 LED_ON 3 4 8
R4
18 17 5 6 3
SW2 10k
20 19 7 8 7
22 21 +5V_D 9 10 2
24 23 6 GND
GND 26 25 BT_ON/OFF 1 R5
LED_BAT
HEADER 5X2 CON/CANNON9
HEADER 13x2 270
C D3 C
L53ND
GND Switch/P-0SEB
2
1
GND
R6 R7
LED_LEV1 J4 LED_BYPASS
PSH02_02W
1300 1300
R8
LED_LEV2 D4
1300 L53LYD
J6 J5
R9
LED_LEV3 5
1300 9
R10 1 2 4
LED_LEV4 3 4 8 GND
5 6 3 BEEP
1300
R11 7 8 7
B LED_LEV5 9 10 2 BZ1 B
1300 6
R12 1
LED_LEV6 HEADER 5X2
CON/CANNON9 SA003
1300
D5 D6 D7 D8 D9 D10
L53LID L53LGD L53LGD L53LGD L53LGD L53LID GND
+5V_D +5V_D
GND
GND
D D
C103
4.7nF/Y1
J102 MH1 PE
PE
GROUND CONNECTION
B MH2 B
GROUND CONNECTION
1. Feno, I.: Analysis and Synthesis of the IGBT switching techniques and verification in Partial Series
Resonant Converter. Ph.D. Dissertation, University of Zilina, Faculty of Electrical Engineering,
August 2003.
2. A More Realistic Characterization Of Power MOSFET Output Capacitance Coss. Application Note
AN-1001, International Rectifier.
3. Billings, K.: Switchmode Power Supply Handbook, second edition. McGraw-Hill, 1999.
4. Pressman, A. I.: Switching Power Supply Design, second edition, McGraw-Hill, 1998.
5. International Standard IEC62040-1-1, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in operator access areas.
6. International Standard IEC62040-1-2, Uninterruptable power systems (UPS) - Part 1-2: General
and safety requirements for UPS used in restricted access locations.
7. International Standard IEC62040-2, Uninterruptable power systems (UPS) - Part 2:
Electromagnetic compatibility (EMC) requirements.
8. International Standard IEC62040-3, Uninterruptable power systems (UPS) - Part 3: Method of
specifying the performance and test requirements.
9. YUASA NP valve regulated lead acid battery manual. Yuasa Battery GMBH, 1999.
10. TOP242-250 Up to 290 W Extended power, design flexible, EcoSmart, integrated off-line switcher
family, data sheet. Power Integrations, August 2003
11. AN-18, TOPSwitch Flyback Transformer Construction Guide. Power Integrations, 1996.
12. AN-16, TOPSwitch Flyback Design Methodology. Power Integrations, 1996.
13. MC9S12E-Family Device User Guide, data sheet. Motorola, 2003.
14. HCS12 CPU V2.0 Reference Manual, Reference Manual. Motorola, 2003.
15. HCS12 10-Bit, 16-Channel Analog to Digital Converter (ATD) Block Guide. Reference Manual.
Motorola, 2003.
16. HCS12 Background Debug Module Block Guide. Reference Manual. Motorola, 2003.
17. HCS12 Clocks and Reset Generator (CRG) Block Guide. Reference Manual. Motorola, 2003.
18. Digital-to-Analog Converter: 8-Bit, 1-Channel. Reference Manual. Motorola, 2003.
19. Debug Module. Reference Manual. Motorola, 2003.
20. Port Integration Module: 9S12E128. Reference Manual. Motorola, 2003.
21. HCS12 128K FLASH Block Guide. Reference Manual. Motorola, 2003.
22. HCS12 Inter-Integrated Circuit (IIC) Block Guide. Reference Manual. Motorola, 2003.
23. Interrupt (INT) Module V1 Block User Guide. Reference Manual. Motorola, 2003.
24. Multiplexed External Bus Interface (MEBI) Module V3 Block User Guide. Reference Manual.
Motorola, 2003.
25. Module Mapping Control (MMC) V4 Block User Guide. Reference Manual. Motorola, 2003.
26. HCS12 Oscillator Block Guide. Reference Manual. Motorola, 2003.
27. Pulse Modulator with Fault Protection: 15-Bit, 6-Channel. Reference Manual. Motorola, 2003.
28. HCS12 8-Bit, 6-Channel Pulse Width Modulator (PWM) Block Guide. Reference Manual. Motorola,
2003.
29. HCS12 Serial Communications Interface (SCI) Block Guide. Reference Manual. Motorola, 2003.
30. HCS12 Serial Peripheral Interface (SPI) Block Guide. Reference Manual. Motorola, 2003.
31. Timer: 16-Bit, 4-Channel. Reference Manual. Motorola, 2003.
32. Voltage Regulator 3V3 Block User Guide V2. Reference Manual. Motorola, 2003.
33. MC9S12E128 Controller Board, Design Reference Manual, Motorola 2004
Single Phase On-Line UPS Using MC9S12E128
Appendix C. Glossary
ac alternating current
ac/dc converter a converter that converts alternating voltage (ac) to direct voltage (dc)
ATD analog-to-digital converter
A/D analog-to-digital
AVR automatic voltage regulation
CW CodeWarrior; compilers produced by Metrowerks
DAC digital-to-analog converter
dc direct current
dc/ac converter a converter that converts direct voltage (dc) to alternating voltage (ac)
dc/dc converter converter that converts one level of direct voltage to another level of direct voltage
DT dead time; a short time that must be inserted between turning off one transistor in the
inverter half-bridge and turning on the complementary transistor, to allow for the
limited switching speed of the transistors.
duty cycle the ratio of the time the signal is on to the time it is off. Duty cycle is usually quoted
as a percentage.
EMC electro magnetic compatibility
EMI electro magnetic interference
IC integrated circuit
IDE integrated development environment
IGBT Insulated gate bipolar transistor
input/output (I/O) input/output interfaces between a computer system and the external world. A CPU
reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
interrupt a temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
logic 1 a voltage level approximately equal to the input power voltage (VDD)
logic 0 a voltage level approximately equal to the ground voltage (VSS)
HCS12 a Freescale Semiconductor family of 16-bit MCUs
MCU microcontroller unit; a complete computer system, including a CPU, memory, a clock
oscillator, and input/output (I/O) on a single integrated circuit
MW Metrowerks Corporation
PC personal computer
PCB printed circuit board
PCM PC master software for communication between PC and system
PFC power factor correction
PI Controller proportional-integral controller
PID Controller proportional-integral-derivative controller
PLL phase-locked loop; a clock generator circuit in which a voltage controlled oscillator
produces an oscillation that is synchronized to a reference signal
PMP FreeMaster software project file
PVAL PWM value register of motor control PWM module of the MC9S12E128
microcontroller; it defines the duty cycle of the generated PWM signal.
PWM pulse width modulation
RESET to force a device to a known condition
RMS root mean square
SCI serial communications interface module; a module that supports asynchronous
communication
SMPS switched mode power supply
software instructions and data that control the operation of a microcontroller
SPI serial peripheral interface module; a module that supports synchronous
communication
SWI software interrupt; an instruction that causes an interrupt and its associated vector
fetch
THD total harmonic distortion
timer A module used to relate events in a system to a point in time
UPS uninterruptable power supply
DRM064
Rev. 0, 09/2004