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COMPAL CONFIDENTIAL

MODEL NAME : 888L2(SOLANO2-M)


Date: 01/11/01
Version: 2.0

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cover Sheet
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 1 of 42
MODEL NAME : 888L2 (SOLANO2-M)
UPGA2 Decoupling
Socket CapacitorS
PAGE 4,5,6 PAGE 6

FSB BUS
PAGE 13

PAGE 12
CRT CONN. GMCH2-M
IDSEL: AD11
LVDS DVO/Vlink HOST-HUB BRIDGE
LCD/INV. CONN. VCH PAGE 12 IDSEL: AD13 MEMORY BUS SODIMM 0 CLOCK
INTERNAL GFX SODIMM 1 CIRCUIT
DISPLAY CACHE CONN. & ITP PAGE 13 PAGE 7,8,9 PAGE 10

PCI BUS HUB_ILNK


PAGE 11

CARD-BUS MINI_PCI CONN ICH2-M HDD CONN.


CONTROLLER
OZ 6933T MODEM/LAN
AC_LINK1/LAN BUS#0, DEV#30, DEV#31: PAGE 17
DC/DC
IDSEL: AD19 IDSEL: AD27, AD28 HUB, LPC, IDE, USB, SMBUS, CIRCUIT
AC'97 SECOND MODULE
PIRQA#, PIRQC# PAGE 19 PIRQB#, PIRQD# PAGE 29
BUS#1, DEV#8:
CONN. PAGE 17
INTERNAL LAN CONTROLLER
PAGE 14,15,16
CD-ROM
PCCARD CARDBUS CONN. PAGE 17
POWER RJ11 RJ45
SLOT 1/2 PAGE 30-34

PAGE 20 PAGE 20 Sub board USB CONN.


PAGE 18
FWH
PAGE 14 AC_LINK0 AMP & AC97
CODECPAGE 27
LPC BUS

KB BIOS NS PC87393
PAGE 22
NS PC87570EXT X Bus Head
RTC BATT & LPC-TO-X Bus Line in Mic
Phone
ON/OFF BTN KBD & S/IO
PAGE 25 PAGE 28 PAGE 28 PAGE 28

INT KBD PAGE 22 PAGE 21


PAGE 23

PS/2 T-PAD SUSPEND


KEYBOARD& CONN. CKT SIO PIO FDD.
MOUSECONN.
PAGE 25 PAGE 23 PAGE 26 PAGE 24 PAGE 24 PAGE 17
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D System Block Diagram
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 2 of 42
Revision History
# Date Description Version
1 2000/7/21 First Release (EVT-SST) 0.1

2 2000/9/20 Second Release (DVT1-PT1) 0.2A

3 2000/11/3 Third Release (DVT2-PT2) 0.2C1

4 2000/12/27 Fouth Release (ST) 1B

5 2001/01/11 fifth release (QT) 2.0

Chip information EVT (SST)


GMCH2-M QA38ES (A0)
GMCH2-M FW82815EM
ICH2-M Q967ES (B0)
Version S-spec. Q-spec. VCH Q989ES (A0)
A0 QA38 DVT1 (PT1) DVT2 (PT2)
GMCH2-M QA75ES (A1)
A1 SL4MP QA75
ICH2-M QA57ES (B2)
VCH Q076ES (A1)
ICH2-M FW82801BAM
ST
Version S-spec. Q-spec. GMCH2-M A1
ICH2-M B2
A0 Q908, Q909, Q910, Q911, Q912
VCH A2
B0 SL45HQ Q967, Q968 QT same as ST

B1 SL4HN QA36, QA37


B2 QA56, QA57

VCH FW82807AA
Version S-spec. Q-spec.
A0 Q989
A1 QA76
A2 QB41ES

Compal Electronics, Inc.


Title
Revision History
Size Document Number Rev
2.0
888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 3 of 42
A B C D E

HA#[3..31] HD[0..63]
<7> HA#[3..31] HD#[0..63] <7>
CPU_VID[0..4]
U5A CPU_VID[0..4] <5>

HA#3 L3 D10 HD#0 RP40 +3VS +3VS RP41


HA#4 K3 A3# D0# D11 HD#1 8P4R-10K 8P4R-1K
HA#5 J2 A4# COPPERMINE D1# C7 HD#2 1 8 1 8 CPU_VID0
HA#6 L4 A5# D2# C8 HD#3 2 7 2 7 CPU_VID1
HA#7 L1 A6# D3# B9 HD#4 3 6 3 6 CPU_VID2
HA#8 K5 A7# D4# A9 HD#5 4 5 4 5 CPU_VID3
HA#9 K1 A8# D5# C10 HD#6
HA#10 J1 A9# D6# B11 HD#7 1 2 CPU_VID4
HA#11 J3 A10# D7# C12 HD#8 1 2 R20 1K
+CPU_IO A11# D8# +3VS
HA#12 K4 B13 HD#9 R30 @10K
4 4
HA#13 G1 A12# D9# A14 HD#10 VCH_VID[0..4]
A13# D10# VCH_VID[0..4] <12>
R243 1 2 56.2_1% CPURST# HA#14 H1 B12 HD#11 VID[0..4]
A14# D11# VID[0..4] <30>
HA#15 E4 E12 HD#12
R42 1 2 1.5K FLUSH# HA#16 F1 A15# D12# B16 HD#13 U4
HA#17 F4 A16# D13# A13 HD#14 CPU_VID0 3 2 VID0
R107 1 2 150 PICD0_CPU HA#18 F2 A17# D14# D13 HD#15 CPU_VID1 7 A0 C0 6 VID1
HA#19 E1 A18# D15# D15 HD#16 CPU_VID2 11 A1 C1 10 VID2
R106 1 2 150 PICD1_CPU HA#20 C4 A19# D16# D12 HD#17 CPU_VID3 17 A2 C2 16 VID3
HA#21 D3 A20# D17# B14 HD#18 RP42 CPU_VID4 21 A3 C3 20 VID4
R44 1.5K FERR# HA#22 A21# D18# HD#19 8P4R-0 A4 C4
2 1 D1 E14
HA#23 E2 A22# D19# C13 HD#20 VCH_VID0 1 8 R_VID0 4 5
R293 2 1 1.5K RCPUSLP# HA#24 D5 A23# D20# A19 HD#21 VCH_VID1 2 7 R_VID1 8 B0 D0 9
HA#25 D4 A24# D21# B17 HD#22 VCH_VID2 3 6 R_VID2 14 B1 D1 15
HA#26 C3 A25# D22# A18 HD#23 VCH_VID3 4 5 R_VID3 18 B2 D2 19
HA#27 C1 A26# REQUEST DATA D23# C17 HD#24 VCH_VID4 1 2 R_VID4 22 B3 D3 23
HA#28 B3 A27# D24# D17 HD#25 R429 B4 D4
PHASE PHASE
HA#29 A3 A28# D25# C18 HD#26 @0_0402 1 24
A29# SIGNALS SIGNALS D26# BE# VCC +5VS
HA#30 B2 B19 HD#27

1
HA#31 C2 A30# D27# D18 HD#28 13 12 C22
A31# D28# HD#29 BX GND
A4 B20
A5 A32# D29# A20 HD#30 SN74CBT3383 .1UF

2
A33# D30#

2
B4 B21 HD#31
C5 A34# D31# D19 HD#32 R19 R24
A35# D32# C21 HD#33 1K_0402 1K_0402
T2 D33# E18 HD#34
<7> HREQ#0 REQ0# D34#
V4 C20 HD#35 VR_HI/LO#
<7> HREQ#1 REQ1# D35# VR_HI/LO# <15,30>

1
V2 F19 HD#36
+CPU_IO <7> HREQ#2 REQ2# D36#
W3 D20 HD#37
<7> HREQ#3 REQ3# D37#
W5 D21 HD#38 R18 R27
<7> HREQ#4 REQ4# D38#
VID[4:0] CPU VCC VID[4:0] CPU VCC
3 3
W2 H18 HD#39 @1K_0402 R22 1K_0402
2

RP# D39# F18 HD#40 1K_0402


R26 AB2 D40# J18 HD#41
<7> ADS# ADS# D41#
10K_0402
D42#
F21
E20
HD#42
HD#43
00000 2.00 10000 1.275
D43#
BSEL0 AA1
AERR# D44#
H19 HD#44
00001 1.95 10001 1.250
1

AB1 ERROR E21 HD#45


AP0# D45#
Y2
E6 AP1#
SIGNALS
D46#
J20
H21
HD#46
HD#47
00010 1.90 10010 1.225
BERR# D47#
V21
BINIT# D48#
L18 HD#48
HD#49
00011 1.85 10011 1.200
AD9 G20
IERR# D49#
+CPU_IO 10_0402 2 1 R217 C6 D50#
P18
G21
HD#50
HD#51
00100 1.80 10100 1.175
BREQ0# D51#
<7> BPRI#
U4
T4 BPRI# ARBITRATION D52#
K18
K21
HD#52
HD#53
00101 1.75 10101 1.150
<7> BNR#
2

BNR# D53#
R105
<7> HLOCK#
R1
LOCK#
PHASE
D54#
M18
L21
HD#54
HD#55
* 900MHZ 00110 1.70 10110 1.125
SIGNALS D55#
@10K_0402
V1 D56#
R19
K19
HD#56
HD#57
00111 1.65 10111 1.100
<7> HIT# HIT# D57#
<7> HITM#
Y4
HITM#
SNOOP PHASE
D58#
T20 HD#58
* 850MHZ 01000 1.60 11000 1.075
1

BSEL1 U3 SIGNALS J21 HD#59


<7> DEFER# DEFER# D59#
AA21 D60#
L20
M19
HD#60
HD#61
01001 1.55 11001 1.050
1

BP2# D61#
R104
Y21
W21 BP3#
RESPONSE
D62#
U18
R18
HD#62
HD#63
01010 1.50 11010 1.025
PHASE
BPM0# D63#
100_0402 W19
U2 BPM1# SIGNALS 01011 1.45 11011 1.000
<7> HTRDY# TRDY#
<7> RS#0
U1
RS0# DEP0#
V20
01100 1.40 11100 0.975
2

AA2 T21
<7> RS#1 RS1# DEP1#
2
<7> RS#2
W1
RS2# DEP2#
U21
* 01101 1.35 11101 0.950 2
Y1 R21
RSP# DEP3#
AD10 DEP4#
V18
P21
01110 1.30 11110 0.925
<14> A20M# A20M# DEP5#
<14> FERR#
FERR# AC12
AC13 FERR#
PC
DEP6#
P20
U19
01111 NO CPU 11111 NO CPU
<14> IGNNE# C O MPATIBILITY
V5 IGNNE# DEP7#
<14> CPU_PWRGD PWRGOOD SIGNALS
AB10 AA3
<14> SMI# SMI# DBSY# DBSY# <7> +3VS
2 1 T1
+2_5V_CLK DRDY# DRDY# <7>
R210 1.5K ITP_TDO AC15
RP32 1 8 8P4R-1.5K ITP_TDI AD13 TDO DIAGNOSTIC
ITP_TMS TDI
2 7 AD14 & TEST 2 1 1 2
+CPU_IO 3 6 ITP_TRST# AA14 TMS R102 @33_0402 C97 @15PF 1 2
SIGNALS

2
4 5 ITP_TCK AA11 TRST# R245 10K_0402
R100 2 1 1.5K ITP_PREQ# AB20 TCK AA18 C310

15
C L K_APIC_CPU <11>

2
R101 2 1 56.2_1% GTL_PRDY# W20 PREQ# PICCLK Y20 PICD1_CPU R103 2 1 0_0402 PICD1 MAX1617A U20
PRDY# PICD1 PICD1 <14> .1UF

1
BSEL0 AA12 AB21 PICD0_CPU R99 2 1 0_0402 PICD0 16

STBY#

VCC
BSEL1 AB15 BSEL0 PICD0 PICD0 <14> 13 NC
BSEL1 AA10 9 NC 14
INIT# INIT# <14> SMB_EC_CK1 <12,22,23,31>
AB18 AC9 FLUSH# 5 NC SMBC 12
<14> INTR INTR/LINT0 FLUSH# SMB_EC_DA1 <12,22,23,31>
AC19 EXECUTION A6 CPURST# 1 NC SMBD 11
<14> NMI NMI/LINT1 RESET# CPURST# <7,13> NC ALERT#

1
AC11 CONTROL C312 THERMDA 3
<14> STPCLK# STPCLK# DXP

ADD0
ADD1
RCPUSLP# AB12 SIGNALS M3

GND
GND
SLP# BCLK CLK_HOST_CPU <11> 2200PF THERMDC 4
Address: 1001_110x
2

DXN

2
THERMDA AA15 AA16
THERMDC AB16 THERMDA THERMAL DIODE EDGCTRLN R214 R246 1K_0402

10
2

THERMDC

8
7
@33_0402 1 2
+3VS
R261 1 2
COPPERMINE 110_1% R258 1K_0402
11

1 1
C209
1

BSEL[1:0] S T S E M BUS FREQUENCY ITP_TDO @15PF


<13> ITP_TDO
2

ITP_TDI
<13> ITP_TDI
00 66MHZ ITP_TMS
<13> ITP_TMS
ITP_TRST#
* 01 100MHZ
<13> ITP_TRST#
ITP_TCK Compal Electronics, Inc.
<13> ITP_TCK
ITP_PREQ# Title
<13> ITP_PREQ# T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
10 RESERVED GTL_PRDY#
<13> GTL_PRDY#
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D COPPERMINE-A
11 133MHZ D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 4 of 42
A B C D E
A B C D E

1 2 +VCCT_VCCA
+CPU_IO
L47
Murata LQG21N4R7K10

1
C32 C35 U5B

1
C202
22UF_10V_1206 A2
10UF_10V_1206 VSS0
.1UF L2 A7

2
VCCA VSS1 U5C

2
+VCCT_VSSA M2 P L L ANALOG VOLTAGE A8
VSSA VSS2 A12 G6 R12
VSS3 +CPU_IO VCCT0 VSS102
+GTLREF E5 A21 G7 R14
+GTLREF E16 VREF0 VSS4 B1 G8 VCCT1 VSS103 R16

1
C336 E17 VREF1 VSS5 B5 G9 VCCT2 VSS104 R20
C339 C250 C263
F5 VREF2 VSS6 B6 G10 VCCT3 VSS105 T3
.1UF .1UF .1UF .1UF F17 VREF3 VSS7 B7 G11 VCCT4 VSS106 T5
VREF4 VSS8 VCCT5 VSS107
2

2
4 U5 B8 G12 T7 4
Y17 VREF5 VSS9 B10 G13 VCCT6 VSS108 T9
Y18 VREF6 COPPERMINE VSS10 B15 G14 VCCT7 VSS109 T11
VREF7 VSS11 B18 G15 VCCT8 VSS110 T13
H8 VSS12 C9 G16 VCCT9 VSS111 T15
+CPU_CORE VCC0 VSS13 VCCT10 VSS112
H10 C11 G17 T18
H12 VCC1 VSS14 C15 H6 VCCT11 VSS113 T19
H14 VCC2 VSS15 C16 H17 VCCT12 COPPERMINE VSS114 U8
H16 VCC3 VSS16 C19 J6 VCCT13 VSS115 U10
J7 VCC4 VSS17 D2 J17 VCCT14 VSS116 U12
VCC5 VSS18 VCCT15 VSS117
J9 D6 K6 U14
J11 VCC6 VSS19 D7 K17 VCCT16 VSS118 U16
J13 VCC7 VSS20 D9 L6 VCCT17 VSS119 U20
J15 VCC8 VSS21 E3 L17 VCCT18 VSS120 V3
K8 VCC9 VSS22 E7 M6 VCCT19 VSS121 V19
K10 VCC10 POWER, VSS23 E8 M17 VCCT20 VSS122 W4
K12 VCC11 VSS24 E9 N6 VCCT21 VSS123 W18
GROUND,
K14 VCC12 VSS25 E10 N17 VCCT22 P O W E R , GROUND AND NC VSS124 Y3
VCC13 RESERVED VSS26 VCCT23 VSS125
K16 E11 P1 Y9
VCC14 SIGNALS VSS27 +CPU_CORE VCCT24 VSS126
L7 E13 P6 Y10
VCC15 VSS28 VCCT25 VSS127
L9 E19 P17 Y11
L11 VCC16 VSS29 F3 R6 VCCT26 VSS128 Y12
L13 VCC17 VSS30 F6 R17 VCCT27 VSS129 Y13
L15 VCC18 VSS31 F7 T6 VCCT28 VSS130 Y14
M8 VCC19 VSS32 F8 T17 VCCT29 VSS131 Y15
M10 VCC20 VSS33 F9 U6 VCCT30 VSS132 Y16
M12 VCC21 VSS34 F10 U17 VCCT31 VSS133 Y19
M14 VCC22 VSS35 F11 V6 VCCT32 VSS134 AA4
M16 VCC23 VSS36 F12 V7 VCCT33 VSS135 AA13
N7 VCC24 VSS37 F13 V8 VCCT34 VSS136 AA20
3 VCC25 VSS38 VCCT35 VSS137 3
N9 F14 V9 AB3
N11 VCC26 VSS39 F15 V10 VCCT36 VSS138
N13 VCC27 VSS40 F16 V11 VCCT37 AB5
N15 VCC28 VSS41 F20 V12 VCCT38 VSS140 AB9
P8 VCC29 VSS42 G3 V13 VCCT39 VSS141 AB11
P10 VCC30 VSS43 G19 V14 VCCT40 VSS142 AB13
P12 VCC31 VSS44 H2 V15 VCCT41 VSS143 AB14
P14 VCC32 VSS45 H7 V16 VCCT42 VSS144 AB17
P16 VCC33 VSS46 H9 V17 VCCT43 VSS145 AC1
R7 VCC34 VSS47 H11 W6 VCCT44 VSS146 AC2
VCC35 VSS48 VCCT45 VSS147
R9 H13 W7
R11 VCC36 VSS49 H15 W8 VCCT46 AC5
R13 VCC37 VSS50 H20 W9 VCCT47 VSS149 AC10
+2_5V_CLK +2_5V_CLK R15 VCC38 VSS51 J4 W10 VCCT48 VSS150 AC14
T8 VCC39 VSS52 J8 W11 VCCT49 VSS151 AC16
T10 VCC40 VSS53 J10 W12 VCCT50 VSS152 AC18
T12 VCC41 VSS54 J12 W13 VCCT51 VSS153 AC21
C194 C34 T14 VCC42 VSS55 J14 W14 VCCT52 VSS154 AD1
2

.1UF .1UF T16 VCC43 VSS56 J16 W15 VCCT53 VSS155


R209 R25 U7 VCC44 VSS57 J19 W16 VCCT54
1.5K_1% VCC45 VSS58 VCCT55
2K_1% U9 K2 W17
U11 VCC46 VSS59 K7 Y6 VCCT56 AD5
U13 VCC47 VSS60 K9 Y7 VCCT57 VSS159 AD16
VCC48 VSS61 VCCT58 VSS160
1

U15 K11 Y8 AD21


VCC49 VSS62 K13 AA6 VCCT59 VSS161
2

VSS63 K15 AA7 VCCT60 A15


1

R215 R28 VSS64 K20 AA8 VCCT61 NC1 A16


C208 C217 C205
AB19 VSS65 L5 AB6 VCCT62 NC2 A17
2K_1% RSVD VSS66 VCCT63 NC3
1K_1% .1UF .1UF .1UF L8 AB7 C14
VSS67 VCCT64 NC4
2

2 +CLKREF P2 L10 AB8 D8 2


CLKREF VSS68 VCCT65 NC5
1

L12 AC6 D14


VSS69 L14 AC7 VCCT66 NC6 D16
VSS70 L16 AC8 VCCT67 NC7 E15
VSS71 L19 AD6 VCCT68 NC8 G2
+CMOSREF AA9 VSS72 M7 AD7 VCCT69 NC9 G5
AD18 CMOSREF1 VSS73 M9 AD8 VCCT70 NC10 G18
CMOSREF2 VSS74 M11 VCCT71 NC11 H3
VSS75 M13 NC12 H5
VSS76 M15 AD2 NC13 J5
VSS77 <4> CPU_VID0 VID0 NC14
R2 M20 AD3 M4
<15> I S T_CPU_PERF# GHI# VSS78 <4> CPU_VID1 VID1 NC15
AD19 N2 <4> CPU_VID2 AD4 M5
RTTIMPEDP VSS79 N3 AC4 VID2 NC16 P3
VSS80 <4> CPU_VID3 VID3 NC17
N4 AB4 P4
VSS81 <4> CPU_VID4 VID4 NC18
N8 AA5
VSS82 N10 NC19 AA19
R2622 1 +TESTHI AD17 VSS83 N12 NC20 AC3
+CPU_IO TESTHI VSS84 NC21
N14 AC17
1.5K VSS85 N16 NC22 AC20
Y5 VSS86 N18 NC23 AD15
N5 TESTLO1 VSS87 N19 NC24
TESTLO2 VSS88
N20
VSS89 P5 COPPERMINE
TESTLO1

TESTLO2

AD20 VSS90 P7
H4 TESTP1 VSS91 P9
AA17 TESTP2 VSS92 P11
TESTP3 VSS93
G4
TESTP4 VSS94
P13
P15
uPGA2 and uBGA2 PIN P1:
f o r low voltage Cumine CPU: connect to +CPU_CORE, only uBGA2 package.
2

VSS95 P19
R96 R29 R23 VSS96 R3
for normal Cumine CPU: connect to +CPU_IO.
1 1
VSS97 R4
56.2_1% VSS98
1K_0402 1K_0402 R5
VSS99 R8
VSS100
1

R10
VSS101

COPPERMINE Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D COPPERMINE-B
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 5 of 42
A B C D E
A B C D E

4 4

+CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE


1

1
C334 C332 C353 C381 C422 C100 C31 C99 C101
+ C110 + C113 + C105 + C271 + C33 + C321 + C386 + C184
10PF 10PF 10PF 10PF .1UF .1UF .1UF .1UF .1UF 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2

2
+CPU_CORE +CPU_CORE +CPU_CORE +CPU_CORE
1

1
C392 C345 C391 C237 C36 C423 C244 C102 C103
+ C185 + C427 + C183 + C296 + C420 + C409 + C406 + C173
3 3
1UF 1UF 1UF 1UF .1UF .1UF .1UF .1UF .1UF 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V 220UF_D_4V
2

2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V

2
+CPU_CORE
+CPU_IO
1

1
C267 C268 C278 C277 C276 C279 C292 C291 C290 C289

1
C251 C286 C300 C273 C309 C285 C311 C342 C343 C344
.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2

2
.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402

2
+CPU_CORE
+CPU_IO
1

C275 C305 C303 C293 C265 C266 C269 C301 C302 C304

1
C299 C337 C256 C272 C192 C249 C55 C182
.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 + C188
2

.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 1UF 1UF 220UF_D_4V

2
2 2

2
+CPU_CORE
1

C316 C320 C319 C328 C330 C315 C318 C98 C421 C329

.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF .1UF .1UF_0402
2

+CPU_CORE
1

C504 C505

1UF 1UF
2

1 1

Compal Electronics, Inc.


Title
CPU BYPASS
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
A N D TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 888L2 Main Board
M A Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: T h ursday, January 11, 2001 Sheet 6 of 42
A B C D E
5 4 3 2 1

DVO_D[0..11]
DVO_D[0..11] <12>

U7C
HD#[0..63] HA#[3..31] DVO_CLKOUT
<4> HD#[0..63] HA#[3..31] <4>
VGA_LDQM0 K26 AD16 DVO_D0

2
VGA_LMD4 J22 G_AD0/LDQM0 LTVD0 AF17 DVO_D1
U7A G_AD1/LMD4 LTVD1
VGA_LMD7 K25 AE17 DVO_D2 R47
@33_0402 VGA_LMD3 J21 G_AD2/LMD7 LTVD2 AD17 DVO_D3 @33_0402
HD#0 AA1 U6 1 2 VGA_LMD6 L24 G_AD3/LMD3 LTVD3 AF18 DVO_D4
HD#1 AB2 HD#0 GTLREFA AA10 R296 C408 @18PF VGA_LMD2 J20 G_AD4/LMD6 LTVD4 AD18 DVO_D5
HD#1 GTLREFB +GTLREF G_AD5/LMD2 LTVD5

1 1
HD#2 AF2 VGA_LMD5 L26 AF20 DVO_D6
HD#3 HD#2 VGA_LMD1 G_AD6/LMD5 LTVD6 DVO_D7 C62
D AD4 AA7 CLK_HOST_GMCH <11> K23 AD20 D
HD#4 AB1 HD#3 HCLKIN VGA_LMD0 K22 G_AD7/LMD1 LTVD7 AC20 DVO_D8
HD#5 AB3 HD#4 H3 VGA_LMA4 M25 G_AD8/LMD0 LTVD8 AF21 DVO_D9 @10PF
HD#5 RSTIN# PCIRST# <12,14,19,21,29> G_AD9/LMA4 LTVD9

2
HD#6 AA3 VGA_LDQM1 M24 AE21 DVO_D10
HD#7 AC4 HD#6 VGA_LMA2 M26 G_AD10/LDQM1 LTVD10 AD21 DVO_D11
HD#8 AC1 HD#7 VGA_LMD8 M21 G_AD11/LMA2 LTVD11 AB19 DVO_BL#
HD#8 G_AD12/LMD8 BLANK# DVO_BL# <12>
HD#9 AF3 AA5 VGA_LMA5 N24 AC18 DVO_CLKOUT
HD#9 CPURST# CPURST# <4,13> G_AD13/LMA5 TVCLKIN/STALL DVO_CLKOUT <12>

DVO
HD#10 AD1 L4 VGA_LMD9 N22 AE19
HD#10 HLOCK# HLOCK# <4> G_AD14/LMD9 CLKOUT0 DVO_CLK# <12>
HD#11 AE3 M3 VGA_LMA1 N26 AF19
HD#11 DEFER# DEFER# <4> G_AD15/MA1 CLKOUT1 DVO_CLK <12>
HD#12 AD2 G1 VGA_LMA8 T26 AC16 DVO_VSYNC
HD#12 ADS# ADS# <4> G_AD16/LMA8 LTVVSYNC DVO_VSYNC <12>
HD#13 AD3 N4 VGA_LMD14 T22 AB17 DVO_HSYNC
HD#13 BNR# BNR# <4> G_AD17/LMD14 LTVHSYNC DVO_HSYNC <12>
HD#14 AF1 M5 VGA_LMA11 U24 AA20 LTVDA
HD#14 BPRI# BPRI# <4> G_AD18/LMA11/LBA LTVDA LTVDA <12>
HD#15 AA4 J3 VGA_LMD15 T23 AB21 LTVCL
HD#15 DBSY# DBSY# <4> G_AD19/LMD15 LTVCK LTVCL <12>
HD#16 AD6 J1 VGA_LMA9 U26
HD#16 DRDY# DRDY# <4> G_AD20/LMA9
HD#17 AC3 K1 VGA_LMD16 T24 AB18
HD#17 HIT# HIT# <4> G_AD21/LMD16 DDCK 3VDDCCL <13>
HD#18 AE1 L3 VGA_LMA0 V24 AA18 MODIFY ON 6/11
HD#18 HITM# HITM# <4> G_AD22/LMA0 DDDA 3VDDCDA <13>
HD#19 AB6 K3 VGA_LMD17 U21 AE24 CLK_DOT_GMCH
HD#19 HTRDY# HTRDY# <4> G_AD23/LMD17 DCLKREF CLK_DOT_GMCH <11>
HD#20 AF4 VGA_LCKE V25 Y20
HD#20 <13> VGA_LCKE G_AD24/LCKE IWASTE
HD#21 AE5 R4 HA#3 VGA_LMD18 V21 AD23 R92 1 2 174_1%
HD#22 AC8 HD#21 HA#3 P1 HA#4 VGA_LCAS# V26 G_AD25/LMD18 IREF
HD#22 HA#4 <13> VGA_LCAS# G_AD26/LCAS#
HD#23 AB5 T2 HA#5 VGA_LMD19 W21 AF22 CRT_VSYNC
HD#23 HA#5 G_AD27/LMD19 VSYNC CRT_VSYNC <13>
HD#24 AF5 R3 HA#6 VGA_LTCLK1 W24 AF23 CRT_HSYNC
HD#24 HA#6 +3VS <13> VGA_LTCLK1 G_AD28/LTCLK1 HSYNC CRT_HSYNC <13>
HD#25 AC6 N5 HA#7 VGA_LMD20 W22 AD22 CRT_R

AGP
HD#26
HD#27
AF6
AD11
HD#25
HD#26 HOST HA#7
HA#8
P5
R1
HA#8
HA#9 1 2 LTVDA
<13> VGA_LTCLK0
VGA_LTCLK0
VGA_LMD21
W26
Y21
G_AD29/LMD20
G_AD30/LTCLK0
RED
GREEN
AE22
AE23
CRT_G
CRT_B
CRT_R <13>
CRT_G <13>
CRT_B <13>
HD#28 AF8 HD#27 HA#9 U1 HA#10 R195 10K_0402 G_AD31/LMD21 BLUE
HD#29 AD8 HD#28 HA#10 P2 HA#11 1 2 LTVCL VGA_LMA3 H23
HD#30 AD5 HD#29 HA#11 T1 HA#12 R204 10K_0402 VGA_LMD10 N21 G_C/BE#0/LMA3 F22 CLK_HUB_GMCH
HD#31 AB7 HD#30 HA#12 T3 HA#13 VGA_LMD13 T25 G_C/BE#1/LMD10 HLCLK H24 HL0
HD#32 AF7 HD#31 HA#13 P3 HA#14 VGA_LRAS# Y26 G_C/BE#2/LMD13 HL0 H26 HL1
C HD#32 HA#14 <13> VGA_LRAS# G_C/BE#3/LRAS# HL1 C
HD#33 AD7 T5 HA#15 H25 HL2
HD#34 AB8 HD#33 HA#15 R5 HA#16 VGA_LMA10 R26 HL2 G24 HL3 +1_8VS
HD#35 AE7 HD#34 HA#16 V5 HA#17 VGA_LMD11 P26 G_FRAME#/LMA10 HL3 F24 HL4
HD#36 AE9 HD#35 HA#17 Y2 HA#18 VGA_LMD12 P23 G_DEVSEL#/LMD11 HL4 E26 HL5

1
HD#37 AB9 HD#36 HA#18 V3 HA#19 VGA_LMA7 P21 G_IRDY#/LMD12 HL5 E25 HL6
HD#38
HD#39
AF9
AD10
HD#37
HD#38
HA#19
HA#20
W1
U4
HA#20
HA#21 +3VS <13> VGA_LCS#
VGA_LCS#
VGA_LMA6
P25
R24
G_TRDY#/LMA7
G_STOP#/LCS#
HUB HL6
HL7
D26
D25
HL7
HL8
R72
300_1%_0402
HD#40 AF12 HD#39 HA#21 V2 HA#22 VGA_LMD27 AE26 G_PAR/LMA6 HL8 D24 HL9
HD#41 AB11 HD#40 HA#22 W3 HA#23 1 2 AD25 G_REQ#/LMD27 HL9 C26 HL10
HD#41 HA#23 G_GNT# HL10

2
HD#42 AB10 W4 HA#24 R255 4.7K_0402 VGA_LMD24 AC26 H21 +HUBREF_GMCH
HD#43 HD#42 HA#24 HA#25 PIPE#/LMD24 HLREF HL_STB
AD9 U5 G25 HL_STB <14>

1
HD#44 AC10 HD#43 HA#25 Y5 HA#26 AGP_ADSTB0 M22 HLPSTRB F26 HL_STB# R70
HD#44 HA#26 <12> GMBSDA AD_STB0 HLPSTRB# HL_STB# <14>
HD#45 AF10 Y3 HA#27 AGP_ADSTB#0 L23 H20 +GMCH_HLCOMP 1 2
+1_8VS

1
HD#46 AD14 HD#45 HA#27 U3 HA#28 AGP_ADSTB1 U22 AD_STB#0 HLZCOMP R71 36.5_1% C355
HD#47 AD12 HD#46 HA#28 Y1 HA#29 AGP_ADSTB#1 V23 AD_STB1
HD#48 AB12 HD#47 HA#29 W5 HA#30 AGP_SBSTB Y23 AD_STB#1 .01UF
HD#48 HA#30 SB_STB

2
HD#49 AE11 V1 HA#31 AGP_SBSTB# AA24 AB22 VGA_LMD31
HD#49 HA#31 <12> GMBSCL SB_STB# SBA0/LMD31
HD#50 AE15 AB25 VGA_LMD25
HD#51 AF11 HD#50 +3VS SBA1/LMD25 AB23 VGA_LDQM2
HD#52 AF13 HD#51 M1 HREQ#0 VGA_LMD30 AD26 SBA2/LDQM2 AB26 VGA_LMD26 300_1%_0402
HD#53 HD#52 HREQ#0 HREQ#1 RBF#/LMD30 SBA3/LMD26 VGA_LMD23
AB14 N1 1 2 AB24 AA22
HD#54 AF14 HD#53 HREQ#1 M2 HREQ#2 R79 4.7K_0402 WBF# SBA4/LMD23 AA26 VGA_LWE#
HD#54 HREQ#2 SBA5/LWE# VGA_LWE# <13>
HD#55 AB13 L5 HREQ#3 +AGPREF_2GMCH J24 Y22 VGA_LMD22
HD#56 AB15 HD#55 HREQ#3 N3 HREQ#4 HREQ#[0..4] 1 2 GRCOMP J26 AGPREF SBA6/LMD22 Y25 VGA_LFSEL
HD#56 HREQ#4 HREQ#[0..4] <4> GRCOMP SBA7/LGM_FRQ_SEL VGA_LFSEL <8,13>
HD#57 AE13 R73 36.5_1% G10
HD#58 AC14 HD#57 K2 RS#0 10_0402 NC AD24 VGA_LMD28
HD#59 AD13 HD#58 RS#0 L1 RS#1 R265 1 2 R22 ST0/LMD28 AC24 VGA_LDQM3
HD#60 AD15 HD#59 RS#1 H1 RS#2 RS#[0..2] P22 LOCLK ST1/LDQM3 AC23 VGA_LMD29
HD#60 RS#2 RS#[0..2] <4> LRCLK ST2/LMD29
HD#61 AF16
HD#61
B HD#62 AF15
HD#62
Place 10 ohm within 0.5" of B
HD#63 AC12 C356 HL[0..10]
HD#63 GMCH ball 'R22' and route GMCH2v0 HL[0..10] <14>

trace 1.5" to ball 'P22' @22PF


GMCH2v0

+CPU_IO For external AGP bus pull up/down resistors. <13> VGA_LMA[0..11]
VGA_LMA[0..11]
+3VS +3VS VGA_LMD[0..31]
<13> VGA_LMD[0..31]
VGA_LDQM[0..3]
TYPEDET# +VDDQ AGP-REF
RP38 <13> VGA_LDQM[0..3]
0 1.5V 0.5VDDQ
1

VGA_LMA7 1 10
R299 VGA_LMD11 2 9 VGA_LCS#
1K_1% VGA_LMD12 3 8 VGA_LMA10
1 3.3V 0.4VDDQ
VGA_LMD30 4 7 VGA_LMD24 +3VS
5 6 VGA_LMD27 C76
2

470PF_0402
10P8R-8.2K CLK_DOT_GMCH CLK_HUB_GMCH
+GTLREF CLK_HUB_GMCH <11>

1
1

1
+3VS R76 R77

1
R314 300_1%_0402 82_0402 R267
2K_1% C424 VGA_LMD28 1 2 AGP_ADSTB#0 1 2 R263 @33_0402
C400 R391 8.2K_0402 R392 8.2K_0402 @33_0402
.1UF

2
.1UF VGA_LDQM3 1 2 AGP_ADSTB#1 1 2
2

12
R393 8.2K_0402 R394 8.2K_0402 +AGPREF_2GMCH

2
VGA_LMD29 1 2 AGP_SBSTB# 1 2 C370
1

1
R395 8.2K_0402 R396 8.2K_0402 R75 C317
AGP_ADSTB0 1 2 VGA_LMA6 1 2 R74 82_0402 @22PF

2
R397 8.2K_0402 R398 100K_0402 200_1%_0402 @18PF
A AGP_ADSTB1 1 2 A
R399 8.2K_0402
2

2
AGP_SBSTB 1 2 C75
R400 8.2K_0402
470PF_0402

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D GMCH2-M - 1/3
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 7 of 42
5 4 3 2 1
5 4 3 2 1

Power-Up Strap Options


Pin Name Strap Description Configuration Interface Internal
SCAS# Host Freq. "H" : 133MHz (Default) System PULL_UP U7B

"L" : 100MHz Memory MMD0 D23 D13 MMA0


SMD0 SMAA0 MMA0 <10>
MMD1 C23 B16 MMA1
SMD1 SMAA1 MMA1 <10>
MMD2 D22 F12 MMA2
SWE# Host Freq. "H" : 100MHz (Default) System MMD3 F21 SMD2 SMAA2 A16 MMA3
MMA2 <10>
PULL_UP MMD4 E21 SMD3 SMAA3 B12
MMA3 <10>
"L" : 66MHz Memory MMD5 SMD4 SMAA4
D G20 A12 D
MMD6 F20 SMD5 SMAA5 C11
SMAA11 IOQ Depth "H" : 4 (Default) System MMD7 D20 SMD6 SMAA6 A11
PULL_UP MMD8 F19 SMD7 SMAA7 D12 MMA8
"L" : 1 Memory MMD9 E19 SMD8 SMAA8 C13 MMA9
MMA8 <10>
SMD9 SMAA9 MMA9 <10>
MMD10 D19 E11 MMA10
SMAA10 ALL Z "H" : Normal System MMD11 E18 SMD10 SMAA10 A13 MMA11
MMA10 <10>
PULL_UP MMD12 B18 SMD11 SMAA11 B7 MMA12
MMA11 <10>
"L" : All Z Memory MMD13 F18 SMD12 SMAA12 MMA12 <10>
MMD14 G18 SMD13 B15 MAB#4_R MAB#6_R 1 8 MAB#6
SMAA9 FSB P-MOS Kicker Enable "H" : Enabled (Default) System MMD15 SMD14 SMAB#4 MAB#5_R MAB#7_R
MAB#6 <10>
PULL_UP D17 A15 2 7 MAB#7 MAB#7 <10>
MMD16 A3 SMD15 SMAB#5 C14 MAB#6_R MAB#4_R 3 6 MAB#4
"L" : Disabled (Cumine) Memory MMD17 A1 SMD16 SMAB#6 A14 MAB#7_R MAB#5_R 4 5 MAB#5
MAB#4 <10>
SMD17 SMAB#7 MAB#5 <10>
MMD18 C1 RP8 8P4R-10
SMAC6# Enable VCH Serial "H" : Enabled (Default) System MMD19 F2 SMD18 B10 SMAC#4 SMAC#6 1 8 MAC#6
Programming Mode PULL_UP MMD20 G3 SMD19 SMAC#4 A10 SMAC#5 SMAC#7 2 7 MAC#7
MAC#6 <10>
"L" : Disabled Memory MMD21 D6 SMD20 SMAC#5 C10 SMAC#6 SMAC#4 3 6 MAC#4
MAC#7 <10>
SMD21 SMAC#6 MAC#4 <10>
MMD22 C5 A9 SMAC#7 SMAC#5 4 5 MAC#5
* SMAC5# Enable Quick Start "L" : Enabled (Default) System MMD23 B4 SMD22 SMAC#7 RP9 8P4R-10
MAC#5 <10>
Support (Quick Start Mode) MMD24 D4 SMD23 B13 SBS0
Memory PULL_UP SMD24 SBS0 SBS0 <10>

MEMORY
MMD25 SBS1
"H" : Disabled C2
SMD25 SBS1
D11 SBS1 <10>
MMD26 D3
(Stop Grant Mode) MMD27 E4 SMD26 D15
MMD28 F5 SMD27 SCSA#0 A17
MMD29 G4 SMD28 SCSA#1 D14 CSA#2
L o cal Memory Freq. Select "H" : 133MHz (Default) AGP/LM i815/i815-m MMD30 J6 SMD29 SCSA#2 E14 CSA#3
CSA#2 <10>
VGA_LFSEL# MMD31 K5 SMD30 SCSA#3 E13 CSA#4
CSA#3 <10>
"L" : 100MHz MMD32 A26 SMD31 SCSA#4 B17 CSA#5
CSA#4 <10>
SMD32 SCSA#5 CSA#5 <10>
MMD33 A25
MMD34 B24 SMD33 F9
C MMD35 SMD34 SCSB#0 C
A24 F8
MMD36 B23 SMD35 SCSB#1 D10
MMD37 A23 SMD36 SCSB#2 D9
MMD38 C22 SMD37 SCSB#3 B9
MMD39 A22 SMD38 SCSB#4 A8
MMD40 D21 SMD39 SCSB#5
MMD41 B21 SMD40 C16 SRASA#
SMD41 SRAS# SRASA# <10>
MMD42 A21 D18 SCASA#
SMD42 SCAS# SCASA# <10>
MMD43 C20 E16 RMWEA#
SMD43 SWE# RMWEA# <10>
MMD44 B20
MMD45 SMD44
A20 D8
MMD46 C19 SMD45 SCKE0 E8
MMD47 A19 SMD46 SCKE1 E9 CKE2
SMD47 SCKE2 CKE2 <10>
MMD48 A4 D7 CKE3
SMD48 SCKE3 CKE3 <10>
MMD49 A2 C8
SMD49 SCKE4 CKE4 <10>
RP2 8P4R-10 RP27 8P4R-10 MMD50 B1 C7 1 2
SMD50 SCKE5 CKE5 <10>
MD32 5 4 MMD32 MD3 5 4 MMD3 MMD51 E1 R315 @33_0402
C410 @22PF
MD33 6 3 MMD33 MD2 6 3 MMD2 MMD52 G2 SMD51 F7
SMD52 SCLK CLK_MEM_GMCH <11>
MD34 7 2 MMD34 MD1 7 2 MMD1 MMD53 E6
MD35 8 1 MMD35 MD0 8 1 MMD0 MMD54 D5 SMD53 D16 DQMA#0
SMD54 SDQM0 DQMA#0 <10>
MMD55 C4 F15 DQMA#1
SMD55 SDQM1 DQMA#1 <10>
MD36 5 4 MMD36 MD7 5 4 MMD7 MMD56 B3 A7 DQMA#2
SMD56 SDQM2 DQMA#2 <10>
MD37 6 3 MMD37 MD6 6 3 MMD6 MMD57 D2 A6 DQMA#3
SMD57 SDQM3 DQMA#3 <10>
MD38 7 2 MMD38 MD5 7 2 MMD5 MMD58 E3 A18 DQMA#4
SMD58 SDQM4 DQMA#4 <10>
MD39 8 1 MMD39 MD4 8 1 MMD4 MMD59 F4 C17 DQMA#5
SMD59 SDQM5 DQMA#5 <10>
MMD60 F6 B6 DQMA#6
SMD60 SDQM6 DQMA#6 <10>
RP3 8P4R-10 RP28 8P4R-10 MMD61 G5 A5 DQMA#7
SMD61 SDQM7 DQMA#7 <10>
MMD62 H4
RP4 8P4R-10 RP29 8P4R-10 MMD63 J4 SMD62 G7 SRCOMP R297 1 2 36.5_1%
SMD63 SRCOMP +3V
B MD43 4 5 MMD43 MD8 4 5 MMD8 B
MD42 3 6 MMD42 MD9 3 6 MMD9
MD41 2 7 MMD41 MD10 2 7 MMD10
MD40 1 8 MMD40 MD11 1 8 MMD11 GMCH2v0

MD47 4 5 MMD47 MD15 4 5 MMD15


MD46 3 6 MMD46 MD14 3 6 MMD14
MD45 2 7 MMD45 MD13 2 7 MMD13
MD44 1 8 MMD44 MD12 1 8 MMD12

RP5 8P4R-10 RP7 8P4R-10

RMWEA# R285 1 2 @10K_0402


RP10 8P4R-10 RP33 8P4R-10 SCASA# R281 1 2 10K_0402
MD20 1 8 MMD20 MD60 1 8 MMD60 SBS0 R292 1 2 10K_0402
MD21 2 7 MMD21 MD61 2 7 MMD61 MMA9 R301 1 2 10K_0402
MD22 3 6 MMD22 MD62 3 6 MMD62 MAC#5 R305 1 2 10K_0402
MD23 4 5 MMD23 MD63 4 5 MMD63 MAC#6 R307 1 2 @10K_0402
CSA#4 R290 1 2 @10K_0402
MD16 1 8 MMD16 MD59 1 8 MMD59 VGA_LFSEL# R68 2 1 @10K_0402
<7,13> VGA_LFSEL
MD17 2 7 MMD17 MD58 2 7 MMD58
MD18 3 6 MMD18 MD57 3 6 MMD57
MD19 4 5 MMD19 MD56 4 5 MMD56

RP31 8P4R-10 RP34 8P4R-10

RP15 8P4R-10 RP11 8P4R-10


MD28 1 8 MMD28 MD52 1 8 MMD52 MD[0..63]
MD29 2 7 MMD29 MD53 2 7 MMD53 <10> MD[0..63]
A MD30 3 6 MMD30 MD54 3 6 MMD54 A
MD31 4 5 MMD31 MD55 4 5 MMD55

MD24 1 8 MMD24 MD48 1 8 MMD48


MD25 2 7 MMD25 MD49 2 7 MMD49
MD26 3 6 MMD26 MD50 3 6 MMD50
MD27 4 5 MMD27 MD51 4 5 MMD51
Compal Electronics, Inc.
RP13 8P4R-10 RP12 8P4R-10 Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D GMCH2-M - 2/3
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 8 of 42
5 4 3 2 1
5 4 3 2 1

+1_8VS +1_8VS
U7D
+VCCDPLL J7 W6
VCC1_8/VCCDPLL VCC1_8
K7 G26
GND/VSSDPLL VCC1_8 M6
AE25 VCC1_8 P6

1
+ C118 C418 AF24 GND/VSSDACA1 VCC1_8 Y9
E22 GND/VSSDACA2 VCC1_8 Y18
22UF_6.3V_1210_X5R .1UF Y8 GND/VSSBA VCC1_8 AA8
GND VCC1_8

2
AB4 AA11
M13 GND VCC1_8 AA13
AC2 GND VCC1_8 AA15
AC5 GND VCC1_8 AA17 +3VS +1_8VS +3V
GND VCC1_8
D AC7 AA19 D
AC9 GND VCC1_8 AB16
AC11 GND VCC1_8 AB20 +1_8VS C274 C119 C120
AC13 GND VCC1_8 AC22 1 2

+
AC15 GND VCC1_8 AD19

1
AC17 GND VCC1_8 C25 22UF_6.3V_1210_X5R 22UF_6.3V_1210_X5R 150UF_6.3V_E

2
AC19 GND VCC1_8 E24 R319
AC21 GND VCC1_8 F23 0_0402 C482 C104 C432

+
AC25 GND VCC1_8 G22 L16 1 2 .01UF

+
AE2 GND VCC1_8 K6 68nH 22UF_6.3V_1210_X5R
GND VCC1_8 C393

2
AE4 Y7 150UF_6.3V_E
GND VCC1_8

1
AE6 AA21 +VCCDA C371 .01UF
AE8 GND VCCDA/(VCC1_8) E23 .1UF C398 .1UF
AE10 GND VCCBA/(VCC1_8) AF26 C404

1
AE12 GND VCCDACA1/(VCC1_8) AF25 C407 C358 82PF

1
AE14 GND VCCDACA2/(VCC1_8) AA6 .1UF C109 .1UF
C367 C399
AE16 GND HCLK# V7 10UF_10V_1206 C431
GND VCC1_8 .1UF 22UF_10V_1206 C325

2
AE18 T6 .01UF
GND VCC1_8 +3V

2
AE20 .1UF C417 82PF
B26 GND C394
GND C359 .01UF
C3 B2
C6 GND VSUS_3.3_1 B5 .1UF C415 .1UF
C9 GND VSUS_3.3_2 B8 C428
C12 GND VSUS_3.3_3 B11 C326 82PF
C15 GND VSUS_3.3_4 B14 .1UF C416 .1UF
C18 GND VSUS_3.3_5 B19 C126
C21 GND VSUS_3.3_6 B22 C324 .01UF
C24 GND VSUS_3.3_7 B25 82PF C414 82PF
D1 GND VSUS_3.3_8 E2 C433
E5 GND VSUS_3.3_9 F10 .01UF
C GND VSUS_3.3_10 C357 C413 .1UF C
E10 F14
E12 GND VSUS_3.3_11 F17 82PF C419
E15 GND VSUS_3.3_12 G6 82PF
E17 GND VSUS_3.3_13 G8 C372 .1UF
E20 GND VSUS_3.3_14 G19 C354 C333
F1 GND VSUS_3.3_15 H2 82PF .01UF
F3 GND VSUS_3.3_16 H5 C383 82PF
F11 GND VSUS_3.3_17 H7 +3VS C352
F13 GND VSUS_3.3_18 .01UF
T21 GND K20 +3VS C377 .1UF
GND VDDQ
U2 Y24
U7 GND VDDQ L21
K24 GND VDDQ M23 C346 .1UF

1
V4 GND VDDQ U25
V6 GND VDDQ N25 R280
V20 GND VDDQ R21 10K_0402 1 2
V22 GND VDDQ U20 C483 .1UF_0402
W2 GND VDDQ U23
GND VDDQ

2
W23 W20
W25 GND VDDQ 1 2
GND C484 .1UF_0402
Y4 Y17
POWER/GND

Y6 GND INTRPT# E7 R112 1 2 0_0402


GND AGPBUSY# A G P_BUSY# <15>
Y10 M14
Y19 GND GND M15
AA2 GND GND M16
AA9 GND GND N2
AA12 GND GND N6
AA14 GND GND N11
AA16 GND GND N12
B P11 GND GND N13 B
GND GND
P12 N14
P13 GND GND N15
P14 GND GND N16
P15 GND GND N23
P16 GND GND P4
R2 GND GND AA23
R6 GND GND F16
R11 GND GND F25
R12 GND GND G9
R13 GND GND G17
GND GND
R14 G21
GND GND
R15
GND GND
G23 PIN# DT_GMCH GMCH2-M
R16 P24
R23 GND GND H6
GND GND
R25
GND GND
H22 E7 VSS (GND) AGPBUSY# (OUTPUT)
T4 J2
T11 GND GND J5
GND GND
T12
GND GND
J23 AA6 V_1.8 (1.8V) RESERVED (1.8V)
T13 J25
T14 GND GND K4
GND GND
T15 K21 Y17 VSS (GND) INTRPT# (INPUT)
T16 GND GND L2
L15 GND GND L6
GND GND
L16
GND GND
L11 AC18 LTVCLKIN (INPUT) LTVCLKIN/STALL (INPUT)
L22 L12
L25 GND GND L13
M4 GND GND L14
M11 GND GND AA25
M12 GND GND W7
A A
GND GND

GMCH2v0

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D GMCH2-M - 3/3
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 9 of 42
5 4 3 2 1
1 2 3 4 5 6 7 8

+3V
+3V
+3V +3V

JP17 JP16
1 2 1 2
MD31 3 VSS VSS 4 MD55 MD55 3 VSS VSS 4 MD31
MD30 5 DQ0 DQ32 6 MD54 MMA13 MD54 5 DQ0 DQ32 6 MD30
MD29 7 DQ1 DQ33 8 MD53 MD53 7 DQ1 DQ33 8 MD29

1
MD28 9 DQ2 DQ34 10 MD52 R86 MD52 9 DQ2 DQ34 10 MD28
11 DQ3 DQ35 12 11 DQ3 DQ35 12
MD27 13 VCC VCC 14 MD51 MD51 13 VCC VCC 14 MD27
MD26 DQ4 DQ36 MD50 1K_0402 MD50 DQ4 DQ36 MD26
A 15 16 15 16 A
MD25 17 DQ5 DQ37 18 MD49 MD49 17 DQ5 DQ37 18 MD25
DQ6 DQ38 DQ6 DQ38

2
MD24 19 20 MD48 MD48 19 20 MD24
21 DQ7 DQ39 22 21 DQ7 DQ39 22
DQMA#3 23 VSS VSS 24 DQMA#6 DQMA#6 23 VSS VSS 24 DQMA#3
DQMA#2 25 CE0# CE4# 26 DQMA#7 DQMA#7 25 CE0# CE4# 26 DQMA#2
27 CE1# CE5# 28 27 CE1# CE5# 28
MMA0 29 VCC VCC 30 MMA3 MMA0 29 VCC VCC 30 MMA3
<8> MMA0 A0 A3 MMA3 <8> <8> MMA0 A0 A3 MMA3 <8>
MMA1 31 32 MAB#4 MMA1 31 32 MAC#4
<8> MMA1 A1 A4 MAB#4 <8> <8> MMA1 A1 A4 MAC#4 <8>
MMA2 33 34 MAB#5 MMA2 33 34 MAC#5
<8> MMA2 A2 A5 MAB#5 <8> <8> MMA2 A2 A5 MAC#5 <8>
35 36 35 36
MD23 37 VSS VSS 38 MD63 MD63 37 VSS VSS 38 MD23
MD22 39 DQ8 DQ40 40 MD62 MD62 39 DQ8 DQ40 40 MD22
MD21 41 DQ9 DQ41 42 MD61 MD61 41 DQ9 DQ41 42 MD21
MD20 43 DQ10 DQ42 44 MD60 MD60 43 DQ10 DQ42 44 MD20
45 DQ11 DQ43 46 45 DQ11 DQ43 46
MD19 47 VCC VCC 48 MD59 MD59 47 VCC VCC 48 MD19
MD18 49 DQ12 DQ44 50 MD58 MD58 49 DQ12 DQ44 50 MD18
MD17 51 DQ13 DQ45 52 MD57 MD57 51 DQ13 DQ45 52 MD17
MD16 53 DQ14 DQ46 54 MD56 MD56 53 DQ14 DQ46 54 MD16
DQ15 DQ47 C81 DQ15 DQ47
55 56 55 56
R93 57 VSS VSS 58 1 2 1 2 57 VSS VSS 58
5PF 6.8_0402 59 RESVD/DQ64 RESVD/DQ68 60 R89 6.8_0402 59 RESVD/DQ64 RESVD/DQ68 60
1 2 1 2 RESVD/DQ65 RESVD/DQ69 5PF RESVD/DQ65 RESVD/DQ69
C86
61 62 61 62
<11> CLK_MEM2 RFU/CLK0 RFU/CKE0 CKE2 <8> <11> CLK_MEM4 RFU/CLK0 RFU/CKE0 CKE4 <8>
63 64 63 64
65 VCC VCC 66 65 VCC VCC 66
<8> SRASA# RFU RFU SCASA# <8> <8> SRASA# RFU RFU SCASA# <8>
RMWEA# 67 68 RMWEA# 67 68
<8> RMWEA# WE# RFU/CKE1 CKE3 <8> <8> RMWEA# WE# RFU/CKE1 CKE5 <8>
69 70 MMA12 69 70 MMA12
B <8> CSA#2 RE0# RFU MMA12 <8> <8> CSA#4 RE0# RFU MMA12 <8> B
71 72 MMA13 71 72 MMA13
<8> CSA#3 RE1# RFU <8> CSA#5 RE1# RFU
73 74 73 74
OE#/RESVD RFU/CLK1 CLK_MEM3 <11> OE#/RESVD RFU/CLK1 CLK_MEM5 <11>
75 76 75 76
77 VSS VSS 78 77 VSS VSS 78
79 RESVD/DQ66 RESVD/DQ70 80 79 RESVD/DQ66 RESVD/DQ70 80

1
81 RESVD/DQ67 RESVD/DQ71 82 81 RESVD/DQ67 RESVD/DQ71 82
MD47 83 VCC VCC 84 MD15 R84 MD15 83 VCC VCC 84 MD47
MD46 85 DQ16 DQ48 86 MD14 6.8_0402 MD14 85 DQ16 DQ48 86 MD46 R85
MD45 87 DQ17 DQ49 88 MD13 MD13 87 DQ17 DQ49 88 MD45 6.8_0402
MD44 89 DQ18 DQ50 90 MD12 MD12 89 DQ18 DQ50 90 MD44
DQ19 DQ51 DQ19 DQ51

1 2

1 2
91 92 91 92
MD43 93 VSS VSS 94 MD11 C84 MD11 93 VSS VSS 94 MD43
MD42 95 DQ20 DQ52 96 MD10 MD10 95 DQ20 DQ52 96 MD42 C85
MD41 97 DQ21 DQ53 98 MD9 5PF MD9 97 DQ21 DQ53 98 MD41 5PF
DQ22 DQ54 DQ22 DQ54

2
MD40 99 100 MD8 MD8 99 100 MD40
101 DQ23 DQ55 102 101 DQ23 DQ55 102
MAB#6 103 VCC VCC 104 MAB#7 MAC#6 103 VCC VCC 104 MAC#7
<8> MAB#6 A6 A7 MAB#7 <8> <8> MAC#6 A6 A7 MAC#7 <8>
MMA8 105 106 SBS0 MMA8 105 106 SBS0
<8> MMA8 A8 A11/BA0 SBS0 <8> <8> MMA8 A8 A11/BA0 SBS0 <8>
107 108 107 108
MMA9 109 VSS VSS 110 SBS1 MMA9 109 VSS VSS 110 SBS1
<8> MMA9 A9 A12/BA1 SBS1 <8> <8> MMA9 A9 A12/BA1 SBS1 <8>
MMA10 111 112 MMA11 MMA10 111 112 MMA11
<8> MMA10 A10 A13/A11 MMA11 <8> <8> MMA10 A10 A13/A11 MMA11 <8>
113 114 113 114
DQMA#5 115 VCC VCC 116 DQMA#1 DQMA#1 115 VCC VCC 116 DQMA#5
DQMA#4 117 CE2#/RESVD CE6#/RESVD 118 DQMA#0 DQMA#0 117 CE2#/RESVD CE6#/RESVD 118 DQMA#4
119 CE3#/RESVD CE7#/RESVD 120 119 CE3#/RESVD CE7#/RESVD 120
MD39 121 VSS VSS 122 MD7 MD7 121 VSS VSS 122 MD39
MD38 123 DQ24 DQ56 124 MD6 MD6 123 DQ24 DQ56 124 MD38
MD37 125 DQ25 DQ57 126 MD5 MD5 125 DQ25 DQ57 126 MD37
MD36 127 DQ26 DQ58 128 MD4 MD4 127 DQ26 DQ58 128 MD36
C 129 DQ27 DQ59 130 129 DQ27 DQ59 130 C
MD35 VCC VCC MD3 MD3 VCC VCC MD35
131 132 131 132
MD34 133 DQ28 DQ60 134 MD2 MD2 133 DQ28 DQ60 134 MD34
MD33 135 DQ29 DQ61 136 MD1 MD1 135 DQ29 DQ61 136 MD33
MD32 137 DQ30 DQ62 138 MD0 MD0 137 DQ30 DQ62 138 MD32
139 DQ31 DQ63 140 139 DQ31 DQ63 140
141 VSS VSS 142 SMB_ICH_DAT_M1 141 VSS VSS 142 SMB_ICH_CLK_M
<11> SMB_ICH_DAT_M0 SDA SCL SMB_ICH_CLK_M <11> <11> SMB_ICH_DAT_M1 SDA SCL
143 144 143 144
VCC VCC VCC VCC
SO-DIMM144_R SO-DIMM144

DIMM1 DIMM2
REVERSE <8> MD[0..63]
MD[0..63] H=5.2mm
H=4.0mm <8> DQMA#[0..7]
DQMA#[0..7]

+3V +3V +3V

1
+3V +3V +3V C39 C48 C61 C56 C92 C91 C96 C106 C93 C108 C74 C436

1000PF .1UF 1000PF .1UF .1UF .1UF .1UF .1UF 1000PF .1UF 1000PF 10UF_10V_1206
2

2
1

C107 C40 C50 C58 C66 C90 C94 C51 C67 C77 C95 C437

1000PF .1UF 1000PF .1UF .1UF .1UF .1UF .1UF 1000PF .1UF 1000PF 10UF_10V_1206
2

D D

For SO-DIMM2

For SO-DIMM1
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
P10-SODIMM0/1.SCH
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
B
Date: T h ursday, January 11, 2001 Sheet 10 of 42
1 2 3 4 5 6 7 8
A B C D E

+3V_CLK
L14
1 2 +3V_CLK
+3VS
BLM21A601SPT

1
C72 C65 C63 C57 C64 C68 C73 C80 L15
+2_5V_CLKS 2 1
+2_5V_CLK
4.7UF_10V_0805 .1UF .1UF .1UF .1UF .1UF .1UF .1UF BLM21A601SPT

1
C79 C83 C82

.1UF .1UF 4.7UF_10V_0805


4 4

2
C78
2 1 CK133-XIN U6

23

22
17

10
37
27
44
35

51
53
1

2
18PF R65 Y1

VCC3/(SDRAM6)
VCC3
VCC3
VCC3

VCC3
VCC3
VCC3

VCC2
VCC2
VDDA
GNDA
3
C71 2M 14.318MHZ X1

2
2 1 CK133-XOUT 4 55 APIC0 R88 1 2 33_0402
X2 APIC0 CLK_APIC_CPU <4>

2
54 APIC1 R87 1 2 47_0402
APIC1 CLK_APIC_ICH <14>
R82 2 1 33_0402 18PF
<15> CLK_14M_ICH
SEL0 28
SEL1 29 SEL0 52 HCLK1 R83 1 2 33_0402
SEL1(TRIST#) CPU0 CLK_HOST_CPU <4>
R81 2 1 33_0402 CLK_14M 1 50 HCLK2 R69 1 2 33_0402
<21> CLK_14M_SIO REF0/(SEL1) CPU1 CLK_HOST_GMCH <7>
49
CPU2(ITP)
46
<15> PCI_STP# R62 1 2 33_0402 PCISTP# 11 SDRAM0 45
<14> CLK_PCI_ICH PCI_STP#/(VCC3) SDRAM1
CLK_ICH 12 43 SDRAM2 R58 1 2 10_0402
PCI_F(PCI0_ICH) SDRAM2 CLK_MEM2 <10>
R61 1 2 33_0402 CLK_PCI1 13 42 SDRAM3 R60 1 2 10_0402
<19> CLK_PCI_PCM PCI1 SDRAM3 CLK_MEM3 <10>
R59 1 2 @33_0402 CLK_FWH 15 40 SDRAM4 R56 1 2 10_0402
<14> CLK_PCI_FWH PCI2 SDRAM4 CLK_MEM4 <10>
R55 1 2 33_0402 CLK_SIO 16 39 SDRAM5 R57 1 2 10_0402
<21> CLK_PCI_SIO PCI3 SDRAM5 CLK_MEM5 <10>
18
R53 1 2 22_0402 CLK_MDM 19 PCI4 36 OSCVCH R52 1 2 33_0402
<29> CLK_PCI_MINI PCI5 VCH_CLK/(SDRAM7) CLK_OSC_VCH <12>
20
PCI6
9
R51 1 2 33_0402 CLK_USB 25 3V66_AGP 8 CLK_3V66_1 R64 1 2 33_0402
<15> CLK_USB_ICH USB(48M) 3V66_1 CLK_HUB_GMCH <7>
R49 1 2 33_0402 CLK_DOT 26 7 CLK_3V66_0 R67 1 2 33_0402
3 <7> CLK_DOT_GMCH DOT(48M) 3V66_0 CLK_HUB_ICH <15> 3

1 2 33 38 DCLK R54 1 2 33_0402


+3V_CLK TEST#/(VCC3) DCLK/(VCC3) CLK_MEM_GMCH <8>
R46 1 2 0_0402 32 34
PWR_DWN# CPU_STP#(DCLK) CPU_STP# <15>
<15,22> SLP_S1# 8.2K_0402R50
30
<15> SMB_ICH_DAT SDATA
31

GND
GND
GND
GND
GND
GND
GND
GND
GND
<15> SMB_ICH_CLK SCLK

CK133-SOLANO2-M

14
21
24
41
47
48
56
1

5
6
+3V_CLK R45

10K_0402

2
SEL1 SEL0 PSB SDRAM

0 0 66 100

+3V_CLK
* 0 1 100 100

1 0 133 133
1

R41
<15> SEL_DIMM0
+3V
2 10K_0402 1 1 133 100 2
<15> SEL_DIMM1
2

SEL0 +3VS CK-Solano CK-Solano2-m


1

1
Pin #
1

R33 R35 R32 W218 C9815 W224 C9835


R43 10K_0402 10K_0402 10K_0402
1

2
G

@1K_0402
1 REF0/SEL1 REF/SEL1 REF REF
2

2
R38 R37 3 1
SMB_ICH_DAT_M0 <10>
11 VCC3 VCC3 PCI_STP# PCI_STP#
S

D
2

4.7K_0402 10K_0402 Q8
2N7002
2 G

29 Tristate# Tristate# SEL1 SEL1


2

<15> SMB_ICH_DAT
Q9 3 1
SMB_ICH_DAT_M1 <10> 33 VCC3 VCC3 TEST# TEST#
S

2N7002
+5VS 34 DCLK DCLK CPU_STP# CPU_STP#
+3V_CLK
36 SDRAM7 SDRAM7 VCH_CLK VCH_CLK
2
G
1

37 SDRAM6 SDRAM6 VCC3 VCC3


R40 3 1 Q10
<15> SMB_ICH_CLK SMB_ICH_CLK_M <10>
@10K_0402 2N7002 38 VCC3 VCC3 DCLK DCLK
S

D
2

SEL1
2

1 R39 1
1K_0402
1

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Clock Synthesizer
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 11 of 42
A B C D E
5 4 3 2 1

U15A
E3 G14
E2 P0 DVOrVSYNC G13
E1 P1 DVOrHSYNC G12
F3 P2 DVOrBLANK# F14 1 2 DVO_D[0..11] VCH_VID[0..4]
P3 DVOrCLKIN <7> DVO_D[0..11] VCH_VID[0..4] <4>
F2 J13 R377 2.4K
F1 P4 DVOrCLKOUT0 J12 U15B
P5 DVOrCLKOUT1 GMBSDA
D G3 H14 M11 D13 GMBSDA <7> D
G2 P6 DVOrDATA0 H13 P10 DVODATA0 GMBSDA D12 GMBSCL
P7 DVOrDATA1 DVODATA1 GMBSCL GMBSCL <7>
G1 H12 N10 E13 PID3
H3 P8 DVOrDATA2 J14 M10 DVODATA2 GPIO5 E12 PID2
H2 P9 DVOrDATA3 K14 P9 DVODATA3 GPIO4 F12 VCH_VID2
H1 P10 DVOrDATA4 K13 M9 DVODATA4 GPIO6 C13 PID1
J3 P11 DVOrDATA5 K12 P8 DVODATA5 GPIO3 B13 PID0
J2 P12 DVOrDATA6 L14 P7 DVODATA6 GPIO2 F13 VCH_VID0
J1 P13 DVOrDATA7 L13 N7 DVODATA7 GPIO8 1 2 C54 @18PF
K3 P14 DVOrDATA8 L12 M7 DVODATA8 R36 @33_0402
P15 DVOrDATA9 DVODATA9 VCH_VID1
K2 M14 P6 E14
K1 P16 DVOrDATA10 M13 N6 DVODATA10 GPIO7 M12
P17 DVOrDATA11 DVODATA11 OSC CLK_OSC_VCH <11>
L3
L2 P18
L1 P19 A3 LCD0 M8 D14
P20 YA0P <7> DVO_CLK# DVOCLKIN0 PCIRST PCIRST# <7,14,19,21,29>
M3 B3 LCD1 N8 C12 VCH_VID4 2 1 M_SEN#
P21 YA0M <7> DVO_CLK DVOCLKIN1 GPIO0 M_SEN# <13>
M2 A4 LCD2 33_0402 N11 C14 VCH_VID3 R431 0_0402
P22 YA1P <7> DVO_BL# DVOBLK GPIO1
M1 B4 LCD3 1 2 P12 B14 2 1
P23 YA1M <7> DVO_CLKOUT DVOCLKOUT TESTIN +3VS
N1 A5 LCD4 R48 P11 R432 10K_0402
P24 YA2P <7> DVO_HSYNC DVOHSYNC
N2 B5 LCD5 N12 N9 TV_ZCOM 1 2
P25 YA2M <7> DVO_VSYNC DVOVSYNC DVOrZCOM +1_8VS
P2 A7 P13 R34 36.5_1%
N3 P26 YA3P B7 LCDVREF
P3 P27 YA3M A6 LCD6
M4 P28 CLKAP B6 LCD7 +1_8VS +3VALW +5VALW
N4 P29 CLKAM A8 LCD10 H5
P4 P30 YB0P B8 LCD11 A1 VSS H6

1
M5 P31 YB0M A9 LCD12 A14 VSS VSS H7

1
N5 P32 YB1P B9 LCD13 R235 B1 VSS VSS H8 6.8K_0402 INV_PWR
P5 P33 YB1M A10 LCD14 2K_1% C4 VSS VSS H9 R426 R420 R421
M6 P34 YB2P B10 LCD15 D11 VSS VSS H10 0_0402 6.8K_0402 2 1
C P35 YB2M VSS VSS C30 .01UF C
C1 A11 E5 J5
FLM YB3P VSS VSS

2
B2 B11 E6 J6
LP YB3M VSS VSS

2
D2 A12 LCD16 E7 J7 Q49 2 1

2
DE CLKBP +1_8VS VSS VSS

G
D3 B12 LCD17 E9 J8 2N7002 C29 .1UF
SHFCLK CLKBM E10 VSS VSS J9 JP7

1
D8 1 2 F5 VSS VSS J10 3 1 2 1 1
<4,22,23,31> SMB_EC_DA1

1
VREF_HI VSS VSS 1

D
D7 R185
1 150
2 R234 C240 F6 K5 C28 .1UF 2
+3VS VREF_LO R184 150 2K_1% F7 VSS VSS K6 3 2
A2 .1UF F8 VSS VSS K7 4 3
VCC3.3 VSS VSS +5V 4

2
A13 C2 F9 K8 Q50 5
VCC3.3 ENABKL ENABKL <13,23> VSS VSS +5VALW 5

G
2
2

C9 C3 ENVDD F10 K9 2N7002 6


D4 VCC3.3 ENAVDD D1 G5 VSS VSS K10 SMB_INV_DA 7 6
D6 VCC3.3 ENEXBUF G6 VSS VSS L4 3 1 SMB_INV_CK 8 7
VCC3.3 VSS VSS <4,22,23,31> SMB_EC_CK1 8

D
D9 G7 N14 9
E4 VCC3.3 C5 G8 VSS VSS P1 10 9
VCC3.3 VCC1.8 VSS VSS <13> DISPOFF# 10
F11 D5 G9 P14 11
G4 VCC3.3 VCC1.8 D10 G10 VSS VSS 12 11
H4 VCC3.3 VCC1.8 E8 VSS PID3 13 12
J4 VCC3.3 VCC1.8 E11 +1_8VS PID3 PID2 14 13
K4 VCC3.3 VCC1.8 F4 PID2 15 14
VCC3.3 VCC1.8 VCH 15
L6 G11 PID1 PID1 16
C6 VCC3.3 VCC1.8 H11 PID0 PID0 17 16
VCC3.3 VCC1.8 J11 18 17
VCC1.8 K11 C23 C25 C26 C27 19 18
+1_8VS VCC1.8 LCDVDD 19
L10 L5 20
C10 PLL_VCC VCC1.8 L7 +1_8VS +3VS .1UF_0402 .1UF_0402 2 1 21 20
C7 LVDSPLL_VCC VCC1.8 L8 C24 22 21
DC_CKT_CKT VCC1.8 L9 .1UF_0402 .1UF_0402 23 22
VCC1.8 +3V 23
N13 .1UF_0402 24
1

1
B L11 VCC1.8 LTVCL 25 24 B
C44 C52 C41 C220 C37 C206 C46 C42 C47 C176 C45 C38 C53 C197 <7> LTVCL
PLL_VSS C172 C201 LTVDA 25
C11 <7> LTVDA 26
C8 LVDSPLL_VSS .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 10UF_10V_1206 27 26
DC_CKT_VSS 27
2

2
LCD1 28
PID3 LCD0 29 28
10UF_10V_1206 30 29
VCH 30
PID2 LCD3 31
LCD2 32 31
+12VALW LCDVDD LCDVCC PID1 33 32
LCD5 34 33
PID0 LCD4 35 34
35
1

INV_PWR LCDVDD +12VALW L10 4.7K_0402 36


B+ 36
S

Q24 R11 3 1 1 2 1 2 LCD7 37


+3VS +3VS 37
1 8 FBM-11-451616-800A R186 LCD6 38
1

2 7 100K_0402 Q19 1 2 39 38
3 6 R175 R16 SI2302DS R187 4.7K_0402 LCD11 40 39
G
1

40
2

C169 5 1 2 LCD10 41
R183 470 100K_0402 R188 4.7K_0402 42 41
.1UF FDS4435 1 2 LCD13 43 42
43
2

100K_0402 SI2302DS: NCHANNEL R189 4.7K_0402 LCD12 44


Q21 44
45
D D VGS:4.5V, RDS:85mOHM 45
1

1
2

FDS4435:PCHANNAL LCD15 46
2N7002 46
2 2 R10 VGS:2.5V, RDS:115mOHM LCD14 47
1

G G C16 48 47
R190 S Q3 S 150K Id(MAX): 2.8A LCD17 49 48
.01UF LCDVDD 49
VGS(MAX): +/-8V
3

2N7002 LCD16 50
1

75K 50
2

C Q18 LCD CONN


+5V
2

1
A C164 A
D
1

ENVDD 2 22K C165


2 Q28 B 10UF_10V_1206 .1UF
2

G 2N7002 E
S 22K DTC124EK
3

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D VCH
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 12 of 42
5 4 3 2 1
5 4 3 2 1

DISPLAY CACHE INTERFACE DSCACHE# Status

0 Display cache exist


+3VS +3VS

1 Display cache no exist


1 2 1 2
C59 .1UF JP9 C60 .1UF
1 2
VGA_LMD4 1 2 VGA_LMD3
D 3 4 D
VGA_LMD5 5 3 4 6 VGA_LMD2 VGA_LMA[0..11]
5 6 <7> VGA_LMA[0..11] +3VS
VGA_LMD6 7 8 VGA_LMD1 VGA_LMD[0..31]
7 8 <7> VGA_LMD[0..31]
VGA_LMD7 9 10 VGA_LMD0 VGA_LDQM[0..3]
9 10 <7> VGA_LDQM[0..3]
11 12

1
VGA_LMA4 13 GND GND 14 VGA_LDQM0
VGA_LMA5 15 13 14 16 VGA_LMA3 R179
VGA_LMA6 17 15 16 18 VGA_LMA2 4.7K_0402
VGA_LMA7 19 17 18 20 VGA_LMA1
VGA_LDQM1 21 19 20 22 VGA_LMA0
21 22

2
VGA_LMD8 23 24 VGA_LCS# 1 2 1 2
23 24 VGA_LCS# <7> <22> BKOFF# DISPOFF# <12>
VGA_LMD9 25 26 VGA_LMA8 D9 R416 100_0402
VGA_LMD10 27 25 26 28 VGA_LMA9 RB751V
VGA_LMD11 29 27 28 30 VGA_LMA10
31 29 30 32 1 2
GND GND <12,23> ENABKL
VGA_LMD12 33 34 VGA_LMA11 D16
VGA_LMD13 35 33 34 36 VGA_LCKE RB751V
35 36 VGA_LCKE <7>
VGA_LMD14 37 38 VGA_LCAS#
37 38 VGA_LCAS# <7>
VGA_LMD15 39 40 VGA_LRAS#
39 40 VGA_LRAS# <7>
VGA_LMD16 41 42 VGA_LWE#
41 42 VGA_LWE# <7>
VGA_LMD17 43 44 VGA_LFSEL 1 2 1 2
43 44 VGA_LFSEL <7,8>
VGA_LMD18 45 46 DSCACHE# R251 10_0402 C243 10PF
45 46 DSCACHE# <15>
VGA_LMD19 47 48 VGA_LTCLK0
47 48 VGA_LTCLK0 <7>
49 50
VGA_LMD20 51 GND GND 52 VGA_LTCLK1
51 52 VGA_LTCLK1 <7>
VGA_LMD21 53 54
VGA_LMD22 55 53 54 56 VGA_LMD31 1 2 1 2
VGA_LMD23 57 55 56 58 VGA_LMD30 R250 10_0402 C242 10PF
VGA_LDQM2 59 57 58 60 VGA_LMD29
VGA_LDQM3 61 59 60 62 VGA_LMD28
C VGA_LMD24 61 62 C
63 64 VR_POK <30>
VGA_LMD25 65 63 64 66
65 66 ITP_VR_POK <25>
VGA_LMD26 67 68
67 68 ITP_TDI <4>
69 70
VGA_LMD27 71 GND GND 72
71 72 ITP_TDO <4>
73 74
<4> ITP_TCK 73 74 ITP_TRST# <4>
75 76
<4> ITP_TMS 75 76 ITP_PREQ# <4>
77 78
<4,7> CPURST# 77 78 GTL_PRDY# <4>
79 80
79 80 +CPU_IO CRTVCC +3VS +3VS
1

C231
CONN 2X40

2
.1UF

1
2

R324
0_0402
R422 R423 R3
10K_0402 10K_0402 0_0402 R172 R2
1

2K_0402 2K_0402

2
CRTVCC

2
G
Q15
2N7002
SI2301DS: P CHANNEL 1 3
3VDDCDA <7>

1
VGS: -4.5V, RDS: 130mOHM D1 @DAN217 D3 @DAN217 D2 @DAN217 C162

S
VGS: -2.5V, RDS:190mOHM

2
G
.1UF Q1
Id(MAX): 2.3A

2
2N7002
1 3
B
VGS(MAX): +-8V 3VDDCCL <7> B

S
+1_8VS
2

3
JP4
3 2 6
S G M_SEN# L6 11
DDC_MONID0 <12> M_SEN#
CRTR 1 2 1
<7> CRT_R
FCM2012C-800(0805) 7
L7 12
SI2301DS <7> CRT_G
CRTG 1 2 2
FCM2012C-800(0805) 8
D 1 L8 13
+5VS

D S
CRTVCC
<7> CRT_B
CRTB 1 2
FCM2012C-800(0805)
3
9
CRT CONN.
1

14
1

1
1 3 R6 R5 R4 C3 C6 C5 4
Q62 75 75 75 10
SI2301DS 18PF 18PF 18PF 15
2

2
5
G
1
2

1 2 5
R433 10K_0402 CRT CONN.
2 4 L36 1 2
<7> CRT_HSYNC
FBM-11-160808-121
DDC2_MONID2
74AHCT1G125GW
U34
CRTVCC
3

L35 1 2
FBM-11-160808-121
2

1
C161 C160 C2 C7 C4 C8
1

C503 R170 R167


4.7K_0402 4.7K_0402 27PF 27PF 100PF 100PF 100PF 100PF
2

2
A .1UF A
2

5
CRTVCC
2 4
<7> CRT_VSYNC
74AHCT1G125GW
U35 Compal Electronics, Inc.
3

Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CRT CONN
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 13 of 42
5 4 3 2 1
5 4 3 2 1

+3VS
+3VS
+3VS +3VS
FWH

2
R199 1 2 @0_0402 +VPP_R
1

1
R213 R211 PCIRST# CLK_PCI_FWH
<7,12,19,21,29> PCIRST# CLK_PCI_FWH <11>
C191 C211 C218 C207 @10K_0402 @10K_0402
RX1

1
.1UF .1UF .1UF .1UF RP25
2

2
C189 C190 5 4 FWH_GPI3 2 1 1 2
D RX2 D

1
IDE_PATA66DET @.1UF @.1UF 6 3 FWH_GPI2 R202 C177 @22PF

2
IDE_SATA66DET 7 2 FWH_GPI4 @33_0402
8 1

2
@8P4R-10K

32
31
30
4
3
2
1
R216 R208 @4.7K_0402 U19
@10K_0402 @10K_0402 R218 1 2

VPP
FGPI2
FGPI3

FGPI4
RY1

RST#

VCC
CLK
RY2 @10K_0402

1
IDE_SATA66DET 5 29 FWH_IC 2 1
IDE_PATA66DET 6 FGPI1 IC 28 R203
R220 1 2 @0_0402 FWP# 7 FGPI0 GNDA 27
WP# VCCA +3VS
<15> FWH_WPTBL# R224 1 2 @0_0402 TBL# 8 26
9 TBL# GND 25
1 2 10 ID3 VCC 24
R227 @4.7K_0402 11 ID2 INIT# 23 LFRAME#
ID1 FWH4 LFRAME# <15,21>
12 22
LAD0 13 ID0 RFU22 21
<15,21> LAD0 FWH0 RFU21

RFU18
RFU19
RFU20
+CPU_IO

FWH1
FWH2

FWH3
GND

1
+3VS

ICH-2M

14
15
16
17
18
19
20
@FWH-PLCC R236

1
@1.5K
AD[0..31] LAD1 R222
<19,29> AD[0..31] <15,21> LAD1

22
@10K_0402
U10A (FW82801BAM) LAD2

B
C <15,21> LAD2 C

E
AD0 AA4 D11 A20M# LAD3 1 3
AD0 A20M# A20M# <4> <15,21> LAD3 INIT# <4>
AD1 AB4 A12 Q29 @3904
AD2 Y4 AD1 CPUSLP# R22 FERR#
AD2 FERR# FERR# <4>
AD3 W5 A11 IGNNE#
AD3 IGNNE# IGNNE# <4>
AD4 W4 C12 INIT#
AD4 INIT# INIT# <4>
AD5 Y5 C11 INTR
AD6 AB3 AD5 CPU INTR B11 NMI
INTR <4>
NMI <4>
AD7 AA5 AD6 NMI B12 SMI#
AD8 AB5 AD7 SMI# C10 STPCLK#
SMI# <4> ATA Mode Stuff
AD8 STPCLK# STPCLK# <4>
AD9 Y3 B13 KBRST#
AD9 RCIN# KBRST# <22>
AD10 W6 C13 GATEA20
AD11 W3 AD10 A20GATE A13 CPU_PWRGD
GATEA20 <22> ATA33 RX
AD11 CPUPWRGD CPU_PWRGD <4>
AD12 Y6
AD13 Y2 AD12
AD14 AA6 AD13 A4 HL0 HL[0..10]
ATA66 RY
AD14 HL0 HL[0..10] <7>
AD15 Y1 B5 HL1
AD16 V2 AD15 HL1 A5 HL2
AD17 AA8 AD16 HL2 B6 HL3
Default None; Driver side
AD18 V1 AD17 HL3 B7 HL4
detection
AD19 AD18 HL4 HL5 +1_8VS
AB8 A8
AD20 U4 AD19 HL5 B8 HL6
AD21 W9 AD20 HUB HL6 A9 HL7
AD22 U3 AD21 HL7 C8 HL8
AD23 Y9 AD22 HL8 C6 HL9

1
AD24 U2 AD23 HL9 C7 HL10
AD25 AB9 AD24 PCI HL10 C5 HL11 R340 1 2 @10K_0402
+1_8VS
R113
AD26 U1 AD25 HL11 A6 HL_STB 300_1%
AD26 HL_STB HL_STB <7> +3VS
AD27 W10 A7 HL_STB#
AD27 HL_STB# HL_STB# <7>
B AD28 T4 A3 +ICH_HLCOMP 1 2 RP36 B
AD28 HLCOMP +1_8VS

2
AD29 Y10 B4 R115 36.5_1% +HUBREF_ICH 1 8 GPI2
AD30 T3 AD29 HUBREF 2 7 BD_ID0

1
AD31 AA10 AD30 C121 3 6 BD_ID1

2
AD31 P1 PIRQA# R114 C122 4 5 GPI5
PIRQA# PIRQA# <16,19> +3VS
AA3 P2 PIRQB# .01UF 300_1% .1UF
<19,29> C/BE#0 C/BE0# PIRQB# PIRQB# <16,29>

2
AB6 P3 PIRQC# 8P4R-100K
<19,29> C/BE#1 C/BE1# IRQ PIRQC# PIRQC# <16,19>

1
Y8 N4 PIRQD#
+3VS <19,29> C/BE#2 C/BE2# PIRQD# PIRQD# <16,29>

2
AA9 R339 1 2 10K_0402
<19,29> C/BE#3 C/BE3# R338 1 2 10K_0402
R352 1 2 8.2K_0402 AB7 F21
<16,19,29> DEVSEL# DEVSEL# IRQ14 IRQ14 <17>
R355 1 2 8.2K_0402 V3 C16 1 2 BD_ID1
<16,19,29> FRAME# FRAME# IRQ15 IRQ15 <17>
R345 1 2 8.2K_0402 W8 N20 R413 @10K_0402
<16,19,29> IRDY# IRDY# APICCLK CLK_APIC_ICH <11>
V4 P22 1 2 BD_ID0
<16,19,29> TRDY# TRDY# APICD0 PICD0 <4>
W1 N19 R415 @10K_0402
<16,19,29> STOP# STOP# APICD1 PICD1 <4>
W2 N21 SIRQ
<19,29> PAR PAR SERIRQ SIRQ <16,19,21>
AA15 2 1
<7,12,19,21,29> PCIRST# PCIRST#
AA7 N3 GPI2 R350 @0_0402
<16,19> PLOCK#
<16,19,29> SERR#
W7 PLOCK# GPIO2/PIRQE# N2 BD_ID0 2 1 11: SigmaTel ST9700
SERR# GPIO3/PIRQF#
PME# has internal PU <16,19,29> PERR#
Y7
Y15 PERR# GPIO4/PIRQG#
N1
M4
BD_ID1
GPI5
R354
1
@0_0402
2
01: AD1881A
PME# GPIO5/PIRQH#
REQA#
REQA# M3
GPIO0/REQA# PIN N3, M4 can not use GPIO. R356 @0_0402
GNTA# L2 1 2 1 2
GNTA# GPIO16/GNTA# R353 0_0402 C454 10PF
W11 M2 GNT#0
<11> CLK_PCI_ICH PCICLK GNT0# GNT#0 <16>
M1 GNT#1
GNT1# GNT#1 <16,29>
1 2 1 2 REQ#0 R2 R4 GNT#2
<16> REQ#0 REQ0# GNT2# GNT#2 <16,29> +3VS
C457 R361 @33_0402 REQ#1 R3 T2 GNT#3
<16,29> REQ#1 REQ1# GNT3# GNT#3 <16,19>
@22PF REQ#2 T1 R1 GNT#4
<16,29> REQ#2 REQ2# GNT4# GNT#4 <16>
A REQ#3 AB10 L4 1 2 A
<16,19> REQ#3 REQ3# GPIO17/GNTB#/GNT5#
REQ#4 P4 R349 8.2K_0402
<16> REQ#4 REQ4# MODRST# <17>
L3
1 2 GPIO1/REQB#/REQ5#
<29> MPCIACT#
R384 0_0402 ICH-2M
1

R348 Compal Electronics,Inc.


@1K_0402
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
ICH2-m-A (FW82801BAM) & FWH
GNTA# Strapping for "A16 swap override" : "0" -> Enable
2

A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 14 of 42
5 4 3 2 1
5 4 3 2 1

+3VALW

1
R363

10K_0402
U10B

2
THRM# AA13 U20 R359 1 2 0_0402
D +3VS <22> THRM# THRM# BATLOW# BATTLOW# <23> D
SLP_S1# D14 B14 R117 1 2 0_0402
<11,22> SLP_S1# SLP_S1# CPUPERF# I S T_CPU_PERF# <5>
SLP_S3# W16 A14
<22> SLP_S3# SLP_S3# SSMUXSEL# VR_HI/LO# <4,30>
SLP_S5# AB18 B15
<22> SLP_S5# V_GATE <30>

2
SYS_PWROK R20 SLP_S5# VGATE/VRMPWRGD
<16,25> SYS_PWROK PWROK
R151 W21 P20
+RTCVCC <23> PWRBTN_OUT# PWRBTN# CLK48 CLK_USB_ICH <11>
10K_0402 AA17 M19
<23> SWI# RI# CLK14 CLK_14M_ICH <11>
RSMRST# R21 D4
<25> RSMRST# RSMRST# CLK66 CLK_HUB_ICH <11>
W15
<14> FWH_WPTBL# GPIO25

1
AA18 F20 PDA0
<19,20> RTCCLK SUSCLK PDA0 PDA0 <17>
Y11 F19 PDA1
<9> A G P_BUSY# SYSTEM PDA1 <17>

1
A15 AGPBUSY# PDA1 E22 PDA2
<11> PCI_STP# STP_PCI# PDA2 PDA2 <17>
R161 C14 E21 PDCS1# R358 R357 R344
<11> CPU_STP# STP_CPU# PDCS1# PDCS1# <17>
1 2 V21 E19 PDCS3# @33_0402 @33_0402 @33_0402
<16,19,21,29> CLKRUN# CLKRUN# PDCS3# PDCS3# <17>
Y17
R286 J5 <21> SUS_STAT# SUSSTAT#
15K 1 2 T19 G22 PDDREQ
+RTCVCC INTRUDER# PDREQ PDDREQ <17>

2
1 2 2 1 R160 10K_0402 F22 PDDACK#
PDDACK# <17>
1

C149 AA16 PDDACK# G19 PDIOR#


+3VALW <11> SMB_ICH_DAT SMBDATA PDIOR# PDIOR# <17>
1K_0402 JOPEN AB16 G21 PDIOW#
<11> SMB_ICH_CLK PDIOW# <17>

1
1UF 10K_0402 1 2 0_0402 AB17 SMBCLK PDIOW# G20 PDIORDY C456 C455 C453
<22,31> ACIN SMLINK0 SMBALERT#/GPIO11 PIORDY PDIORDY <17>
2

R360 1 2 R364 U19


1 2 SMLINK1 V20 SMLINK0 H19 PDD0 @10PF @10PF @10PF
SMLINK1 PDD0

2
R147 10K_0402 H22 PDD1
R162 +RTCRST# T20 PDD1 J19 PDD2
1 2 +R_VBAIS 1 2 +VBIAS T21 RTCRST# PDD2 J22 PDD3
RTCX1 U22 VBIAS PDD3 K21 PDD4
1K_0402 C153 RTCX2 T22 RTCX1 PDD4 L20 PDD5
R156 RTCX2 PDD5
.047UF 1 2 AC_SDOUT Strapping: "1" -> Safe Mode Boot M21 PDD6
R163
10M
+3VS
R143 1 2 @10K_0402 IDE PDD6 M22 PDD7
1 2 X1 V22 PDD7 L22 PDD8 PDD[0..15]
C <27,29> AC97_RST# AC_RST# PDD8 PDD[0..15] <17> C
ICH_AC_SYNC P19 L21 PDD9
10M IAC_BITCLK R19 AC_SYNC AC97 PDD9 K22 PDD10
<27,29> IAC_BITCLK AC_BIT_CLK PDD10
32.768KHZ ICH_AC_SDOUT P21 K20 PDD11
1

C146 C147 SDATA_IN0 Y22 AC_SDOUT PDD11 J21 PDD12


<27> SDATA_IN0 AC_SDIN0 PDD12
SDATA_IN1 W22 J20 PDD13
<29> SDATA_IN1 AC_SDIN1 PDD13
12PF 12PF SPKR N22 H21 PDD14
<28> SPKR SPKR PDD14
2

H20 PDD15
Y14 PDD15
<21,22> EC_SMI# GPIO8
DSCACHE# AA11 A16 SDA0
<13> DSCACHE#
<22> SCI#
W14 GPIO7 GPIO SDA0 D16 SDA1
SDA0 <17>
SDA1 <17>
LID_OUT# GPIO12 SDA1 SDA2
<23> LID_OUT# AB15 B16 SDA2 <17>
1 2 L1 GPIO13 SDA2 C15 SDCS1#
<17> PIDERST# C3_STAT#/GPIO21 SDCS1# SDCS1# <17>
R140 0_0402 AB14 D15 SDCS3#
<11> SEL_DIMM0 GPIO27 SDCS3# SDCS3# <17>
AA14
+3VS <11> SEL_DIMM1 GPIO28 B18 SDDREQ
SDDREQ SDDREQ <17>
LAD0 Y12 B17 SDDACK#
<14,21> LAD0 LAD0/FWH0 SDDACK# SDDACK# <17>
DSCACHE# 1 2 LAD1 W12 D17 SDIOR#
R153 10K_0402
<14,21> LAD1
<14,21> LAD2
LAD2 AB13 LAD1/FWH1 LPC SDIOR# C17 SDIOW#
SDIOR# <17>
SDIOW# <17>
LID_OUT# 1 2 LAD3 AB12 LAD2/FWH2 SDIOW# A17 SDIORDY
<14,21> LAD3 LAD3/FWH3 SIORDY SDIORDY <17>
R155 10K_0402 LDRQ#0 Y13
<21> LDRQ#0 LDRQ0#
IAC_BITCLK 1 2 1 2 LDRQ1# W13 D18 SDD0
+3VS LDRQ1# SDD0
R127 10K_0402 R369 @10K_0402 LFRAME# AB11 B19 SDD1
<14,21> LFRAME# LFRAME#/FWH4 SDD1
SDATA_IN0 1 2 1 2 AA12 D19 SDD2
R368 10K_0402 R158 @10K_0402 FSO SDD2 A20 SDD3
SDATA_IN1 1 2 USBP0+ W17 SDD3 C20 SDD4
R366 10K_0402 USBP0- Y18 USBP0+ SDD4 C21 SDD5
SPKR 1 2 USBP1+ AB19 USBP0- SDD5 D22 SDD6
R141 @1K_0402 USBP1- AA19 USBP1+ SDD6 E20 SDD7
USBP2+ W18 USBP1- SDD7 D21 SDD8
B USBP2- Y19 USBP2+ USB SDD8 C22 SDD9 B
USBP3+ USBP2- SDD9 SDD10
AB20 D20
USBP3- AA20 USBP3+ SDD10 B20 SDD11
USBP3- SDD11
SPKR Strapping: "0" -> No Reboot SDD12
C19 SDD12
W19 A19 SDD13
+3V <18> OVCUR#0 OC0# SDD13
Y20 C18 SDD14
<16> OVCUR#1 OC1# SDD14
Y21 A18 SDD15 SDD[0..15]
<18> OVCUR#2 OC2# SDD15 SDD[0..15] <17>
1 2 OVCUR#3 W20
R365 10K_0402 OC3#
ICH-2M
1 2 ICH_AC_SYNC
<27,29> IAC_SYNC
R427 22_0402
1 2 ICH_AC_SDOUT
<27,29> IAC_SDATAO
R428 22_0402
1 2
1

C485 C486 RP19 C152 5PF


USBP3+ USBP2+ 1 8
27PF 27PF USBP3- USBP2- 2 7 USB2_D+ <18>
USB2_D- <18>
2

USBP1+ USBP0+ 3 6
USBP1- USBP0- 4 5 USB0_D+ <18>
USB0_D- <18>
4
3
2
1

8
7
6
5

4
3
2
1
8P4R-15 1 2
RP20 CP7 RP22 C151 5PF
Placement close to ICH2-M (U10) 8P4R-15K 8P4C-33PF 8P4R-15K

Modify on ST 11/3/2000
5
6
7
8

1
2
3
4

5
6
7
8

A A
CLOSE TO ICH2-M(< 1 inch)

Compal Electronics,Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ICH2-m-B (FW82801BAM)
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 15 of 42
5 4 3 2 1
5 4 3 2 1

PCI +3VS
+1_8VS
U10C
RP18
1 10 D10 E14
<14,19,29> PERR# +3VS VCC1_8_1 VCC3_3_1
2 9 E5 E15
<15> OVCUR#1 3 8 PIRQA# <14,19> K19 VCC1_8_2 VCC3_3_2 E16
<14,19,29> STOP# 4 7 PIRQB# <14,29> L19 VCC1_8_3 VCC3_3_3 E17
<14,19,29> SERR# REQ#4 <14> VCC1_8_4 VCC3_3_4
5 6 P5 E18
+3VS GNT#4 <14> VCC1_8_5 VCC3_3_5
D V9 F18 D
10P8R-8.2K VCC1_8_6 VCC3_3_6 G18
VCC3_3_7 H18
A1 VCC3_3_8 J18
A2 GND1 VCC3_3_9 P18
RP21 A10 GND2 VCC3_3_10 R18
1 10 B1 GND3 VCC3_3_11 R5 +3VS +5VS
<14,19,29> IRDY# +3VS GND4 VCC3_3_12
2 9 B2 T5
<14,19,29> TRDY# 3 8 PIRQC# <14,19> B3 GND5 VCC3_3_13 U5

1
<14,19,29> DEVSEL# 4 7 PIRQD# <14,29> B9 GND6 VCC3_3_14 V5
<14,19,29> FRAME# SIRQ <14,19,21> GND7 VCC3_3_15 R118
5 6 B10 V6
PLOCK# <14,19> GND8 VCC3_3_16
+3VS C2 V7 D4 1K_0402
10P8R-8.2K C3 GND9 VCC3_3_17 V8 1SS355
C4 GND10 VCC3_3_18
GND11

2
C9 K2 +VCC5REF
D5 GND12 V5REF1 M20

1
RP37 D6 GND13 V5REF2 C134

1
REQ#0 1 10 D7 GND14 V14 C125
<14> REQ#0 +3VS GND15 VCCSUS1_8_1 +1_8VALW
REQ#1 2 9 GNT#0 D8 V15 .1UF
<14,29> REQ#1 GNT#0 <14> GND16 VCCSUS1_8_2

2
REQ#2 3 8 GNT#1 D9 V16 1UF
<14,29> REQ#2 GNT#1 <14,29> GND17 VCCSUS1_8_3

2
REQ#3 4 7 GNT#2 E6
<14,19> REQ#3 GNT#2 <14,29> GND18
5 6 GNT#3 E7 T18
+3VS GNT#3 <14,19> GND19 VCCSUS3_3_1 +3VALW
E8 U18
10P8R-8.2K E9 GND20 VCCSUS3_3_2 H5 1 2
GND21 VCCLAN1_8_1 +1_8VALW
J10 J5 R367 0_0402
J11 GND22 VCCLAN1_8_2
J12 GND23 F5 1 2
GND24 VCCLAN3_3_1 +3VALW
J13 G5 R145 0_0402
J14 GND25 VCCLAN3_3_2
J9 GND26 V17
C GND27 VCCSUS3_3_3 +CPU_IO C
K10 V18
K11 GND28 VCCSUS3_3_4
K12 GND29 D12
K13 GND30 V_CPU_IO_1 D13 +1_8VS
K14 GND31 V_CPU_IO_2
K9 GND32 D2
L10 GND33 VCC1_8_7
L11 GND34 U21 1 2
GND35 VCCRTC +RTCVCC
L12 1K_0402 R159
L13 GND36 V19
GND37 V5REF_SUS +3VALW
L14 1 2
L9 GND38 C150 .1UF
M10 GND39
M11 GND40 EEPROM K4
LAN_EECS <29>
M12 GND41 EE_CS J3
+3VS GND42 EE_SHCLK LAN_EECLK <29>
M13 J4
GND43 EE_DOUT LAN_EEDO <29>
M14 K3
GND44 EE_DIN LAN_EEDI <29>
R148 10K_0402 M9
1 2 N10 GND45 1 2
CLKRUN# <15,19,21,29> +3VS N11 GND46
GND47
LAN R347 @10K_0402
N12
P9 GND48 G3
GND49 LAN_CLK LAN_PHYCLK <29>
P14 G2
GND50 LAN_RXD0 LAN_RXD0 <29>
P13 G1
GND51 LAN_RXD1 LAN_RXD1 <29>
P12 H1
GND52 LAN_RXD2 LAN_RXD2 <29>
P11 F3
LAN_TXD0 <29>
1

C466 P10 GND53 LAN_TXD0 F2


LAN_TXD1 <29>
1

+ C463 C462 C446 C447 C470 C448 C443 C449 N9 GND54 LAN_TXD1 F1
GND55 LAN_TXD2 LAN_TXD2 <29>
N14 H2
GND56 LAN_RSTSYNC LAN_PHYRST <29>
B 4.7UF_10V_0805 .1UF .1UF .1UF .1UF .1UF .1UF 1000PF 1000PF N13 Y16 R146 1 2 B
GND57 LAN_PWROK SYS_PWROK <15,25>
2

A21
A22 GND58 0_0402
B21 GND59
B22 GND60
+1_8VS AA1 GND61
AA2 GND62
AA21 GND63
AA22 GND64
AB1 GND65
AB2 GND66
GND67
1

C135 C452 C461 C458 C116 C450 C139 AB21


+ AB22 GND68
.1UF .1UF .1UF .1UF 1000PF 1000PF K1 GND69
GND70
2

10UF_10V_1206 D3
GND71
2

C467 ICH-2M
10UF_10V_1206

+1_8VALW +3VALW +CPU_IO


1

C464 C465
C460 C459 C115
A .1UF .1UF .1UF .1UF .1UF A
2

Compal Electronics,Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ICH2-m-C (FW82801BAM)
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 16 of 42
5 4 3 2 1
1 2 3 4 5 6 7 8

IDE,CD-ROM & FDD Module CONN.


+5VS
+5VS

PDD[0..15] +5VS
<15> PDD[0..15]

1
JP13 +5VS
PIDERST# R342 R343 R346
<15> PIDERST# 1 2
PDD7 PDD8 100K_0402 100K_0402 100K_0402

3
PDD6 3 4 PDD9
PDD5 5 6 PDD10 Q43
D14

5
7 8 E

2
PDD4 PDD11 HDD_LED# 1 U30 47K DTA114YKA
PDD3 9 10 PDD12 B
A 3 1 A
PDD2 11 12 PDD13 SIDEACT# 2 4 ACTLED# 2
PDD1 13 14 PDD14 2 10K
PDD0 15 16 PDD15 RB717F C
17 18 TC7S08F
19 20

3
PDDREQ DRV0#
<15> PDDREQ 21 22

1
PDIOW#
<15> PDIOW# 23 24 MASTER
PDIOR#
<15> PDIOR# 25 26
PDIORDY PCSEL 1 2 1 2
<15> PDIORDY 27 28 ACTLED <18>
RPDDACK# R362 470 R173 470
RIRQ14 29 30
PDA1 31 32 ATA66S/PDIAG# +5VS +5VS
<15> PDA1 33 34
PDA0 PDA2
<15> PDA0 35 36 PDA2 <15>
PDCS1# PDCS3#
<15> PDCS1# PDCS3# <15>

2
HDD_LED# 37 38
39 40 R336 R335
41 42 +5VS +3VALW 10K_0402 10K_0402
43 44
HDD 44P
+5VS

1
IDE_CSEL_M# IDE_CSEL_S
HDD 14
U29D
74LVC14 D D

1
9 8 2 Q42 2 Q41
<22> S I DE_CS_M#/S G G
2N7002 2N7002
JP8 S S

3
<27> INT_CD_L 1 2 INT_CD_R <27>
1 2 1 2
<27> INT_CD_GND 3 4
MODRST# SDD8 R334 470 R337 470
SDD7 5 6 SDD9
B SDD6 7 8 SDD10 B

SDD5 9 10 SDD11
SDD4 11 12 SDD12
SDD3 13 14 SDD13
SDD2 15 16 SDD14
SDD1 17 18 SDD15
SDD0 19 20 SDDREQ
21 22 SDIOR#
SDIOW# 23 24 PDDACK# 1 2 RPDDACK# +5VS
25 26 <15> PDDACK#
SDIORDY SDDACK# R144 22_0402
RIRQ15 27 28 IRQ14
<14> IRQ14 1 2 RIRQ14
SDA1 29 30 CD_PDIAG 1 2 A T A66P/PDIAG R142 22_0402
SDA0 31 32 SDA2 R31 0 PDDREQ 1 2

1
SDCS1# 33 34 SDCS3# R149 @5.6K_0402 C441 C440 C502
SIDEACT# 35 36 1 2
37 38 +5VS
C143 33PF 4.7UF_10V_0805 .1UF 22UF_10V_1206
+5VS 39 40

2
PDD7 2 1
41 42 R150 @10K_0402
43 44
IDE_CSEL_M# 45 46
47 48 +5VS
49 50
HEADER 2X25 PDIORDY 1 2
HDD CAP.
R351 1K_0402

CDROM/DVD
RP17
WRDATA# 1 10
+5VS
WGATE# 2 9 STEP#
C H1SEL# 3 8 MTR0# C
DIR# 4 7 DRV0# +5VS
+5VSMOD 5 6 RDATA#
+5VS
SDD[0..15]
<15> SDD[0..15] JP11 10P8R-1K

1
MOD_CD_R 1 2 MOD_CD_L C43
<27> MOD_CD_R 1 2 MOD_CD_L <27> +5VS +5VS
H1SEL# 3 4 WGATE# Q40 +5VSMOD C49
<21> H1SEL# 3 4 WGATE# <21> .1UF
RDATA# 5 6 SI3456DV RP16 10UF_10V_1206
<21> RDATA# 5 6 CD/FDD# <23>

2
7 8 6 DISKCHG# 1 8
<15> SDCS3# 7 8 SDA0 <15>
WRPRT# 9 10 5 4 INDEX# 2 7
<21> WRPRT# 9 10
11 12 2 WRPRT# 3 6
<15> SDIOW# 11 12 INT_CD_GND <27>
SDD15 13 14 SDD1 1 TRK0# 4 5
SDD12 15 13 14 16 SDD4
SDD9 17 15
17
16
18
18 SDD7
+12VALW
8P4R-1K CDROM/DVD CAP.
3

19 20
DISKCHG# 21 19 20 22 MTR0# R341
<21> DISKCHG# 21 22 MTR0# <21>
WRDATA# 23 24 STEP# 2 1
<21> WRDATA# 23 24 STEP# <21>
25 26
<21> INDEX# 25 26 +5VSMOD
27 28 100K_0402 SDDACK# 1 2 RSDDACK#
<15> SDCS1# 27 28 <15> SDDACK#
RIRQ15 29 30 SDIORDY R131 22_0402
29 30 SDIORDY <15>
31 32 SDDREQ IRQ15 1 2 RIRQ15
31 32 SDDREQ <15> D <14> IRQ15
1

SDD0 33 34 SDD13 R129 22_0402


1

1
SDD3 35 33 34 36 SDD10 2 SDDREQ 1 2 C442
<22> MODEN#

1
SDD6 37 35 36 38 G C445 R132 @5.6K_0402
39 37 38 40 Q44 S .01UF 1 2 10UF_10V_1206 C444
39 40 .1UF
3

2
TRK0# 41 42 DRV0# 2N7002 C117 33PF
<21> TRK0# 41 42 DRV0# <21>

2
43 44 DIR# SDD7 1 2
<21> 1.6M_EN# 43 44 DIR# <21>
MODPRES# 45 46 SIDEACT# R133 @10K_0402
<23> MODPRES# 45 46
47 48
<15> SDA2 47 48 SDA1 <15>
D RSDDACK# 49 50 A T A66P/PDIAG D

<15> SDIOR#
SDD14
51
53
49
51
50
52
52
54
IDE_CSEL_S
SDD2
SI3456DV: NCHANNEL +5VS SECOND MODULE CAP.
SDD11 55 53 54 56 SDD5
VGS: 4.5V, RDS: 65mOHM SDIORDY 2 1
SDD8 57 55 56 58 MODRST# Id(MAX): 5.1A R130 1K_0402
57 58 MODRST# <14>
59 60
59 60

COMBO-60P
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
MODULE A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IDE/FDD MODULE
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
FDD/CDROM/DVD U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board 2.0

Date: T h ursday, January 11, 2001 Sheet 17 of 42


1 2 3 4 5 6 7 8
A B C D E

+3VS
USB&LED INTERFACE
+3VALW

1
R385 R386

3
USB_AS USB_BS 100K_0402 100K_0402
Q20
E
47K DTA114YKA
+5VS B

2
4 U33 4
1 8 1 2 2
GND OC1# OVCUR#0 <15> <23> PWR_LED#
2 7 R388 47K_0402 10K
3 IN OUT1 6 C
4 EN1# OUT2 5 1 2
EN2# OC2# OVCUR#2 <15>
R389 47K_0402

1
TPS2042 C479 C480

.1UF .1UF 1 2 PWR_LED

2
R174 470

USB_AS USB_A USB_B USB_BS


L11 L9
1 2 1 2 +3VALW 1 2
FBM-11-451616-800A FBM-11-451616-800A C17 22PF
JP6

<23> BAT1_LED# 2 1 INT_MIC <28>


C170 C9
<23> BAT2_LED#
1

1
+ C20 + C15 4 3
6 5 VDDA
150UF_E_10V .1UF 150UF_E_10V .1UF 8 7
10 9 ON/OFFBTN <25>
2

2
<17> ACTLED 12 11
PWR_LED
14 13 KSO17 <22>
<22> CAP_LED# 16 15 KSI0 <22,23>
3 <22> NUM_LED# 18 17 KSI1 <22,23> 3
JP5
<22> SRL_LED# 20 19 KSI2 <22,23>
1 5
VCC VCC 22 21 KSI3 <22,23>
0 1 2 R14 USB0_DD- 2 6 USB2_DD- 0 1 2 R15
<15> USB0_D- D0- D1- USB2_D- <15> 24 23 KSI4 <22,23>
0 1 2 R13 USB0_DD+ 3 7 USB2_DD+ 0 1 2 R12
<15> USB0_D+ D0+ D1+ USB2_D+ <15> 26 25 KSI5 <22,23>
GND_USBA 4 8 GND_USBB
VSS VSS 28 27
1

1
30 29 +5VS +5V
1

L13 C19 11 9 32 31

1
12 G3 G1 10 C18 L12 +3VS 34 33
FBM-11-451616-800A .1UF G4 G2 FBM-11-451616-800A 36 35
38 37
2

Molex-67300 .1UF
40 39
2

2
SWITCH_CONN

PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 FD5 FD2 FD6 FD1 FD4 FD3 CFD12 CFD14 CFD1 CFD2 CFD3 CFD8 CFD11 CFD6 CFD10 CFD13 CFD5 CFD9 CFD4 CFD7
2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL
1

1
CFD15 CFD16
2 M17 M18 M19 M20 M21 M22 M2 M3 M7 M6 M4 FIDUCIAL FIDUCIAL 2
PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 NON-PDH NON-PDH NON-PDH NON-PDH NON-PDH NON-PDH PDH PDH PDH PDH PDH
2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD O211X67D211X67N O211X67D211X67N O211X67D211X67N O211X67D211X67N O177X98D177X98N O177X98D177X98N C276D169 C276D169 C276D169 C276D169 C276D128

1
1

1
M15 M10 M9 M23 M1 M5 M8 M16
PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 S T A NDOFF_SUPPORT_TB S T A N DOFF_SUPPORT_KB S T D F _SUPPORT_VGA_CACHE S T D F_SUPPORT_VGA_CACHE PDH PDH PDH PDH
2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD C315D177 C315D177 C315D177 C315D177 C276D128 C295D147 T394B295D128 T394B304D128
1

1
PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PAD32 M11 M12 GND5 GND6 GND7 GND8 GND9 GND1 GND2 GND3 GND4 GND10 GND11 GND12
2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD 2.2x3 PAD PDH PDH PDH PDH PDH PDH PDH PDH PDH PDH PDH PDH PDH PDH
C236D118 C276D128 SMD197X225 SMD197X197 SMD197X197 SMD197X197 SMD197X197 SMD197 SMD197 SMD197 SMD197 SMD197X225 SMDO280X118 SMDO280X118
1

1
1 1
PAD33 PAD34 PAD35 PAD36 PAD37 PAD38
CLIP CLIP CLIP CLIP CLIP 5x5 PAD
SMD87X134 SMD87X134 SMD87X134 SMD87X134 SMD87X134 SMD197X197

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
USB & FRONT PANEL I/F
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 18 of 42
A B C D E
8 7 6 5 4 3 2 1

S1_IOWR#
S1_IOWR# <20>
S1_A[0..25] S1_IORD#
S1_A[0..25] <20> S1_IORD# <20>
S1_OE#
S1_OE# <20>
S1_D[0..15] S1_CE2#
S1_D[0..15] <20> S1_CE2# <20>

+3VALW +3VS +3VS

PCMRST# <20,22>

S1_IOWR#

S1_IORD#

S1_CE2#
S1_D10

S1_D15

S1_D13

S1_D12

S1_D11
S1_OE#
S1_A25

S1_A24
S1_A17

S1_A11

S1_A10
S1_D9
S1_D1
S1_D8
S1_D0

S1_D7

S1_D6

S1_D5

S1_D4
S1_D3
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6

S1_A7

S1_A9
D D
S1_VCC

127

134
180

124
122
121
120
119
116
113
111
109
107
105
103
102
100
U24

21
37
50

79

99
83
81
80
78
77
75
74
73
71
68
67
66
65
64
63
62
59
6
C239 C368 C351

A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20

A_A7/CAD18

A_A9/CAD14

A_A10/CAD9
AUX_VCC

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

A_A25/CAD19

A_A24/CAD17
A_A17/CAD16

A_A11/CAD12
A_OE#/CAD11
A_IOWR/CAD15

A_IORD#/CAD13

A_CE2#/CAD10

A_D7/CAD7

A_D6/CAD5

A_D5/CAD3

A_D4/CAD1
A_D3/CAD0
A_D10/CAD31
A_D9/CAD30
A_D1/CAD29
A_D8/CAD28
A_D0/CAD27

A_D15/CAD8

A_D13/CAD6

A_D12/CAD4

A_D11/CAD2
CORE_VCC
CORE_VCC
CORE_VCC
117
AD31 4 GRST# 98 .1UF .1UF .1UF
AD30 5 AD31 A_SKT_VCC 60
AD29 AD30 A_SKT_VCC
7
AD28 8 AD29 112
AD28 A_REG#/CCBE3# S1_REG# <20>
AD27 9 97 S1_A12
AD26 10 AD27 A_A12/CCBE2# 82 S1_A8
AD25 11 AD26 A_A8/CCBE1# 70
AD25 A_CE1#/CCBE0# S1_CE1# <20>
AD24 12
AD23 16 AD24 93 R2481 332 S1_A16
AD22 17 AD23 A_A16/CCLK 96 S1_A23
AD21 18 AD22 A_A23/CFRAME# 95 S1_A15
AD20 19 AD21 A_A15/CIRDY# 94 S1_A22
AD19 AD20 A_A22/CTRDY# S1_A21
20 92
AD18 22 AD19 A_A21/CDEVSEL# 90 S1_A20
AD17 23 AD18 A_A20/CSTOP# 84 S1_A13
AD16 24 AD17 A_A13/CPAR 86 S1_A14
AD16 A_A14/CPERR#

AD[0..31]
AD15
AD14
AD13
38
39
40
AD15
AD14
O 2 MICRO CORP. A_WAIT#/CSERR#
A_INPACK#/CREQ#
108
110
89
S1_WAIT# <20>
S1_INPACK# <20>
<14,29> AD[0..31] AD13 A_WE#/CGNT# S1_WE# <20>
AD12 41 91
AD11
AD10
42
43
AD12
AD11
CARDBUS CONTROLLER A_RDY_IRQ#/CINT#
A_A19/CBLOCK#
88
125
S1_A19 S1_RDY# <20>

C AD10 A_WP/CCLKRUN# S1_WP <20> C


AD9
AD8
AD7
45
46
48
AD9
AD8
OZ6933T (TQFP) A_RST/CRST#
A_R2_D2/RFU
106
123
69
S1_D2
S1_D14
S1_RST <20>

AD6 49 AD7 A_R2_D14/RFU 85 S1_A18


AD5 51 AD6 A_R2_A18/RFU 76
AD5 A_VS1/CVS1 S1_VS1 <20>
AD4 52 104
AD3 53 AD4 A_VS2/CVS2 61 S1_VS2 <20>
AD2 54 AD3 A_CD1#/CCD1# 126 S1_CD1# <20>
AD1 55 AD2 A_CD2#/CCD2# 114 S1_CD2# <20>
AD0 56 AD1 A_BVD2/CAUDIO 118 S1_BVD2 <20>
AD0 A_BVD1/CSTSCHG S1_BVD1 <20>
13 192
<14,29> C/BE#3 C/BE3# B_BVD1/CSTCHG S2_BVD1 <20>
CLK_PCI_PCM 25 190
<14,29> C/BE#2 C/BE2# B_BVD2/CAUDIO S2_BVD2 <20>
36 202
<14,29> C/BE#1 S2_CD2# <20>
2

47 C/BE1# B_CD2#/CCD2# 136


<14,29> C/BE#0 C/BE0# B_CD1#/CCD1# S2_CD1# <20>
R289 R287 100_0402 179
@33_0402 AD19 1 2 15 B_VS2/CVS2 152 S2_VS2 <20>
CLK_PCI_PCM 1 IDSEL B_VS1/CVS1 161 S2_A18 S2_VS1 <20>
<11> CLK_PCI_PCM PCI_CLK B_R2_A18/RFU
31 145 S2_D14
<14,16,29> DEVSEL# DEVSEL# B_R2_D14/RFU
1

27 198 S2_D2
<14,16,29> FRAME# FRAME# B_R2_D2/RFU
<14,16,29> IRDY# 29 182
IRDY# B_RST/CRST# S2_RST <20>
C384 30 201
<14,16,29> TRDY# TRDY# B_WP/CCLKRUN# S2_WP <20>
@10PF 32 164 S2_A19
<14,16,29> STOP# STOP# B_A19/CBLOCK#
35 167
<14,29> PAR PAR B_RDY_IRQ#/CINT# S2_RDY# <20>
33 165
<14,16,29> PERR# PERR# B_WE#/CGNT# S2_WE# <20>
34 186
<14,16,29> SERR# SERR# B_INPACK#/CREQ# S2_INPACK# <20>
3 184
<14,16> REQ#3 PCI_REQ# B_WAIT#/CSERR# S2_WAIT# <20>
2 162 S2_A14
<14,16> GNT#3 PCI_GNT# B_A14/CPERR#
203 159 S2_A13
<14,16> PIRQA# IRQ9/INTA# B_A13/CPAR
B 204 166 S2_A20 B
<14,16> PIRQC# IRQ4/INTB#/A_VPP_PGM B_A20/CSTOP#
58 168 S2_A21
<14,16> PLOCK# LOCK# B_A21/CDEVSEL#
207 170 S2_A22
<7,12,14,21,29> PCIRST# RST# B_A22/CTRDY# 171 S2_A15
163 B_A15/CIRDY# 172 S2_A23
<23> PCM_PME# IRQ12/PME# B_A23/CFRAME#
208 169 R2471 332 S2_A16
SLATCH/SMBCLK/B_VCC_5#

<15,16,21,29> CLKRUN# IRQ14/CLKRUN# B_A16/CCLK


72
<24> PCM_RI#
IRQ10/B_VPP_VCC_PGM

128 IRQ15/RI_OUT# 147


IRQ9/A_VPP_VCC_PGM

<28> PCM_SPK# SPKR_OUT# B_CE1#/CCBE0# S2_CE1# <20>


LEDO 133 157 S2_A8
IRQ11 193 LEDO#/SKTA_ACTV B_A8/CCBE1# 173 S2_A12
SDATA/B_VCC_3#

B_IOWR#/CAD15
IRQ11/SKTB_ACTV B_A12/CCBE2#
SCLK/A_VCC_5#

B_IORD#/CAD13
IRQ3/A_VCC_3#

188

B_CE2#/CAD10
B_REG#/CCBE3# S2_REG# <20>

B_OE#/CAD11
B_D10/CAD31

B_A25/CAD19

B_A24/CAD17
B_A17/CAD16

B_A11/CAD12
205
B_D9/CAD30
B_D1/CAD29
B_D8/CAD28
B_D0/CAD27

B_D15/CAD8

B_D13/CAD6

B_D12/CAD4

B_D11/CAD2
B_A0/CAD26
B_A1/CAD25
B_A2/CAD24
B_A3/CAD23
B_A4/CAD22
B_A5/CAD21
B_A6/CAD20

B_A7/CAD18

B_A9/CAD14

B_A10/CAD9
<14,16,21> SIRQ

B_D7/CAD7

B_D6/CAD5

B_D5/CAD3

B_D4/CAD1
B_D3/CAD0
IRQ7 206 IRQ5/SERIRQ# 143
IRQ7/SIN#/B_VPP_PGM B_SKT_VCC S2_VCC
160
B_SKT_VCC 200
GND
GND
GND
GND
GND
GND
GND
GND

B_SKT_VCC
101
129
177

132
131
130
115
146

199
197
196
195
194
191
189
187
185
183
181
178
176
175
174
158
156
155
154
153
151
150
149
148
144
142
141
140
139
138
137
135
OZ6933TQFP C223 C348 C360
14
26
28
44
57

87

.1UF .1UF .1UF


S2_IOWR#

S2_IORD#

S2_CE2#
S2_D10

S2_D15

S2_D13

S2_D12

S2_D11
S2_OE#
S2_A25

S2_A24
S2_A17

S2_A11

S2_A10
S2_D9
S2_D1
S2_D8
S2_D0

S2_D7

S2_D6

S2_D5

S2_D4
S2_D3
S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6

S2_A7

S2_A9

+3VS
1

C380 S2_A[0..25]
S2_A[0..25] <20>
C389 C387 C298
SLATCH <20>
4.7UF_10V_0805 S2_IOWR# S2_D[0..15]
.1UF .1UF .1UF SLDATA <20> S2_IOWR# <20> S2_D[0..15] <20>
2

S2_IORD#
RTCCLK <15,20> S2_IORD# <20>
S2_OE#
+3VALW S2_OE# <20>
A S2_CE2# A
S2_CE2# <20>
+3VS

C385 C224 C226 C225 C227


.1UF .1UF .1UF .1UF .1UF
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
O2Micro OZ6933 Cardbus Controller
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 19 of 42
8 7 6 5 4 3 2 1
PCMCIA POWER CTRL.
CARDBUS SOCKET
S1_VPP S1_A[0..25]
S1_VPP <19> S1_A[0..25]
S1_D[0..15]
<19> S1_D[0..15] S2_A[0..25]
+12VALW S1_VCC <19> S2_A[0..25]
U18 S2_D[0..15]
<19> S2_D[0..15]

1
C221
25 8
+5VALW VCC_5V AVPP 9 4.7UF_10V_0805
AVCC

2
7 10
1 2 C174 24 12V AVCC 11

2
1UF 12V AVCC J1
1 2 C214 1 23 S2_VPP C388 A1 B1 C390
5V BVPP S2_VPP A1 B1
.1UF 2 20 1000PF A2 B2 1000PF
+3VALW 5V BVCC A2 B2

1
1 2 C187 30 21 S1_D3 A3 B3 S2_D3
5V BVCC S2_VCC A3 B3
.1UF 22 S1_CD1# A4 B4 S2_CD1#
<19> S1_CD1# S2_CD1# <19>

1
1 2 C213 15 BVCC C175 S1_D4 A5 A4 B4 B5 S2_D4
.1UF 16 3.3V 6 S1_D11 A6 A5 B5 B6 S2_D11
1 2 C181 17 3.3V RESET 14 4.7UF_10V_0805 S1_D5 A7 A6 B6 B7 S2_D5
3.3V RESET# A7 B7

2
.1UF S1_D12 A8 B8 S2_D12
1 2 C215 3 26 A9 A8 B8 B9
<19> SLDATA DATA NC A9 B9
.1UF 5 27 S1_D6 A10 B10 S2_D6
<19> SLATCH LATCH NC A10 B10
1 2 C180 4 28 S1_D13 A11 B11 S2_D13
.1UF <15,19> RTCCLK CLOCK NC 29 S1_D7 A12 A11 B11 B12 S2_D7
NC PCMRST# <19,22> A12 B12
13 S1_D14 A13 B13 S2_D14
APWR_GOOD# S1_CE1# A13 B13 S2_CE1#
19 A14 B14
BPWR_GOOD# <19> S1_CE1# A14 B14 S2_CE1# <19>
18 12 S1_D15 A15 B15 S2_D15
OC# GND A16 A15 B15 B16
S1_A10 A17 A16 B16 B17 S2_A10
TPS2216 S1_CE2# A18 A17 B17 B18 S2_CE2#
<19> S1_CE2# A18 B18 S2_CE2# <19>
S1_OE# A19 B19 S2_OE#
<19> S1_OE# S1_VS1 A20 A19 B19 B20 S2_VS1 S2_OE# <19>
<19> S1_VS1 S1_A11 A21 A20 B20 B21 S2_A11 S2_VS1 <19>
A22 A21 B21 B22
S1_IORD# A23 A22 B22 B23 S2_IORD#
<19> S1_IORD# A23 B23 S2_IORD# <19>
S1_A9 A24 B24 S2_A9
S1_IOWR# A25 A24 B24 B25 S2_IOWR#
<19> S1_IOWR# A25 B25 S2_IOWR# <19>
S1_A8 A26 B26 S2_A8
S1_A17 A27 A26 B26 B27 S2_A17
A28 A27 B27 B28
S1_VPP A28 B28
S1_VCC S1_A13 A29 B29 S2_A13
1

C238 S1_A18 A30 A29 B29 B30 S2_A18


1

+ C234 C322 C347 S1_A14 A31 A30 B30 B31 S2_A14


.1UF 4.7UF_25V_1206 S1_A19 A32 A31 B31 B32 S2_A19
A32 B32
2

25V .1UF 10UF_10V_1206 S1_WE# A33 B33 S2_WE#


<19> S1_WE# A33 B33 S2_WE# <19>
2

S1_A20 A34 B34 S2_A20


S1_RDY# A35 A34 B34 B35 S2_RDY#
<19> S1_RDY# A35 B35 S2_RDY# <19>
S1_A21 A36 B36 S2_A21
S1_VCC A37 A36 B36 B37 S2_VCC
S1_VCC A37 B37 S2_VCC
S1_VCC A38 B38 S2_VCC
S1_VPP A39 A38 B38 B39 S2_VPP
S1_VPP A39 B39 S2_VPP
S1_VPP A40 B40 S2_VPP
S2_VPP S2_VCC A40 B40
S1_A16 A41 B41 S2_A16
1

C282 C288 C307 A42 A41 B41 B42


+ C264 S1_A22 A43 A42 B42 B43 S2_A22
.1UF 4.7UF_25V_1206 .1UF 10UF_10V_1206 S1_A15 A43 B43 S2_A15
A44 B44
A44 B44
2

25V S1_A23 A45 B45 S2_A23


S1_A12 A46 A45 B45 B46 S2_A12
S1_A24 A47 A46 B46 B47 S2_A24
S1_A7 A48 A47 B47 B48 S2_A7
A49 A48 B48 B49
S1_A25 A50 A49 B49 B50 S2_A25
S1_A6 A51 A50 B50 B51 S2_A6
S1_VS2 A52 A51 B51 B52 S2_VS2
<19> S1_VS2 A52 B52 S2_VS2 <19>
S1_A5 A53 B53 S2_A5
S2_WP S1_RST A53 B53 S2_RST
1 2 <19> S1_RST A54 B54
S2_VCC A54 B54 S2_RST <19>
R276 22K_0402 S1_A4 A55 B55 S2_A4
S2_A23 1 2 S1_WAIT# A56 A55 B55 B56 S2_WAIT#
S2_VCC <19> S1_WAIT# A56 B56 S2_WAIT# <19>
R252 22K_0402 A57 B57
S1_A3 A58 A57 B57 B58 S2_A3
S1_INPACK# A59 A58 B58 B59 S2_INPACK#
<19> S1_INPACK# A59 B59 S2_INPACK# <19>
S1_A2 A60 B60 S2_A2
S1_A23 1 2 S1_REG# A61 A60 B60 B61 S2_REG#
S1_VCC <19> S1_REG# S1_A1 A62 A61 B61 B62 S2_A1 S2_REG# <19>
R244 22K_0402 A62 B62
S1_WP 1 2 S1_BVD2 A63 B63 S2_BVD2
S1_VCC <19> S1_BVD2 A63 B63 S2_BVD2 <19>
R225 22K_0402 S1_A0 A64 B64 S2_A0
A65 A64 B64 B65
S1_BVD1 A66 A65 B65 B66 S2_BVD1
<19> S1_BVD1 A66 B66 S2_BVD1 <19>
S1_D0 A67 B67 S2_D0
S1_D8 A68 A67 B67 B68 S2_D8
S1_D1 A69 A68 B68 B69 S2_D1
S1_D9 A70 A69 B69 B70 S2_D9
S1_D2 A71 A70 B70 B71 S2_D2
S1_D10 A72 A71 B71 B72 S2_D10
A73 A72 B72 B73
S1_WP A73 B73 S2_WP
A74 B74
<19> S1_WP A74 B74 S2_WP <19>
S1_CD2# A75 B75 S2_CD2#
<19> S1_CD2# A75 B75 S2_CD2# <19>
A76 B76
A77 A76 B76 B77

1
A77 B77
C204 80 78 C203
1000PF 81 80 78 79 1000PF
81 79

2
P C MCIA CONN P154
J5
PCMCIA CONN P154
BERG62183-001T

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOXCONN Cardbus CONN .154PIN
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 20 of 42
5 4 3 2 1

+3VS

+3VS
+3VS

14
39
63
88
U11
1 2

1
C124 C112 C144 C148 R152 10K_0402

VDD
VDD
VDD
VDD
.1UF .1UF 1000PF 4.7UF_10V_0805 LAD0 15 52 LPD0
+3VS <14,15> LAD0 LAD0 PD0/INDEX# LPD0 <24>
2

2
LAD1 16 50 LPD1
<14,15> LAD1 LAD1 PD1/TRK0# LPD1 <24>
LAD2 17 48 LPD2
D <14,15> LAD2 LAD2 PD2/WP# LPD2 <24> D
LAD3 18 46 LPD3
<14,15> LAD3 LPD3 <24>

1
LAD3 PD3/RDATA# 45 LPD4
PD4/DSKCHG# LPD4 <24>
R137 CLK_PCI_SIO 8 44 LPD5
<11> CLK_PCI_SIO LCLK PD5/MSEN0 LPD5 <24>
4.7K_0402 PCIRST# 9 43 LPD6
<7,12,14,19,29> PCIRST# LRESET# PD6/DRATE0 LPD6 <24>
LFRAME# 12 42 LPD7
<14,15> LFRAME# LFRAME# PD7/MSEN1 LPD7 <24>
LDRQ#0 11
<15> LDRQ#0 LDRQ#
PC87393

2
7 35
<15> SUS_STAT# LPCPD# PNF/XRDY
CLKRUN# 6 36 LPTSLCT
<15,16,19,29> CLKRUN# CLKRUN#/GPIO36 SLCT/WGATE# LPTSLCT <24>
SIRQ 10 37 LPTPE
<14,16,19> SIRQ SERIRQ PE/WDATA# LPTPE <24>
<15,22> EC_SMI# 1 2 LPCSMI# 19 40 LPTBUSY
LPTBUSY <24>
R138 @0_0402 SMI#/GPIO35 BUSY_WAIT#/MTR1# 41 LPTACK#
ACK#/DR1# LPTACK# <24>
CLK_PCI_SIO CLK_14M_SIO CLK_14M_SIO 20 47 LPTSLCTIN#
<11> CLK_14M_SIO CLKIN SLIN#_ASTRB#/STEP# LPTSLCTIN# <24>
1 2 49 LPTINIT#
+3VS LPTINIT# <24>
1

R139 @10K_0402 INIT#/DIR# 51 LPTERR#


ERR#/HDSEL# LPTERR# <24>
R135 R136 DISKCHG# 21 53 LPTAFD#
<17> DISKCHG# DSKCHG# AFD#_DSTRB#/DENSEL LPTAFD# <24>
H1SEL# 22 54 LPTSTB#
<17> H1SEL# HDSEL# STB#_WRITE# LPTSTB# <24>
@33_0402 @33_0402 RDATA# 23
<17> RDATA# RDATA#
WRPRT# 24
<17> WRPRT# WP#
2

TRK0# 25 55 DCDA#
<17> TRK0# TRK0# DCD1# DCDA# <24>
WGATE# 26 56 DSRA#
<17> WGATE# DSRA# <24>
1

C133 C132 WRDATA# 27 WGATE# DSR1# 57 RXDA


<17> WRDATA# WDATA# SIN1 RXDA <24>
STEP# 28 58 RTSA#
<17> STEP# SETP# RTS1#/TEST RTSA# <24>
@15PF @15PF DIR# 29 59 TXDA
<17> DIR# DIR# SOUT1/XCNF0 TXDA <24>
2

DRV0# 30 60 CTSA#
<17> DRV0# DR0# CTS1# CTSA# <24>
MTR0# 31 61 DTRA#
<17> MTR0# MTR0# DTR1#_BOUT1/BADDR DTRA# <24>
+3VS INDEX# 32 62 RIA#
<17> INDEX# INDEX# RI1# RIA# <24>
1.6M_EN# 33
<17> 1.6M_EN# DENSEL
34
DRATE0/IRSL2 70
C IRTX C
69
5
6
7
8

XA0 95 IRRX1 68
<22> XA0 XA0/GPIO20 IRRX2_IRSL0
RP14 XA1 94 67
<22> XA1 XA1/GPIO21 IRSL1
8P4R-10K XA2 93 66
<22> XA2 XA2/GPIO22 IRSL3/PWUREQ#
XA3 92
<22> XA3 XA3/GPIO23
XSTB0# 91
<22> XSTB0# XA4/GPIO24/XSTB0#
4
3
2
1

XCNF2 90 3 XD0
XA5/XSTB1#/XCNF2 XD0/GPIO00/JOYABTN1 XD0 <22>
87 2 XD1
<22> IRQ1 XA6/GPIO26/PRIQA/XSTB2# XD1/GPIO01/JOYBBTN1 XD1 <22>
IRQ8 86 1 XD2
XA7/GPIO27/PIRQB XD2/GPIO02/JOYAY XD2 <22>
85 100 XD3
<22> IRQ11 XA8/GPIO30/PIRQC XD3/GPIO03/JOYBY XD3 <22>
84 99 XD4
<22> IRQ12 XA9/GPIO31/MTR1#/PIRQD XD4/GPIO04/JOYBX XD4 <22>
XIOR# 83 98 XD5
<22> XIOR# XA10/GPIO32/XIORD#/MDRX XD5/GPIO05/JOYAX XD5 <22>
XIOW# 82 97 XD6
<22> XIOW# XA11/GPIO33/XIOWR#/MDTX XD6/GPIO06/JOYBBTN0 XD6 <22>
XA12 81 96 XD7
<22> XA12 XA12/GPIO10/JOYABTN1/RI2# XD7/GPIO07/JOYABTN0 XD7 <22>
XA13 80
<22> XA13 XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
XA14 79 4 XMEMW#
<22> XA14 XA14/GPIO12/JOYAY/CTS2# XWR#/XCNF1 XMEMW# <22>
XA15 78 5 XMEMR#
<22> XA15 XA15/GPIO13/JOYBY/SOUT2 XRD#/GPIO34/WDO# XMEMR# <22>
XA16 77 73
<22> XA16 XA16/GPIO14/JOYBX/RTS2# XIOWR#/XCS1#/MTR1#/DRATE0
XA17 76 71
<22> XA17 XA17/GPIO15/JOYAX/SIN2 XIORD#/GPIO37/IRSL2/DR1# EC_FLASH# <22>
XA18 75 72 XIOCHRDY
<22> XA18 XA18/GPIO16/JOYBBTN0/DSR2# XCS0#/DR1#/XDRY/GPIO25 XIOCHRDY <22>
74
XA19/DCD2#/JOYABTN0/GPIO17

VSS
VSS
VSS
VSS
2 1
10K_0402 R108 +3VS
PC87393

13
38
64
89
B B
Signal Pin # Description

BADDR 61 BASE Address Selection


"0": 2E~2F (Default)
"1": 4E~4F
BADDR PULL-UP :4E
+3VS BADDR PULL-DOWN:2E
TEST 58 "0": Normal (Default) (DEFAULT)
+3VS
"1": Test Mode
TXDA 1 2
XCNF0 R311 @10K_0402 DTRA# 1 2
2 1 0 Function R109 @10K_0402
XCNF[2:0] 90, 4, 59 XMEMW# 1 2
x 0 0 No BIOS XCNF1 R318 10K_0402

x 0 1 Normal Mode. XRDY disabled XCNF2 1 2


R312 @10K_0402
Pin # 61
(default) 0 1 0 Latch Mode. XA12-19, XRDY enabled * 1 ROM SOLUTION XBUS RESET CONFIGURATION BASE ADDRESS CONFIGURATION
1 1 0 Latch Mode. GPIO10~17,XRDY enabled
0 1 1 Latch Mode. XA12-19, XRDY disabled
1 1 1 Latch Mode. GPIO10~17,XRDY disabled
A A

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SUPER I/O PC87393 CHIP
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 21 of 42
5 4 3 2 1
5 4 3 2 1

+5VALW +3VALW T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
L19 +3VALW D E P ARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

1
+3VALW @BLM11A20 L17 U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
1 2

1
BLM11A20
KB_VCC R97
L18

1
C128 C426 C129 C111 C89 10K_0402

2
C87 1 2 ECAGND 1 2
.1UF .1UF 1000PF .1UF 1000PF Pin 130 PU for
BLM11A20 Zero Latch

161
108
2

2
.1UF

67
23

91
80

92
U9

VREF
AVCC
VCC
VCC
VCC
VCC

AGND
U21
D 39F040 D
XA0 166 114 KBA0 12 13 ADB0
<21> XA0 HA0 A0 A0 D0
XA1 167 115 KBA1 11 14 ADB1
<21> XA1 HA1 A1 A1 D1
XA2 168 116 KBA2 10 15 ADB2
<21> XA2 HA2 A2 A2 D2
XA3 169 117 KBA3 9 17 ADB3
<21> XA3 HA3 A3 A3 D3
XD0 170 118 KBA4 8 18 ADB4
<21> XD0 HA4 A4 A4 D4 +3VALW
XD1 171 119 KBA5 7 19 ADB5
<21> XD1 HA5 A5 A5 D5
XD2 172 120 KBA6 6 20 ADB6
<21> XD2
<21> XD3
XD3 173 HA6
PC87570 A6 121 KBA7 5 A6 D6 21 ADB7

1
XD4 174 HA7 A7 122 KBA8 27 A7 D7
<21> XD4 HA8 A8 A8
XD5 3 123 KBA9 26 R242
<21> XD5 HA9 A9 A9
XD6 4 124 KBA10 23 1 KBA18 0_0402
<21> XD6 HA10 A10 A10 VPP
XD7 5 125 KBA11 25
<21> XD7 HA11 A11 A11
XA12 6 126 KBA12 4
<21> XA12 HA12 A12 A12

2
XA13 7 127 KBA13 28
<21> XA13 HA13 A13/BE0 A13
XA14 8 128 KBA14 29
<21> XA14 HA14 A14/BE1 A14
XA15 9 129 KBA15 3
<21> XA15

1
XA16 10 HA15 A15/PG1/CBRD 130 KBA16 2 A15
<21> XA16

2
XA17 11 PA3/HA16 A16/PA5/FXBUSEN 135 KBA17 30 A16 32 + C241 C255
<21> XA17 PA4/HA17 A17/PA6 A17 VCC
XA18 12 136 KBA18
<21> XA18 PE0/HA18 A18/PE1/SHBM#
22 10UF_10V_1206 .1UF
CE#

1
XD0 15 137 ADB0 24
XD1 16 HD0 D0 138 ADB1 31 OE# 16
XD2 17 HD1 D1 139 ADB2 WE# GND
XD3 18 HD2 D2 140 ADB3
<21> XSTB0# HD3 D3
XD4 19 141 ADB4
1

XD5 20 HD4 D4 142 ADB5


R331 XD6 21 HD5 D5 143 ADB6 +3VALW
R328
10K_0402 1 2 XD7 22 HD6 D6 144 ADB7
+5VS HD7 D7 +3VALW
C 100K_0402 C

2
13 111 FRD# C402 R294
HAEN RD/HDEN
2

14 112 FWR# 2 1 1 2
<21> XIOCHRDY HIOCHRDY WR0# +5VS
158 105 FSEL# R288
<21> XIOR#
2

2
HIOR# HRMS/SEL0#
G

G
159 .1UF 100K_0402 100K_0402
<21> XIOW# HIOW#
2 R321
1 157 14
HMEMCS#/PA0

1
Q37 3 1 HMEMR# 1K_0402 162 36 KSI0 12 1 3
<21> XMEMR# HMEMRD#/PA1 KBSIN0 EC_FLASH# <21>
S

2N7002 HMEMW# 163 35 KSI1 FWE# 11

S
2

HMEMWR#/PA2 KBSIN1
G

34 KSI2 13 FWR# Q33


156 KBSIN2 33 KSI3 7 2N7002 RP6
<21> IRQ1 IRQ1 KBSIN3
Q38 3 1 155 32 KSI4 U25D FSEL# 1 8
<21> XMEMW# IRQ8# KBSIN4
2N7002 KSI5 74LVC32 KBA18
S

<21> IRQ11 154 31 2 7


153 IRQ11 KBSIN5 30 KSI6 KBA15 3 6
+3VALW <21> IRQ12 IRQ12 KBSIN6 29 KSI7 KBA17 4 5
KBSIN7
2 1 PFAIL# 79 56 KSO0 8P4R-10K
R308 10K_0402 51RST 164 PFAIL# KBSOUT0 55 KSO1
165 HMR KBSOUT1 54 KSO2 +3VS
<25> EC_HPOWON RP35
HPWRON KBSOUT2 53 KSO3 10 1 KBD_DATA
KBSOUT3 +5VS
52 KSO4 9 2 KBD_CLK
2 1 51RST 95 KBSOUT4 51 KSO5 8 3 TP_DATA
<25> FAN_L_H# DA0 KBSOUT5

1
10K_0402 R110 96 50 KSO6 PS2_DATA 7 4 TP_CLK
<32> IREF
N C : 1 , 2 ,43,44,45,46,87,88,89,90,131,132,133,134,175,176

97 DA1 KBSOUT6 49 KSO7 PS2_CLK 6 5


<32> ADPREF DA2 KBSOUT7 +5VS
2 1 98 48 KSO8 R122 R116 R124
<33> POK DAC_BRIG DA3 KBSOUT8
@0_0402 R111 47 KSO9 10K_0402 10K_0402 10K_0402 10P8R-10K
KBSOUT9 42 KSO10
KBSOUT10

2
A_BATT_PRE# 81 41 KSO11
<31> A_BATT_PRE# PD0/AD0 KBSOUT11 +3VALW
IREF: Charger current control 82
PD1/AD1 KBSOUT12
40 KSO12 GATEA20
83 39 KSO13 KBRST# RP30
ADPREF: Adapter current control <15> SLP_S5# PD2/AD2 KBSOUT13
84 38 KSO14 THRM# 1 8
<15> SLP_S3# PD3/AD3 KBSOUT14
B 85 37 KSO15 FRD# 2 7 B
<11,15> SLP_S1# PD4/AD4 KBSOUT15
86 SELIO# 3 6
93 PD5/AD5 BKOFF# 4 5
<25> FAN0_TACH PD6/AD6
A_BATT_PRE# 1 2 ECAGND 94 57 KBD_DATA
<25> FAN1_TACH PD7/AD7 PSDAT1 KBD_DATA <25>
C88 .01UF 58 KBD_CLK 8P4R-10K
PSCLK1 KBD_CLK <25>
59 PS2_DATA
PSDAT2 PS2_DATA <25>
61 60 PS2_CLK
PC0 PSCLK2 PS2_CLK <25>
62 69 TP_DATA
<18> SRL_LED# PC1 PSDAT3/PC7 TP_DATA <23>
63 70 TP_CLK +3VALW
<18> NUM_LED# PC2 PSCLK3/PC6 TP_CLK <23>
64
<18> CAP_LED# PAD_LED# PC3/EXINT0
65 113 THRM#
PC4/EXINT11 PG4/WR1# THRM# <15>
<24,26,30,33> SUSP# 68 106 S I DE_CS_M#/S <17>

1
PC5/EXINT15 PG3/SEL1# 107
PG2/CLK MODEN# <17>
110
PG0/SELIO SELIO# <23>
71 R310 R316
<24> RING# PB0/RING#
SMB_EC_CK1 72 4.7K_0402 4.7K_0402
<4,12,23,31> SMB_EC_CK1 PB1/SCL
SMB_EC_DA1 73 104
<4,12,23,31> SMB_EC_DA1 PB2/SDA PH0/BST0/ENV0 KSO16 <23>

2
74 103
INVT_PWM PB3/TA PH1/BST1/ENV1 KSO17 <18>
75 102 ACOFF SMB_EC_DA1
<19,20> PCMRST# PB4/TB/EXINT10 PH2/BST2/TRIS ACOFF <32>
GATEA20 76 101 EC_SMI# SMB_EC_CK1
<14> GATEA20 PB5/GA20 PH3/PFS EC_SMI# <15,21>
KBRST# 77 100 EC_ON
<14> KBRST# PB6/HRSTO# PH4/PLI EC_ON <25>
<25> ON/OFF 78 99 SCI# <15>
PB7/SWIN PH5/ISE#
1UF
C130 28 145
+RTCVCC VBAT D8/PF0 EN_FAN0# <25>
1 2 146 ADB[0..7]
D9/PF1 EN_FAN1# <25> ADB[0..7] <23>
147
D10/PF2 VR_ON <26,30>
CRY1 25 148 EC_SMI# 1 2 KBA[0..17]
32KX1/32CLKIN D11/PF3 FSTCHG <32> KBA[0..17] <23>
27 149 R98 10K_0402
32KX2 D12/PF4 MUTE <27>
A 150 KSI[0..7] A
R329 D13/PF5 SYSON <26,31> KSI[0..7] <18,23>
1 2 CRY2 151
D14/PF6 ACIN <15,31>
152 KSO[0..15]
D15/PF7 BKOFF# <13> KSO[0..15] <23>
22M R330
GND
GND
GND
GND
GND

X2 C435
2 1
109
160

Compal Electronics, Inc.


24
26
66
1

C434 32.768KHZ 51K PC87570-176PIN


10PF 33PF Title
KBC/EC PC87570EXT
2

Size Document Number Rev


2.0
888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 22 of 42
5 4 3 2 1
1 2 3 4 5 6 7 8

ADB[0..7]
<22> ADB[0..7]

<22> KBA[0..17]
KBA[0..17]
INPUT OUTPUT
+3VS +3VALW +3VALW
C411
RP26 8P4R-100K C373 1 2
1 8 1 2
2 7 .1UF
3 6

20
.1UF
4 5 U28

20
U26 ADB0 3 2

VCC
D0 Q0 PWR_LED# <18>
2 18 ADB0 ADB1 4 5

VCC
A <17> MODPRES# 1A1 1Y1 D1 Q1 BAT2_LED# <18> A
4 16 ADB1 C403 ADB2 7 6
<17> CD/FDD# 1A2 1Y2 D2 Q2 SWI# <15>
6 14 ADB2 1 2 ADB3 8 9
1A3 1Y3 +3VALW D3 Q3 LID_OUT# <15>
MINI_PME# 8 12 ADB3 ADB4 13 12
<29> MINI_PME# 1A4 1Y4 D4 Q4 PWRBTN_OUT# <15>
LID_SW# 11 9 ADB4 .1UF ADB5 14 15 VLBA# 1 2
2A1 2Y1 U25A D5 Q5 BATTLOW# <15>
PCM_PME# 13 7 ADB5 ADB6 17 16
<19> PCM_PME# 2A2 2Y2 74LVC32 D6 Q6 BAT1_LED# <18>
15 5 ADB6 14 ADB7 18 19 D12 1SS355
<12,13> ENABKL 2A3 2Y3 D7 Q7 BEEP# <28>
17 3 ADB7 KBA3 1
<31> AIR_ADP# 2A4 2Y4 3 AA 11

GND
1 SELIO# 2 LARST# 1 CLK

GND
1G CLR
19 7
+3VALW 2G 74LVC273

10
74LVC244

10
U25B
14 74LVC32 C425
KBA1 4 1 2 1 2
+3VALW
6 CC R317 20K_0402
SELIO# 5
<22> SELIO# 7 1UF
+3V +3VALW

2
R120 R119 R279 R278
100K_0402 100K_0402 100K_0402 100K_0402

1
N M 2 4 C 1 6 4 A d dress definition: 1 A2 A1# A0 B2 B1 B0 R/W# PCM_PME# AA
B B
MINI_PME# CC

+3VALW

+3VALW
1

1 2
C412 .1UF R300
100K_0402
U27
2

8 1
7 VCC A0 2
6 WC A1 3
<4,12,22,31> SMB_EC_CK1 SCL A2
5 4
<4,12,22,31> SMB_EC_DA1 SDA GND
NM24C16

EC I2C Bus Address:


24C164: 1011xxx R/W#
24C16: 1010xxx R/W#

CP8
KSO4 8 1
KSO5 7 2
KSO16 6 3
C KSO0 5 4 C
JP12
JP10 @8P4C-10PF 1 2
1 2 TP_CLK <22>
KSO4 3 4
KSO5 25 CP9 5 3 4 6
24 <27> INTSPK_L- 5 6 TP_DATA <22>
KSO16 KSO3 8 1 7 8
23 32 <27,28> INTSPK_L+ 7 8
KSO0 KSO2 7 2 9 10
22 <27> INTSPK_R- 9 10
KSO3 KSO1 6 3 11 12
21 <27,28> INTSPK_R+ 11 12
KSO2 KSO8 5 4 13 14
KSI3 20 15 13 14 16 1 2
19 15 16 +5VS
KSO1 @8P4C-10PF 17 18 L22 FBM-11-451616-800A
18 17 18
KSI5 19 20 RBAT

1
KSI6 17 CP10 21 19 20 22 C145
KSI0 16 KSO12 8 1 23 21 22 24 LID_SW#
15 30 23 24
<22> KSO[0..16]
KSO[0..16] KSO8
14 29
KSO10 7 2 25
25
LID_CL+ .1UF

2
KSO12 KSO14 6 3
KSI[0..7] KSI7 13 28 KSO6 5 4 JP 25PIN
<18,22> KSI[0..7] 12 27
KSO10
KSO14 11 26 @8P4C-10PF
KSI4
KSI2
10
9 CP11
TO TOUCH PAD
KSI1 8 KSO7 8 1
KSO6 7 KSO9 7 2
KSO7 6 KSO13 6 3
KSO9 5 KSO15 5 4
KSO13 4
KSO15 3 31 @8P4C-10PF
KSO11 2
1 KSO11 1 2
D int. kb C487 @10PF D

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
EC Extended I/O Port
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 23 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

SERIAL / PARALLEL PORT SERIAL & PARALLEL

+5V

A A

1
C13
U3 .1UF

2
1 2 C1 28 26
C1+ VCC
.1UF
24
C1- 27 1 2 C12
1 2 C11 1 V+ 1 2
C2+ .1UF
.1UF L43 68
2 3 1 2 C14 1 2
C2- V- L41 68 JP2
.1UF
14 9 TXD1 1 2
<21> TXDA T1IN T1OUT
13 10 RTS1# L40 68 5
<21> RTSA# T2IN T2OUT
12 11 DTR1# 1 2 RI0F 9
<21> DTRA# T3IN T3OUT L44 68 DTR0F 4
20 COM_RI 1 2 CTS0F 8
4 R2OUTB 19 L42 68 TXD0F# 3
R1IN R1OUT DCDA# <21>
5 18 RTS0F 7
R2IN R2OUT RIA# <21>
6 17 1 2 RXD0F# 2
R3IN R3OUT RXDA <21>
7 16 L39 68 DSR0F 6
R4IN R4OUT CTSA# <21>
8 15 1 2 DCD0F 1
R5IN R5OUT DSRA# <21>
L38 68
<22,26,30,33> SUSP# 22 21 1 2 DSUB-9
23 FORCEOFF INVILID 25 L37 68 FOXCONN
FORCEON GND

4
3
2
1

4
3
2
1
MAX3243/MAX3243E
CP4 CP3

B 8P4C-47PF 8P4C-47PF
SERIAL B

5
6
7
8

5
6
7
8
+5V_PRN

PARALLEL +5VS
2
D8
1

1SS355

1
+3VALW R168
LPD[0..7] 2.7K_0402
<21> LPD[0..7]
2

R169

2
R313 <21> LPTSTB# LPTSTB# 1 2 1 2 C158
20K_0402 47PF
33_0402 +5VS_JP5
D13
1

1 1
<29> MINI_RI# 3 1 2 AFD/3M# 14
RING# <22> <21> LPTAFD#
2 L1LPD0 1 2 FD0 2
<19> PCM_RI# 68
1 2 L2 68 ERR# 15
<21> LPTERR#
C RB717F L3 LPD1 1 2 FD1 3 C
D 68
1

1 2 L4 68 PRNINIT# 16
<21> LPTINIT#
COM_RI 2 Q36 L25 LPD2 1 2 FD2 4
G 68
2N7002 1 2 L26 68 SLCTIN# 17
<21> LPTSLCTIN#
S L5 LPD3 1 2 FD3 5
68
3

L24 68 18
LPD4 1 2 FD4 6
L23 68 19
LPD5 1 2 FD5 7
L31 68 20
LPD6 1 2 FD6 8
L30 68 21 JP3
+5V_PRN +5V_PRN LPD7 1 2 FD7 9
CP5 CP6 LPTCN-25
L29 68 22
FD7 8 1 SLCT 8 1 1 2 ACK# 10
<21> LPTACK#
FD6 7 2 PE 7 2 L28 68 23
FD5 6 3 BUSY 6 3 1 2 BUSY 11
<21> LPTBUSY
FD4 5 4 ACK# 5 4 L27 68 24
1 2 PE 12
<21> LPTPE
L34 68 25
8P4C-47PF 8P4C-47PF 1 2 SLCT 13
<21> LPTSLCT
5
4
3
2
1

5
4
3
2
1

L33 68
RP23 RP24
10P8R-2.7K 10P8R-2.7K
10

10
6
7
8
9

6
7
8
9

D D

+5V_PRN +5V_PRN
CP2 8P4C-47PF CP1 8P4C-47PF
FD3 1 8 FD1 1 8
SLCTIN# 2 7 ERR# 2 7
FD2 3 6 FD0 3 6
PRNINIT# 4 5 AFD/3M# 4 5
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Serial/parallel ports
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 24 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

+5VALW +5VALW

2
+12VALW +12VALW
R198 R205 R191 R192
33.2K_1% 1M 33.2K_1% 1M
U14A U14B
+5VALW +5VALW
2SC2411K 2SC2411K

8
1

1
LM358 1K_0402 Q27 LM358 1K_0402 Q26
A A
3 + R182 1 5 + R196 1
1 2 1 2 7 2 1 2
2 - 3 6 - 3

2
R197 R193

4
64.9K_1% JP14 64.9K_1% JP15

1 1
2 2

1
3 3
1 D D

1
MOLEX 53398-0290 MOLEX 53398-0290
2 2
<22> FAN_L_H# <22> FAN_L_H#

1
G G
Q7 S C168 +3VS Q5 S C171 +3VS
3

3
2N7002 4.7UF_10V_0805 2N7002 4.7UF_10V_0805

2
1 D D

1
2 R181 2 R177
<22> EN_FAN1# <22> EN_FAN0#
G 10K_0402 G 10K_0402
Q6 S Q4 S
3

3
2N7002 2N7002

2
FAN1_TACH <22> FAN0_TACH <22>

B B

+3VALW RTC BATT


BATT1
+3VALW +3VALW
- +
1

2 1
R333
47K_0402 PWR ON CKT
U29A U29B
14 74LVC14 14 74LVC14 RTCBATT

1
R327
2

R325 100_0402
2 1 1 2 3 4 2 1 D15
RSMRST# <15> <13> ITP_VR_POK EC_HPOWON <22>

+3V POWER +3V POWER R326 100_0402


1

330K 2 1 +RTCVCC
SYS_PWROK <15,16>
C438
.1UF

2
2

CHGRTC
HSM126S

PS2 CONN. +3VALW

C
POWER BTN C

1
U2
PS2_DATA 1 6 R123
<22> PS2_DATA DATA IN DATA OUT 100K_0402
2 5
PS2_CLK 3 GND VCC 4
<22> PS2_CLK CLK IN CLK OUT D5

2
KBMF01SC6 1 ON/OFF
ON/OFF <22>
3
<18> ON/OFFBTN
2
EC_ON# <32>
+5VS PS2KB_VCC KB_AS JP1 +3VALW
DAN202U
F3 KBD/PS2_6
W=40mils 1 2 W=40mils

1
L32 4 6
D6
1

1
P O LYSWITCH_1.1A FBM-11-451616-800A 2 R125 C127

1
4516 C159 1 4.7K_0402
1UF 3 5 1000PF

2
RLZ20A
2

2
R126
22K

2
EC_ON 1 2 2
<22> EC_ON
22K_0402 22K

Q11
DTC124EK

3
U1
KBD_DATA 1 6
<22> KBD_DATA DATA IN DATA OUT
2 5
KBD_CLK 3 GND VCC 4
<22> KBD_CLK CLK IN CLK OUT WHEN R=0,Vbe=1.35V
KBMF01SC6 WHEN R=33K,Vbe=0.8V
D D

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PS/2/RTC/RST CKT
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 25 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

RESET & SUSPEND CKT

+12VALW
+5V +5VS
JP19
1

3MM

A
R372 +5VALW TO +5V Transfer 1 2 A
100K_0402

+5VALW
2

SI4800 +5V
U31 +3V +3VS
JP20
1

8 1 +12VALW
D
1

1
C471 7 D S 2 3MM

1
SYSON# 2 R371 6 D S 3 1 2

1
G .01UF 5 D S 4 C468 R370
C469
D G
2

Q46 S 1M_0402 470 R298


3

2N7002 10UF_10V_1206 .1UF 10K_0402

2
SUSON

12
D

2
SUSP
<27> SUSP
2 SYSON#
D

1
G
S SUSP# 2 Q32
<22,24,30,33> SUSP#

3
Q45 G 2N7002
2N7002 S

3
+3VALW TO +3V Transfer +CPU_CORE
+3VALW +3V +3VALW
SI4800

1
U8

@330_0603
8 1 R332

R171
2
7 D S 2 @100K_0402 +12VALW
1

6 D S 3 +CPU_IO
1

5 D S 4 C123 C114 R121


B D G B

2
470
1

1
C131 .1UF
D

1
2

1
R284

@330_0603
12

10UF_10V_1206 VR_ON# 2

R1
D 100K_0402
G
2

22UF_10V_1206 2 SYSON# S Q17

2
G @2N7002

2
SUSON S Q12 SYSON#
D SYSON#

1
3

2N7002
D D

1
VR_ON 2
<22,30> VR_ON
G 2 2 Q35
<22,31> SYSON
S Q39 G G 2N7002

3
@2N7002 S Q2 S

2
3

3
@2N7002

+5VALW Q63
@SMO5
1

+12VALW +5VALW TO +5VS Transfer

3
C472
4.7UF_10V_0805
2
1

+5VALW +5VS
R374
100K_0402 U32 SI4800
8 1
7 D S 2
1

D S
2

6 3
5 D S 4 R373
1

C D G C474 470 C
C473
D
1

C476
SUSP 2 RUNON 22UF_10V_1206
G
2

R375 .01UF
2

Q47 S 1M_0402
3

2N7002 Q48
.1UF
D
1

2 SUSP
G
S
+1_8VALW TO +1_8VS Transfer
3

2N7002

+1_8VALW +1_8VS

U13 SI4800
+3VALW +3VS 8 1
+3VALW TO +3VS Transfer 7 D S 2
1

1
U12 SI4800 6 D S 3 C166 C167
8 1 5 D S 4 R178
7 D S 2 D G .1UF 470
D S
1

6 3 C140 C136
5 D S 4 R134
D G
2

.1UF 470 C163 Q22


1

10UF_10V_1206 22UF_10V_1206 2N7002


D
1

C138
2

10UF_10V_1206 RUNON 2 SUSP


2

22UF_10V_1206 Q13 G
D
1

2N7002 S
3

D RUNON 2 SUSP D
G
S
3

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DC/DC INTERFACE
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 26 of 42
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

VDDA

+5VS
1 2 +5VAU
R229 0_1206 L55 +5VALW
1 2 2 1 +12VALW
R194 @0_1206 Note: direct connect GNDA to GND. BLM21A601SPT
+5VALW
.1UF

1
1 2

1
R309 C405 C378

1
C198 C235 2.4K
C199 .1UF

18
7

8
GNDA GND

2
4.7UF_10V_0805 .1UF U17 R306 U23A
D

1
2

2
.1UF 1 2 3

LVDD
RVDD
A + A
1 2 Q30
D

1
100K_0402 2 G SI2306DS
-

1
INTSPK_L+ 1 2 D11 C379 2 LM358 S
SUSP <26>

1
G

3
150K R226 AS2431L 2 .1UF

4
LEFT C246 1UF 1 2 4 S Q34 R273
LLINEIN INTSPK_R+

3
75K R233 22 2N7002 5.1K
ROUT+ INTSPK_R+ <23,28>

1
INTSPK_R+ 1 2
150K R200 21
RLINEIN INTSPK_R-

2
RIGHT C178 1UF 1 2 15 2 1
ROUT- INTSPK_R- <23>
75K R201 C366 68PF
INTSPK_L+ 1 2
75K R232 3 INTSPK_L+ R271 R270
LOUT+ INTSPK_L+ <23,28>
C245 1UF 1 2 5 1 2 1 2 1 2
75K R231 LHPIN R272 5.11K_0.5%
INTSPK_R+ 1 2 10 INTSPK_L- 442_1% 5.11K_0.5%
LOUT- INTSPK_L- <23>
75K R206 20
C179 1UF 1 2 RHPIN 0_0402
75K R207 1 2 2 1
VDDA
9 MUTEOUT R277 C365 220PF
MUTEOUT

1
HP_SENSE 16 C364
<28> HP_SENSE HO/LINE#
14 2 .1UF
SE/BTL# NC

2
MUTEOUT 8 17
11 SHUTDW NC 23
<22> MUTE MUTEIN NC

6
LBYPASS +3VS
GND/HS
GND/HS
GND/HS
GND/HS

19
B RBYPASS B

1
C193 C478
TPA0202 R282
24
13
12
1

4.7UF_10V_0805 .1UF 0_1206


VDDA +5VS VDD_AC97 STAC9700 AD1881A

1
VDDA W=25mils

2
1 2
R269 @0_1206 C248 1UF 4.7UF_10V_0805
1

1
C349 C376 W=25mils C363
.1UF C369
C260 1000PF 270PF
1

4.7UF_10V_0805 @4.7UF_10V_0805 C314 1 C270 4.7UF_10V_0805


2

2
.1UF 4.7UF_10V_0805

25

38
C259 1000PF 270PF

9
2

1 2
R95 6.8K 1 2

AVCC

AVCC

VCC

VCC
1 2 C287 1000PF
R94 6.8K 1 2 C501 Depop 1UF
1 2 2 1 C283 1000PF
<17> MOD_CD_L
R91 6.8K C331 1UF 14 35 LEFT
1 2 2 1 AUX_L LINE_OUT_L 1 2
<17> MOD_CD_R
R90 6.8K C335 1UF 15 36 RIGHT C297 1000PF
AUX_R LINE_OUT_R
1 2 16 37 MONO_OUT 1 2 MD_MIC
VIDEO_L MONO_OUT MD_MIC <29>
R238 6.8K C308 1UF
1 2 17 39 1 2 1 2
R241 6.8K VIDEO_R HP_OUT_L C327 @1000PF R259
1 2 1 2 23 41 1 2 100K_NC
<28> LINE_IN_L LIN_IN_L HP_OUT_R EMI Solution 3/1/2000
R239 6.8K C253 2.2UF_0805 C340 @1000PF 1 2
1 2 1 2 24 C375 15PF ADD 15PF(EMI Request)
<28> LINE_IN_R LIN_IN_R
C R240 6.8K C254 2.2UF_0805 6 BIT_CLK_R 1 2 C
BIT_CLK IAC_BITCLK <15,29>
1 2 1 2 CD_L_IN 18 R274 22
<17> INT_CD_L CD_L
R257 6.8K C306 1UF 8 SDATA_IN_R 1 2
SDATA_IN SDATA_IN0 <15>
1 2 1 2 CD_R_IN 20 R275 47
<17> INT_CD_R CD_R
R253 6.8K C284 1UF 2 XTL_IN
1 2 INT_CD_AGND 19 XTL_IN

2
R249 6.8K CD_GNA Y2 C374
1 2 21
<28> EXTMICIN MIC1
R260 6.8K 22PF

1
22 3 XTL_OUT 24.576 MHz 1 2
MIC2 XTL_OUT C382 22PF
MD_SPK 1 2 PHONE 13 29 AFTL1 C260 1 2 1000PF C261 1 2 .1UF
<29> MD_SPK PHONE AFLT1
C341 .1UF
MONO_IN 1 2 1 2 12 30 AFTL2 C259 1 2 1000PF C247 1 2 1UF
<28> MONO_IN PC_BEEP AFLT2
R266 C361 1UF
2

47K_0402 28 VREFOUT W=15mils


<28> PC_BEEP VREFOUT <28>
1

R268 C350 11 VREFOUT


<15,29> AC97_RST# RESET#
4.7K_0402 27 REFFLT
2700PF 10 REFFLT
<15,29> IAC_SYNC SYNC FLT3D
2

32 CAP2
CAP2
1

5
<15,29> IAC_SDATAO SDATA_OUT

1
C258 C262 C248
45 31 BPCFG 1 2 C501
46 NC ID0# NC 33 FLT1 @1UF 1UF .1UF 1UF
NC ID1# NC FLT0

2
34
47 NC 43
1

R256 NC EAPD NC 44 C257 C500


1 2 1 2 INT_CD_AGND 48 NC
<17> INT_CD_GND NC SPDF
C294 1UF 40 1000PF .047UF
NC
2

D 3.3K 4 26 D
2

7 GND AGND 42
R254 GND AGND

3.3K
U22 STAC9700
1

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AUDIO CODEC & AMP
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 27 of 42
1 2 3 4 5 6 7 8
A B C D E

AUDIO JACK
+3VALW +5VS

+3VALW

1
+3VALW R320 R295
4 4
100K_0402 100K_0402
U25C
U29C VDDA
14 74LVC32 14
74LVC14 VDDA

2
9 R291
<23> BEEP#

1
8 1 2 5 6 1 2 1 2
10 C401 1UF R264
R322

1
7 C439 2K_0402 100K_0402
10K_0402 +3V POWER R237
100K_0402
.1UF

2
EXT. LINE_OUT

2
J3 JA6333L-100
<27> HP_SENSE
5
C362
MONO_IN <27>
1UF 4
1 C233
1 2 1 2 2 Q31 150UF_6.3V_E L50 BLM11A121S 3
<19> PCM_SPK# 2K_0402 R304 1UF C397 3 2SC2411K 1 2 1 2 6

+
<23,27> INTSPK_R+
2
1

+
1 2 1 2 1 2 1 2
<23,27> INTSPK_L+

1
<15> SPKR 2K_0402 R302 1UF C395 C281 L51 C230

1
150UF_6.3V_E BLM11A121S C280 C252 C236

1
47PF

2
D10 47PF 47PF 47PF

2
1SS355

3 3

2
1 2
1 2 1 2 C219 4.7UF_10V_0805
<29> MOD_MON PC_BEEP <27> VDDA
10K_0402 R303 1UF C396

2
R430 1 2 1 2
4.7K_0402 R212 1K_0402 C212 .1UF

EXT. MIC

1
1
J4 JA6333L-100
R424 R387 R223
@2K_0402 2K_0402 2K_0402 5

2
1 2 3
L52 BLM11A121S 6
VDDA <18> INT_MIC
EXT_MIC 1 2 2
L53 BLM11A121S 1
@2K_0402 @2K_0402
1 2 1 2

1
U16A R221 R219 C323 C338 C295
8

3 @APA2308 C229 C210 47PF 47PF 47PF


<27> VREFOUT +

2
1
1

C313 C195 2 - @.1UF @10UF_10V_1206


2

2
1

2 @4.7UF_10V_0805 @.1UF 2
2

C196
@.1UF
2

VDDA U16B
1 2
8

@APA2308 C200 @1UF


5
7
+ EXT. LINE IN
<27> EXTMICIN
- 6 1 2 1 2 C232 EXT_MIC
J2 JA6333L-100
R228 33_0402
0.47UF
5
4

4
1 2 L46 BLM11A121S
R230 LINE_IN_R 1 2 3
0_0402 <27> LINE_IN_R
6
1 2 LINE_IN_L 1 2 2
<27> LINE_IN_L
@220PF C228 L49 1

BLM11A121S

1
C222 C186 C216

47PF 47PF 47PF

2
1 1

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MONO_IN
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 28 of 42
A B C D E
1 2 3 4 5 6 7 8

For Compal private Mini-PCI combo card - Mini-PCI type IIIc +3V_MINIPCI
+3V_MINIPCI

pin 21. LAN REQ#


pin 22. LAN GNT#

1
pin 36. LAN PME#
C475 C451 C142 C141 C155 C154 C477
.1UF 1000PF .1UF .1UF .1UF .1UF 10UF_10V_1206

2
pin 43. LAN IDSEL
A A

MINI_PCI CONNECTOR
RP39 8P4R-0
1 8 LAN_EECS_R JP18
<16> LAN_EECS
2 7
<16> LAN_EEDI 1 2
3 6 LAN_EEDI_R LAN_EECS_R
<16> LAN_EEDO 3 4
4 5 LAN_EEDO_R LAN_PHYRST_R R401 2 1 0_0402
<16> LAN_EECLK 5 6 LAN_PHYRST <16>
LAN_EECLK_R LAN_TXD2_R R402 2 1 0_0402
7 8 LAN_TXD2 <16>
R403 2 1 0_0402 LAN_RXD2_R R417 2 1 0_0402
<16> LAN_RXD2 9 10
R418 2 1 0_0402 LAN_TXD1_R R404 2 1 0_0402
11 12 LAN_TXD1 <16>
R405 2 1 0_0402 LAN_RXD1_R LAN_TXD0_R R406 2 1 0_0402
<16> LAN_RXD1 13 14 LAN_TXD0 <16>
R407 2 1 0_0402 LAN_RXD0_R R408 2 1 0_0402
<16> LAN_RXD0 15 16 LAN_PHYCLK <16>
<14,16> PIRQB# 17 18 +5VS
1 2 L21 2 1 2 1
+3V 19 20 PIRQD# <14,16>
0 2 1 2 1 R166 @33_0402 C157 @22PF
<14,16> REQ#2 R378 @0_0402 21 22 R379 @0_0402 GNT#2 <14,16>
+3V_MINIPCI 23 24 +3VAUX
B <11> CLK_PCI_MINI 25 26 PCIRST# <7,12,14,19,21> B
1 2 L57 +3V
REQ#1 27 28 GNT#1 0
<14,16> REQ#1 29 30 GNT#1 <14,16>
31 32 +3V_MINIPCI
AD31
33 34 MINI_PME# <23>
AD29 2 1
35 36 AD30 R380 @0_0402
@100_0402 AD27 37 38
AD28 1 2 AD25 39 40 AD28 +5VS
R157 41 42 AD26
43 44 AD24
<14,19> C/BE#3 45 46

1
AD23 1 2 AD27 C137
47 48 R154 100_0402
AD21 49 50 AD22 .1UF
51 52

2
AD19 AD20
53 54
AD17 55 56 AD18 PAR <14,19>
57 58 AD16
<14,19> C/BE#2 59 60
<14,16,19> IRDY# 61 62
63 64 FRAME# <14,16,19>
CLKRUN#
<15,16,19,21> CLKRUN# 65 66 TRDY# <14,16,19>
67 68 STOP# <14,16,19>
<14,16,19> SERR#
69 70
<14,16,19> PERR# 71 72 DEVSEL# <14,16,19>
<14,19> C/BE#1 73 74
AD14 AD15
75 76 AD13
CLK_PCI_MINI AD12 77 78 AD11
AD10 79 80
2

81 82 AD9
C R164 AD8 83 84 C
AD7 85 86 C/BE#0 <14,19>
33_0402
87 88 AD6
AD5 89 90 AD4
91 92
1

AD2
AD3 93 94 AD0
2

95 96
C156 +5VS AD1 97 98
22PF 99 100
101 102
1

1 2
<15,27> IAC_SYNC 103 104 R419 1K_0402
<15> SDATA_IN1 105 106 IAC_SDATAO <15,27>
IAC_BITCLK
<15,27> IAC_BITCLK
IAC_BITCLK AC_CODEC_ID0# Connection AC_CODEC_ID1# AC_CODEC_ID0#
107 108
+3VAUX AC97_RST# <15,27>
2

109 110
AC_CODEC_ID1# <28> MOD_MON
MOD_MON
111 112 SDATA_IN1 0 1
R409
113 114 MD_SPK
@33_0402 <27> MD_MIC 115 116 MD_SPK <27>
117 118
119 120
1

2 1
<24> MINI_RI# 121 122 MPCIACT# <14>
R381 @0_0402
+3VAUX
2

1 2 123 124
+5VS
C481 L56 FBM-11-160808-121
@22PF MINI_PCI CONN. +3VAUX +3VALW +3V
1

+5VS_MINIPCI
1 2
1

R165 @0
C430 1 2
.1UF R323 0
2

D MOD_MON 2 1 MD_SPK C429 D


R128 @0_0402
.1UF
2

AD[0..31]
<14,19> AD[0..31]

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Mini-PCI Connector
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 29 of 42
1 2 3 4 5 6 7 8
A B C D E

B+CPU_CORE

PL9
FBM-L11-322513-121AT
2 1
B+
+5VALWP

@4.7UF_1210_25V

0 . 1UF_0805_25V
4 . 7UF_1210_25V
PR106

4.7UF_1210_25V

4.7UF_1210_25V

4.7UF_1210_25V
5
6
7
8

5
6
7
8
@0

1
<4,15> VR_HI/LO# 1 2 PQ1 PQ2 2 1

PC1

PC2

PC3

PC4

PC5
PC97
2
SI4884DY SI4884DY

RB751V
PD1
IRF7811A IRF7811A

2
PJP11
4 4 @3MM
1 1
PR1

1
0
<22,24,26,33> SUSP# 1 2 BSTCORE1

0.1UF_0805_25V
1

3
2
1

3
2
1
PR2

PC6
PR101
100K PL1
@1UH 0.003_2512_1%

2
1 2 2 1
PU1 +CPU_CORE

2
MAX1711

PR98
2.2
PL2 PR3
<4> VID4 16 21
D4 SKIP 0.9UH/20A_LPI 0.003_2512_1%

1
+3VALWP <4> VID3 17 23 LXCORE 1 2 2 1
D3 LX

5
6
7
8
<4> VID2 18 24 DHCORE

5
6
7
8

5
6
7
8

1
D2 DH

220UF_D_4V
PQ3 PQ4 PQ29
2

1
EC10QS04
19 22 BSTCORE SI4404DY SI4404DY @

PD2
<4> VID1 D1 BST +
FDS7764A FDS7764A

PC8
PR4

1
20 14

EC31QS04
100K <4> VID0 D0 PGND 4

PD21
0 PR5

2
1 2 2 13 DLCORE 4 4
<22,26> VR_ON SHDN DL
1

12 1 PR6
<15> V_GATE PGOOD V+

2
20

3
2
1
15 7 VCCORE 2 1
+5VALWP VDD VCC

3
2
1

3
2
1
0.22UF_0805_16V
5 3

PC11
CC FB
2 PC10 2
2VREF 9 4
REF FBS 2200PF

6 11
ILIM GNDS PR7
0.22UF_0805_16V
1UF_0805_25V

0
10 8 2 1 PR99
GND TON +5VALWP
220PF

0
PC13

PC14

1
PC12

2 1 FBCORE
150K_1%

2 1
PR8

PR9 2 PR100
1M_1% PR10 @
2

10K_1% 2 1 2VREF
1

PQ6
SI3442DV
+3VALWP
2

D
6

S
RB751V

5 4
PD22

+1_8VALWP +CPU_IOP
+CPU_IOP 2
2

4 . 7UF_1206_25V
1

1
PR13 +5VALWP

G
PR92
+
1

1.2M_1% PC15

PR12
5.1K
PR11
100K

PC16

0
1 2 150UF_D_6.3V_KO

0.1UF_16V
1

1
1

2
1
<13> VR_POK

1
PU2B PR14 PD23

PC17

220PF
LM358 PR15 100K_1%

PC18
3 2.5VREF 1SS355 3
D 243K_1%
1

2
+ 5 1 2
2

PQ7 2 7
2N7002 G 6 PU2A PR16
-

8
S 100K_1%
LM358
3

+ 3 2 1 2VREF
2

1
1

PC98 PR17 PR18 PC79 2 +5VALWP


-

2
1000PF 100K_1% 200K_1% 1UF_0805_16V

300K_0.5%
PR19
0.01UF
CPU_IOP Detector

2
PQ8
2

PC19
PC20

1
DTC115EK
1

PR21
Low 1.43 1.35 1.29

100K
68PF

PR20
5.1K
High 1.08 1.03 0.99

1
1 2
100K

1
2
PQ9
Delay time (ms)

1
DTC115EK
100K
264 156 108 +3VALWP PQ10 +2_5V_CLKP
2SB1132

3
100K
SOT-89 2 VR_ON <22,26>
3 2

100K
PC21 + + PC22
1

3
22UF_B_6.3V PU3 22UF_B_6.3V
1

S-816A25
4 5
EXT

4 4
VIN VOUT
VSS

1 2 3
<22,24,26,33> SUSP# ON/OFF#
@0
PR22 Compal Electronics, Inc
2

1 2 Title
<22,26> VR_ON T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL CORE/IO/CLK
0 A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PR23 D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board 2.0

Date: T h ursday, January 11, 2001 Sheet 30 of 42


A B C D E
PJP10
@3MM
+3VALWP 1 2

BATT+ BATT++

1
PR24
47K PL8
1 2
+3VALWP

2
FBM-L11-322513-121AT

0.1UF_0805_25V
AIR_ADP# <23>

0.1UF_0805_25V
1

1
PC82

PC83
PQ11

2
2

2
100K DTC115EK

3
2 PR25
47K
100K

1
3

PD3 PD4 PD5

1
@BAS40-04 @BAS40-04 @BAS40-04
PCN1 A_BATT_PRE# <22>
BP02078-H1
PCN2 PL3 VIN PR27
PR34-8R-3PDLA OC9080-D601 1 100
BATT+ 2 1 2
CLK_SMB SMB_EC_CK1 <4,12,22,23>
3 ADPIN 2 3 3
VIN DAT_SMB 4
1 BATT_PRS# 5 1 2
GND SMB_EC_DA1 <4,12,22,23>

1
SYS_PRES# 6
AIR_ADP 2 PR109 REMOTE-SNS 7 PR28
10_1206 GND 100 1 2
1 4
1

1
PR26
4
5
6
7

PC26 PC27 PC28 PC23 PC24 PC25


100

2
@ @
1000UF_50V 100PF_50V 100PF_50V 1000PF_50V

1
2

2
PZD5
RLZ24B

2
ADPGND
Precharge detector while AC adaptor
High 16.5 15.8 15.1
Low 13.9 13.2 12.5

PR29 PR30
100K 1M_1%
1 2 2 1
+5VP
B+

Vin Detector

1
High 18.7 17.9 17.1 PR31

499K_1%
Low 18.0 17.3 16.5 PU4B
LM393A
PD6

2
RB751V
PR32 + 5
1M_1% 2 1 7
<33> SHDN#
1 2 - 6

1
PD7

2
VIN VS VS PR36 PR37

0.1UF_16V
RB751V

1
PC30 PR38 249K_1% 499K_1% PC93

PC31
2 1 1000PF 10K 1000PF
1

<32> ACON

2
1

PR33

2
PC29 PR34 PR35

1
78.7K_1% 0.01UF 10K 10K
PU4A 1 2
ACIN <15,22>

1
2

PR39 RTCVREF
8
2

22K LM393A PR42


1 2 3 + 47K
1 2 2 1 PACIN
2 PACIN <32> PQ12
-
1

2N7002
1

1
3
PC32 PR40 PC33
4

1000PF 20K_1% 0.1UF_16V PZD1 PR41


RLZ3.6B 10K
2

100K
2

2
PQ13 SYSON <22,26>
2

2 1 RTCVREF
DTC115EK
PR43 100K
10K

3
Compal Electronics, Inc.
Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Detector
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 31 of 42
P2 P3 B+ B++ B+
PQ14 PQ15 PR44 PQ16
SI4835DY SI4835DY 0.02_2512_1% SI4835DY
VIN 8 1 1 8 2 1 1 8
7 2 2 7 2 7

4.7UF_1210_25V
4.7UF_1210_25V
6 3 3 6 3 6

4.7UF_1210_25V

0.1UF_0805_25V
1

1
5 5 5

PC34

PC35

PC36
1

2200PF
PC84

PC85
200K
PR46
Iadp = 0~3.33A

PR45
4

4
47K
Iadp = 0.964*ADPREF

2
1 2
VIN

3
2
1
2

2
1
PR96
PR48 4

1
PU5 0 @47K
PD26
MB3878

PR47
150K
@1SS355

1
1 24
-INC2 +INC2

2
1 2 1 2
ACOFF# <22> ADPREF ACOFF#
PR97 PQ17

2
2 1 2 23 PC37

1
75K_1% OUTC2 GND

5
6
7
8
2200PF FDS4435
PR50 PR49
D
1
47K PQ18 100K 3 22 1 2
1 2 2 2N7002 +INE2 CS
<31> PACIN PQ28 100K
G 2

1
S 4 21 1 2 PC86 @DTC115EK ACOFF <22>

1
-INE2 VCC(o)
3

PR51 0.1UF_0805_25V

1
PR53 @20K_1% 100K
PC96 69.8K_1% 1 2 1 2 5 20
<31> ACON FB2 OUT

3
@ PC39

2
PC38 PR52 0.1UF_16V

2
4700PF 10K 6 19 1 2 LXCHRG
VREF VH PC92 CC = 0~2.7A
0.1UF_0805_25V
Ich = 0.808*IREF

1
1 2 1 2 7 18 1 2
FB1 VCC PR57
PC41
0.1UF_16V
PR93
@30.1K_1% PC40 PR54
PL4
22UH_SPC-1205PA 0.02_2512_1%
CV = 17.47V BATT+
FSTCHG <22>

2
2200PF 1K 8 17 1 2 1 2 1 2
PR55 -INE1 RT

4.7UF_1210_25V
100K_1% PR56

4 . 7UF_1210_25V
1 2 9 16 66.5K_1%

4.7UF_1210_25V
1
<22> IREF +INE1 -INE3

33UF_EC_25V
PD8

1
+

PC42

PC44

PC45

PC46
1SS355

1
2 1 10 15 1 2 1 2
1

PR60 OUTC1 FB3


PD10

2
PC94 69.8K_1% PR58 PR59 PC43
EA60QC04

3
@ 10K 11 14 330K 1500PF
OUTD CTL
2

1
2

12 13 PC100 PR61
-INC1 +INC1 22PF 10K
1 2

2
CSH

PR65
150K_1%
VS 2 1 2 1

PD11 PD12 PR63


PR62 VS1 47.5K_1% PC99
RLS4148

1
100_1206 RLS4148 22PF
2 1 1 2 2 1 PC95 2 1
VIN
@22PF

2
1

1
PD13
RLS4148 PR70 PR71 PR72 PR73 PR74
1K_1206 1K_1206 1K_1206 1K_1206 1K_1206
2 1 PQ19
BATT+ TP0610T +5VP
2

2
PR67 PC49
10K 0.1UF_16V
B+
2 1 2 1 3 1 1 2

PR66 PZD2
0.22UF_1206_25V
1

200_0805 RLZ4.3B
1

1
2

PC48 PR69
PC47

PR68 0.1UF_0805_25V 150K PZD3


100K RLZ5.1B
2

2
2

1 2
<25> EC_ON#
PR75
22K

PU6 RTCVREF
S-81235SG
PR76
200_0805
CHGRTCP 2 3 1 2
IN OUT CHGRTC
1

GND
PZD4 PC50 PC51
1

RLZ16B 1UF_0805_25V 4.7UF_1206_25V


2

Compal Electronics, Inc.


2

Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Charger
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 32 of 42
B++
PL10
FBM-L11-322513-121AT
2 1
B+

PJP12 PL5 PC52


@3MM 1UH_BLM3216 2.2UF_1206_25V
2 1 SNB1 1 2
2 1

1
470PF_0805_100V
2
1UF_0805_25V
PC55 PD15

PC53
VL PD14
0.1UF_0805_25V RB751V

PC54
PR77 EC11FS2

1
1 2 BST31 1 2 22_1206

2
SNB 2 1 FLYBACK

4 2
0.1UF_0805_25V

4.7UF_1210_25V

8
7
6
5
4.7UF_1210_25V PQ26 PD16 PC56
1

1
2200PF

SI4800DY VS RB751V 0.1UF_0805_25V 1 3


PC57

PC58
PC80

PC81

2 1 BST51 1 2
PT1

4.7UF_1206_25V
2

4 DH3 B++ SDT-1205P-100-120

0.1UF_16V
10_1206

2
PR78

PR79

PC62

PC87
+12VALWP
0

4.7UF_1210_25V
0.1UF_0805_25V

4.7UF_1210_25V
1
2
3

1
LX3

1
2

PC59

PC60
2200PF
8
7
6
5

PC88

PC89
0.1UF_0805_25V
PR80

4.7UF_1210_25V
PQ27

0.1UF_0805_25V

2
4.7UF_1210_25V
0

1
PC63
SI4800DY

PC90
PC64
1

PC91

1
4 DL3

6
5
EC10QS04

2
1
PD24

2
1000PF
PC61
4
3
2

1
2
3

22

21
8
BST3 25 4 DL5 2

VL
V+
1

BST3 12OUT 5 VDD


27 VDD 18 BST5 PQ21

1
DH3 BST5

1000PF
SI4834DY

1
PL6 16 DH5

PC65
10UH_SPC-1205P 26 DH5 17 LX5
24 LX3 LX5 19
DL3 DL5

2
20
PGND
2

14
CSH3 CSH5
1 13
2 CSH3 PU7 CSL5 12 CSH5
PR107 3 CSL3 MAX1632 FB5 15
1

@0 10 FB3 SEQ 9
SKIP# REF 2.5VREF
PR81 1 2 23 6 PR108

1
0.012_2512_1% SHDN# SYNC 11 @0

4.7UF_1206_25V
PR102 7 RST# 1 2 PR82
+3VALWP

1
@0 TIME/ON5 0.015_2512_1%

PC66
2

1 2 28

GND
RUN/ON3 PR103

2
@0
1

2 1
1 5 0 U F _D_6.3V_KO

PR83
1 5 0 U F _D_6.3V_KO

PR84 +5VALWP
1
150UF_D_6.3V_KO

8
PR104 PR94
150UF_D_6.3V_KO

@0 0
BYS10-45
1

0 1 2 1 2
PD17

VL

1
+ + + +
PC67

0
PC68

PC69

PC70

@ 1 5 0 U F _D_6.3V_KO
PR105
2

150UF_D_6.3V_KO

150UF_D_6.3V_KO
1

1
0
2

BYS10-45
+ + +

PD18

PC72

PC73
PC71
2
+3VALWP

2
2
<22,24,26,30> SUSP#

100K
PR95
PD25
PR85 RB751V

2
10K
+5VP 1 2 1 2
SHDN# <31> POK <22>
1

PC74
0.047UF_16V
2

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
3.3V/5V/12V
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 33 of 42
5 4 3 2 1

PL11

D
5UH_SPC_06703 +1.8V+-5% D
2 1

+1_8VALWP
PQ22
+5VALWP PL7 PJP4
SI3445DV
@4.7UH_SLF7045T 3MM

D
6 LX18 2 1 1 2

S
4 5 +CPU_IOP +CPU_IO
2

1
1 PJP5
2

1
PR86

RB051L-40
10K + PC75 2MM

PD19
1

3
PD20 PQ23 150UF_D_6.3V_KO 1 2
+2_5V_CLKP +2_5V_CLK
PC76 RB751V PR88 2SC2411K

2
4.7UF_1206_25V 1K 1 PR87
2

2
1 2 2 10K
PJP6

1
3
3MM

2
PR89
1

@10K 1 2
PC77 +5VALWP +5VALW
2200PF
2

2
PJP7
3MM
VS 1 2
PU8A +3VALWP +3VALW

8
LM393A
3 + 3 PR90
PJP8
PQ24 2 1 38.3K_1%
C 2MM C
2SA1036K 1 - 2 2 1 2.5VREF
1 2
+12VALWP +12VALW

1
4

1
PC78 PR91
0.01UF 100K_1%
PJP9
3MM

2
1 2
+1_8VALWP +1_8VALW

B B

A A

Compal Electronics, Inc.


Title
T H I S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
A N D TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+1_8VS
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
2.0
U S E D BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC. 888L2 Main Board
Date: T h ursday, January 11, 2001 Sheet 34 of 42
5 4 3 2 1
www.s-manuals.com

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