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13 C51M--PCI-E 70 POWER_PROTECT
14 C51M--CRT & LVDS 71 POWER_SWITCH_+5VLCM
15 C51M--PWR/GND 72 POWER_DIAGRAM
16 VGA CONN
17 LVDS & INVERTER CONN
18 CRT & TV_OUT
19 MCP51--HT
20 MCP51--PCI
21 MCP51--IDE
22 MCP51--USB & HDA & GPIO
3
23 MCP51--PWR/GND 3
24 HDD & CD-ROM CONN
25 USB PORTS
26 SUPER I/O LPC47N217
27 BIOS & FIR
28 KBC 38857
29 SM BUS & POWER PORT
30 PCI-E--MINI CARD
31 PCI-E--NEW CARD
32 PCI--LAN RTL8110CL
33 RJ45 & RJ11
34 PCI--1394,CardReader R5C832
4 35 PCI--4 IN1 CON 4
5 5
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 1 OF 55 PAGE REF. RELEASE DATE : Albert Su
A B C D E
A B C D E
3S2P
1394 USB MIC LINE_IN
40,44
AMD
638 POWER
4,5,6,7
SEQENCE RESET SM_BUS
LFB LFB LFB LFB 42 42 29
LVDS & INV
2 CON 17
HT X16 2
DDR2 533/667
Nvidia PCI-E DDR
CRT & TV
VGA VGA x16
DDR2 SDRAM 533/667MHz
SODIMM X2
+1.8V
.... CAP/RES
10
CON 18
CON G7x series CON
C51MV +0.9V
8,9
72
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 2 OF 55 BLOCK DAIGRAM RELEASE DATE : Albert Su
A B C D E
A B C D E
1394 AD16 0 A
4 IN 1 0 B
GPIO_34 SUS_CLK +3VSUS GPIO47 GPI +3VS P27 GPO SCR_LED# +3V
GPIO_35 GPO WLAN_ON# +3VSUS P26 GPO NUM_LED# +3V
GPIO_36 +3VSUS P25 GPO CAP_LED# +3V
GPIO_37 GPO OP_SD# +3VSUS P24 GPO SET_PCIRSTNS# +3V
GPIO_38 GPO MXM_PWR_ON +3VS P40 GPO KBC_EXTSMI +3V
GPIO_39 GPI VGA_DETECT# +3VS P41 GPO PANLOCK_LED +3V
GPIO_40 GPO BACK_OFF# +3VS
GPIO_41 GPI VGA_PWRGD +3VS
GPIO_42 PM_CLKRUN# +3VS
GPIO_43 PCI_PERR# +3VS
GPIO_44 ACZ_SYNC +3VS
5 5
GPIO_45 ACZ_SDOUT +3VS
GPIO_46 GPO BT_ON/OFF# +3VS
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 3 OF 55 SCHEMATICS REF. RELEASE DATE : Albert Su
A B C D E
5 4 3 2 1
D D
U1A
A A
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 4 OF 55 S1 CPU HT RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
+2.5VS
L100
1 2 VDDA
+1.8V
+2.5VS +1.8V
R792
1 1KOhm 2 RN34A 1 300Ohm 2
RN35A +1.8V
3 1KOhm 4 RN34B 3 300Ohm 4
RN35B R794 10KOhm
5 1KOhm 6 RN34C 5 300Ohm 6
RN35C For future processors
7 1KOhm 8 RN34D U52A 7 300Ohm 8
RN35D 300Ohm
B VCC B
1 2 CPU_RST# CPU_VID1 1 2
11 HTCPU_RST#
R793 300Ohm
GND H_PROCHOT# PROCHOT#
PROCHOT# 28
74LVC07AD
Q109
U52B
VCC PMBS3904
3 4 CPU_PWRGD +VCORE
11 HTCPU_PWRGD
GND R797
74LVC07AD 1 2
CPU_VDD_FB PWRLMT# 22,68,71
1 2
R798 51Ohm 0Ohm R2.1
U52C CPU_VDD_FB# 1 2
VCC R799 51Ohm
5 6 CPU_STP#
11 HTCPU_STP#
GND AMD circuit is 51 ohm
74LVC07AD
+5VO
nVIDIA circuit is 10 ohm
R21 +3VSUS
Q2B Q3A Q3B +3VSUS
1KOhm UM6K1N UM6K1N UM6K1N
A
U52D U52E U52F A
5 2 5 VCC VCC VCC
C1 9 8 11 10 13 12
Q2A
UM6K1N 0.1UF/16V GND GND GND
2 74LVC07AD 74LVC07AD 74LVC07AD
22,70 PWRGD
R1.1
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 5 OF 55 S1 CPU CNTL RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
M_A_DQ[0..63] M_B_DQ[0..63]
8 M_A_DQ[0..63] 9 M_B_DQ[0..63]
U1B U1C
D D
8 M_CLK_DDR1 Y16 MA0_CLK_H2 9 M_CLK_DDR3 AF18 MB0_CLK_H2
8 M_CLK_DDR#1 AA16 MA0_CLK_L2 9 M_CLK_DDR#3 AF17 MB0_CLK_L2
E16 AA12 M_A_DQ63 A17 AD11 M_B_DQ63
8 M_CLK_DDR0 MA0_CLK_H1 MA_DATA63 M_A_DQ62 9 M_CLK_DDR2 MB0_CLK_H1 MB_DATA63 M_B_DQ62
8 M_CLK_DDR#0 F16 AB12 9 M_CLK_DDR#2 A18 AF11
MA0_CLK_L1 MA_DATA62 M_A_DQ61 MB0_CLK_L1 MB_DATA62 M_B_DQ61
AA14 AF14
MA_DATA61 M_A_DQ60 MB_DATA61 M_B_DQ60
8,10 M_A_CS#3 V19 MA0_CS_L3 MA_DATA60 AB14 9,10 M_B_CS#3 Y26 MB0_CS_L3 MB_DATA60 AE14
J22 W11 M_A_DQ59 J24 Y11 M_B_DQ59
8,10 M_A_CS#2 MA0_CS_L2 MA_DATA59 M_A_DQ58 9,10 M_B_CS#2 MB0_CS_L2 MB_DATA59 M_B_DQ58
8,10 M_A_CS#1 V22 Y12 9,10 M_B_CS#1 W24 AB11
MA0_CS_L1 MA_DATA58 M_A_DQ57 MB0_CS_L1 MB_DATA58 M_B_DQ57
8,10 M_A_CS#0 T19 MA0_CS_L0 MA_DATA57 AD13 9,10 M_B_CS#0 U23 MB0_CS_L0 MB_DATA57 AC12
AB13 M_A_DQ56 AF13 M_B_DQ56
MA_DATA56 M_A_DQ55 MB_DATA56 M_B_DQ55
8,10 M_ODT1 V20 MA0_ODT1 MA_DATA55 AD15 9,10 M_ODT3 W23 MB0_ODT1 MB_DATA55 AF15
U19 AB15 M_A_DQ54 W26 AF16 M_B_DQ54
8,10 M_ODT0 MA0_ODT0 MA_DATA54 M_A_DQ53 9,10 M_ODT2 MB0_ODT0 MB_DATA54 M_B_DQ53
AB17 AC18
MA_DATA53 M_A_DQ52 MB_DATA53 M_B_DQ52
8,10 M_A_CAS# U20 MA_CAS_L MA_DATA52 Y17 9,10 M_B_CAS# V26 MB_CAS_L MB_DATA52 AF19
U21 Y14 M_A_DQ51 U22 AD14 M_B_DQ51
8,10 M_A_WE# MA_WE_L MA_DATA51 M_A_DQ50 9,10 M_B_WE# MB_WE_L MB_DATA51 M_B_DQ50
8,10 M_A_RAS# T20 MA_RAS_L MA_DATA50 W14 9,10 M_B_RAS# U24 MB_RAS_L MB_DATA50 AC14
W16 M_A_DQ49 AE18 M_B_DQ49
MA_DATA49 M_A_DQ48 MB_DATA49 M_B_DQ48
8,10 M_A_BS#2 K22 AD17 9,10 M_B_BS#2 K26 AD18
MA_BANK2 MA_DATA48 M_A_DQ47 MB_BANK2 MB_DATA48 M_B_DQ47
8,10 M_A_BS#1 R20 MA_BANK1 MA_DATA47 Y18 9,10 M_B_BS#1 T26 MB_BANK1 MB_DATA47 AD20
T22 AD19 M_A_DQ46 U26 AC20 M_B_DQ46
8,10 M_A_BS#0 MA_BANK0 MA_DATA46 M_A_DQ45 9,10 M_B_BS#0 MB_BANK0 MB_DATA46 M_B_DQ45
AD21 AF23
MA_DATA45 M_A_DQ44 MB_DATA45 M_B_DQ44
8,10 M_CKE1 J20 MA_CKE1 MA_DATA44 AB21 9,10 M_CKE3 H26 MB_CKE1 MB_DATA44 AF24
J21 AB18 M_A_DQ43 J23 AF20 M_B_DQ43
8,10 M_CKE0 MA_CKE0 MA_DATA43 M_A_DQ42 9,10 M_CKE2 MB_CKE0 MB_DATA43 M_B_DQ42
AA18 AE20
MA_DATA42 M_A_DQ41 MB_DATA42 M_B_DQ41
8,10 M_A_A15 K19 AA20 9,10 M_B_A15 J25 AD22
MA_ADD15 MEMORY MA_DATA41 M_A_DQ40 MB_ADD15 MEMORY
MB_DATA41 M_B_DQ40
8,10 M_A_A14 K20 Y20 9,10 M_B_A14 J26 AC22
MA_ADD14 MA_DATA40 M_A_DQ39 MB_ADD14 MB_DATA40 M_B_DQ39
8,10 M_A_A13 V24 MA_ADD13 INTERFACE MA_DATA39 AA22 9,10 M_B_A13 W25 MB_ADD13 INTERFACE MB_DATA39 AE25
K24 Y22 M_A_DQ38 L23 AD26 M_B_DQ38
C
8,10 M_A_A12 MA_ADD12 MA_DATA38 M_A_DQ37 9,10 M_B_A12 MB_ADD12 MB_DATA38 M_B_DQ37 C
8,10 M_A_A11 L20 W21 9,10 M_B_A11 L25 AA25
MA_ADD11 MA_DATA37 M_A_DQ36 MB_ADD11 MB_DATA37 M_B_DQ36
8,10 M_A_A10 R19 W22 9,10 M_B_A10 U25 AA26
MA_ADD10 MA_DATA36 M_A_DQ35 MB_ADD10 MB_DATA36 M_B_DQ35
8,10 M_A_A9 L19 AA21 9,10 M_B_A9 L24 AE24
MA_ADD9 MA_DATA35 M_A_DQ34 MB_ADD9 MB_DATA35 M_B_DQ34
8,10 M_A_A8 L22 MA_ADD8 MA_DATA34 AB22 9,10 M_B_A8 M26 MB_ADD8 MB_DATA34 AD24
L21 AB24 M_A_DQ33 L26 AA23 M_B_DQ33
8,10 M_A_A7 MA_ADD7 MA_DATA33 M_A_DQ32 9,10 M_B_A7 MB_ADD7 MB_DATA33 M_B_DQ32
8,10 M_A_A6 M19 MA_ADD6 MA_DATA32 Y24 9,10 M_B_A6 N23 MB_ADD6 MB_DATA32 AA24
M20 H22 M_A_DQ31 N24 G24 M_B_DQ31
8,10 M_A_A5 MA_ADD5 MA_DATA31 M_A_DQ30 9,10 M_B_A5 MB_ADD5 MB_DATA31 M_B_DQ30
8,10 M_A_A4 M24 MA_ADD4 MA_DATA30 H20 9,10 M_B_A4 N25 MB_ADD4 MB_DATA30 G23
M22 E22 M_A_DQ29 N26 D26 M_B_DQ29
8,10 M_A_A3 MA_ADD3 MA_DATA29 M_A_DQ28 9,10 M_B_A3 MB_ADD3 MB_DATA29 M_B_DQ28
8,10 M_A_A2 N22 E21 9,10 M_B_A2 P24 C26
MA_ADD2 MA_DATA28 M_A_DQ27 MB_ADD2 MB_DATA28 M_B_DQ27
8,10 M_A_A1 N21 MA_ADD1 MA_DATA27 J19 9,10 M_B_A1 P26 MB_ADD1 MB_DATA27 G26
R21 H24 M_A_DQ26 T24 G25 M_B_DQ26
8,10 M_A_A0 MA_ADD0 MA_DATA26 M_A_DQ25 9,10 M_B_A0 MB_ADD0 MB_DATA26 M_B_DQ25
MA_DATA25 F22 MB_DATA25 E24
W12 F20 M_A_DQ24 AF12 E23 M_B_DQ24
8 M_A_DQS7 MA_DQS_H7 MA_DATA24 M_A_DQ23 9 M_B_DQS7 MB_DQS_H7 MB_DATA24
W13 C23 AE12 C24 M_B_DQ23
8 M_A_DQS#7 MA_DQS_L7 MA_DATA23 M_A_DQ22 9 M_B_DQS#7 MB_DQS_L7 MB_DATA23 M_B_DQ22
Y15 MA_DQS_H6 MA_DATA22 B22 9 M_B_DQS6 AE16 MB_DQS_H6 MB_DATA22 B24
8 M_A_DQS6 M_A_DQ21 M_B_DQ21
8 M_A_DQS#6 W15 MA_DQS_L6 MA_DATA21 F18 9 M_B_DQS#6 AD16 MB_DQS_L6 MB_DATA21 C20
AB19 E18 M_A_DQ20 AF21 B20 M_B_DQ20
8 M_A_DQS5 MA_DQS_H5 MA_DATA20 M_A_DQ19 9 M_B_DQS5 MB_DQS_H5 MB_DATA20 M_B_DQ19
8 M_A_DQS#5 AB20 MA_DQS_L5 MA_DATA19 E20 9 M_B_DQS#5 AF22 MB_DQS_L5 MB_DATA19 C25
AD23 D22 M_A_DQ18 AC25 D24 M_B_DQ18
8 M_A_DQS4 MA_DQS_H4 MA_DATA18 M_A_DQ17 9 M_B_DQS4 MB_DQS_H4 MB_DATA18 M_B_DQ17
8 M_A_DQS#4 AC23 C19 9 M_B_DQS#4 AC26 A21
MA_DQS_L4 MA_DATA17 M_A_DQ16 MB_DQS_L4 MB_DATA17 M_B_DQ16
8 M_A_DQS3 G22 G18 9 M_B_DQS3 F26 D20
MA_DQS_H3 MA_DATA16 M_A_DQ15 MB_DQS_H3 MB_DATA16 M_B_DQ15
8 M_A_DQS#3 G21 G17 9 M_B_DQS#3 E26 D18
MA_DQS_L3 MA_DATA15 M_A_DQ14 MB_DQS_L3 MB_DATA15 M_B_DQ14
8 M_A_DQS2 C22 MA_DQS_H2 MA_DATA14 C17 9 M_B_DQS2 A24 MB_DQS_H2 MB_DATA14 C18
C21 F14 M_A_DQ13 A23 D14 M_B_DQ13
8 M_A_DQS#2 MA_DQS_L2 MA_DATA13 M_A_DQ12 9 M_B_DQS#2 MB_DQS_L2 MB_DATA13 M_B_DQ12
8 M_A_DQS1 G16 E14 9 M_B_DQS1 D16 C14
MA_DQS_H1 MA_DATA12 M_A_DQ11 MB_DQS_H1 MB_DATA12 M_B_DQ11
8 M_A_DQS#1 G15 H17 9 M_B_DQS#1 C16 A20
MA_DQS_L1 MA_DATA11 M_A_DQ10 MB_DQS_L1 MB_DATA11 M_B_DQ10
8 M_A_DQS0 G13 E17 9 M_B_DQS0 C12 A19
MA_DQS_H0 MA_DATA10 M_A_DQ9 MB_DQS_H0 MB_DATA10 M_B_DQ9
8 M_A_DQS#0 H13 MA_DQS_L0 MA_DATA9 E15 9 M_B_DQS#0 B12 MB_DQS_L0 MB_DATA9 A16
B M_A_DQ8 M_B_DQ8 B
MA_DATA8 H15 MB_DATA8 A15
Y13 E13 M_A_DQ7 AD12 A13 M_B_DQ7
8 M_A_DM7 MA_DM7 MA_DATA7 M_A_DQ6 9 M_B_DM7 MB_DM7 MB_DATA7 M_B_DQ6
8 M_A_DM6 AB16 MA_DM6 MA_DATA6 C13 9 M_B_DM6 AC16 MB_DM6 MB_DATA6 D12
Y19 H12 M_A_DQ5 AE22 E11 M_B_DQ5
8 M_A_DM5 MA_DM5 MA_DATA5 M_A_DQ4 9 M_B_DM5 MB_DM5 MB_DATA5 M_B_DQ4
8 M_A_DM4 AC24 H11 9 M_B_DM4 AB26 G11
MA_DM4 MA_DATA4 M_A_DQ3 MB_DM4 MB_DATA4 M_B_DQ3
8 M_A_DM3 F24 G14 9 M_B_DM3 E25 B14
MA_DM3 MA_DATA3 M_A_DQ2 MB_DM3 MB_DATA3 M_B_DQ2
8 M_A_DM2 E19 MA_DM2 MA_DATA2 H14 9 M_B_DM2 A22 MB_DM2 MB_DATA2 A14
C15 F12 M_A_DQ1 B16 A11 M_B_DQ1
8 M_A_DM1 MA_DM1 MA_DATA1 M_A_DQ0 9 M_B_DM1 MB_DM1 MB_DATA1 M_B_DQ0
8 M_A_DM0 E12 MA_DM0 MA_DATA0 G12 9 M_B_DM0 A12 MB_DM0 MB_DATA0 C11
SOCKET638 SOCKET638
M_CLK_DDR1 M_CLK_DDR3
C133 C756
1.5PF/50V 1.5PF/50V
M_CLK_DDR#1 M_CLK_DDR#3
M_CLK_DDR0
M_CLK_DDR2
C134
A
C757 A
1.5PF/50V
1.5PF/50V
M_CLK_DDR#0
M_CLK_DDR#2
<1200 mil from CPU
<1200 mil from CPU
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 6 OF 55 S1 CPU MEM RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 7 OF 55 S1 CPU PWR/GND RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
D D
6,10 M_A_A[0..15]
CON2A
M_A_A0 102 5 M_A_DQ9 +1.8V
M_A_A1 A0 DQ0 M_A_DQ13 CON2B
101 A1 7
M_A_A2 DQ1 M_A_DQ15
100 A2 DQ2 17 112 VDD1 VSS16 18
M_A_A3 99 19 M_A_DQ11 111 24
M_A_A4 A3 DQ3 M_A_DQ8 VDD2 VSS17
98 A4 4 117 41
M_A_A5 DQ4 M_A_DQ12 VDD3 VSS18
97 A5 DQ5 6 96 VDD4 VSS19 53
M_A_A6 94 14 M_A_DQ10 95 42
M_A_A7 A6 DQ6 M_A_DQ14 VDD5 VSS20
92 A7 DQ7 16 118 VDD6 VSS21 54
M_A_A8 93 23 M_A_DQ30 81 59
M_A_A9 A8 DQ8 M_A_DQ27 VDD7 VSS22
91 25 82 65
M_A_A10 A9 DQ9 M_A_DQ25 VDD8 VSS23
105 A10/AP DQ10 35 87 VDD9 VSS24 60
M_A_A11 90 37 M_A_DQ29 103 66
M_A_A12 A11 DQ11 M_A_DQ24 VDD10 VSS25
89 A12 DQ12 20 88 VDD11 VSS26 127
M_A_A13 116 22 M_A_DQ28 +3VS 104 139
M_A_A14 A13 DQ13 M_A_DQ26 VDD12 VSS27
86 36 128
M_A_A15 A14 DQ14 M_A_DQ31 VSS28
84 A15 DQ15 38 199 VDDSPD VSS29 145
85 43 M_A_DQ51 165
6,10 M_A_BS#2 A16_BA2 DQ16 VSS30
45 M_A_DQ50 C135 83 171
DQ17 6,10 M_A_CS#2 NC1 VSS31
107 55 M_A_DQ54 120 172
6,10 M_A_BS#0 BA0 DQ18 6,10 M_A_CS#3 NC2 VSS32
106 57 M_A_DQ49 0.1U 50 177
6,10 M_A_BS#1 BA1 DQ19 NC3 VSS33
110 44 M_A_DQ55 69 187
6,10 M_A_CS#0 S0# DQ20 VTT_REF NC4 VSS34
115 46 M_A_DQ48 163 178
6,10 M_A_CS#1 S1# DQ21 NCTEST VSS35
30 56 M_A_DQ52 190
6 M_CLK_DDR0 CK0 DQ22 VSS36
32 58 M_A_DQ53 1 9
6 M_CLK_DDR#0 CK0# DQ23 VREF VSS37
164 61 M_A_DQ57 21
6 M_CLK_DDR1 CK1 DQ24 VSS38
C 166 63 M_A_DQ56 C136 201 33 C
6 M_CLK_DDR#1 CK1# DQ25 GND0 VSS39
79 73 M_A_DQ60 202 155
6,10 M_CKE0 CKE0 DQ26 GND1 VSS40
80 75 M_A_DQ61 0.1U 34
6,10 M_CKE1 CKE1 DQ27 VSS41
113 62 M_A_DQ58 203 132
6,10 M_A_CAS# CAS# DQ28 NP_NC1 VSS42
108 64 M_A_DQ59 204 144
6,10 M_A_RAS# RAS# DQ29 NP_NC2 VSS43
109 74 M_A_DQ62 156
6,10 M_A_WE# WE# DQ30 VSS44
198 76 M_A_DQ63 47 168
SA0 DQ31 M_A_DQ6 VSS1 VSS45
200 SA1 DQ32 123 133 VSS2 VSS46 2
197 125 M_A_DQ7 183 3
9,22 SMB_MEM_SCL SCL DQ33 VSS3 VSS47
195 135 M_A_DQ2 77 15
9,22 SMB_MEM_SDA SDA DQ34 VSS4 VSS48
137 M_A_DQ3 12 27
DQ35 M_A_DQ4 VSS5 VSS49
6,10 M_ODT0 114 ODT0 DQ36 124 48 VSS6 VSS50 39
119 126 M_A_DQ5 184 149
6,10 M_ODT1 ODT1 DQ37 VSS7 VSS51
134 M_A_DQ1 78 161
6 M_A_DM[0..7] DQ38 VSS8 VSS52
M_A_DM1 10 136 M_A_DQ0 71 28
M_A_DM3 DM0 DQ39 M_A_DQ42 VSS9 VSS53
26 DM1 DQ40 141 72 VSS10 VSS54 40
M_A_DM6 52 143 M_A_DQ47 121 138
M_A_DM7 DM2 DQ41 M_A_DQ44 VSS11 VSS55
67 DM3 DQ42 151 122 VSS12 VSS56 150
M_A_DM0 130 153 M_A_DQ40 196 162
M_A_DM5 DM4 DQ43 M_A_DQ46 VSS13 VSS57
147 DM5 DQ44 140 193 VSS14
M_A_DM2 170 142 M_A_DQ43 8
M_A_DM4 DM6 DQ45 M_A_DQ45 VSS15
185 152
DM7 DQ46 M_A_DQ41 DDR_DIMM_200P
6 M_A_DQS[0..7] 154
M_A_DQS1 DQ47 M_A_DQ21
13 DQS0 DQ48 157
M_A_DQS3 31 159 M_A_DQ17
M_A_DQS6 DQS1 DQ49 M_A_DQ20
51 173
M_A_DQS7 DQS2 DQ50 M_A_DQ19
70 175
M_A_DQS0 DQS3 DQ51 M_A_DQ16
131 158
M_A_DQS5 DQS4 DQ52 M_A_DQ22
B
148 DQS5 DQ53 160
M_A_DQ23
Layout Note: Place these Caps near SO DIMM 0 B
M_A_DQS2 169 174
M_A_DQS4 DQS6 DQ54 M_A_DQ18 +1.8V
6 M_A_DQS#[0..7] 188 176
M_A_DQS#1 DQS7 DQ55 M_A_DQ38
11 DQS#0 DQ56 179
M_A_DQS#3 29 181 M_A_DQ36
M_A_DQS#6 DQS#1 DQ57 M_A_DQ37
49 189
M_A_DQS#7 DQS#2 DQ58 M_A_DQ32 C137 C138 C139 C140
68 191
M_A_DQS#0 DQS#3 DQ59 M_A_DQ33
129 DQS#4 DQ60 180
M_A_DQS#5 146 182 M_A_DQ39 0.1U 0.1U 0.1U 0.1U
M_A_DQS#2 DQS#5 DQ61 M_A_DQ35
167 DQS#6 DQ62 192
M_A_DQS#4 186 194 M_A_DQ34
DQS#7 DQ63
DDR_DIMM_200P
+1.8V
A A
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 8 OF 55 DDR2 SO-DIMM0 RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
6,10 M_B_A[0..15]
D D
CON1A
M_B_A0 102 5 M_B_DQ43
M_B_A1 A0 DQ0 M_B_DQ42
101 7
M_B_A2 A1 DQ1 M_B_DQ46
100 17
M_B_A3 A2 DQ2 M_B_DQ47
99 A3 DQ3 19
M_B_A4 98 4 M_B_DQ41
M_B_A5 A4 DQ4 M_B_DQ45 +1.8V
97 6
M_B_A6 A5 DQ5 M_B_DQ44
94 A6 DQ6 14
M_B_A7 92 16 M_B_DQ40 CON1B
M_B_A8 A7 DQ7 M_B_DQ48
93 A8 DQ8 23 112 VDD1 VSS16 18
M_B_A9 91 25 M_B_DQ53 111 24
M_B_A10 A9 DQ9 M_B_DQ55 VDD2 VSS17
105 35 117 41
M_B_A11 A10/AP DQ10 M_B_DQ54 VDD3 VSS18
90 A11 DQ11 37 96 VDD4 VSS19 53
M_B_A12 89 20 M_B_DQ49 95 42
M_B_A13 A12 DQ12 M_B_DQ52 VDD5 VSS20
116 A13 DQ13 22 118 VDD6 VSS21 54
M_B_A14 86 36 M_B_DQ51 81 59
M_B_A15 A14 DQ14 M_B_DQ50 VDD7 VSS22
84 38 82 65
A15 DQ15 M_B_DQ58 VDD8 VSS23
6,10 M_B_BS#2 85 A16_BA2 DQ16 43 87 VDD9 VSS24 60
45 M_B_DQ63 103 66
DQ17 M_B_DQ56 VDD10 VSS25
6,10 M_B_BS#0 107 55 88 127
BA0 DQ18 M_B_DQ57 +3VS VDD11 VSS26
6,10 M_B_BS#1 106 BA1 DQ19 57 104 VDD12 VSS27 139
110 44 M_B_DQ62 128
6,10 M_B_CS#0 S0# DQ20 M_B_DQ59 VSS28
6,10 M_B_CS#1 115 46 199 145
S1# DQ21 M_B_DQ61 VDDSPD VSS29
6 M_CLK_DDR3 30 56 165
CK0 DQ22 M_B_DQ60 C148 VSS30
6 M_CLK_DDR#3 32 58 6,10 M_B_CS#2 83 171
CK0# DQ23 M_B_DQ35 NC1 VSS31
6 M_CLK_DDR2 164 CK1 DQ24 61 6,10 M_B_CS#3 120 NC2 VSS32 172
166 63 M_B_DQ39 0.1U 50 177
C
6 M_CLK_DDR#2 CK1# DQ25 M_B_DQ37 NC3 VSS33 C
6,10 M_CKE2 79 73 69 187
CKE0 DQ26 M_B_DQ36 VTT_REF NC4 VSS34
6,10 M_CKE3 80 75 163 178
+3VS CKE1 DQ27 M_B_DQ38 NCTEST VSS35
6,10 M_B_CAS# 113 62 190
CAS# DQ28 M_B_DQ34 VSS36
6,10 M_B_RAS# 108 RAS# DQ29 64 1 VREF VSS37 9
109 74 M_B_DQ33 21
6,10 M_B_WE# WE# DQ30 M_B_DQ32 VSS38
198 76 C149 C150 201 33
SA0 DQ31 M_B_DQ30 GND0 VSS39
200 SA1 DQ32 123 202 GND1 VSS40 155
197 125 M_B_DQ31 1U/6.3V_* 0.1U 34
8,22 SMB_MEM_SCL SCL DQ33 M_B_DQ29 VSS41
8,22 SMB_MEM_SDA 195 135 203 132
SDA DQ34 M_B_DQ24 NP_NC1 VSS42
137 204 144
DQ35 M_B_DQ26 NP_NC2 VSS43
6,10 M_ODT2 114 ODT0 DQ36 124 VSS44 156
119 126 M_B_DQ27 47 168
6,10 M_ODT3 ODT1 DQ37 M_B_DQ25 VSS1 VSS45
6 M_B_DM[0..7] DQ38 134 133 VSS2 VSS46 2
M_B_DM5 10 136 M_B_DQ28 183 3
M_B_DM6 DM0 DQ39 M_B_DQ18 VSS3 VSS47
26 141 77 15
M_B_DM7 DM1 DQ40 M_B_DQ22 VSS4 VSS48
52 DM2 DQ41 143 12 VSS5 VSS49 27
M_B_DM4 67 151 M_B_DQ20 48 39
M_B_DM3 DM3 DQ42 M_B_DQ21 VSS6 VSS50
130 DM4 DQ43 153 184 VSS7 VSS51 149
M_B_DM2 147 140 M_B_DQ19 78 161
M_B_DM0 DM5 DQ44 M_B_DQ23 VSS8 VSS52
170 DM6 DQ45 142 71 VSS9 VSS53 28
M_B_DM1 185 152 M_B_DQ17 72 40
DM7 DQ46 M_B_DQ16 VSS10 VSS54
6 M_B_DQS[0..7] 154 121 138
M_B_DQS5 DQ47 M_B_DQ0 VSS11 VSS55
13 157 122 150
M_B_DQS6 DQS0 DQ48 M_B_DQ1 VSS12 VSS56
31 DQS1 DQ49 159
M_B_DQ7
Layout Note: Place these Caps near SO DIMM 1 196 VSS13 VSS57 162
M_B_DQS7 51 173 193
M_B_DQS4 DQS2 DQ50 M_B_DQ3 +1.8V VSS14
70 175 8
M_B_DQS3 DQS3 DQ51 M_B_DQ4 VSS15
131 158
M_B_DQS2 DQS4 DQ52 M_B_DQ5 DDR2_DIMM_200P
148 160
M_B_DQS0 DQS5 DQ53 M_B_DQ6
169 DQS6 DQ54 174
B M_B_DQS1 M_B_DQ2 C151 C152 C153 C154 B
6 M_B_DQS#[0..7] 188 DQS7 DQ55 176
M_B_DQS#5 11 179 M_B_DQ9
M_B_DQS#6 DQS#0 DQ56 M_B_DQ8 0.1U 0.1U 0.1U 0.1U
29 DQS#1 DQ57 181
M_B_DQS#7 49 189 M_B_DQ13
M_B_DQS#4 DQS#2 DQ58 M_B_DQ12
68 191
M_B_DQS#3 DQS#3 DQ59 M_B_DQ11
129 180
M_B_DQS#2 DQS#4 DQ60 M_B_DQ14
146 DQS#5 DQ61 182
M_B_DQS#0 167 192 M_B_DQ15
M_B_DQS#1 DQS#6 DQ62 M_B_DQ10
186 DQS#7 DQ63 194
C160
R156 +5V
C155 C156 C157 C158 C159 0.1U VTT_REF
10K_1
1U/6.3V 1U/6.3V 1U/6.3V 1U/6.3V 1U/6.3V U5
1 V+ T21
+
4
3 -
C161 R157 V-
LMV321IDBVR C166 C758
0.01U/X7R 10K_1
1U/6.3V 1000PF/50V
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 9 OF 55 DDR2 SO-DIMM1 RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
D D
R158 47 M_CKE0
M_CKE1 M_CKE0 6,8
R159 47
M_CKE1 6,8
R168 47 M_A_BS#2
M_A_A4 M_A_BS#2 6,8
R184 47
M_A_A14 M_A_A4 6,8
R185 47
M_A_A15 M_A_A14 6,8
R187 47
M_A_A15 6,8
1 16 RN9A M_ODT3
47 M_A_CS#3 M_ODT3 6,9
2 15 RN9B
47 M_ODT0 M_A_CS#3 6,8
3 14 RN9C
47 M_ODT1 M_ODT0 6,8
4 13 RN9D
47 M_A_CS#1 M_ODT1 6,8
5 12 RN9E
47 M_A_CS#0 M_A_CS#1 6,8
6 11 RN9F
47 M_A_CS#0 6,8
7 10 RN9G
47 M_A_CAS# 6,8
8 9 RN9H
47 M_A_RAS# 6,8
1 2 RN10A M_A_BS#1
+0.9V 47OHM M_A_A13 M_A_BS#1 6,8
3 4 RN10B
47OHM M_A_A10 M_A_A13 6,8
5 6 RN10C
47OHM M_A_A10 6,8
7 8 RN10D
47OHM
C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179
1 16 RN4A M_A_A9
47 M_A_CS#2 M_A_A9 6,8
C 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 2 15 RN4B C
47 M_A_A12 M_A_CS#2 6,8
3 14 RN4C
47 M_A_A3 M_A_A12 6,8
4 13 RN4D
47 M_A_A1 M_A_A3 6,8
5 12 RN4E
47 M_A_A5 M_A_A1 6,8
6 11 RN4F
47 M_A_A8 M_A_A5 6,8
7 10 RN4G
47 M_A_A2 M_A_A8 6,8
8 9 RN4H
47 M_A_A2 6,8
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9V
1 16 RN7A M_A_A0
47 M_A_A11 M_A_A0 6,8
2 15 RN7B
47 M_A_A7 M_A_A11 6,8
3 14 RN7C
47 M_A_A6 M_A_A7 6,8
4 13 RN7D
47 M_A_A6 6,8
5 12 RN7E M_A_BS#0
+0.9V 47 M_A_WE# M_A_BS#0 6,8
+1.8V 6 11 RN7F
47 M_B_CS#2 M_A_WE# 6,8
7 10 RN7G
47 M_CKE2 M_B_CS#2 6,9
8 9 RN7H
47 M_CKE2 6,9
C180 C182 C183 C184 C185 C187 C188 C189 C190 C191
1 16 RN2A M_B_BS#2
47 M_B_A9 M_B_BS#2 6,9
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 2 15 RN2B
47 M_B_CS#1 M_B_A9 6,9
3 14 RN2C
47 M_B_CS#1 6,9
4 13 RN2D
47 M_B_CAS# 6,9
5 12 RN2E
47 M_B_A10 M_B_WE# 6,9
6 11 RN2F
47 M_B_BS#0 M_B_A10 6,9
7 10 RN2G
47 M_B_BS#0 6,9
8 9 RN2H M_B_A14
47 M_B_A14 6,9
B RN6A M_CKE3 B
1 47 16 M_CKE3 6,9
2 15 RN6B M_B_A12
47 M_B_A15 M_B_A12 6,9
3 14 RN6C
47 M_B_A11 M_B_A15 6,9
4 13 RN6D
47 M_B_A7 M_B_A11 6,9
5 12 RN6E
47 M_B_A5 M_B_A7 6,9
6 11 RN6F
47 M_B_A8 M_B_A5 6,9
7 10 RN6G
47 M_B_A4 M_B_A8 6,9
8 9 RN6H
47 M_B_A4 6,9
1 16 RN5A
47 M_B_A3
2 15 RN5B
47 M_B_A6 M_B_A3 6,9
3 14 RN5C
47 M_B_A1 M_B_A6 6,9
4 13 RN5D
47 M_B_A0 M_B_A1 6,9
5 12 RN5E
47 M_B_A2 M_B_A0 6,9
6 11 RN5F
47 M_B_A2 6,9
7 10 RN5G
47 M_B_RAS# 6,9
8 9 RN5H
47 M_B_BS#1 6,9
1 RN3A M_B_CS#0
47OHM 2 M_ODT2 M_B_CS#0 6,9
3 RN3B
47OHM 4 M_B_A13 M_ODT2 6,9
5 RN3C
47OHM 6 M_B_CS#3 M_B_A13 6,9
7 RN3D
47OHM 8 M_B_CS#3 6,9
A A
WWW.AliSaler.Com
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 10 OF 55 DDR2 ADDRESS TERMINATION RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U4A
4 HTCPU_RXDP[0..15] HTCPU_TXDP[0..15] 4
HTCPU_RXDP0 Y23 C23 HTCPU_TXDP0
HTCPU_RXDP1 HT_CPU_RXD0_P HT_CPU_TXD0_P HTCPU_TXDP1
W24 HT_CPU_RXD1_P HT_CPU_TXD1_P D23
HTCPU_RXDP2 V24 E22 HTCPU_TXDP2
HTCPU_RXDP3 HT_CPU_RXD2_P HT_CPU_TXD2_P HTCPU_TXDP3
D U22 F23 D
HTCPU_RXDP4 HT_CPU_RXD3_P HT_CPU_TXD3_P HTCPU_TXDP4
R24 H22
HTCPU_RXDP5 HT_CPU_RXD4_P HT_CPU_TXD4_P HTCPU_TXDP5
P24 HT_CPU_RXD5_P HT_CPU_TXD5_P J21
HTCPU_RXDP6 P22 K21 HTCPU_TXDP6
HTCPU_RXDP7 HT_CPU_RXD6_P HT_CPU_TXD6_P HTCPU_TXDP7
N22 K23
HTCPU_RXDP8 HT_CPU_RXD7_P HT_CPU_TXD7_P HTCPU_TXDP8
Y21 D21
HTCPU_RXDP9 HT_CPU_RXD8_P HT_CPU_TXD8_P HTCPU_TXDP9
V21 HT_CPU_RXD9_P HT_CPU_TXD9_P F19
HTCPU_RXDP10 W21 F21 HTCPU_TXDP10
HTCPU_RXDP11 HT_CPU_RXD10_P HT_CPU_TXD10_P HTCPU_TXDP11
T21 G20
HTCPU_RXDP12 HT_CPU_RXD11_P HT_CPU_TXD11_P HTCPU_TXDP12
R18 HT_CPU_RXD12_P HT_CPU_TXD12_P J19
HTCPU_RXDP13 P16 L17 HTCPU_TXDP13
HTCPU_RXDP14 HT_CPU_RXD13_P HT_CPU_TXD13_P HTCPU_TXDP14
N20 HT_CPU_RXD14_P HT_CPU_TXD14_P L20
HTCPU_RXDP15 M17 L18 HTCPU_TXDP15
HT_CPU_RXD15_P HT_CPU_TXD15_P
4 HTCPU_RXDN[0..15] HTCPU_TXDN[0..15] 4
HTCPU_RXDN0 Y22 C24 HTCPU_TXDN0
HTCPU_RXDN1 HT_CPU_RXD0_N HT_CPU_TXD0_N HTCPU_TXDN1
W23 HT_CPU_RXD1_N HT_CPU_TXD1_N D24
HTCPU_RXDN2 V23 E23 HTCPU_TXDN2
HTCPU_RXDN3 HT_CPU_RXD2_N HT_CPU_TXD2_N HTCPU_TXDN3
U21 F24
HTCPU_RXDN4 HT_CPU_RXD3_N HT_CPU_TXD3_N HTCPU_TXDN4
R23 HT_CPU_RXD4_N HT_CPU_TXD4_N H23
HTCPU_RXDN5 P23 J22 HTCPU_TXDN5
HTCPU_RXDN6 HT_CPU_RXD5_N HT_CPU_TXD5_N HTCPU_TXDN6
P21 K22
HTCPU_RXDN7 HT_CPU_RXD6_N HT_CPU_TXD6_N HTCPU_TXDN7
N21 HT_CPU_RXD7_N HT_CPU_TXD7_N K24
HTCPU_RXDN8 Y20 D22 HTCPU_TXDN8
HTCPU_RXDN9 HT_CPU_RXD8_N HT_CPU_TXD8_N HTCPU_TXDN9
W20 E20
HTCPU_RXDN10 HT_CPU_RXD9_N HT_CPU_TXD9_N HTCPU_TXDN10
W22 E21
HTCPU_RXDN11 HT_CPU_RXD10_N HT_CPU_TXD10_N HTCPU_TXDN11
U20 G19
HTCPU_RXDN12 HT_CPU_RXD11_N HT_CPU_TXD11_N HTCPU_TXDN12
R19 HT_CPU_RXD12_N HT_CPU_TXD12_N J18
HTCPU_RXDN13 P17 K17 HTCPU_TXDN13
C HTCPU_RXDN14 HT_CPU_RXD13_N HT_CPU_TXD13_N HTCPU_TXDN14 C
N19 K19
HTCPU_RXDN15 HT_CPU_RXD14_N HT_CPU_TXD14_N HTCPU_TXDN15
N18 L19
HT_CPU_RXD15_N HT_CPU_TXD15_N
B24 CLK_CPU 5
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N B23 CLK_CPU# 5
A22 1 T239
+1.2VS_HT CLKOUT_SEC_200MHZ_P T240
CLKOUT_SEC_200MHZ_N B21 1
< 500 mil; 5/10 +2.5VS
1 2 HTCPUCA_1P2V W19 Int. PU
HTCPUCA_GND HT_CPU_CAL_1P2V
R800
1 150Ohm
2 Y19 F18 HTCPU_REQ# 1 2
R801 150Ohm HT_CPU_CAL_GND HT_CPU_REQ* R802 22kOhm_*
G18 HTCPU_STP# 5
HT_CPU_STOP* breakout: 5/5
D20 HTCPU_RST# 5
HT_CPU_RESET*
HT_CPU_PWRGD E19 HTCPU_PWRGD 5 normal: 5/10
1.5" ~ 7"
+1.2VS N16 +2.5VS
L101 +1.2V_PLLHTCPU L102
1 2 +1.2VS_PLLHT T13 L16 +2.5VS_PLLHT 1 2
+1.2V_PLLHTMCP +2.5V_PLLHTCPU
B B
120Ohm/100Mhz C51MV 120Ohm/100Mhz
C759 C760 C761 C762
Near BGA
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 11 OF 55 C51M HT RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U4B
19 HTMCP_RXDP[0..7] HTMCP_TXDP[0..7] 19
D D
HTMCP_RXDP0 AD6 AC24 HTMCP_TXDP0
HTMCP_RXDP1 HT_MCP_RXD0_P HT_MCP_TXD0_P HTMCP_TXDP1
AC7 HT_MCP_RXD1_P HT_MCP_TXD1_P AD23
HTMCP_RXDP2 AA8 AC22 HTMCP_TXDP2
HTMCP_RXDP3 HT_MCP_RXD2_P HT_MCP_TXD2_P HTMCP_TXDP3
AA9 AC20
HTMCP_RXDP4 HT_MCP_RXD3_P HT_MCP_TXD3_P HTMCP_TXDP4
AD10 AB18
HTMCP_RXDP5 HT_MCP_RXD4_P HT_MCP_TXD4_P HTMCP_TXDP5
AD11 HT_MCP_RXD5_P HT_MCP_TXD5_P AA17
HTMCP_RXDP6 AC12 AB16 HTMCP_TXDP6
HTMCP_RXDP7 HT_MCP_RXD6_P HT_MCP_TXD6_P HTMCP_TXDP7
AC13 AC16
HT_MCP_RXD7_P HT_MCP_TXD7_P
AA6 HT_MCP_RXD8_P HT_MCP_TXD8_P AB21
W7 HT_MCP_RXD9_P HT_MCP_TXD9_P AB20
Y8 HT_MCP_RXD10_P HT_MCP_TXD10_P AB19
V9 W18
HT_MCP_RXD11_P HT_MCP_TXD11_P
Y10 W15
HT_MCP_RXD12_P HT_MCP_TXD12_P
AA11 HT_MCP_RXD13_P HT_MCP_TXD13_P AA15
V11 HT_MCP_RXD14_P HT_MCP_TXD14_P Y14
W12 HT_MCP_RXD15_P HT_MCP_TXD15_P W13
19 HTMCP_RXDN[0..7] HTMCP_TXDN[0..7] 19
HTMCP_RXDN0 AC6 AC23 HTMCP_TXDN0
HTMCP_RXDN1 HT_MCP_RXD0_N HT_MCP_TXD0_N HTMCP_TXDN1
AB7 AD22
HTMCP_RXDN2 HT_MCP_RXD1_N HT_MCP_TXD1_N HTMCP_TXDN2
AB8 AC21
HTMCP_RXDN3 HT_MCP_RXD2_N HT_MCP_TXD2_N HTMCP_TXDN3
AB9 HT_MCP_RXD3_N HT_MCP_TXD3_N AD20
HTMCP_RXDN4 AC10 AC18 HTMCP_TXDN4
HTMCP_RXDN5 HT_MCP_RXD4_N HT_MCP_TXD4_N HTMCP_TXDN5
AC11 AB17
HTMCP_RXDN6 HT_MCP_RXD5_N HT_MCP_TXD5_N HTMCP_TXDN6
AB12 AB15
HTMCP_RXDN7 HT_MCP_RXD6_N HT_MCP_TXD6_N HTMCP_TXDN7
AB13 AD16
HT_MCP_RXD7_N HT_MCP_TXD7_N
Y6 HT_MCP_RXD8_N HT_MCP_TXD8_N AB22
Y7 HT_MCP_RXD9_N HT_MCP_TXD9_N AA20
C AA7 AA19 C
HT_MCP_RXD10_N HT_MCP_TXD10_N
W9 V17
HT_MCP_RXD11_N HT_MCP_TXD11_N
W10 V15
HT_MCP_RXD12_N HT_MCP_TXD12_N
Y12 HT_MCP_RXD13_N HT_MCP_TXD13_N Y15
W11 W14
HT_MCP_RXD14_N HT_MCP_TXD14_N
V13 HT_MCP_RXD15_N HT_MCP_TXD15_N Y13
OD AB5
breakout: 5/5 19 HTMCP_REQ# HT_MCP_REQ*
19 HTMCP_STP# AA5 HT_MCP_STOP*
normal: 5/10 1.5" ~ 7" AC5
19 HTMCP_RST# HT_MCP_RESET*
19 HTMCP_PWRGD
1.5" ~ 7" OD AD5 B22 CLKOUT_CTERM_GND 1 2
HT_MCP_PWRGD CLKOUT_CTERM_GND R805 2.37KOhm
SCLKIN_MCLKOUT_200MHZ_P A20
SCLKIN_MCLKOUT_200MHZ_N B20
A A
WWW.AliSaler.Com
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 12 OF 55 C51M HT TO MCP RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U4C
16 EXP_RXP[0..15] EXP_TXP[0..15] 16
EXP_RXP15 J8 L1 EXP_TXP15
EXP_RXP14 PE0_RX0_P PE0_TX0_P EXP_TXP14
J6 PE0_RX1_P PE0_TX1_P L3
EXP_RXP13 K9 L4 EXP_TXP13
EXP_RXP12 PE0_RX2_P PE0_TX2_P EXP_TXP12
D L6 M4 D
EXP_RXP11 PE0_RX3_P PE0_TX3_P EXP_TXP11
L7 P1
EXP_RXP10 PE0_RX4_P PE0_TX4_P EXP_TXP10
M9 PE0_RX5_P PE0_TX5_P R1
EXP_RXP9 N8 R3 EXP_TXP9
EXP_RXP8 PE0_RX6_P PE0_TX6_P EXP_TXP8
N6 R4
EXP_RXP7 PE0_RX7_P PE0_TX7_P EXP_TXP7
R6 U4
EXP_RXP6 PE0_RX8_P PE0_TX8_P EXP_TXP6
P3 PE0_RX9_P PE0_TX9_P V1
EXP_RXP5 R8 W1 EXP_TXP5
EXP_RXP4 PE0_RX10_P PE0_TX10_P EXP_TXP4
U6 W3
EXP_RXP3 PE0_RX11_P PE0_TX11_P EXP_TXP3
T8 PE0_RX12_P PE0_TX12_P AA1
EXP_RXP2 U7 AB1 EXP_TXP2
EXP_RXP1 PE0_RX13_P PE0_TX13_P EXP_TXP1
V4 PE0_RX14_P PE0_TX14_P AC1
EXP_RXP0 Y3 AD2 EXP_TXP0
PE0_RX15_P PE0_TX15_P
16 EXP_RXN[0..15] EXP_TXN[0..15] 16
EXP_RXN15 J7 L2 EXP_TXN15
EXP_RXN14 PE0_RX0_N PE0_TX0_N EXP_TXN14
J5 PE0_RX1_N PE0_TX1_N M2
EXP_RXN13 J9 M3 EXP_TXN13
EXP_RXN12 PE0_RX2_N PE0_TX2_N EXP_TXN12
L5 N3
EXP_RXN11 PE0_RX3_N PE0_TX3_N EXP_TXN11
L8 PE0_RX4_N PE0_TX4_N P2
EXP_RXN10 M8 R2 EXP_TXN10
EXP_RXN9 PE0_RX5_N PE0_TX5_N EXP_TXN9
N7 T2
EXP_RXN8 PE0_RX6_N PE0_TX6_N EXP_TXN8
N5 PE0_RX7_N PE0_TX7_N T3
EXP_RXN7 R5 U3 EXP_TXN7
+3VS EXP_RXN6 PE0_RX8_N PE0_TX8_N EXP_TXN6
P4 V2
EXP_RXN5 PE0_RX9_N PE0_TX9_N EXP_TXN5
R7 W2
EXP_RXN4 PE0_RX10_N PE0_TX10_N EXP_TXN4
U5 Y2
EXP_RXN3 PE0_RX11_N PE0_TX11_N EXP_TXN3
T9 PE0_RX12_N PE0_TX12_N AA2
EXP_RXN2 U8 AB2 EXP_TXN2
C R808 EXP_RXN1 PE0_RX13_N PE0_TX13_N EXP_TXN1 C
V3 AC2
EXP_RXN0 PE0_RX14_N PE0_TX14_N EXP_TXN0
16,20 GPU_ON 1 2 AA3 AD3
R7141 0Ohm_* 10KOhm PE0_RX15_N PE0_TX15_N
AC3 PE_REFCLKIN_P
AB3 G1 PE_RST# 16,30
PE_REFCLKIN_N PE_RESET*
+1.2VS
L103
B +1.2VS_PLLPE B
1 2 T11 +1.2V_PLLPE PE_CTERM_GND D2 1 2
R810 2.37KOhm
120Ohm/100Mhz C51MV
C767 C768
1UF/16V_* 0.1UF/16V
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 13 OF 55 C51M PCI-E RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U4D
DAC_R_C51M A5 C14
DAC_G_C51M DAC_RED IFPA_TXC_P LVDS_CLKAP_C51M 17
B6 B13 LVDS_CLKAN_C51M 17
DAC_B_C51M DAC_GREEN IFPA_TXC_N
A6
DAC_BLUE
IFPA_TXD0_P A15 LVDS_YA0P_C51M 17
18 DAC_HSYNC_C51M B7 DAC_HSYNC IFPA_TXD1_P D15 LVDS_YA1P_C51M 17
18 DAC_VSYNC_C51M C7 A14 LVDS_YA2P_C51M 17
R813 R814 R815 DAC_VSYNC IFPA_TXD2_P
D F14 D
IFPA_TXD3_P
150Ohm 150Ohm 150Ohm B15
DAC_RSET IFPA_TXD0_N LVDS_YA0N_C51M 17
D8 DAC_RSET IFPA_TXD1_N C15 LVDS_YA1N_C51M 17
DAC_VREF D9 B14
DAC_VREF IFPA_TXD2_N LVDS_YA2N_C51M 17
C8 E14
R816 R817 C769 DAC_IDUMP IFPA_TXD3_N
Place near C51M IFPB_TXC_P
A10 LVDS_CLKBP_C51M 17
124Ohm_*124Ohm 0.01UF/25V B10
IFPB_TXC_N LVDS_CLKBN_C51M 17
+3VS B11
IFPB_TXD4_P LVDS_YB0P_C51M 17
L104 10 mA E13
+3VS_DAC IFPB_TXD5_P LVDS_YB1P_C51M 17
1 2 A9 D13 LVDS_YB2P_C51M 17
+3.3V_DAC IFPB_TXD6_P
B12
120Ohm/100Mhz C770 C771 IFPB_TXD7_P
+3VS
PKG_TEST D17
TEST_MODE_EN C17 1 2
R820 1KOhm
+1.2VS R821 R822
22KOhm_* 22KOhm_*
1 2 +1.2VS_PLLGCI R9 C18 2 1
R823 0Ohm +1.2V_PLLGPU JTAG_TCK
JTAG_TDI B19 R824 22KOhm_*
P9 +1.2V_PLLCORE JTAG_TDO C19
C780 C781 B18
JTAG_TMS
H16 A19
0.1UF/16V 0.1UF/16V +1.2V_PLLIFP JTAG_TRST*
C51MV +5VS
R825
TV SLI Mux Between C51 & G7X
22KOhm_*
C7109
TV_C_NV
B TV_Y_NV 0.1UF/16V B
Place near connector
TV_CVBS_NV
U54
17,18,22 IGP_SELECT 1 S VCC 16
16 TV_C_NV 2 15
R201 R202 R203 TVDAC_C_NB IA0 E#
C51MV TV/CRT 3
4
IA1 ID0
14
13
LCD_BACKEN_NV 16
SELECT +5VS 150_1 150_1 150_1
18
16
TV_C
TV_Y_NV 5
YA
IB0
ID1
YD 12
LCD_BKLEN_C51M 23
LCD_BACKEN 17
+3VS TVDAC_Y_NB 6 11
IB1 IC0 TV_CVBS_NV 16
7 10 TVDAC_CVBS_NB
18 TV_Y YB IC1
R1.1 8 9 TV_CVBS 18
C7110 GND YC
Place near switch
R826 PI5C3257QE
0.1UF/16V
22KOhm
R827 0Ohm U53 +5VS
22 MCP_TV_EN 1 2 1 S 16
DAC_R_NB VCC
TVDAC_C_NB
2
3
IA0 E#
15
14 LOAD_VIDEO
CRT SLI Mux Between C51 & G7X
DAC_R_C51M IA1 ID0 LOAD_VGA C7111
4 YA ID1 13
DAC_G_NB 5 12 DAC_R_NV Place near connector
TVDAC_Y_NB IB0 YD DAC_B_NB LOAD_TEST 22 DAC_G_NV
6 11 0.1UF/16V
DAC_G_C51M IB1 IC0 TVDAC_CVBS_NB DAC_B_NV
7 10
YB IC1 DAC_B_C51M U55
8 9
GND YC IGP_SELECT 1 S VCC 16
PI5C3257QE 2 15
16 DAC_R_NV DAC_R_NB IA0 E#
Place near connector R204 R205 R206 3 14
IA1 ID0 LCD_VDD_EN_NV 16
R31 R32 R33 4 13
18 DAC_R_CRT YA ID1 LCD_VDDEN_C51M 23
1 RN36A 150_1 150_1 150_1
A 10KOhm 2 16 DAC_G_NV DAC_G_NB
5
IB0 YD
12 LCD_VDD_EN 17 A
150Ohm 150Ohm
10KOhm 4 RN36B
3 150Ohm 6 11
IB1 IC0 DAC_B_NB DAC_B_NV 16
5 RN36C
10KOhm 6 18 DAC_G_CRT 7
YB IC1
10
7 10KOhm 8
RN36D R1.1 8 GND YC 9 DAC_B_CRT 18
R1.1 R1.1 Place near switch
PI5C3257QE
Place near switch Place near
switch
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 14 OF 55 C51M CRT&LVDS RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U4F
C1 GND1 V19
GND34
AA21 GND2 GND35 T14
+1.2VS_CORE +1.2VS AA13 C20
GND3 GND36
5.6A C51MV U4E
U14 GND4 GND37
R17
D 300 mA L108 H14 AB14 D
3.5A C51M +1.2VS_NBCORE +1.2VS_PEA GND5 GND38
B5 +1.2V_CORE1 A3 1 2 C11 U12
+1.2V_PEA1 GND6 GND39
C6 +1.2V_CORE2 +1.2V_PEA2 B3 AB4 GND7 GND40 G13
C783 C784 C785 C786 C787 C788 D7 C4 C789 C790 C791 C792 C793 C794 C795 C796 120Ohm/100Mhz AA4 Y16
+1.2V_CORE3 +1.2V_PEA3 GND8 GND41
E8 D5 J15 H21
22UF/6.3V 22UF/6.3V 1UF/10V 1UF/10V 1UF/10V 1UF/10V +1.2V_CORE4 +1.2V_PEA4 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/10V 1UF/10V 22UF/6.3V 22UF/6.3V GND9 GND42
E9 E6 E12 C22
+1.2V_CORE5 +1.2V_PEA5 GND10 GND43
E10 +1.2V_CORE6 +1.2V_PEA6 F7 AB10 GND11 GND44 AB6
F10 F8 Y18 F22
+1.2V_CORE7 +1.2V_PEA7 GND12 GND45
F11 F9 E18 L22
+1.2V_CORE8 +1.2V_PEA8 GND13 GND46
G11 +1.2V_CORE9 U18 GND14 GND47 R22
C797 C798 C799 C800 C801 H11 E15 V22
+1.2V_CORE10 GND15 GND48
J11 +1.2V_CORE11 Y11 GND16 GND49 AA22
1UF/10V 1UF/10V 1UF/10V 0.1UF/16V 0.1UF/16V J12 L109 U19 A23
+1.2V_CORE12 +1.2VS_PLL GND17 GND50
J13
+1.2V_CORE13 +1.2V_PLL1
A2 260 mA 1 2 N17
GND18 GND51
AA23
J14 +1.2V_CORE14 +1.2V_PLL2 B2 F16 GND19 GND52 AA24
C2 C802 C803 C804 C805 C806 C807 C808 C809 120Ohm/100Mhz J17 L11
+1.2VS_HTMCP +1.2V_PLL3 GND20 GND53
1 2 200 mA T15 +1.2V_HTMCP1 +1.2V_PLL4 C3 L13 GND21 GND54 M11
R831 0Ohm U13 D4 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 4.7U/6.3V 47UF/6.3V B1 N11
+1.2VS C810 C811 C812 +1.2V_HTMCP2 +1.2V_PLL5 GND22 GND55
U11 E5 T17 P11
+1.2V_HTMCP3 +1.2V_PLL6 GND23 GND56
Y9 +1.2V_HTMCP4 +1.2V_PLL7 F6 D11 GND24 GND57 M12
1UF/10V 1UF/10V 1UF/10V AB11 G7 T12 N12
+1.2V_HTMCP5 +1.2V_PLL8 GND25 GND58
AA18 G8 J16 P12
+1.2V_HTMCP6 +1.2V_PLL9 GND26 GND59
W16 +1.2V_HTMCP7 +1.2V_PLL10 G9 D19 GND27 GND60 M13
U16 +1.2V_HTMCP8 +1.2V_PLL11 H10 H19 GND28 GND61 N13
1 2 150 mA +1.2VS_PED U15 J10 +2.5VS L21 P13
R832 0Ohm +1.2V_HTMCP9 +1.2V_PLL12 GND29 GND62
M19 M14
C813 C814 +2.5VS_CORE GND30 GND63
B4
+1.2V_PED1 200 mA 1 2 P19
GND31 GND64
N14
C5 R833 0Ohm T19 P14
0.1UF/16V 0.1UF/16V +1.2V_PED2 C815 C816 GND32 GND65
D6 +1.2V_PED3 L14 GND33 GND66 L12
C +1.2VS_HT E7 C
+1.2V_PED4 0.1UF/16V 0.1UF/16V
K16 C16 +1.8VS
+1.2VS_C51MHT 370 mA +1.2V_HT1 +2.5V_CORE_1
1 2 M16 +1.2V_HT2 +2.5V_CORE_2 B16
R834 0Ohm R16 L110
C817 C818 C819 C820 C821 +1.2V_HT3 +1.8VS_IFPAB 100 mA 1
M21 +1.2V_HT4 +2.5V_IFPA G15 2
J20 +1.2V_HT5 +2.5V_IFPB H15
47UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V T16 C822 C823 120Ohm/100Mhz
+1.2V_HT6
U17 F3 K6
+1.2V_HT7 0.1UF/16V 1UF/10V PE_GND1 PE_GND12
C21 L9 M6
+1.2V_HT8 PE_GND2 PE_GND13
H17 +1.2V_HT9 P8 PE_GND3 PE_GND14 P6
C824 C825 C826 C827 N9 T6
+3VS PE_GND4 PE_GND15
K4 PE_GND5 PE_GND16 W6
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V D18 N4 W8
+3.3V_1 PE_GND6 PE_GND17
C10 T4 H8
+3.3V_2 PE_GND7 PE_GND18
15 mA W4 PE_GND8 PE_GND19 K8
C51MV Y4 PE_GND9 PE_GND20 V6
C828 U9 F4
PE_GND10 PE_GND21
H9 PE_GND11 PE_GND22 V8
1UF/10V
C51MV
B B
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 15 OF 55 C51M PWR/GND RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 16 OF 55 VGA CONN RELEASE DATE : Albert Su
5 4 3 2 1
A B C D E
+1.8_2.1VS
LVDS A Channel SLI MUX
+1.8VS +1.8V +1.8V 5,7,8,9,10,38,65
+1.8_2.1VS
+3VS +3VS 5,8,9,13,14,15,16,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+3VSUS +3VSUS 5,20,22,23,28,29,32,42,46,48,70
+12VS +12VS 16
Vref=1.215V 1 2
U56A +3VS R38 0Ohm_*
U31 +2.1VS
1 16 LVDS_YA0P_NV 38 0B1 GND1 1 1 VIN 1
37 2 LVDS_YA0P 5 1 2
16 LVDS_YA0N_NV 1B1 A0 LVDS_YA0N VOUT
36 3 2 R36 R37 0Ohm
16 LVDS_YA1P_NV 2B1 A1 GND
16 LVDS_YA1N_NV 35 3B1 4 4 1 2
GND2 FB FootPrinter from 12-172010300
14 LVDS_YA0P_C51M 34 0B2 5 3
VDD1 LVDS_YA1P SD# 34KOhm CON4 LVDS_CON
14 LVDS_YA0N_C51M 33 1B2 A2 6
32 7 LVDS_YA1N C15
14 LVDS_YA1P_C51M 2B2 A3 SI9183DT
31 8 R35 C14 30 29 +LCD_VCC
14 LVDS_YA1N_C51M 3B2 VDD2 IGP_SELECT +LCD_VCC 30 29 +LCD_VCC
30 9 1UF/16V 47KOhm 4.7U/6.3V 28 27
VDD6 SEL IGP_SELECT 14,18,22 +3VS EDID_CLK 28 27 EDID_DATA
16 LVDS_YA2P_NV 29 4B1 GND3 10 26 26 25 25
28 11 LVDS_YA2P 24 23
16 LVDS_YA2N_NV 5B1 A4 LVDS_YA2N LVDS_YB0N 24 23 LVDS_YA0N
16 LVDS_CLKAP_NV 27 6B1 12 22 21
A5 LVDS_YB0P 22 21 LVDS_YA0P
16 LVDS_CLKAN_NV 26 7B1 VDD3 13 20 20 19 19
25 14 +3VS 18 17
14 LVDS_YA2P_C51M 4B2 GND4 LVDS_CLKAP LVDS_YB1N 18 17 LVDS_YA1N
14 LVDS_YA2N_C51M 24 5B2 A6 15 16 16 15 15
23 16 LVDS_CLKAN LVDS_YB1P 14 13 LVDS_YA1P
14 LVDS_CLKAP_C51M 6B2 A7 14 13
22 17 C228 12 11
14 LVDS_CLKAN_C51M 7B2 GND5 LVDS_YB2N 12 11 LVDS_YA2N
U56B 10 9
0.1U LVDS_YB2P 10 9 LVDS_YA2P
44 GND11 8 8 7 7
45 GND12 6 6 5 5
PI2PCIE412E 46 LVDS_CLKBN 4 3 LVDS_CLKAN
GND13 LVDS_CLKBP 4 3 LVDS_CLKAP
47 2 1
GND14 2 1
2 PI2PCIE412E 2
+1.8_2.1VS
LVDS B Channel SLI MUX
+3VS +3VS
U57A
EDID SLI MUX
16 LVDS_CLKBP_NV 38 0B1 GND1 1
37 2 LVDS_CLKBP +3VS R7116 R7117 R188 R189
16 LVDS_CLKBN_NV 1B1 A0 LVDS_CLKBN
36 3 2.7K 2.7K
16 LVDS_YB2P_NV 2B1 A1
35 4 Q110A 10K 10K
16 LVDS_YB2N_NV 3B1 GND2
34 5 UM6K1N
14 LVDS_CLKBP_C51M 0B2 VDD1 LVDS_YB2P
33 6 6 1 EDID_CLK
14 LVDS_CLKBN_C51M 1B2 A2 LVDS_YB2N 16 EDID_CLK_NV
32 7 R7120
14 LVDS_YB2P_C51M 2B2 A3
31 8 47K 3 4 EDID_DATA
14 LVDS_YB2N_C51M 3B2 VDD2 IGP_SELECT 16 EDID_DATA_NV
30 VDD6 9
SEL Q110B
3 16 LVDS_YB0P_NV 29 4B1 10 3
GND3 LVDS_YB0P UM6K1N C229 C230
16 LVDS_YB0N_NV 28 5B1 A4 11
27 12 LVDS_YB0N
16 LVDS_YB1P_NV 6B1 A5 18 NV_DDC_EN
26 13 100P 100P
16 LVDS_YB1N_NV 7B1 VDD3 3
14 LVDS_YB0P_C51M 25 4B2 GND4 14 D
24 15 LVDS_YB1P +3VS
14 LVDS_YB0N_C51M 5B2 A6 LVDS_YB1N
23 16 Q111
14 LVDS_YB1P_C51M 6B2 A7 1
22 17 2N7002
14 LVDS_YB1N_C51M 7B2 GND5 18,22 IGP_DDC_SELECT
U57B G
44 2 S
GND11 R7121 R7122
45 GND12
PI2PCIE412E_* 46 2.7K 2.7K
GND13 Q112A
47
GND14 UM6K1N
PI2PCIE412E_* 6 1
22 EDID_CLK_C51M
22 EDID_DATA_C51M 3 4
Q112B
R736 100 UM6K1N
Q4
2N7002
4 INVERTOR 4
CNT
+3VSUS +12VS +3VS
L14 80/2A
AC_BAT_SYS
C231 CON5
R192 R193 1
Q5 0.1U/X7R VCC1
2 8
10K 1M VCC2 8
1 6 3
D1 D GND1
2 5 4
S 4 L15 1K/300mA GND2
1 2 3 28 ADJ_BL 5 VREF 9 9
G +LCD_VCC R194 100K L16 1K/300mA 6
+LCD_VCC BKEN
1SS355 PMN45EN 7
R195 470K L17 80/2A D11 RB717F C232 C233 PWM
1 Inverter_CON
41,42 LID_SW#
5 C234 3 0.1U 0.1U
Q8B 2
20 BACK_OFF#
C235 UM6K1N 1000P C236 C237 C238 C239
14 LCD_VDD_EN 2
Q8A 0.1U/X7R 0.1U 0.1U 10U/10V 10U/10V D2 F01J4L
UM6K1N 2 1
14 LCD_BACKEN
R198
5 5
10K R26
10K
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 17 OF 55 LVDS,INVERTER CONN RELEASE DATE : Albert Su
A B C D E
A B C D E
D6
+5VS 1 2
+3VS
1SS355
+2.5VS +2.5VS 5,11,14,15,16,38,48
R828 R829
+3VS +3VS 5,8,9,13,14,15,16,17,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
1 RN43A
2.2kOhm2 +5V +5V 9,16,25,28,31,38,40,41
3 RN43B 2.2KOhm 2.2KOhm
2.2kOhm4 +5VS +5VS 14,23,24,28,29,36,37,38,39,40,41,61
Q113A
1 UM6K1N 1
6 1 DDC2BC_5
16 DDC2BC_NV
3 4 DDC2BD_5
16 DDC2BD_NV
Q113B
UM6K1N DAC_R_CRT L18 0.068U/300mA RED
14 DAC_R_CRT
17 NV_DDC_EN DAC_G_CRT GREEN
L19 0.068U/300mA
14 DAC_G_CRT
DAC_B_CRT L20 0.068U/300mA BLUE
+3VS 14 DAC_B_CRT
DDC2BD_5 L21 120/400mA DDC2BD
5 RN43C
2.2kOhm6 HSYNC_CRT HSYNC
7 RN43D Q114A R199 33_0603
2.2kOhm8
UM6K1N
6 1 VSYNC_CRT R200 33_0603 VSYNC
22 DDC2BC_C51M
3 4 DDC2BC_5 L22 120/400mA DDC2BC
22 DDC2BD_C51M
Q114B
UM6K1N
D3 D4 D5
17,22 IGP_DDC_SELECT
2 C241 C242 C243 C244 C245 C246 C247 C248 C249 C250 2
BAV99_* BAV99_* BAV99_*
8.2P 8.2P 8.2P 8.2P 8.2P 8.2P 82P 10P 10P 82P
DDC MUX Between C51 & G7X
+2.5VS
3 U58C
D
Q115 VCC VSYNC_CRT
14 DAC_VSYNC_C51M 9 8
1 2N7002 GND
14,17,22 IGP_SELECT
G
2 S SN74HCT125DR
16 HDTV_EN# 1 2
+5V IGP_SELECT R46 0Ohm_*
4 4
U58B TV_C L23 1.8U/50mA
14 TV_C
16 DAC_HSYNC_NV 5 VCC 6
GND +3VS D7 BAV99_* C251 C252 3 CON7
GND1
1 1 GND0
SN74HCT125DR 3 TV_C 82P 82P
2 5
C_CON NC
+5V D8 BAV99_*
+5V IGP_SELECT 1 6
C
3 TV_Y 14 TV_Y
TV_Y L24 1.8U/50mA Y_CON 4 Y
C240 2
7
0.1U U58D D9 BAV99_* C253 C254 CVBS_CON CVBS2
2
CVBS1 MINI_DIN_7P
1
16 DAC_VSYNC_NV 12 VCC 11 3 TV_CVBS 82P 82P
GND 2
SN74HCT125DR
5 5
C255 C256
82P 82P
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 18 OF 55 CRT & TV OUT RELEASE DATE : Albert Su
A B C D E
5 4 3 2 1
U3A
12 HTMCP_TXDP[0..7] HTMCP_RXDP[0..7] 12
HTMCP_TXDP0 K1 AA1 HTMCP_RXDP0
HTMCP_TXDP1 HT_MCP_RXD0_P HT_MCP_TXD0_P HTMCP_RXDP1
L1 HT_MCP_RXD1_P HT_MCP_TXD1_P Y1
HTMCP_TXDP2 M1 AA3 HTMCP_RXDP2
HTMCP_TXDP3 HT_MCP_RXD2_P HT_MCP_TXD2_P HTMCP_RXDP3
D N1 W5 D
HTMCP_TXDP4 HT_MCP_RXD3_P HT_MCP_TXD3_P HTMCP_RXDP4
R1 U5
HTMCP_TXDP5 HT_MCP_RXD4_P HT_MCP_TXD4_P HTMCP_RXDP5
T1 HT_MCP_RXD5_P HT_MCP_TXD5_P T5
HTMCP_TXDP6 U1 R5 HTMCP_RXDP6
HTMCP_TXDP7 HT_MCP_RXD6_P HT_MCP_TXD6_P HTMCP_RXDP7
V1 P5
HT_MCP_RXD7_P HT_MCP_TXD7_P
12 HTMCP_TXDN[0..7] HTMCP_RXDN[0..7] 12
HTMCP_TXDN0 K2 AA2 HTMCP_RXDN0
HTMCP_TXDN1 HT_MCP_RXD0_N HT_MCP_TXD0_N HTMCP_RXDN1
L2 Y2
HTMCP_TXDN2 HT_MCP_RXD1_N HT_MCP_TXD1_N HTMCP_RXDN2
M2 HT_MCP_RXD2_N HT_MCP_TXD2_N AA4
HTMCP_TXDN3 N2 W6 HTMCP_RXDN3
HTMCP_TXDN4 HT_MCP_RXD3_N HT_MCP_TXD3_N HTMCP_RXDN4
R2 HT_MCP_RXD4_N HT_MCP_TXD4_N U6
HTMCP_TXDN5 T2 T6 HTMCP_RXDN5
HTMCP_TXDN6 HT_MCP_RXD5_N HT_MCP_TXD5_N HTMCP_RXDN6
U2 R6
HTMCP_TXDN7 HT_MCP_RXD6_N HT_MCP_TXD6_N HTMCP_RXDN7
V2 HT_MCP_RXD7_N HT_MCP_TXD7_N P6
12 HTMCP_TXCLK0 P1 V5 HTMCP_RXCLK0 12
HT_MCP_RX_CLK_P HT_MCP_TX_CLK_P
12 HTMCP_TXCLK0# P2 V6 HTMCP_RXCLK0# 12
HT_MCP_RX_CLK_N HT_MCP_TX_CLK_N
12 HTMCP_TXCTL W1 N5 HTMCP_RXCTL 12
HT_MCP_RXCTL_P HT_MCP_TXCTL_P
12 HTMCP_TXCTL# W2 HT_MCP_RXCTL_N HT_MCP_TXCTL_N N6 HTMCP_RXCTL# 12
C 1 2 HTMCP_COMP_GND1 AB1 Y5 1 2 C
HTMCP_COMP_GND2 AB2 HT_MCP_COMP_GND1 CLKOUT_25MHZ CLK_25M 12
R8381 2 150Ohm AD2 R839 22Ohm
HT_MCP_COMP_GND2 HT_MCP_PWRGD HTMCP_PWRGD 12
R840 49.9Ohm AE1
HT_MCP_RST# HTMCP_RST# 12
THERMTRIP#/GPIO_58 J6 CPU_THRMTRIP# 5
K6 2 1
VDLT_PWRGD CLK200_TERM_GND R841 976Ohm
48 HT_VLD F22 HT_VLD
VCORE_PWRGD N26
61,70 CPUPWR_GD VDDIO_PWRGD CPU_VLD
48 MEM_VLD M24 MEM_VLD
67 HTVDD_EN 1 2 F23
R7134 0Ohm HTVDD_EN
61 CPU_VRON N25
CPUVDD_EN
+1.5VS 1 2 150 mA
HTVDD_EN R843 0Ohm +3VS
C829
H22 1 RN1A
JTAG_TCK 10KOhm2
C7112 0.1UF/16V H21 3 RN1B
JTAG_TDI 10KOhm4
+3VS H23
0.1UF/16V_* L111 JTAG_TDO RN1C
M6 +1.5V_PLL_CPU_HT JTAG_TMS D26 5 10KOhm6
1 2 +3VS_PLL_CPUHT 20 mA M5 F25 7 RN1D
+3.3V_PLL_CPU_HT JTAG_TRST# 10KOhm8
120Ohm/100Mhz MCP51
C830 C4 C5 C831
B B
+3VS
HTMCP_RST#
HTMCP_REQ#
HTMCP_STP#
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 19 OF 55 MCP51 HT I/F RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
D D
PCI_AD[0..31] U3B
32,34 PCI_AD[0..31] +3VS
PCI_AD0 AF19 AA22 PCI_REQ#0
PCI_AD1 PCI_AD0 PCI_REQ0# PCI_REQ#1 PCI_REQ#0 34 PCI_FRAME#
AB21 AE22 RP6A 1 5
PCI_AD2 PCI_AD1 PCI_REQ1# PCI_REQ#2 PCI_REQ#1 32 8.2K
AC19 PCI_AD2 AF21 10
PCI_AD3 PCI_REQ2# MXM_PWR_ON PCI_IRDY# RP6B
AA20 PCI_AD3 AF22 MXM_PWR_ON 16 2 8.2K 5
PCI_AD4 PCI_REQ3#/GPIO_38
AA19 PCI_AD4 PCI_REQ4#/GPIO_40 AE23 BACK_OFF# 17 10
PCI_AD5 AF20 PCI_TRDY# RP6C 3 5
PCI_AD6 PCI_AD5 8.2K
AE19 PCI_AD6 10
PCI_AD7 AE20 AE21 PCI_GNT#0 PCI_STOP# RP6D 4 5
PCI_AD8 PCI_AD7 PCI_GNT0# PCI_GNT#0 34 8.2K
AB20 AC21 PCI_GNT#1 PCI_GNT#1 32 10
PCI_AD9 PCI_AD8 PCI_GNT1# PCI_SERR#
AB19 PCI_AD9 PCI_GNT2# AA21 T2451 RP6E 6 8.2K 5
PCI_AD10 AA18 AB24 1 2 10
PCI_AD11 PCI_AD10 PCI_GNT3#/GPIO_39 VGA_DETECT# 13,16 PCI_DEVSEL#
AB18 PCI_AD11 PCI_GNT4#/GPIO_41 AB22 R103
1 20Ohm VGA_PWRGD 16,70
RP6F 7 8.2K 5
PCI_AD12 AE18 R102 0Ohm_* 10
PCI_AD13 PCI_AD12 PCI_PERR# RP6G
AF18 8 8.2K 5
PCI_AD14 PCI_AD13 PCI_INTA#
AC17 PCI_AD14 PCI_INTW# AE11 PCI_INTA# 34 10
PCI_AD15 AA17 AB11 PCI_INTB# PM_CLKRUN# RP6H 9 5
PCI_AD16 PCI_AD15 PCI_INTX# PCI_INTB# 34 8.2K
AB15 AC11 PCI_INTC# 10
PCI_AD17 PCI_AD16 PCI_INTY# PCI_INTD# PCI_INTC# 32
AF15 PCI_AD17 PCI_INTZ# AA11
PCI_AD18 AE15
PCI_AD19 PCI_AD18 PCI_REQ#0 RN12A
AF14 1 8.2KOHM2
PCI_AD20 PCI_AD19 PCI_CLK0
AE14 AE24 1 2 CLK_LANPCI 32
PCI_AD21 PCI_AD20 PCI_CLK0 PCI_CLK1 R852 PCI_REQ#1
AA14 AF24 1 22Ohm 2 CLK_CBPCI 34 3 8.2KOHM4
RN12B
PCI_AD22 PCI_AD21 PCI_CLK1 PCI_CLK2 R853 22Ohm
AB14 PCI_AD22 PCI_CLK2 AD23 1 2 CLK_TPMPCI 38
PCI_AD23 AC13 AF23 R7115 22Ohm PCI_REQ#2 5 RN12C
PCI_AD24 PCI_AD23 PCI_CLK3 8.2KOHM6
C AB13 AB23 PCI_CLK4 1 2 C
PCI_AD25 PCI_AD24 PCI_CLK4 R854 22Ohm MXM_PWR_ON RN12D
AE13 7 8.2KOHM8
PCI_AD26 PCI_AD25 PCI_CLKIN
AA12 AC23
PCI_AD27 PCI_AD26 PCI_CLKIN
AF13 PCI_AD27
PCI_AD28 AB12 C832 C833 C7108 C834
PCI_AD29 PCI_AD28
AF12 PCI_AD29
PCI_AD30 AE12 10PF/50V10PF/50V 10PF/50V 10PF/50V LPC_AD0 RP7A 1 5
PCI_AD31 PCI_AD30 8.2K
AF11 _* _* _* _* 10
PCI_C/BE#[0..3] PCI_AD31 LPC_AD1 RP7B
32,34 PCI_C/BE#[0..3] 2 8.2K 5
10
PCI_C/BE#0 AD19 K24 LPC_AD0 LPC_AD2 RP7C 3 5
PCI_C/BE#1 AB17 PCI_CBE0# LPC_AD0 LPC_AD0 26,27,28,31,38 8.2K
H26 LPC_AD1 10
PCI_C/BE#2 AA15 PCI_CBE1# LPC_AD1 LPC_AD2 LPC_AD1 26,27,28,31,38 LPC_AD3
H25 RP7D 4 5
PCI_C/BE#3 AA13 PCI_CBE2# LPC_AD2 LPC_AD2 26,27,28,31,38 8.2K
K22 LPC_AD3 10
PCI_CBE3# LPC_AD3 LPC_AD3 26,27,28,31,38 LPC_DRQ#0 RP7E 6 5
8.2K
10
PCI_FRAME# AC15 LPC_DRQ#1 RP7F 7 5
32,34 PCI_FRAME# PCI_IRDY# PCI_FRAME# 8.2K
32,34 PCI_IRDY# AD15 PCI_IRDY# 10
PCI_TRDY# AB16 RP7G 8 5
32,34 PCI_TRDY# PCI_STOP# PCI_TRDY# 8.2K
32,34 PCI_STOP# AE16 PCI_STOP# 10
PCI_DEVSEL# AA16 RP7H 9 5
32,34 PCI_DEVSEL# PCI_PAR PCI_DEVSEL# 8.2K
32,34 PCI_PAR AE17 10
PCI_PERR# PCI_PAR
32,34 PCI_PERR# AF16
PCI_SERR# PCI_PERR#/GPIO_43
32,34 PCI_SERR# AF17 PCI_SERR#
PCI_PME# AD11 INT_SERIRQ R858 10K
32,34 PCI_PME# PM_CLKRUN# PCI_PME#/GPIO_30 LPC_FRAME#
26,28,34,38 PM_CLKRUN# AF25 G25 LPC_FRAME# 26,27,28,31,38
PCI_CLKRUN#/GPIO_42 LPC_FRAME# LPC_DRQ#0
K21 LPC_DRQ#0 26
LPC_DRQ0# LPC_DRQ#1
K23
LPC_CS#/LPC_DRQ1# PCI_INTA# RN44A
LPC_SERIRQ L22 INT_SERIRQ 26,28,34,38 1 8.2KOHM2
B PCI_INTB# RN44B B
3 8.2KOHM4
1 2 AE25 H24 GPU_ON PCI_INTC# 5 RN44C
32 PCIRST_LAN# PCI_RESET0# LPC_PWRDWN#/GPIO_54 GPU_ON 13,16 PCI_INTD# 8.2KOHM6
R857 33Ohm 7 RN44D
8.2KOHM8
34 PCIRST_CB# 1 2 AD24 PCI_RESET1# 1 2 CLK_KBCPCI 28
R859 33Ohm R860 22Ohm
1 2 AE26 F26 LPC_CLK0 1 2
5,31 PCIRST_NEWC# PCI_RESET2# LPC_CLK0 CLK_SIOPCI 26,31
R7112 33Ohm R862 22Ohm
1 2 W22 G26 LPC_CLK1 1 2
24 IDE_RST# PCI_RESET3# LPC_CLK1 CLK_FWHPCI 27
R864 33Ohm R865 22Ohm
1 2 L26 +3VSUS
26 LPCSIO_RST# LPC_RESET#
R866 33Ohm C835 C836
1 2 MCP51
27 LPCFWH_RST#
R7142 33Ohm 10PF/50V10PF/50V
1 2 _* _* PCI_PME# 2 1
28 LPCKBC_RST#
R7143 33Ohm R867 8.2KOhm
38 LPCTPM_RST# 1 2
R7144 33Ohm
BACK_OFF#
R30
10K
A A
WWW.AliSaler.Com
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 20 OF 55 MCP51 PCI RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U3C IDE_PDD[15..0]
IDE_PDD[15..0] 24
B20 F8 IDE_PDD0
24 SATA_TXP0 SATA_A0_TX_P IDE_DATA_P0
A20 D8 IDE_PDD1
24 SATA_TXN0 SATA_A0_TX_N IDE_DATA_P1
A9 IDE_PDD2
IDE_DATA_P2 IDE_PDD3
24 SATA_RXN0 A19 E9
SATA_A0_RX_N IDE_DATA_P3 IDE_PDD4
24 SATA_RXP0 B19 A10
SATA_A0_RX_P IDE_DATA_P4 IDE_PDD5
IDE_DATA_P5 E10
C10 IDE_PDD6
IDE_DATA_P6 IDE_PDD7
E11
IDE_DATA_P7 IDE_PDD8
D F11 D
IDE_DATA_P8 IDE_PDD9
D10
IDE_DATA_P9 IDE_PDD10
B18 SATA_A1_TX_P IDE_DATA_P10 F10
A18 B10 IDE_PDD11
SATA_A1_TX_N IDE_DATA_P11 IDE_PDD12
F9
IDE_DATA_P12 IDE_PDD13
A17 B9
SATA_A1_RX_N IDE_DATA_P13 IDE_PDD14
B17 SATA_A1_RX_P IDE_DATA_P14 E8
A8 IDE_PDD15
IDE_DATA_P15
IDE_ADDR_P0 A6 IDE_PDA0 24
IDE_ADDR_P1 D6 IDE_PDA1 24
IDE_ADDR_P2 B6 IDE_PDA2 24
B15
SATA_B0_TX_P
A15 A5 IDE_PDCS1# 24
SATA_B0_TX_N IDE_CS1_P#
IDE_CS3_P# B5 IDE_PDCS3# 24
A16 SATA_B0_RX_N IDE_DACK_P# B7 IDE_PDDACK# 24
B16 SATA_B0_RX_P IDE_IOW_P# F7 IDE_PDIOW# 24
E6 IDE_PINTR 24
IDE_INTR_P
B8 IDE_PDDREQ 24
IDE_DREQ_P
IDE_IOR_P# E7 IDE_PDIOR# 24
A7 IDE_PIORDY 24
IDE_RDY_P R941 0_*
C6 IDE_PDIAG 24
CABLE_DET_P/GPIO_63
B13 SATA_B1_TX_P
A13 IDE_SDD[15..0]
SATA_B1_TX_N IDE_SDD[15..0] 24
A14 E4 IDE_SDD0
SATA_B1_RX_N IDE_DATA_S0 IDE_SDD1
B14 D1
SATA_B1_RX_P IDE_DATA_S1 IDE_SDD2
IDE_DATA_S2 D4
C2 IDE_SDD3
C IDE_DATA_S3 IDE_SDD4 C
B2
IDE_DATA_S4 IDE_SDD5
C3
IDE_DATA_S5 IDE_SDD6
A3
IDE_DATA_S6 IDE_SDD7
24 SATA_LED# C20 SATA_LED#/GPIO_57 IDE_DATA_S7 A4
B4 IDE_SDD8
IDE_DATA_S8 IDE_SDD9
IDE_DATA_S9 B3
1 2 SATA_TSTCLK D14 A2 IDE_SDD10
23 SATA_TSTCLK# SATA_TSTCLK_P IDE_DATA_S10 IDE_SDD11
R868 100Ohm_* E13 B1
SATA_GND IDE_DATA_S11 IDE_SDD12
C1
IDE_DATA_S12 IDE_SDD13
F13 D2
T7127 SATA_TEST IDE_DATA_S13 IDE_SDD14
IDE_DATA_S14 E3
1 2 F14 E5 IDE_SDD15
R869 2.49KOhm SATA_TERMP IDE_DATA_S15
E14 SATA_TERMN
G4 IDE_SDA0 24
IDE_ADDR_S0
G6 IDE_SDA1 24
+1.5VS IDE_ADDR_S1
IDE_ADDR_S2 G2 IDE_SDA2 24
L112 180 mA
1 2 +1.5VS_PLL_SP_VDD F18 G1
+1.5V_PLL_SP_VDD IDE_CS1_S# IDE_SDCS1# 24
IDE_CS3_S# G3 IDE_SDCS3# 24
120Ohm/100Mhz F5
IDE_DACK_S# IDE_SDDACK# 24
C837 C838 C839 C840 E1
IDE_IOW_S# IDE_SDIOW# 24
F6 IDE_SINTR 24
0.1UF/16V 10uF/10V 0.01UF/25V 0.1UF/16V IDE_INTR_S
E2 IDE_SDDREQ 24
IDE_DREQ_S
IDE_IOR_S# F2 IDE_SDIOR# 24
IDE_RDY_S F1 IDE_SIORDY 24
G5 R274 0_*
CABLE_DET_S/GPIO_64 IDE_SDIAG 24
+3VS
B B
+3VS +3VS_PLL_SP_SS
L113 F19 +1.5V_PLL_SP_SS IDE_COMP_3P3 B11 IDE_COMP_3P3V R870 1 2 121Ohm
1 2 12 mA D20 +3.3V_PLL_SP_SS IDE_COMP_GND A11 IDE_COMP_GND R871 1 2 121Ohm
120Ohm/100Mhz MCP51
C841 C842 C843 C844
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 21 OF 55 MCP51 IDE RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
USB_PP0 1 2
1 2 AC_SRT# STRAP (LAN) USB_PN0 1R1 15KOhm
2
36 ACZ_BCLK_AUD AC_BITCLK USB_PP1
R872 22Ohm 0 M11 1R2 15KOhm
2
1 2 1 RGMII USB_PN1 1R3 15KOhm
2
38 ACZ_BCLK_MDC U3D
R873 22Ohm R4 15KOhm
USB_PP2 1 2
1 2 R22 AC26 USB_PN2 1R5 15KOhm
2
36 ACZ_SYNC_AUD AC_BITCLK AC97_CLK USB0_P USB_PP0 25
R874 22Ohm AC_SYNC U26 AC25 USB_PP3 1R8 15KOhm
2
AC_BITCLK/HDA_BCLK USB0_N USB_PN0 25 USB_PN3
38 ACZ_SYNC_MDC 1 2 1R9 15KOhm
2
R875 22Ohm AC_SDOUT T25 AB26 R10 15KOhm
AC_SDIN_0 (AC/HAD)_SDATA_OUT0/GPIO_45 USB1_P USB_PP1 25
D R26 AB25 USB_PP4 1 2 D
36 ACZ_SDIN0_AUD AC_SDIN_1 (AC/HAD)_SDATA_IN0/GPIO_22 USB1_N USB_PN1 25 USB_PN4
36,37 ACZ_RST#_AUD 1 2 38 ACZ_SDIN1_MDC T24 (AC/HAD)_SDATA_IN1/GPIO_23 1R11 15KOhm
2
R876 22Ohm AC_RST# U21 AA26 USB_PP6 1R12 15KOhm
2
69 CHG_FULL_OC (AC/HAD)_SDATA_IN2/GPIO_24 USB2_P USB_PP2 38 USB_PN6
38 ACZ_RST#_MDC 1 2 USB2_N AA25 USB_PN2 38 1R13 15KOhm
2
R877 22Ohm AC_RST# U25 R14 15KOhm
AC_SYNC AC_RESET#/HDA_RST# USB_PP5
R21 AC_SYNC/HDA_SYNC/GPIO_44 Y26 USB_PP3 38 1 2
USB3_P USB_PN5
36 ACZ_SDOUT_AUD 1 2 USB3_N Y25 USB_PN3 38 1R15 15KOhm
2
R878 22Ohm AC_SDOUT BT_ON/OFF# USB_PP7 1R16 15KOhm
2
38 BT_ON/OFF# USB_PN7
38 ACZ_SDOUT_MDC 1 2 W26 USB_PP4 40 1R17 15KOhm
2
R879 22Ohm USB4_P R18 15KOhm
1 2 T26 SPDIF0/GPIO_46 USB4_N W25 USB_PN4 40
SPDIFO strap for BUF_SIO_CLK R880 10KOhm
0 14.318MHz (default) V24 USB_PP5 25
USB5_P
1 24MHz V23 USB_PN5 25
DDC_CLKC51M USB5_N
18 DDC2BC_C51M AE10 DDC_CLK0
18 DDC2BD_C51M AF10 DDC_DATA0 USB6_P V26 USB_PP6 31
USB6_N V25 USB_PN6 31
14 LOAD_TEST AF9 HPLUG_DET0/GPIO_47
T22 USB_PP7 25
USB7_P R87
17 EDID_DATA_C51M AB10 T23 USB_PN7 25
DDC_DATA1/GPIO_53 USB7_N BATT_65C#
AE9 NC 1 2 PROCHOT# 5
EDID_CLKC51M AA10
17 EDID_CLK_C51M DDC_CLK1/GPIO_52 0Ohm_*
3 Q190
D
PCB_ID2 J4 1
GPIO_1/SLV_RDY4PWRDWN BATT_TALARM 69
J3 +3VSUS G
28 KB_SCI# GPIO_2/CPU_SLP S2
J5 2N7002
5,68,71 PWRLMT# GPIO_3/CPU_CLKRUN
C AE2 1 RN41A C
26,38 PM_SUS_STAT# GPIO_4/AGPSTP/SUS_STAT 10KOhm 2
K5 3 RN41B
41 802_LED_EN# GPIO_5/SYS_SHUTDOWN 10KOhm 4 R2.1
J2 5 RN41C
14 MCP_TV_EN GPIO_6/NFERR/SYS_PERR 10KOhm 6
J1 7 RN41D
34 CB_SD# GPIO_7/FERR/SYS_SERR 10KOhm 8
47 CR_VID0 AC9
GPIO_8/CR_VID0
47 CR_VID1 AB9 GPIO_9/CR_VID1
AA9 Y24 BATT_65C#
RN42A GPIO_10/CR_VID2 USB_OC0#/GPIO_18 T305
1 10KOhm 2 P24 GPIO_11/CPU_VID0 USB_OC1#/GPIO_19 Y23 1
3 RN42B +3VS
10KOhm 4 P25
GPIO_12/CPU_VID1 USB_OC2#/GPIO_20
U22 1HZ 41
5 RN42C
10KOhm 6 P22
GPIO_13/CPU_VID2 USB_OC3#/GPIO_21
V22 1 2 IGP_DDC_SELECT 17,18
7 RN42D R7146 0Ohm
10KOhm 8 P26 GPIO_14/CPU_VID3
1 10KOhm 2
RN45A R25 GPIO_15/CPU_VID4 USB_RBIAS_GND AD25USB_RBIAS_GND 1 2
3 RN45B R883 732Ohm SMB_MEM_SCL 1
10KOhm 4 P23 GPIO_16/CPU_VID5 SMB_MEM_SDA R7135
2
1 2.7KOhm
2
R7136 2.7KOhm
+3VS +VCC_RTC +3VSUS
+3VSUS J22
A20GATE/GPIO_55 HA20GATE 28
A24 1 2 +3VSUS
INTRUDER# R885 1MOhm
1 2 B25 LID#/GPIO_17 EXT_SMI#/GPIO_32 M26 EXTSMI#_3A 28
R881 R886T246 110KOhm B24 M25 RI# 5
SLP_DEEP# RI#/GPIO_33 10KOhm6 SIO_SMI#
+VCC_RTC 1 2 E22 E26 RN45C 7 RN45D
V3P3_DEEP SPKR SPKR_SB 36 10KOhm 8
100KOhm R8881 20Ohm G22 D23
LLB# PWRBTN# PM_PWRBTN# 42
1 2 RTC_RST# R889 10KOhm A25 RTC_RST# SIO_PME#/GPIO_31 M23 SIO_SMI# 26
LOAD_TEST R891 49.9KOhm J21
KBRDRSTIN#/GPIO_56 KBDCPURST 28
AC3 PCIE_WAKE# 30,31
C7113 C846 JRST1 PE_WAKE# SMB_MEM_SCL
H1 SMB_MEM_SCL 8,9
SMB_CLK0/GPIO_25 SMB_MEM_SDA
H2 SMB_MEM_SDA 8,9
0.01UF/25V 1UF/10V RTC_RST# SMB_DATA0/GPIO_26 +3VSUS
SMB_CLK1/GPIO_27 M21 SMB_CLK_SB 29,31
B +VCC_RTC B
SMB_DATA1/GPIO_28 L25 SMB_DAT_SB 29,31
M22 SMB_ALERT# 1 2
SMB_ALERT#/GPIO_29 R892 2.7KOhm
+3.3V_VBAT A23
+3VS_PLL_SP_SS J26 1 2
BUF_SIO_CLK CLK_SIO14 26
B22 N21 SUSCLK 1 2 SUS_CLK 38
R893 22Ohm
+1.5V_PLL_LEG SUS_CLK/GPIO_34 R7147 22Ohm C847 C848
5 mA A22
+3.3V_PLL_LEG THERM#/GPIO_59
K25 PM_THRM# 5
+RTCBAT +3VA +VCC_RTC F21 RSTBTN#
D67 +1.5VS RSTBTN# 10PF/50VSB_ 0.1UF/16V
2 L114 C26
+1.5VS_PLLUL 20 mA SLP_S5# SUSC# 42,67
T301 3 1 2 F24
SLP_S3# SUSB# 31,32,42,67,70
1 R882 1K 1 B26
PWRGD_SB PM_RSMRST# 42
C845 120Ohm/100Mhz N22 PWRGD_SB => +xVSUS OK
PWRGD PCB_ID0 PWRGD 5,70
T300 RB715F C849 C850 L21 PWRGD => +xVS and +xV OK
1UF/X7R FANRPM/GPIO_60 PCB_ID1
1 FANCTL0/GPIO_61 J25
CON44 0.01UF/25V 0.1UF/16V Y21 K26 IGP_SEL 1 2 IGP_SELECT 14,17,18
+1.5V_PLL_USB FANCTL1/GPIO_62
AD26 D25 1R7148 2 0Ohm
RTC_CON +3.3V_PLL_USB TEST_MODE_EN R894 1KOhm
+3VS +3VS +3VS
MCP51
+3VS
L115
1 2 +3VS_PLL_USB 18 mA +3VSUS
+3V R254 R255 R256
120Ohm/100Mhz
C851 C852 C853 C854 CB_SD# 1 2 IGP_SEL 1 2 10K 10K_* 10K_*
R895 10KOhm R7149 10KOhm PCB_(ID2, ID1, ID0)
0.1UF/16V 10uF/10V 0.01UF/25V 0.1UF/16V 802_LED_EN# 1 2 PCB_ID0
R896 10KOhm PCB_ID1 R1.0-->000
CHG_FULL_OC 1 2 SUSCLK 1 2 PCB_ID2 R1.1-->001
A
R897 10KOhm R7150 10KOhm R2.0-->010 A
RSTBTN# 1 2
R898 10KOhm SUSB# 1 2 R263 R264 R265
PCIE_WAKE# 1 2 R25 22kOhm
R899 10KOhm 10K_* 10K 10K
PWRLMT# 1 2 R1.1 (NVIDIA request)
R7113 10KOhm
KB_SCI# 1 2
R7114 10KOhm
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 22 OF 55 MCP51 USB/HDA RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
+5VS
+1.2VS
U3F 50 mA
750 mA
1 2 +1.2VS_MCPCORE U17 Y22 C855 C856
R900 0Ohm +1.2V_1 +5V_1
U16 F12
C857 C858 C859 C860 C861 C862 C863 +1.2V_2 +5V_2 0.1UF/16V 0.1UF/16V
U15
+1.2V_3
U12
22UF/6.3V 4.7U/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V +1.2V_4 +3VS +3VS
U11 +1.2V_5 +3.3V_1 AD21
U10 +1.2V_6 +3.3V_2 AD17
T17 AD13 150 mA 150 mA L116
+1.2V_7 +3.3V_3 +3VS_MCPHT
D T10 AD9 1 2 D
+1.2V_8 +3.3V_4 +3VS_MCPHT C864 C865 C866 C867
R17 AD5
C868 C869 C870 C871 C872 +1.2V_9 +3.3V_HT C873 C874 C875 120Ohm/100Mhz
R10 +1.2V_10 +3.3V_5 C12
M17 C8 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
22UF/6.3V 4.7U/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V +1.2V_11 +3.3V_6 10uF/10V 0.1UF/16V 0.1UF/16V
M10 C4
+1.2V_12 +3.3V_7 +3VSUS
L17
+1.2V_13
L10 +1.2V_14
K17
+1.2V_15 +3.3V_DUAL_1
Y6 55 mA
C876 C877 C878 C879 C880 K16 T21
+1.2V_16 +3.3V_DUAL_2 C881 C882 C883 C884
K15 +1.2V_17 +3.3V_DUAL_3 P21
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V K12 G21 R901
+1.2V_18 +3.3V_DUAL_4 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
K11 +1.2V_19 0Ohm
K10
+1.2V_20
+3.3V_USB_DUAL_1
W21 120 mA
V21 +3VSUS_USB +1.5VS
+1.2VS +3.3V_USB_DUAL_2
U3 +1.2V_HT_1
200 mA R3 L117
+1.2VS_MCPHT +1.2V_HT_2 +1.5VS_SP
1 2 N3
+1.2V_HT_3 +1.5V_SP_A_1
F17 450 mA 1 2
R902 0Ohm L3 E17
C885 C886 C887 C888 C889 C890 +1.2V_HT_4 +1.5V_SP_A_2 C891 C892 C893 C894 120Ohm/100Mhz C895 C897
W3 +1.2V_HT_5 +1.5V_SP_D_1 F15
E15
0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/6.3V 22UF/6.3V 22UF/6.3V +1.5V_SP_D_2 4.7U/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 10uF/10V
AE3 +1.2V_DUAL_1
AF3 +1.2V_DUAL_2 +1.5V_SP_A_3 E16
+1.5V_SP_A_4
F16 175 mA
+1.5VSUS +1.5VSUS_DUAL
150 mA MCP51
1 2 C898 C899 C900
R903 0Ohm
C C901 C902 C903 10uF/10V 0.1UF/16V 0.01UF/16V C
U3G
1UF/6.3V 0.1UF/16V 0.01UF/16V
AF26 GND1 GND47 N16
AF1 GND2 N15
GND48
AD22 GND3 GND49 N14
AD20 GND4 GND50 N13
AD18 N12 U3E
GND5 GND51
AD16 N11
GND6 GND52
AD14 N10 AE7 E19
GND7 GND53 RGMII_TXD0/MII_TXD0 NC1
AD12 GND8 GND54 M16 AF6 RGMII_TXD1/MII_TXD1 NC2 D12
AD10 GND9 GND55 M15 AB6 RGMII_TXD2/MII_TXD2 LCD_BKL_ON/GPIO_51 C25 LCD_BKLEN_C51M 14
AD8 GND10 GND56 M14 AA6 RGMII_TXD3/MII_TXD3 NC3 E25
AD6 M13 1 2 AA7 C24 FWH_WP# 27
GND11 GND57 R904 10KOhm RGMII_TXCLK/MII_TXCLK LCD_BKL_CTL/GPIO_49
AD4 M12 AB7 E12
GND12 GND58 RGMII_TXCTL/MII_TXEN NC4
AC24 GND13 GND59 M11 5 10kOhm1RP9A LCD_PANEL_PWR/GPIO_50 D24 LCD_VDDEN_C51M 14
AB3 GND14 GND60 M3 10
AA24 GND15 GND61 L24 5 10kOhm2 AF7 RGMII_RXD0/MII_RXD0
Y3 L16 10 RP9B AF8
GND16 GND62 RGMII_RXD1/MII_RXD1
W24 GND17 GND63 L15 5 3 AD7 RGMII_RXD2/MII_RXD2
10kOhm RP9C
V3 L14 10 AB8
GND18 GND64 RGMII_RXD3/MII_RXD3
U24 L13 5 10kOhm4RP9D AC7
GND19 GND65 RGMII_RXCLK/MII_RXCLK
U14 L12 10 AE8
GND20 GND66 RGMII_RXCTL/MII_RXDV
U13 GND21 GND67 L11 5 10kOhm6
T16 K14 10 RP9E
GND22 GND68
T15 K13 5 10kOhm7RP9F AF4
GND23 GND69 RGMII_VREF/MII_VREF
T14 K3 10
GND24 GND70
T13 J24 5 10kOhm8
GND25 GND71 RP9G
T12 GND26 GND72 H3 10 AF5 RGMII_MDC/MII_MDC
B B
T11 GND27 GND73 G24 5 10kOhm9 AE6 RGMII_MDIO/MII_MDIO
T3 F3 10 RP9H AD3
GND28 GND74 MII_RXER/GPIO_36
R24 GND29 GND75 E24 AC4 MII_COL
R16 D3 AF2 E21 XIN_25M
GND30 GND76 MII_CRS XTALIN XOUT_25M X7
R15 C23 37 OP_SD# AE5 D22
GND31 GND77 RGMII_PWRDWN/MII_PWRDWN/GPIO_37 XTALOUT 1 2
R14 C11 1 2 AA8
GND32 GND78 R905 10KOhm RGMII_INTR/MII_INTR/GPIO_35
R13 GND33 GND79 C9
R12 C7 C904 25Mhz C905
GND34 GND80 BUF_25MHZ AC5
R11 GND35 GND81 C5 32 BUF_25M 1 2 BUF_25MHZ
P17 A26 R28 22Ohm 18PF/50V 18PF/50V
GND36 GND82
P16 A1
GND37 GND83
P15 GND38 GND84 H5
P14 GND39 GND85 H6
P13 GND40 GND86 U4
P12 R4
GND41 GND87
P11 N4
GND42 GND88
P10 L4
GND43 GND89 +1.5VSUS_DUAL
P3 W4
GND44 GND90
N24 L5
GND45 GND91 +3VSUS
N17 GND46 GND92 L6
10 mA AE4 +1.2V_PLL_MAC_DUAL XTALIN_RTC C22 RTC_X0
F20 C21 1 2 5 mA AB5 B23 RTC_X1
SATA_GND1 SATA_GND10 R907 0Ohm +3.3V_PLL_MAC_DUAL XTALOUT_RTC
E18 C19 2 1
SATA_GND2 SATA_GND11 C907 C908 C909 C910 MCP51 R906 1MOhm_*
D18 C17
SATA_GND3 SATA_GND12
D16 SATA_GND4 SATA_GND13 C15
E20 C13 0.1UF/16V 10uF/10V 0.1UF/16V 0.01UF/16V X8 32.768Khz
SATA_GND5 SATA_GND14
C18 C14 SATA_TSTCLK# 21 1 4
SATA_GND6 SATA_TSTCLK_N
C16 B12
SATA_GND7 SATA_GND15
A B21 A12 A
SATA_GND8 SATA_GND16 C911 C906
A21 SATA_GND9
MCP51 18PF/50V 18PF/50V
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 23 OF 55 MCP51 PWR/GND RELEASE DATE : Albert Su
5 4 3 2 1
A B C D E
21 IDE_PDD[15:0]
IDE_PDD[15:0]
+5VS PATA HDD CON +5VS
1 1
+5VS C304 C305 C306 C307
U9
1 A VCC 5
R273 0.1U 0.1U 10U/10V 10U/10V
20 IDE_RST#
2 B 10K_*
CON9 PATA_HDD_CON_*
3 GND 4 IDERST#_5 44 44
Y IDE_PDD7 43 43 IDE_PDD8 +3VS +3VS
42 42 41 41
NC7ST32M5X_* IDE_PDD6 40 40 IDE_PDD9
IDE_PDD5 39 39 IDE_PDD10
38 38 37 37
1 2 IDE_PDD4 36 36 IDE_PDD11 +3VS
+3VS R908 33Ohm IDE_PDD3 35 35 IDE_PDD12 R282 R748
34 34 33 33
IDE_PDD2 32 32 IDE_PDD13
R275 4.7K_* IDE_PIORDY IDE_PDD1 31 31 IDE_PDD14 10K 10K
30 30 29 29
IDE_PDD0 28 28 IDE_PDD15 R281
27 27
26 26 25 25 41 HDD_LED#
R913 4.7K IDE_SIORDY IDE_PDDREQ 24 24 1K_*
21 IDE_PDDREQ
IDE_PDIOW# 23 23 D62
21 IDE_PDIOW# 22 22 21 21
R276 1K_* IDE_PDIOR# 20 20 IDE_PDASP#
IDE_SCSEL 21 IDE_PDIOR# IDE_PIORDY 19 19 IDE_PCSEL
1
21 IDE_PIORDY 18 18 17 17 5 2 3
R277 470 IDE_PDDACK# 16 16 15 2 IDE_SDASP#
21 IDE_PDDACK# 15
IDE_PINTR 14 14 Q108B Q108A
R278 470_* IDE_PCSEL 21 IDE_PINTR
IDE_PDA1 13 13 IDE_PDIAG UM6K1N UM6K1N DAP202K
2 21 IDE_PDA1 12 12 11 11 IDE_PDIAG 21 2
IDE_PDA0 10 10 IDE_PDA2
R279 5.6K_* IDE_PDDREQ 21 IDE_PDA0
IDE_PDCS1# 9 9 IDE_PDCS3# IDE_PDA2 21
21 IDE_PDCS1# 8 8 7 7 IDE_PDCS3# 21
IDE_PDASP# 6 6
R914 5.6K IDE_SDDREQ 5 5 1 2 SATA_LED# 21
4 4 3 3
2 2 D68 1SS355
R280 10K_* IDE_PDD7 1 1
IDE_SDD[15:0]
21 IDE_SDD[15:0]
3 3
Differential
Pair PATA CD-ROM CON
21 SATA_TXP0
C693 0.01UF/16V
SATA HDD CON +5VS +5VS
5 5
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 24 OF 55 HDD & CD-ROM CONN RELEASE DATE : Albert Su
A B C D E
A B C D E
1 1
CON11
R141 0 USBP5- 5 7
22 USB_PN5 SIDE_G1
+5VUSB5 1 VCC SIDE_G3
DATA0+
GND
USB
FOR EMI C312 6 SIDE_G2 8
SIDE_G4
2 +5V +5V_USB57 2
0.1U USB_CON_1X4P
+12V
R133 F1 1.5A/6V
2 1 +5VUSB_57 L30 80/2A +5VUSB7
R139 0 USBP7- 10K R764 0_0805_*
22 USB_PN7
C313 + C314 R765 0_0805_*
R137 0 USBP7+ CE1 CON12 R762 0_0805_*
22 USB_PP7
Q22 10U/10V 100UF/10V 0.1U 5 SIDE_G1 7 R763 0_0805_*
PMN45EN +5VUSB7 1 VCC SIDE_G3
USBP7- 2
USB
DATA0-
4 GND
6 SIDE_G2 8
SIDE_G4
USB_CON_1X4P
3 3
R138 0 USBP1-
22 USB_PN1
+5V +5V_USB01 10 12
R136 0 USBP1+ CON14
22 USB_PP1 +12V
GND4 GND6
8 GND2
R132 F3 1.5A/6V USBP1+ 7
+5VUSB_01 L35 80/2A +5VUSB0 USBP1- 0P+
2 1 6
FOR EMI 10K
C317
+
CE3 C318
+5VUSB0 5
0P-
VCC2 USB
4 GND1
Q19 10U/10V 100U/6.3V 0.1U USBP0+ 3
PMN45EN USBP0- 1P+
2 1P-
R135 0 USBP0- +5VUSB0 1
22 USB_PN0 VCC1
4 4
R134 0 USBP0+ GND3 GND5
22 USB_PP0
USB_CON_2X4P
9 11
FOR EMI
5 5
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 25 OF 55 USB PORTS RELEASE DATE : Albert Su
A B C D E
A B C D E
+3VS
1
CLK_SIOPCI 1
+3VS
2 2
DSR1#
U10 LPC47N217
1 nRTS1 PD3 48
CTS1# 2 47
nCTS1 PD2
3 46
RI1# nDTR1 PD1
4 45 +3VS
DCD1# nRI1 VCC3
5 nDCD1 PD0 44
IO_PME# 6 43
IO_PME# VSS3
+3VS 7 VTR nSLCTIN 42
8 VSS1 nINIT 41
9 40 ATI_RST#
22 CLK_SIO14 CLOCKI GP23 +3VS
20,27,28,31,38 LPC_AD0 10 39 FIR_SEL 27
LAD0 IRMODE/IRRX3
+3VS 11 38 IR_TXD 27
VCC1 IRTX2
20,27,28,31,38 LPC_AD1 12 LAD1 IRRX2 37 IR_RXD 27
13 36 GPI14
20,27,28,31,38 LPC_AD2 LAD2 GP14/IRQIN2 GPI13
20,27,28,31,38 LPC_AD3 14 LAD3 GP13/IRQIN1 35
15 34 IO_SMI#
20,27,28,31,38 LPC_FRAME# LFRAME# GP12/IO_SMI# SYSOPT SIO_SMI# 22
3 20 LPC_DRQ#0 16 33 3
LDRQ# GP11/SYSOPT Q107
2N7002
SYSOPT=0 --> 0x002E
SYSOPT=1 --> 0x004F
20 LPCSIO_RST# LPCPD#
R299 0_* 1 T7125
22,38 PM_SUS_STAT#
20,28,34,38 PM_CLKRUN#
CLK_SIOPCI
20,31 CLK_SIOPCI
20,28,34,38 INT_SERIRQ
+3VS
+3VS
+3VS
1 10K_* 2 RN26A DSR1#
R294 10K_* GPI14 3 10K_* 4 RN26B CTS1#
4 R295 10K_* GPI13 5 10K_* 6 RN26C RI1# 4
7 10K_* 8 RN26D DCD1#
R297 10K_* IO_PME#
R298 10K LPCPD#
5 5
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 26 OF 55 SUPER IO LPC47N217 RELEASE DATE : Albert Su
A B C D E
A B C D E
+3VS
1 1
+3VS
R7151 0_*
U11
SST 49LF004A-33-4C-N
3 3
IR1
11 SHIELD
10 LEDA
IR_TXD_Q 9
26 IR_TXD TXD
IR_RXD 8
26 IR_RXD RXD
7 GND
6 NC
5 MD1
4 MD0
26 FIR_SEL 3 FIR_SEL
4 2 AGND 4
+3VS 1
VCC
C331 HSDL_3602_007
0.47U
5 5
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 27 OF 55 BIOS , IR RELEASE DATE : Albert Su
A B C D E
A B C D E
KBDDT1 KBDDT0 Matrix
+3V +3V +3V 22,30,31,35,37,38,42 1 1 US
+3V
+3VS +3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,29,30,31,34,36,38,39,41,48,61,70 1 0 UK
CON43
+3VSUS +3VSUS 5,17,20,22,23,29,32,42,46,48,70
P2.1 Low : Power Button Override disable 12 12 +5V +5V 9,16,18,25,31,38,40,41 0 1 JP
14 11 LPC_AD0 KSI0 1 5 CON16
SIDE2 11 10K +5VS +5VS 14,18,23,24,29,36,37,38,39,40,41,61
Input Event only at P54, P55, P60 - P67 10 RP4A 10
10 LPC_AD1 KSI1
+5VLCM +5VLCM 68,69,70,71 SIDE2 30 KSI1
9 9 2 10K 5 28 28
8 RP4B 10 KSO7
8 LPC_AD2 KSI2 27 27 KSI7
P50, P43, P54, P55 are wake-up event 7
7 3 10K 5 26 26
6 DIS_FWH RP4C 10 KSO0
inputs when KBC in standby mode 6 LPC_AD3 DIS_FWH 27,31,38
KSI3 25 25 KSI6
1 5 5 4 10K 5 24 24 1
4 RP4D 10 KSO9
4 LPC_FRAME# KSI4 23 23 KSI5
3 3 6 10K 5 22 22
13 2 RP4E 10 KSO3
SIDE1 2 CLK_KBCPCI KSI5 21 21 KSI4
EC should set 1 1 7 10K 5 20 20
RP4F 10 KSO1
OP_SD low in S3, DEBUG_CON KSI6 19 19 KSI2
8 10K 5 18 18
keep from RP4G 10 KSI3
KSI7 17 17 KSO5
9 5 16 16
leakage. RP4H
10K
10 KSO13
15 15 KSI0
+3V 14 14 KSO2
CLK_KBCPCI 13 13 KSO4 +3V
+3V 12 12 KSO8
C337 11 11 KSO6
10 10 KSO11
10P_* 9 9 KSO10
+3V 8 8 KSO12 R319 R320
7 7 KSO14
U13 M38857 6 6 KSO15 10K 10K
5 5
20,26,34,38 INT_SERIRQ 63 P87/SERIRQ 4 4
64 C338 C339 3 KBDDT0
20 CLK_KBCPCI P86/LCLK 3
20 LPCKBC_RST# 65 P85/LRESET# VCC 71 2 2
66 0.1U 0.1U KBDDT1
2 20,26,27,31,38 LPC_FRAME# P84/LFRAME# 1 1 2
20,26,27,31,38 LPC_AD3 67 P83/LAD3 SIDE1 29
20,26,27,31,38 LPC_AD2 68 P82/LAD2 VREF 72
20,26,27,31,38 LPC_AD1 69 P81/LAD1
20,26,27,31,38 LPC_AD0 70
P80/LAD0 SCR_LED# Internal_KB_CON
31
P27
32
35
P54,P55,P43,P50 are P26
33
NUM_LED# 41
41 MSK_INSTKEY# BAT_LEARN P23 P25 SET_PCIRSTNS# CAP_LED# 41
68 BAT_LEARN 36 P22 wake-up event P24 34
R321 100K 37
42 KBCRSM 38
P21 inputs when KBC in
P20 KSO15
standby mode 39
P17/KSO15 KSO14 +3VS
P16/KOS14 40
23 41 KSO13
40 WATCHDOG P42/INT0 P15/KSO13
22 42 KSO12
41 SWDJ_EN KBCPURST_3Q P43/INT1* P14/KSO12
21 43 KSO11
KBC_GA20 P44/RXD P13/KSO11 KSO10
20 P45/TXD P12/KSO10 44
KBSCI_3Q 19 45 KSO9 R322 R323
P46/SCLK1 P11/KSO9 KSO8
20,26,34,38 PM_CLKRUN# 18 46
P47/SRDY1#/CLKRUN# P10/KSO8 KSO7 10K 10K
P07/KSO7 47
BAT_LLOW#_OC 17 48 KSO6 D15 1SS355
69 BAT_LLOW#_OC P50/INT5* P06/KSO6 KBC_GA20
FAN1_TACH 16 49 KSO5 2 1
40 FAN1_TACH P51/INT20 P05/KSO5 HA20GATE 22
KBDDT0 15 50 KSO4
KBDDT1 P52/INT30/1-WIRE1 P04/KSO4 KSO3 D16 1SS355
3 14 51 3
P53/INT40/1-WIRE2 P03/KSO3 KSO2 KBCPURST_3Q
42 LID_KBC# 13 P54/CNTR0* P02/KSO2 52 2 1 KBDCPURST 22
12 53 KSO1
71 BAT_IN_OC# P55/CNTR1* P01/KSO1 +5VS
11 54 KSO0
40 FAN1_DC P56/DA1/PWM01 P00/KSO0
17 ADJ_BL 10 P57/DA2/PWM11
55 KSI7
P37/KSI8 KSI6
74 P67/AN7 56
P36/KSI7 KSI5
41 PANLOCK_# 75 57
P66/AN6 P35/KSI6 KSI4 KBSCI_3Q
41 MARATHON_# 76 58 KB_SCI# 22
P65/AN5 P34/KSI5 KSI3
68 AC_IN# 77 P64/AN4 P33/KSI4 59
78 60 KSI2 Q13
P63/AN3 P32/KSI3 KSI1 2N7002
41 WIRELESS_# 79 61
P62/AN2 P31/PWM10/KSI2 KSI0
41 INTERNET_# 2 1 80 62
P61/AN1 P30/PWM00/KSI0
41 BLUETOOTH_# 1
D14 P60/AN0 X1_KBC
XIN 28
1SS355 RN30A 1 2 29 X2_KBC
+3V 10K XOUT
RN30B 3 4 4
10K P75/INT41 KBC_EXTSMI
RN30C 5 6 5 27
10K P74/INT31 P40/XCOUT
RN30D 7 8 6 26
10K P73/INT21 P41/XCIN PANLOCK_LED 41
7
P72 X1_KBC C340 10P
8
INTCLK_5S P71 PCI_RSTNS#
9 P70 RESET# 25
INTDATA_5S X3
4 2 24 R324 2 4
P77/SCL CNVSS
3 30
P76/SDA VSS 1M 8MHZ
73
AVSS
80mA X2_KBC C341 10P
+5VLCM +5VLCM +3VSUS
+3V
+5V
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 28 OF 55 KBC 38857 RELEASE DATE : Albert Su
A B C D E
A B C D E
E E
Q18A
UM6K1N
22,31 SMB_CLK_SB 6 1 SCL_3S 5,16
D D
Termal Sensor,
TPM
MCP51
Q18B
UM6K1N
22,31 SMB_DAT_SB 3 4 SDA_3S 5,16
+0.9VS +0.9VS 16
B B
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 29 OF 55 SM BUS & POWER PORT RELEASE DATE : Albert Su
A B C D E
A B C D E
1 1
CON19
WLAN_WAKE# 1 2
R359 0 WAKE# 3.3V_1
38 CH_DATA_A 3 BT_DATA GND7 4
R360 0 5 6
38 CH_CLK_A BT_CHCLK 1.5V_1
13 CLK_REQ_MINICARD# 7 CLKREQ# Reserved11 8
9 GND1 10
Reserved12
13 CLK_PCIE_MINICARD# 11 REFCLK- 12
Reserved13
13 CLK_PCIE_MINICARD 13 REFCLK+ Reserved14 14
15 GND2 Reserved15 16
17 18
Reserved1 GND8 R123 0_*
19 Reserved2 W_DISABLE# 20 802_ON/OFF# 41
2 21 22 PE_RST# 13,16 2
GND3 PERST#
13 PCIE_RXN1_MINICARD 23 24
PERn0 3.3Vaux
13 PCIE_RXP1_MINICARD 25 PERp0 GND9 26
27 GND4 1.5V_2 28
29 30
GND5 Reserved16
13 PCIE_TXN1_MINICARD 31 32
PETn0 Reserved17
13 PCIE_TXP1_MINICARD 33 34
PETp0 GND10
35 GND6 Reserved18 36
37 Reserved3 Reserved19 38
39 40
Reserved4 GND11
41 42
Reserved5 NC1 WLAN_LED# T218
43 44
Reserved6 LED_WLAN#
45 Reserved7 NC2 46
47 48
Reserved8 1.5V_3
49 Reserved9 GND12 50
51 Reserved10 3.3V_2 52
53 56
CON20 GND13 NP_NC2
54 GND14 NP_NC1 55
3 P_GND2
1 MINI_PCI_LATCH_52P
GND +3V
2
P_GND1
3 3
MINI_PCI_LATCH_3P
WLAN_WAKE#
22,31 PCIE_WAKE#
+3VS +3V
Q100
2N7002
+1.5VS
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 30 OF 55 MINI CARD RELEASE DATE : Albert Su
A B C D E
5 4 3 2 1
0.1U_*
C C
CON37
1 GND1
D59 USB_P6- 2 29
SHDN# USB_P6+ USB_D- GND5
42,46,67 VSUS_ON 2 1 3 USB_D+ NP_NC1 27
CP_USB# 4
1SS355_* R757 33_* CPUSB#
20,26,27,28,38 LPC_AD3 5 RESERVED1
R756 33_* 6
27,28,38 DIS_FWH RESERVED2
SMB_CLK_SB_R 7
U48 R5538D001 SMB_DAT_SB_R SMBCLK
8 SMBDATA
Int.PU 1 19 OD T83 9
22,32,42,67,70 SUSB# SHDN# Int.PU 20 STBY# OC# +1.5VS_PE +1.5V_1
SHDN# 1.5VOUT_1 11 +1.5VS_PE 10 +1.5V_2
PERST# R758 1K 8 13 PCIE_WAKE#_R 11
PERST# 1.5VOUT_2 WAKE# CON41
+3V_PE 12 +3.3VAUX
PERST# 13 2
PERST# P_GND2
+3VS 2A 2 3.3VIN_1 AUXOUT 15 +3V_PE +3VS_PE 14 +3.3V_1 P_GND1 1
4 3.3VIN_2 15 +3.3V_2
CLK_REQ# 16 CARD_EJECTOR_2P_*
CP_PE#_R CLKREQ#
+1.5VS 1A 14
1.5VIN_1 3.3VOUT_1
3 +3VS_PE 17 CPPE#
12 1.5VIN_2 3.3VOUT_2 5 13 CLK_PCIE_NEWCARD# 18 REFCLK-
13 CLK_PCIE_NEWCARD 19 REFCLK+
0.7A 17 10 CP_PE# Int.PU 20
+3V AUXIN CPPE# CP_USB# Int.PU PRSNT_NEWCARD# 13 GND2
CPUSB# 9 13 PCIE_RXN2_NEWCARD 21 PERn0
Int.PU 6 18 Int.PU 22
5,20 PCIRST_NEWC# SYSRST# RCLKEN 13 PCIE_RXP2_NEWCARD PERp0
7 GND1 23 GND3
B B
21 GND2 NC 16 13 PCIE_TXN2_NEWCARD 24 PETn0 NP_NC2 28
+3VS 25 30
13 PCIE_TXP2_NEWCARD PETp0 GND6
26 GND4
EXPRESS_CARD_26P
R909 R910
22KOhm 22KOhm
+3VS_PE +3V_PE +1.5VS_PE
CLK_REQ_NEWCARD# 13
C659 C660 C661 C662 C663 C664
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 31 OF 55 NEW CARD RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
PCI_AD[31:0] 20,34
PCI_C/BE#0 20,34
+3V_LAN PCI_C/BE#1 20,34
1 2 PCI_PAR 20,34
R948 0Ohm
PCI_SERR# 20,34
U17
RTL8100C RTL8110SB
R953 RTL8110SBL
8100:5.6KOHM(1%)
8110:2.49KOHM(1%) 2.49KOhm N/A 3.3AVDD PIN 10/120
AVDDH
71mA
GND
AVDDH 2.5AVDD 3.3AVDD PIN 12
DVDD V_12P
15mA
+3V_LAN AVDDL 3.3AVDD 2.5AVDD
V_DAC 307mA PIN 3/7/20/16
R952
V_DAC N/A 2.5AVDD
0Ohm 8100:NOT SYUFF
8110:STUFF PIN 24/32/45/54/64
DVDD 2.5VDD 1.2VDD /78/99/110/116
AVDDL 226mA
L_TDP PCI_PME# 20,34
PCI_REQ#1 20
L_TDN
PCI_GNT#1 20 DVDD_A N/A 1.2AVDD PIN 126
L_RDP 11mA
L_RDN CLK_LANPCI 20
L_TRDP2 PCIRST_LAN# 20
L_TRDM2 PCI_INTC# 20
L_TRDP3 1 R6 2
L_TRDM3 SUSB# 22,31,42,67,70
0Ohm
DVDD
1 2
Q52 R45 0Ohm
R947 2SB772PT
AVDDL 1 2 1 2 DVDD_A
R945 0Ohm
A 0Ohm 8100/ N/A PIN C923 C920 C913 C932 C931 C914 C918 C922 C371 C919 A
C939 C938 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 22UF/6.3V 0.1UF/16V
22UF/6.3V
8110/1.2V 126
22UF/6.3V
CTRL12
8100:NO STUFF
8110:STUFF
<Core Design>
WWW.AliSaler.Com
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 32 OF 55 LAN -- RTL8110CL RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
U59
L_RDN 1 16 L_RXN
L_RDP TD+ TX+ L_RXP
3 TD- TX- 14
RDC 2 15 L_CMT1
TDCT TXCT
L_TDN HA003 L_TXN
6 11
L_TDP RD+ RX+ L_TXP
8 9
RD- RX- L_CMT0
7 10
RDCT RXCT
TAIMIC
4 NC1 NC3 12
5 NC2 13
NC4
D D
LFE8505 _*
8100:NO STUFF
8110:STUFF
V_DAC
R7
1 2 U15 R150 0
24 MCT1 L_CMT3
RDC0Ohm TCT1 1 L_TXN LTXN
L42 180OHM/100MHz_*
TD1+ 2 L_TRLM3 CON17
32 L_TRDM3 23 MX1+ CON18
L_TXP LTXP 3 1 17
SIDE1 RING L46 1 1 SIDE1
1 1 2 1KOhm/100Mhz RING_J 2 2 P_GND1 15
TD1- 3 R149 0 2 TIP L47 1 2 1KOhm/100Mhz TIP_J 3 13
32 L_TRDP3 L_TRLP3 2 3 NP_NC1
22 MX1- SIDE2 4 4 4
21 MCT2 L_CMT2 R148 0 C675 C674 LTXP 5
TCT2 4 MODEM_CON LTXN 5
6
L_RXN LRXN 1000PF/3KV 1000PF/3KV LRXP 6
7 7
LTRLP2 8
TD2+ 5 L_TRLM2 LTRLM2 8
32 L_TRDM2 20 MX2+ L43 180OHM/100MHz_* 9 9
LRXN 10 14
L_RXP LRXP LTRLP3 10 NP_NC2
11 11 P_GND2 16
TD2- 6 LTRLM3 12 18
32 L_TRDP2 L_TRLP2 12 SIDE2
19 MX2- R147 0
18 MCT3 L_CMT1 MODULAR_JACK_12P
TCT3 7 R146 0
C L_TRLM2 LTRLM2 C
TD3+ 8 17 MX3+ L_RXN
32 L_RDN
L44 180OHM/100MHz_*
LG_2402S_1 R142 0
C941 C942
0.01UF/25V 0.01UF/25V
C940 8100:NO STUFF
8110:STUFF
0.01UF/25V
Co- layout
C944
1000PF/50V
A A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 33 OF 55 RJ45 & RJ11 RELEASE DATE : Albert Su
5 4 3 2 1
A B C D E
4 +3VS C424
GND1
GND2 13 TPAN0 108
PCI_AD31 C432 0.1U 0.01U/X7R TPA0-_0 40
125 AD31 GND3 22
PCI_AD30 126 28 1394_FIL 96 109
PCI_AD29 AD30 GND4 U22 FIL0 TPAP0 TPA0+_0 40
127 AD29 GND5 54
PCI_AD28 1 62 1 8
PCI_AD27 AD28 GND6 A0 VCC R393 R392
2 AD27 GND7 63 2 A1 WP 7 1.CLOSE TO R5C841
PCI_AD26 3 68 3 6 1394_SCL R362 10K_1 101
PCI_AD25 AD26 GND8 A2 SCL 1394_SDA REXT 56_1 56_1 2.The area is as compact as possible,length<10 mm
2 5 AD25 GND9 118 4 GND SDA 5 2
PCI_AD24 6 122 3.TPA Pair and TPB pair mismatch<2.5mm
PCI_AD23 AD24 GND10 AT24C02N C435 270P
9 AD23 4.No via recommend , maxmium is one.
PCI_AD22 11 1394_REF 100
PCI_AD21 AD22 VREF R391 5.Total length<50 mm
12 AD21 AGND1 99
PCI_AD20 14 102 C399 5.11K_1 6.Differential impedance is 110+/- 6 ohm
PCI_AD19 AD20 AGND3
15 AD19 AGND2 103 7.TPA Pair trace or TPB pair trace mismatch < 1.25mm
PCI_AD18 17 107 +3VS 0.01U/X7R
PCI_AD17 AD18 AGND4
18 AD17 AGND5 111
PCI_AD16 19
PCI_AD15 AD16
36 AD15 MDIO17 87 MDIO17 35
PCI_AD14 37 R368
PCI_AD13 AD14
38 AD13 MDIO16 92 MDIO16 35
Open Drain: PCI_AD12 39 10K
PCI_AD11 AD12
PME#, 40 AD11 MDIO15 89 MDIO15 35
PCI_AD10 42 69 CB_HWSUSP#
SERR#, PCI_AD9 AD10 HWSPND#
43 AD9 MDIO14 91 MDIO14 35
PCI_AD8 44 +3VS
INTn# AD8
PCI_AD7 46 90
AD7 MDIO13 MDIO13 35
PCI_AD6 47 58 R364 10K
PCI_AD5 AD6 MSEN
48 AD5 MDIO12 93 MDIO12 35
PCI_AD4 49 55 R361 10K
PCI_AD3 AD4 XDEN
50 AD3 MDIO11 81 MDIO11 35
PCI_AD2 51
PCI_AD1 AD2 R369 100K
52 AD1 UDIO5 57 MDIO10 82 MDIO10 35
PCI_AD0 53 +3VS
3 20,32 PCI_AD[31:0] AD0 3
20,32 PCI_PAR 33 PAR
PCI_C/BE#3 7 65 1394_SCL R383 10K 75
20,32 PCI_C/BE#[3:0] C/BE3# UDIO3 1394_SDA MDIO05 MDIO05 35
PCI_C/BE#2 21 59 R384 10K
PCI_C/BE#1 C/BE2# UDIO4
35 C/BE1# MDIO08 88 MDIO08 35
PCI_C/BE#0 45 56
CB_IDSEL_J C/BE0# UDIO2
8 IDSEL MDIO19 83 MDIO19 35
UDIO1 60
20 PCI_REQ#0 124 REQ# MDIO18 85 MDIO18 35
20 PCI_GNT#0 123 GNT# UDIO0/SRIRQ# 72 INT_SERIRQ 20,26,28,38
20,32 PCI_FRAME# 23 FRAME# MDIO02 78 MDIO02 35
20,32 PCI_IRDY# 24 IRDY#
20,32 PCI_TRDY# 25 TRDY#
20,32 PCI_DEVSEL# 26 DEVSEL# MDIO03 77 MDIO03 35
20,32 PCI_STOP# 29 STOP# INTA# 115 PCI_INTA# 20
20,32 PCI_PERR# 30 PERR# MDIO00 80 MDIO00 35
20,32 PCI_SERR# 31 SERR# INTB# 116 PCI_INTB# 20
CB_GBRST# 71 79
GBRST# MDIO01 MDIO01 35
20 PCIRST_CB# 119 PCIRST#
+3VS
Q105
2N7002_*
20,32 PCI_PME#
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 34 OF 55
PCI R5C832 RELEASE DATE : Albert Su
A B C D E
5 4 3 2 1
D D
MDIO17_XDDAT7 +3V
34 MDIO17 MDIO16_XDDAT6
34 MDIO16 MDIO15_XDDAT5
34 MDIO15 MDIO14_XDDAT4
34 MDIO14 MDIO13_SD/MS/XDDAT3
34 MDIO13 MDIO12_SD/MS/XDDAT2 R396
34 MDIO12 MDIO11_SD/MS/XDDAT1 2
34 MDIO11 MDIO10_SD/MS/XDDAT0
S
10K Q28
34 MDIO10
SI2301BDS
11
MDIO05_XDWP# G +MC_VCC
34 MDIO05 MDIO08_SDCMD_MSBS_XDWE# 3 3 D
34 MDIO08 MDIO19_XDALE
D
34 MDIO19 MDIO18_XDCLE Q29
34 MDIO18
MDIO02_XDCE# 1 2N7002 Place as
34 MDIO02 34 MDIO04_SD/MS/XDPWR
G C436 C437 R397
2 S close to
MDIO03_SDWP_XDR/B# 0.1U 0.1U 150K card reader
34 MDIO03
socket as
MDIO00_SDCD#_XDCD#
34 MDIO00 possible
MDIO01_MSCD#_XDCD#
34 MDIO01
MDIO09_SD/MSCLK_XDRE#
34 MDIO09
C C
3 3
D D
Q26 Q27
SDCD#
2N7002 2N7002 34 MDIO00_SDCD#_XDCD# MDIO03_SDWP_XDR/B#
SDCD# 1 XD_CD# 1
G G MSCD# D21
2 S 2 S 34 MDIO01_MSCD#_XDCD# SDCD# 1
C438 C439 C440 3 XD_CD#
MSCD# 2
270P_* 270P_* 270P_*
DAN202K
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 35 OF 55
4 IN 1 CONN RELEASE DATE : Albert Su
5 4 3 2 1
A B C D E
Vout=1.25*(1+(100K/34.8K)= 4.84V
+5VAUD
+5VS
3 1 2 PC_BEEP_C 2 1 3
22 SPKR_SB
R418 47KOhm C482 0.1UF/16V
R2.1
R420 R675 2.2K
+5VAUD
C912 R676 2.2K C479 1UF/X7R R76 0_*
EXT_MIC 37
4.7KOhm 0.01UF/50V
C480 1UF/X7R R77 0
MIC_IN_A 37
40 MIC_IN#_JACK 2 1
R59 20KOhm _* R423
C967 AGND_A
+5VAUD 1UF/10V_* C485 1UF/X7R R424 23.7K_1
CD_GND_A 24
4 4
R425
AGND_A
23.7K_1
R79
100KOhm_*
Q125B AGND_A
5 C486 1UF/X7R R426 47K_1
CD_R_A 24
UM6K1N_*
R427
2 Q125A 47K_1
37,40 HP_IN#_JACK
UM6K1N_* AGND_A For EMI
R912 1 2 0Ohm
AGND_A
AGND_A L57 1 2 120Ohm/100Mhz_*
2 1
L58 1 2 120Ohm/100Mhz_*
+3VS +3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,38,39,41,48,61,70
R78 0Ohm _*
+5V +5V 9,16,18,25,28,31,38,40,41
+5VS +5VS 14,18,23,24,28,29,37,38,39,40,41,61
5 +5VAUD +5VAUD 37 5
AGND_A
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 36 OF 55 CODEC_ADI1986A RELEASE DATE : Albert Su
A B C D E
A B C D E
+5VS
C652 100P U27
36 SPDIF_A 1 A VCC 5
R428 12.7K_1
2 3 OPTIC_VCC 2 B
+5VS
Q33 3 GND 4 SPDIF_O
U28 G1420F31UF SI2301BDS R429 C489 Y
R430 10K_1 21 22 SPKR+ SN74AHCT1G08DBVR
36 OUTR_A RLINEIN ROUT+ R431 100K 100K 0.1U
1 20 15 SPKR- 1
RHPIN ROUT- 3
D
C490 1UF/X7R 19 18
RBYPASS RVDD +5VAMP
Q34
+5VS +5VAMP OPTIC_HP 1 2N7002
G
L60 80/2A 2 2 S
R432 100K TJ HP_IN#
+5VAMP 11 MUTE IN
C491 C492 C493 C494 14 SE/BTL#
MUTE SE/BTL#
9 MUTE OUT
10U/10V 0.1U 10U/10V 0.1U 16
R751 0_* HP/LINE#
8 SHUTDOWN
7 CON27
LVDD
6 LBYPASS NC2 6
17 SPKR- L61 80/2A SPKR-_MB_CON 4
AGND_A AGND_A NC1 4
23 SPKR+ L62 80/2A SPKR+_MB_CON 3
NC2 SPKL- L63 80/2A SPKL-_MB_CON 3
2 2
SPKL+ L64 80/2A SPKL+_MB_CON 1
SPKL+ 1
5 LHPIN LOUT+ 3 NC1 5
AMP R437
22K_1_*
R2.0
AGND_A
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 37 OF 55
AUDIO_AMP(G1420) RELEASE DATE : Albert Su
A B C D E
A B C D E
+3V
E CON31 CON32 E
11 HOLD1
1 2 1
1 2 GND1
22 ACZ_SDOUT_MDC 3 4 22 USB_PP2 2
3 4 USB_D+
5 6 +3V 22 USB_PN2 3
5 6 USB_D-
22 ACZ_SYNC_MDC 7 7 8 8 4 RSVD
R452 39 9 10 5
22 ACZ_SDIN1_MDC 9 10 30 CH_CLK_A CLK
22 ACZ_RST#_MDC 11 12 ACZ_BCLK_MDC 22 22 BT_ON/OFF# 6
11 12 HW_DIS#
30 CH_DATA_A 7
R182 0_* DATA
8 +3.3V
BTOB_CON_12P R183 0 9
41 BT_LED LED
C511 10
GND2
12 HOLD2
0.1U C512
BLUE_TOOTH_CON
0.1U
10U/16V 0.1U
CON39 TPM_CON
20 CLK_TPMPCI 1 1 2 2
20,26,27,28,31 LPC_FRAME# 3 3 4 4 SUS_CLK 22
5 5 CON40
20 LPCTPM_RST# 6 6 +3VA
20,26,27,28,31 LPC_AD3 7 8 LPC_AD2 20,26,27,28,31 22 USB_PN3 1 5
7 8 USBP3- 1 SIDE1
+3VS 9 10 LPC_AD1 20,26,27,28,31 2
9 10 L96 USBP3+ 2
20,26,27,28,31 LPC_AD0 11 11 12 12 3 3
13 13 90/370mA
14 14 4 4 SIDE2 6
+3V 15 15 16 16 INT_SERIRQ 20,26,28,34 22 USB_PP3
17 18 Camera_CON
17 18 PM_CLKRUN# 20,26,28,34
C 19 20 R731 0_* C
22,26 PM_SUS_STAT# 19 20 DIS_FWH 27,28,31
R457 R453
+5V
330 330 +5VS
B B
Q42A R458 Q40A
UM6K1N +1.8V UM6K1N_* R454
2 330 2
41,42 PM_SUSC 41,42 PM_SUSB
330 +1.5VS
Q42B R459
UM6K1N Q40B
5 330_* UM6K1N_* R455
5
330_* +2.5VS
3
D
Q43
2N7002_* Q41A
1 UM6K1N_* R456
G 2
2 S 150_*
Q41B
+1.5VS +1.5VS 19,21,22,23,30,31,48
UM6K1N_*
+1.8V +1.8V 5,7,8,9,10,65
+2.5VS +2.5VS 5,11,14,15,16,18,48 5
+3V +3V 22,28,30,31,35,37,42
A +3VS +3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,39,41,48,61,70 A
+5V +5V 9,16,18,25,28,31,40,41
+5VS +5VS 14,18,23,24,28,29,36,37,39,40,41,61
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 38 OF 55 MDC,B/T,TPM,Camera & DISCHG RELEASE DATE : Albert Su
A B C D E
A B C D E
H8 H16
CR315X354D110N C315D87N
1 CON15 1
2 6 L75 1K/300mA H9 H17
16 DVI_TX2P_NV TMDS_DATA_2+ DDC_CK DVI_DDCCLK_NV 16
1 7 L76 1K/300mA
16 DVI_TX2N_NV TMDS_DATA_2- DDC_DATA DVI_DDCDAT_NV 16
1 NP_NC 1 NP_NC
5 16 L77 1K/300mA R73 10K 2 5 2 5
16 DVI_TX4P_NV TMDS_DATA_4+ HOT_PLUG_DETECT DVI_HDP_NV 16 GND1 GND4 GND1 GND4
4 3 4 3 4 H3 H4
16 DVI_TX4N_NV TMDS_DATA_4- GND2 GND3 GND2 GND3 CT276B167D138 CT276B167D138
10 D17 2
16 DVI_TX1P_NV TMDS_DATA_1+ +3VS
16 DVI_TX1N_NV 9 3
TMDS_DATA_1- CR315X354D110N C315D87N
1
16 DVI_TX3P_NV 13
TMDS_DATA_3+
CPU
12 R74 BAV99_* H10 H18
16 DVI_TX3N_NV TMDS_DATA_3-
18 8 100K 1 1
16 DVI_TX0P_NV TMDS_DATA_0+ V_SYNC NP_NC NP_NC
16 DVI_TX0N_NV 17 TMDS_DATA_0- 2 GND1 GND4 5 2 GND1 GND4 5
3 4 3 4
GND2 GND3 GND2 GND3
16 DVI_TX5P_NV 21
TMDS_DATA_5+
16 DVI_TX5N_NV 20 TMDS_DATA_5- GND_for+5V 15 R2.0
L78 80/2A F4 1.5A/6V D10 H33
23 14 2 1 +5V_DDC 2 1 CR315X354D110N C315D87N DO276X39
16 DVI_CLKP_NV TMDS_CLK+ +5V_POWER +5VS
24
16 DVI_CLKN_NV TMDS_CLK-
TMDS_CLK_Shield
22 C334 FS1J4TP H11 H19 IO Board
25 P_GND1 TMDS_2/4_Shield 3
2 26 11 0.1U 1 1 2
P_GND2 TMDS_DATA_1/3_Shield NP_NC NP_NC
19 2 5 2 5
TMDS_DATA_0/5_Shield GND1 GND4 GND1 GND4
27 NP_NC1 3 GND2 GND3 4 3 GND2 GND3 4
28 NP_NC2
DVI_CON_24P
CR315X354D110N C315D87N
H7 H20
H1 H2
1 1 L4E_1A L4E_1A
NP_NC NP_NC
2 5 2 5
3
GND1 GND4
GND2 GND3 4 3
GND1 GND4
GND2 GND3 4 MDC_NUT
CR315X354D87N C315D87N
H31 H21
H25
1 1 L4E_1A
NP_NC NP_NC
2 GND1 GND4 5 2 GND1 GND4 5
3 4 3 4
3
GND2 GND3 GND2 GND3 TPM_NUT 3
KB NUT
PT7017TPC28T 1 C315D87N
PT7018TPC28T 1
PT7019TPC28T 1 H32
PT7021TPC28T 1
1
NP_NC
2 5
GND1 GND4
GND 3 GND2 GND3 4
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 39 OF 55 DVI CONN & HOLE RELEASE DATE : Albert Su
A B C D E
A B C D E
1 1
+5V +5V_USB4
+12V
D53 RB751V_40
28 FAN1_TACH 1 2
R129
CON24
10K +5VS_FAN HOLD1
1
2
U23 3
2 Q38 F2 1.5A/6V 1 8 C441 C442 HOLD2 2
PMN45EN +5VUSB_4 L32 80/2A +5VUSB4 VEN GND4 FAN_CON
2 1 +5VS 2 VIN GND3 7
+ 3 6 10U/10V 0.1U
C315 CE2 C316 R400 1K VO GND2
28 FAN1_DC 4 VSET GND1 5
FAN CONTROL
Differential Differential
3 Pair Pair 3
L51
34 TPA0+_0 8 1 LTPA0+
CON34 I/O_PORT_CON
DC IN
19 19 +5VUSB4
USBP4- 20 20
17 17 18 18
USBP4+ 15 15
4 16 16 EXT_MIC_JACK 37 T102 T103 T104 T105 4
13 14 INT_MIC_JACK 37
LTPA0- 13 14
11 12 12 OPTIC_VCC_JACK 37
LTPA0+ 11
9 9 10 10 SPDIF_O_JACK 37
7 7 8 8 HP_IN#_JACK 36,37
LTPB0+ 5 5 6 6
36 MIC_IN#_JACK
LTPB0-
MIC_IN#_JACK
3 3
1 1
4 4
2 2
HP_JACK_L 37
HP_JACK_R 37
OPTIC_HP_JACK 37
ACIN_CONN
I/O PORT
5 5
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 40 OF 55 FAN_CTRL & ACIN RELEASE DATE : Albert Su
A B C D E
A B C D E
3 3 4 4 3 3 4 4 3 3 4 4 3 3 4 4 3 3 4 4 3 3 4 4
5 5 5 5 5 5 5 5 5 5 5 5
C449 C448 C451 C450 C452 C454
1 1
100P_* TACT_SWITCH_5P 100P_* TACT_SWITCH_5P 100P_* TACT_SWITCH_5P 100P_* TACT_SWITCH_5P 100P_* TACT_SWITCH_5P 100P_* TACT_SWITCH_5P
SW7
17,42 LID_SW# 1 4
5 6
2 3
C453 +3VS +3VS +3VS +5VS
SWITCH_4P Pwr4_Gear B/T WLAN PADlock Internet PWR
100P_* SW SW SW SW SW SW
R401 R402 R403 R691
2 2
+3VS U50A SN74LVC74APWR
3 LED1 LED2 LED3 LED9
CK Q# 6 GREEN GREEN GREEN GREEN
Q16 2 5
2N7002 D Q
R743 1K R740 100K 7 14
28 MSK_INSTKEY# +3VA GND VCC
24 HDD_LED#
28 CAP_LED#
U50B SN74LVC74APWR
28 NUM_LED#
7 14
GND VCC
Q12 3 11 8
D CK Q#
2N7002 R742 HDD CAP NUM PWR
12 D Q 9 SWDJ_EN 28 38,42 PM_SUSC LED LED LED LED
C74 0.1U 1
38,42 PM_SUSB
G C77 10K Q10
2 S 2N7002
R739 1UF/X7R INTERNET_# R741 10K
C79 INTERNET_# 2 1 GATE_PWR_SW#
100K
0.1U D66 1SS355
3 3
SW8 SW9
TP_LEFT# 1 2 TP_RIGHT# 1 2
1 2 1 2
3 3 4 4 3 3 4 4
C455 5 C456 5
69 CHG_LED_UP 5 5
100P_* 100P_*
TACT_SWITCH_5P TACT_SWITCH_5P
+5V
+5VS +5VS +3VS
+5VS
R405
0.1U
Q32
2N7002
C459
0.1U
CNT
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 41 OF 55 SW & LED & TP RELEASE DATE : Albert Su
A B C D E
A B C D E
D27 1SS355
46,70 FORCE_OFF# 2 1 OTP_RESET# 5 +3VA
1 1
R467 100K
+3VA
R461 20K
+3VSUS
R766 R468
U49 PST9128NR +3VA +3VA U21B SN74LVC74APWR D63
5 VCC 100K 100K 12
+3VSUS T108 D Q 9 1
3 VSUS_ON 31,46,67
U30D U30B PWR_SW 11 8 2
RS# VCC VCC 74LVC14APW_T PWRBTN# CK Q#
VOUT 4 C699 0.1U/X7R 3
D
1 NC 9 8 3 4 R463 0 Q106 7 14 DAN202K R725
PM_RSMRST# 22 GND VCC +3VA
2N7002
SUB GND GND GND C514 PWR_SW# R767 0_* 1 1M
C515 74LVC14APW_T G
0.1U 2 S
1UF/X7R
R472 100K
3 C517 C481
D
C654 1UF/X7R Q103 0.1U/X7R 0.1U
PM_SUSC 1 2N7002
2 G 2
S
R473 2
1M
+3VSUS
+3VA +3VA
3
3 R475 D31 3
D
2 1 LID_KBC# 28
R476 1M Q49 1M C686
+3V
R656 1K 1 2N7002 1SS355 R727 100K
28 KBCRSM A/D_DOCK_IN 40,68,69,70,71
G
2 S LID_SW# 17,41
0.1U/X7R
T303 1 C521 JP8 C520 R728 R729
Q46B Q46A
UM6K1N UM6K1N R730 C685
5 2
100K 0.1U/X7R
+3VA
4 74LVC14APW_T 4
VCC
22,67 SUSC# 1 2 PM_SUSC 38,41
GND
U30A
+3VA
74LVC14APW_T
VCC
22,31,32,67,70 SUSB# 5 6 PM_SUSB 38,41
GND
U30C
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 42 OF 55 POWER-ON SEQUENCE RELEASE DATE : Albert Su
A B C D E
A B C D E
Revision History
Power:
1 1
System:
2 2
3 3
4 4
5 5
<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 43 OF 55 HISTORY RELEASE DATE : Albert Su
A B C D E
5 4 3 2 1
D D
OPTIC_HP_JACK_I/O 6
IO_CON2 1394A
HP_JACK_R_I/O 1
HP_JACK_L_I/O 4 IO_CON1
5 5
HP_IN#_JACK_I/O 7
LINE_OUT LTPB0-_I/O 1
P_GND1
P_GND3 7
GND 11
12 SPDIF LTPB0+_I/O
LTPA0-_I/O
LTPA0+_I/O
2
3
1
2
3
4 4
A GND 9 8
OPTIC_VCC_JACK_I/O VCC MS 10 P_GND4
B 6
SPDIF_O_JACK_I/O Vin P_GND2
C
1394_CON
PHONE_CON
GND GND
IO_CON3
C 1 2 +5VUSB2_I/O C
USBP2-_I/O 3 4
USBP2+_I/O 5 6 EXT_MIC_JACK_I/O
7 8 INT_MIC_JACK_I/O
LTPA0-_I/O 9 10 OPTIC_VCC_JACK_I/O
LTPA0+_I/O 11 12 SPDIF_O_JACK_I/O
13 14 HP_IN#_JACK_I/O
LTPB0+_I/O 15 16 HP_JACK_L_I/O
LTPB0-_I/O 17 18 HP_JACK_R_I/O
MIC_IN#_JACK_I/O 19 20 OPTIC_HP_JACK_I/O
I/O_PORT_CON
IO_CON4
10 NP_NC2
9 NP_NC1
8 P_GND2
7 IO_CON5
MIC_IN#_JACK_I/O P_GND1 USB_CON_1X4P
5 5
4 +5VUSB2_I/O 1
INT_MIC_JACK_I/O
3
6
4
3
6
MIC USBP2-_I/O
USBP2+_I/O
2
3
1
2
3 USB
EXT_MIC_JACK_I/O 2 4
2 4
1 1
GND EXT_MIC_CON
B B
IO_R2 0_0603
A A
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<Core Design>
REVISION DATE: Friday, July 21, 2006 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: A8T 2.1 SHEET 44 OF 55 I/O PORT RELEASE DATE : Albert Su
5 4 3 2 1
5 4 3 2 1
+2.5VREF
PQ7102 5/26 PD ISSUE PQ7105
8 1 1 8 +5VLCM
7 2 2 7
1%
6 3 3 6
5 4 4 5 AC_BAT_SYS_IN PU7103
PT7102 PT7103 PT7104 PT7105 PT7106 PT7101 PT7107 PT7108 AC_BAT_SYS 3 A+ + VCC 8
TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T TPC28T 1
TPC8107 TPC8107 PR7102 2 A- - AO
10mOhm
D A/D_DOCK_IN 1 2 5 B+ D
1% + BO
7
6 B- - GND 4
LM358DR
68 CHG_SRC +5VLCM
PT7109 PT7110
TPC28T TPC28T
PT7111 CSSN 68
TPC28T CSSP 68 PU7104
1 OUT RS- 5
PR7112 PR7113 2 GND
68 MAX8725_PDS 1 2 1 2 3 4
BAT PQ7101 VCC RS+
18KOhm 3/9 for 6.8KOhm 8 1 MAX4073HAXK_T
5,22,68 PWRLMT#
soft 7 2
start
6 3
5 4
C TPC8107 C
PT7118
PT7112 TPC28T PD7104
TPC28T 1 1SS355
3 2 1
68 MAX8725_PDL D
PQ7106
2N7002 1 BATT_PWRLMT 2 1
G
+3VA S 2
PR7122
100KOhm Ibat=2.5*200k/256k/100/0.003=6.51A
PT7113 1%
+5VCHG +5VO
TPC28T @
A/D_DOCK_IN PT7114 PT7115
20050406 TPC28T PD7103 +5VLCM 6/14 EE change @
TPC28T
PU7102
1
3
6/7 for bat
+5VCHG
1 IN OUT 5 2
PT7116 current
2
GND
PR7110
31.6KOHM
F02JK2E
PR7109
TPC28T limit
3 4 1 2 PT7117 1KOhm
EN NC or ADJ TPC28T
+2.5VREF BAT_IN_OC# 28
MIC5235YM5
PR7111 PC7104
B 10KOhm 2.2UF/16V B
PC7105 PQ7104A
1UF/25V 2 UM6K1N
PC7106 3
1UF/10V
39,68,69 TS# 5
GND PQ7104B
UM6K1N
+5VCHG, +5VLCM, +2.5VREF
6/14 EE change
Ref: 1.24V
GND
ON: EN>2V (A/D_DOCK_IN:17V)
BATTERY IN CIRCUIT
OFF: EN<0.6V(A/D_DOCK_IN:5.1V)
A A
<Core Design>
Title : POWER_SWITCH_5VLCM
+2.5VREF
A/D_DOCK_IN LM4040BIM (500uA)
+5VCHG (100mA)
78L05
SI4925BDY SWITCH
(Regulator) +5VLCM
+5VO (20mA) (F02JK2E)
D D
VSUS_GD# SWITCH
+5VO (6A) +5VS
SUSB#_PWR (3.6A)
ON_SUS
+5V
+5VAO SUSC#_PWR (2.0A)
TPS51020 +3VSUS
(Regulator) (0.7A)
+3VO (6.3A)
ON_SUS +3V
SUSC#_PWR (0.6A)
(0.12A)
+1.5VSUS
SI9183 +3.3VS
SUSB#_PWR (4A)
C
+1.2VSUS C
+1.2VS (3.3A)
+1.2VO (5.4A) +1.2VS_HT
SUSB#_PWR HTVDD_EN (2.1A)
ISL6227
AC_BAT_SYS
+1.0VO (3.75A)
SUSB#_PWR +1.0VS
+1.8V (10A)
+1.8VS
+1.8VO (18.2A) SUSB#_PWR (4.5A)
SUSC#_PWR
ISL6227
+0.9VO (4.5A) +0.9VS
SUSC#_PWR SUSB#_PWR (0.5A)
+0.9V (4.0A)
B
+3VAO B
CPU_VDD_FB,
CPU_VDD_FB#,CPU_VID
MAX8760 +VCORE (35A)
CPUPWR_GD
A A
MAX8725 BAT
(Charger)
<Core Design>
WWW.AliSaler.Com
ASUSTECH Engineer: Eric_Ko
Size Project Name Rev
Custom A8T 2.1
Date: Friday, July 21, 2006 Sheet 55 of 55
5 4 3 2 1
5 4 3 2 1
AC_BAT_SYS
+ +
D D
3/8 emi
PQ6101 PQ6102
issue FDS6298 FDS6298
PR6142 (35A)
1 2
PT6102 +VCORE
0Ohm TPC28T
+3VS
r0603_h24 PR6102
PL6101 1mOhm
1 2 1 2
0.56UH
5/26 VDS issue PC6104
0.1UF/50V PR6109 +
1.82KOhm
PR6112
19,70 CPUPWR_GD
1Ohm PD6102 PC6106
1 2 EC31QS04 0.22UF/25V
5 CPU_VID0
PQ6103 PQ6104 2 1
5 CPU_VID1
FDS6676S FDS6676S
5 CPU_VID2
5 CPU_VID3
5 CPU_VID4 1 2
5 CPU_VID5
PD6103 1 PC6107
3 1000PF/50V OAIN-
C +5VS C
2 @
PR6139
PR6140 100KOhm
100KOhm 1%
5/10 change to change OCP >40A 6/14 EE change
VREF = 2V
PT6105 PR6144
SKIP#>2.7V , TWO PHASE PWM MODE
TPC28T 53.6KOhm 2.3V>SKIP#>1.2V , TWO PHASE PFM MODE
1%
SKIP#<0.8V , SINGLE PHASE PFM MODE PT6106 1 TPC28T CPU_VID0
PQ6109B
UM6K1N PT6107 1 TPC28T CPU_VID1
5
CPU_PSI#:HIGH, SKIP#=5V
5 CPU_PSI#
@ CPU_PSI#:LOW, SKIP#=1.74V PT6108 1 TPC28T CPU_VID2
2 PQ6109A
PR6141 UM6K1N PT6109 1 TPC28T CPU_VID3
470KOhm
@ PT6110 1 TPC28T CPU_VID4
A A
D D
PR6202 AC_BAT_SYS
0Ohm
1 2
PC6202 +
1UF/25V PC6204
0.1UF/25V
PQ6202
SI4800BDY
(6A)
PR6205
0Ohm PT6202 PT6201 PT6203
1 2 PT6204 TPC28T TPC28T TPC28T
TPC28T +5VO
AC_BAT_SYS +5VAO PL6201
3.8UH
PC6205 PR6206 1 2
2 1 1 2
PC6211
4.7UF/16V PT6210 PT6211 PT6212
PR6215 (6.3A) TPC28T TPC28T TPC28T (0.7A)
1 2 PT6213
TPC28T PL6202 +3VO
10KOhm 11/23/05 3.8UH PJP621 +3VSUS
1 2 1 1 2 2
F=450KHZ
1MM_OPEN_5MIL
PQ6201 @
SI4894DY PD6201
FS1J4TP
+
PCE624
150UF/4V
PT6214 PT6215 PT6216
B TPC28T TPC28T TPC28T B
PT6218 PT6217
3/3
1 1 +5VAO
PT6219
AC_BAT_SYS
TPC28T TPC28T TPC28T
PR6218 1KOhm
+12VSUS (0.02A) 2 1 RUN_3VO
31,42,67 VSUS_ON
PC6216 PU6201
4.7UF/16V 1 5 +12VO 11/02
IN OUT
2 PD6203 RB751V_40
GND 42,70 FORCE_OFF# RUN_5VO PT6220
2 1 2 1
3 4 1 2 PC6201 1 +3VSUS
EN NC or ADJ PR6201 0Ohm
4.7UF/16V
VSUS_ON MIC5235YM5 PR6219 TPC28T
845KOhm
A 3/3 A
PR6220
95.3KOhm
WWW.AliSaler.Com
Size Project Name Rev
Custom A8T 2.1
Date: Friday, July 21, 2006 Sheet 62 of 55
5 4 3 2 1
5 4 3 2 1
AC_BAT_SYS
D D
PC6302
0.1UF/50V PR6303 +5VO
0Ohm
+ PD6302
RB717F
PQ6303 PT6306
PQ6302
SI4800BDY PT6305 (2.1A) (2.1A) TPC28T
1 D1_1 G1 8 PT6303 PT6304
(6.1A) TPC28T TPC28T TPC28T +1.2VO
2 D1_2 S1/D2_3 7 3MM_OPEN_5MIL
+1.2VS_CORE PC6306 4.7UF/6.3V PL6302 @ PJP631
1 2 3 6 1 2 +1.2VO 1 1 2 2
G2 S1/D2_2
C PT6302 C
(6.1A) PT6307 PT6301 4 S2 S1/D2_1 5 3.8UH +1.2VS
TPC28T TPC28T PT6308 PU6301
TPC28T
+1.0VO TPC28T 28 1
PL6301 VCC GND SI4914DY
27 LGATE2 LGATE1 2 +
PJP632 3.8UH 26 PGND2 PGND1 3
2 1 +1.0VO 1 2 25 4 PCE631
2 1 PHASE2 PHASE1 390UF/2.5V
24 5
PR6306 UGATE2 UGATE1 PR6307
23 BOOT2 BOOT1 6
3MM_OPEN_5MIL + 1 2 22 7 1 2
@ PCE634 2.1KOhm ISEN2 ISEN1
21 EN2 EN1 8
PJP633 390UF/2.5V 20 9 1.2KOhm
VOUT2 VOUT1
2 2 1 1 19 10
VSEN2 VSEN1
18 OCSET2 OCSET1 11
17 SOFT2 SOFT1 12
3MM_OPEN_5MIL 16 13
@ PG2/REF DDR PR6301 @ 0Ohm
15 PG1 VIN 14
2 1
PR6308 @ PQ6304
2 1 SI4894DY ISL6227CAZ_T
PC6301 PR6309
0Ohm 6/14 0.1UF/25V
PR6310 old 1.07k PR6312 6.81KOhm 0Ohm
EE
0Ohm change 2 1
PR6314 6.81KOhm
2 1 +1.0VO_VSEN
PC6312 0.01UF/50V
F=300KHZ 2 1
1 2 4/19 CHANGE
VREF = 0.9V PC6311 0.01UF/50V
+3VS
B PR6315 B
PR6319 PR6320
100KOhm 100KOhm
PR6317 @ PR6318 @
old 196k 10KOhm 4.53KOHM
@ PQ6301B @ PQ6305A
UM6K1N UM6K1N
PR6321 @ @
100Ohm PQ6301A PQ6305B 2 CR_VID1 22
1 2 UM6K1N 5 UM6K1N
16,67 SUSB#_PWR
@ @ @
CR_VID0 22
@ @
PC6313 2 5
0.01UF/50V
@
@
PR6322
100Ohm
1 2
PC6314 PT6309 PT6310 PT6311 PT6312 PT6313 +1.0VO 1.21V 1.11V 1.0V
0.01UF/50V TPC28T TPC28T TPC28T TPC28T TPC28T
@
CR_VID0 0 0 1
A A
CR_VID1 0 1 0
<Core Design>
70 1.2VO_1.0VO_PWRGD
Title : POWER_I/O_1.2VO & 1.0VO
5 4 3 2 1
5 4 3 2 1
3/13
TPC28T
+3VA TPC28T change
PT6402 PT6403
PJP641
+3VAO 1 2 +5VO +1.8VS
1 2 TPC28T TPC28T
3/13 change
1MM_OPEN_5MIL @ PJP642 PT6404 PT6405
2MM_OPEN_5MIL
PR6402
TPC28T @ PU6402 18.2KOhm
Vref = 1.23V PT6406 +3VAO +1.8VS 1 2 1 8 TPC28T
1 2 VIN PGND PT6407
2 7
D VFB AGND D
3 6
TPC28T PJP643 VOUT0 VCCA
IOUT = 40 ~ 60mA 4
VOUT1 REFEN
5
PT6408 2MM_OPEN_5MIL
@
+1.5VS 1 2 CM8562GISTR
PU6403 PR6404 1 2
1 8 16.9KOhm (2A)
ADJ GND4
AC_BAT_SYS 2 IN GND3 7 +
3 6 PCE641 PC6402
OUT GND2 TPC28T 0.1UF/25V
4 EN GND1 5 150UF/2V
PT6401
MIC5236YM
+1.5VO
PC6404
10UF/6.3V
PC6405 PR6407
1UF/25V 10KOhm
+3VA
+1.5VS
3/13
change
C C
3/13 change +5VO +1.8VS
TPC28T TPC28T
PJP647 PT6419 PT6420
2MM_OPEN_5MIL
PR6423
PU6405 18.2KOhm
(0.12A) +1.8VS 1 1 2 2 1 VIN PGND 8 TPC28T
Vref=1.215V 2 7 PT6421
+3VO PT6410 +1.5VSUS PT6411 VFB AGND
3 VOUT0 VCCA 6
TPC28T TPC28T TPC28T PJP648 4 5
PU6401 PT6422 2MM_OPEN_5MIL VOUT1 REFEN
1 PJP644
VIN CM8562GISTR
VOUT 5
PR6411
1 1 2 2 +1.5VS_VG 1 1 2 2
2 GND
FB 4 1 2
3 1MM_OPEN_5MIL +
SD# 23.7KOhm @ PCE643 PC6418
SI9183DT TPC28T PC6419 150UF/2V 0.1UF/25V
PT6423 10UF/10V
PR6414
100KOhm PC6408 +1.5VO_VG
PC6409 4.7UF/6.3V
1UF/10V
+1.5VS_VGA
B B
+1.5VSUS
+3VS
+3VSUS
PR6417 PT6413
3/13 change +3VSUS 100KOhm TPC28T PR6408 PT6409
3/13 change +3VA 100KOhm TPC28T
<Core Design>
Title : POWER_I/O_LDO
WWW.AliSaler.Com
+2.5VS
5 4 3 2
ASUSTECH
C
Date:
Size Project Name
A8T
Friday, July 21, 2006
1
Engineer:
Sheet
Eric_Ko
64 of 55
Rev
2.1
5 4 3 2 1
+5VO
PR6502
2 1
0Ohm
@ AC_BAT_SYS
PR6504
D + D
0Ohm
PR6505
0Ohm
@ PQ6501
PR6506 PD6502 FDS6298
22KOhm 1 2
67 SUSC#_PWR 2 1
PT6502
PC6504 RB751V_40 TPC28T PT6503
0.033UF/16V PT6501 TPC28T PT6504 PT6505
PT6506 TPC28T +1.8VO TPC28T TPC28T
PR6507 TPC28T
0Ohm (12A)
PR6508 @ 5/26 VDS issue PL6501 (12A) PJP652
0Ohm 1 2 1 2
1 2 +1.8V
@ PR6509
2 1 1 21 1Ohm PC6506 1.8UH 3MM_OPEN_5MIL
70 DDR_PWRGD TON DL
2 20 1 2 2 1 H=4.0mm @
PD6503 OVP/UVP BST
3 19
REF LX 0.22UF/25V PJP653
2 1 4 18 +
ILIM DH
5 POK1 VIN 17 1 1 2 2
1SS355 6 16
POK2 OUT PD6501 3MM_OPEN_5MIL
67 SUSC#_PWR 2 1 7 15
PC6508 STBY# FB @
PR6510 22KOhm 0.033UF/16V
VILIM=0.905V, FS1J4TP
Set OCP to PJP651
12.57A PR6511 1 2
150KOhm PU6501 1 2
1% PC6510 MAX8632ETI 3MM_OPEN_5MIL
6/29 modify ocp 0.22UF/10V @
C PR6512 C
point
+1.8VO 2 1 FB=AVDD,OUTPUT=1.8V
PR6514 10Ohm
0Ohm PR6513 2 1
@ 124KOhm 6/29
1%
change
For foldback PR6501
current limit For output adjustable 15.8KOhm
2 1
+0.9VO
PT6507 PR6515
TPC28T 10KOhm 1 2
(1.0A) 1%
PC6517
(1.0A) 4700PF/50V
+0.9V @ PJP654
1 1 2 2
1MM_OPEN_5MIL
PT6508 PT6509 PT6510 PT6511 PT6512
TPC28T TPC28T TPC28T TPC28T TPC28T
PC6518
0.1UF/25V
B B
A A
<Core Design>
Title : POWER_I/O_DDRII
<OrgName> Engineer: Eric_Ko
Size Project Name Rev
Custom A8T 2.1
Date: Friday, July 21, 2006 Sheet 65 of 55
5 4 3 2 1
5 4 3 2 1
TPC28T
PT6702 +3VO PT6704
TPC28T
PQ6702
+1.2VO 8 D S 1 +1.2VS_HT 1.2VHT_EN_ON
7 2 PR6702
100KOhm
PT6705
6
5
3
4 PC6702
(2.62A)
G
TPC28T 0.1UF/25V PQ6703A
PQ6704 UM6K1N
SI4800BDY PR6703 2
1 6 10KOhm PT6706
+0.9VO D +0.9VS 1.2VHT_EN_ON 1
2 5 2 +12VSUS TPC28T
S 4 PQ6703B
3
G
(0.5A) PC6704 UM6K1N
PMN45EN PC6703 0.1UF/25V HTVDD_EN 5
19 HTVDD_EN
0.1UF/25V
D D
3/14 PR6717
470KOhm
3/6 for add @
PJP674
3/13 timing
@ 1 2
change issue 1 2
SGL_JUMP
@
PQ6705 VSUS_ON 31,42,46
DRAIN_1 DRAIN_2 PT6707 PT6708
1 8 TPC28T TPC28T
+1.8VO
SOURCE_1 SOURCE_3 PJP672
2 7
3 6 +1.8VS +3VA 1 1 2 2 CPU_VRON_PWR 61
SOURCE_2 SOURCE_4
4 5 (4.08A) SGL_JUMP
GATE_1 GATE_2 @
PQ6701A
PQ6707B UM6K1N
UM6K1N 2
TPC28T TPC28T SUSB#_PWR 5
PT6714 PT6715
PQ6701B
PQ6708 TPC28T TPC28T PT6718 UM6K1N
DRAIN_1 DRAIN_2
+5VO 1 8 PT6716 PT6717 TPC28T SUSC#_PWR 5
SOURCE_1 SOURCE_3
2 7 PR6719
3 6 470KOhm
+5VS
SOURCE_2 SOURCE_4 @
GATE_1
4 5
GATE_2 PC6710
(4.137A)
0.1UF/25V
+3VA +3VA 22,38,41,48,71
FDW2501NZ
+5VO +5VO 5,46,47,48,65,71
PR6709
AC_BAT_SYS AC_BAT_SYS 16,17,46,47,48,61,65,68,71
10KOhm
TPC28T SUSB#_PWR_ON 2 1 TPC28T +VCORE
+VCORE 5,7,61
PT6719 PT6720
PQ6709 +5VAO 46,70
+5VAO
UMC4N
+12VS +3VO +3VO 46,48
+12VSUS PT6721
TPC28T PR6710
1KOhm
(0.01A) +3V +3V 22
PR6711 +1.2VO
22,31,32,42,70 SUSB# +1.2VO 47
PT6722 100KOhm
TPC28T +12VSUS
+12VSUS 46
PR6701
100KOhm +0.9VS 16
16,47 SUSB#_PWR +0.9VS
@
B B
+2.5VO +2.5VO 48
+1.2VSUS
+1.2VSUS
+1.2VS +1.2VS 11,12,13,14,15,23,47
TPC28T TPC28T TPC28T TPC28T TPC28T
PT6723 PT6724 PT6725 PT6726 PT6727
+3VS +3VS 5,13,14,15,19,20,21,22,23,39,47,48,61,70
PQ6710
+3VSUS +3VSUS 5,20,22,23,32,46,48,70
+3VO 1 6 +3V
2 D 5
S 4 +1.5VSUS +1.5VSUS 23,48
3
G PC6712
(0.81A)
+0.9V +0.9V 7,48,65
PMN45EN 0.1UF/25V
@
+12V +12V 25,35,37,40
+12VS +12VS 41
TPC28T TPC28T TPC28T
+5V +5V 31
TPC28T TPC28T PT6729 PT6730 PT6731
PT6701 PT6728
+5VS +5VS 14,23,61
PQ6711
DRAIN_1 DRAIN_2 +5V +2.5VS +2.5VS 5,11,14,15,48
+5VO 1 8
SOURCE_1
2
SOURCE_3
7 PC6701
(3.0A) +1.8VO +1.8VO 65
Title : POWER_LOAD_SYSTEM
WWW.AliSaler.Com
ASUSTECH Engineer: Eric_Ko
Size Project Name Rev
Custom A8T 2.1
Date: Friday, July 21, 2006 Sheet 67 of 55
5 4 3 2 1
5 4 3 2 1
71 CHG_SRC
71 CSSP
71 CSSN
maxim
recommend
1uF 3/6 PT6802
TPC28T
change
71 MAX8725_PDS
71 MAX8725_PDL AC_BAT_SYS
D D
+
MAX8725_LDO A/D_DOCK_IN PT6803 PT6804
A/D_DOCK_IN TPC28T TPC28T
PT6805 PQ6802
PKPRES# TPC28T SI4835BDY
MAX8725_LDO
CHG_GND
LDO : 5.4V PD6802 MAX8725_LDO
1SS355
PQ6803A PR6803
UM6K1N REF : 4.2235V PR6805 33Ohm
2 100KOhm PU6801
MAX8725_REF 1 2 PC6806 PT6808 PT6809
1UF/25V PT6807 TPC28T TPC28T
1 21 1 2 TPC28T
DCIN DLOV PL6801 PR6806
2 20
PT6810 LDO DLO 10UH 25mOHM
3 19
TPC28T ACIN PGND BAT
4 REF CSIP 18 1 2 1 2 BAT
PQ6803B 5 17
UM6K1N PC6807 GND/PKPRES# CSIN
6 16
0.22UF/10V ACOK BATT
39,69,71 TS# 5 7 15
PT6811 MODE GND1
PR6807 TPC28T PQ6804
13.3KOhm MAX8725ETI SI4800BDY +
C 6/14 EE change C
CHG_GND
5/17 AD_IINP
PC6811
0.047UF/16V
PR6813
2.7KOhm PR6816
10KOhm
PT6812 PQ6806 3
D
TPC28T 2N7002
05/05 5,22,71 PWRLMT#
PT6814 1
PQ6801B 3/3 TPC28T G
5 UM6K1N 2 S
69 PRECHG
69 CHG_EN#
PR6828
470KOhm PR6825 PT6818
470KOhm TPC28T
@ PT6801 @ 1 +5VLCM +2.5VREF
TPC28T PT6815
B TPC28T B
PD6803 PC6814
69 AC_APR_UC
PR6818 PR6826 1SS355 0.1UF/25V PU6802 PR6801
4.7KOhm 15KOhm LMV321IDBVR 107KOhm
AC_IN# 28 3
+5VCHG 1 2 1 2 D 2 1
PIC16F54
+5VLCM
PU6902
5 VCC NC 1
PC6902 2
1UF/25V SUB
D 4 VOUT GND 3 D
TPC28T TPC28TTPC28T TPC28T TPC28T TPC28T MLCC/+80%-20% TPC28T
PT6901 PT6902PT6903 PT6904 PT6905 PT6906 PST9142NR PT6907 TPC28T
PT6908
PU6903
41 CHG_LED_UP 1 RA2 20 AC_APR_UC 68
RA1
68 CHG_EN# 2 RA3 RA0 19 TS# 39,68,71
3 T0CKI 18
VPP4 OSC1/CLKIN TPC28T TPC28T TPC28T
22 CHG_FULL_OC 1 2 MCLR#/VPP 17
OSC2/CLKOUT PT6909 PT6910 PT6911
5 VSS1 VDD2 16
PD6901 RB751V_40 6 15
VSS2 VDD1 ICSPDAT BAT_LLOW
28,39 SMC_BAT 7 RB0 RB7/ICSPDAT 14
8 13 ICSPCLK
28,39 SMD_BAT RB1 RB6/ICSPCLK BATSEL_2P#
22 BATT_TALARM 9 12 BATSEL_3S#
ADP_ERR# RB2 RB5
10 RB3 RB4 11 1 2 PRECHG 68
PIC16F54 TPC28T PR6905 TPC28T PR6904
PT6912 1 2 PT6913 10KOhm_0402
1MOhm_0402
TPC28T
PX6901 @ PT6914
@ PD6906 1 3
RB751V_40 GND PC6903
BAT_LLOW#_OC 28
0.1UF/10V
2 1 4MHZ MLCC/+/-10%
3
D
C 6/14 EE change PQ6902 C
BAT_LLOW 1
1 2 G 2N7002
2 S
PR6918
0Ohm
PR6910
B 120KOhm PD6905 +5VLCM B
1% 2 1 ICSPDAT
+2.5VREF ADP_ERR# VPP ICSPCLK
1SS355
1 V+ PU6901
+
4 1 2 1 B VCC 5
3 3 PCO691
- D
V- PR6911 +5VCHG 2 A PIC_REFRESH_5P
+5VCHG
PU6904 100KOhm PQ6901
LMV321IDBVR 3 GND 4 1 2N7002
PC6904 @ Y G
PR6901 0.1UF/25V 2 S
PC6905 20KOhm NL17SZ08XV5T2
0.1UF/25V 1% @ AC_APR_UC For PIC
refresh
3
D
PQ6903
1 2N7002
G
2 S
Adaptor error circuit for +19V adaptor PR6914
470KOhm
Vth = 17.5V (MAX. 17.8V & MIN. 17.2V)
A A
<Core Design>
Title : POWER_PIC
WWW.AliSaler.Com
<OrgName> Engineer: Eric_Ko
Size Project Name Rev
Custom A8T 2.1
Date: Friday, July 21, 2006 Sheet 69 of 55
5 4 3 2 1
A B C D E
A/D_DOCK_IN
PR7002
47KOHM
PT7002
1 PR7003 TPC28T 1
100KOhm
PT7003
TPC28T OVP=13.405V
THERMAL PROTECTION
+5VAO
Place under CPU
2
E @ PC7002 +5VLCM +2.5VREF
PQ7002 0.1UF/25V BAT_S
68 A/D_SD# B 1
C PMBS3906 PR7005
3 10KOhm
PT7004
PR7006 PR7007 TPC28T PRT701
PQ7003 PT7006 316KOhm 10KOhm 2 1
PMBS3904 PT7005 324k 1%->316k +5VLCM
3 TPC28T TPC28T 100KOhm
C 0.1% PU7001 PC7003
B 1 1 8 0.1UF/16V
VOUT1 VCC
2 VIN1- VOUT2 7
E 3/13 3 6 2 1
2 VIN1+ VIN2-
change 4 GND VIN2+ 5
6/14 EE change
3 3
5,22 PWRGD
+3VSUS +3VS
PT7014 PR7012
TPC28T
22,31,32,42,67 SUSB#
100KOhm PR7001
PT7015
PD70011SS355 100KOhm TPC28T
46 VSUS_GD# 2 1
PT7016 PR7013
TPC28T PD7002 1MOhm
PJP701 1SS355
47 1.2VO_1.0VO_PWRGD 2 1 @
PT7020 PQ7001B
4 TPC28T SHORTPIN UM6K1N 4
PJP702 TPC28T 5
16,20 VGA_PWRGD 2 1 @ +3VSUS PT7022 PR7014
PT7023 PQ7001A
SHORTPIN UM6K1N 0Ohm
TPC28T
PJP703 PU7003 PWROK 2 PC7011
65 DDR_PWRGD 2 1 @ 1 A VCC 5 1UF/10V
FORCE_OFF# 42,46
SHORTPIN 2 B
+3VSUS PR7016
3 GND 4 470KOhm
Y
NC7SZ08P5X
PR7015
11/09 100KOhm
PT7024
TPC28T
19,61 CPUPWR_GD
5 5
<Core Design>
Title : POWER_PROTECT