A B C D E

1 1

PGRAA
2
Superior 10RH 2

LA-7191P REV 1.0 Schematic

3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3

2011-04-26 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 1 of 50
A B C D E
 A B C D E

Compal Confidential
PWM Fan Control Circuit
Model Name : PGRAA Intel CPU page 5
File Name : LA-7191P PCI-Express 16X 5GHz Sandy Bridge
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
1
Dual Channel BANK 0, 1, 2, 3 page 11,12
1

rPGA-989
37.5mm*37.5mm
1.5V DDRIII 1066/1333 MT/s

page 5,6,7,8,9,10

VGA Board connector (GDDR5) USB/B Right Left USB FingerPrinter

USB port 0,1 USB port 2 USB port 8
CRT FDI X8 DMI X4 page 26 page 26 page 35
NVIDIA N11E-GS, 192bit with 1.5GB/3GB page 15
2.7GT/s 5GT/s
IR Emitter Blue Tooth Int. Camera
page 13 USB port 5 USB port 4 USB port 11
USB page 32 page 32 page 14
5V 480MHz

LVDS PCIeMini Card

LVDS Conn.
EDP page 14
USB WiMax USB port 13
2
5V 480MHz page 27 PCIeMini Card 2

PCIe 1x PCIeMini Card JET

EC SMBus 1.5V 5GT/s
HDMI-CEC HDMI Conn. WLAN PCIe port 2 PCIe port 3
page 16 page 27 page 27

page 16 Intel PCH SATA port 0 SATA HDD1

Cougar Point - M 5V 6GHz(600MB/s) SATA port 1
page 26

RJ45 RTL8111E 1G PCIe 1x SATA port 1 SATA HDD2

page 28 1.5V 5GT/s 5V 6GHz(600MB/s) SATA port 2
PCIe port 1 page 26
page 28
FCBGA-989
25mm*25mm
SATA port 2 SATA ODD
Cardreader PCIe 1x 5V 3GHz(300MB/s) SATA port 4
page 26
VGA/B JMB389C 1.5V 5GT/s
PCIe port4 page 17,18,19,20,21,22,23,24,25 PCIe 1x
page 29
3
LS-7191P page 13 1.5V 5GT/s USB3.0 3
TUSB7320
PCIe port6
page 30
Light Bar/B
LPC BUS HD Audio 3.3V 24MHz
LS-7192P page 35
3.3V 33 MHz

TP/B HDA Codec

LS-7193P page 35 ALC269
SPI ROM Debug Port ENE KB930 page 31
page 34 page 33

ODD/B (4MB)
page 17
RTC CKT.
page 17
LS-7194P page 26

Touch Pad Int.KBD EC ROM CIR G-Sensor Int. SPK Conn JPIO Subwoofer
page 31
LED/B page 35 page 34 page 33 page 34 MIC Conn (HP &page
MIC) APA3011
DC/DC Interface CKT. LS-7195P page 35
(128KB)
page 34
page 14 26 page 26

page 36 EC SMBus
Audio & USB/B Cap Sensor SUB Conn
4 page 26 4

Power Circuit DC/DC LS-6064P page 26 & Light Sensor/B

page 37,38,39,40, LS-6062P page 35
41,42,43,44
Finger Printer/B
LS-6065P page 35 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

Power On/Off CKT. Power/B_FPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 35 DA300006JM0 page 35 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7 B

Date: Friday, September 16, 2011 Sheet 2 of 50

A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
SUSP#

SUSP

N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800
KB_LED
D DESIGN CURRENT 400mA D

P-CHANNEL
+5VS_LED
AO-3413
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
TPS51125ARGER ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413

DESIGN CURRENT 2A +1.8VS

SY8033BDBC
SUSP

N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

C
AO-3415 C
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413

DGPU_PWR_EN
DESIGN CURRENT 0.5A +3VS_DGPU
P-CHANNEL
AO-3413

VR_ON

DESIGN CURRENT 94A +CPU_CORE

ISL95831CRZ
DESIGN CURRENT 33A +GFX_CORE

VCCPPWRGD

Ipeak=6A, Imax=4.2A, Iocp min=7.69 DESIGN CURRENT 6A +VCCSA

G5603RU1U
SUSP#

B DESIGN CURRENT 7A B
Ipeak=7A, Imax=4.9A, Iocp min=7.7 +1.05VS
G5603RU1U

SUSP#
Ipeak=7.5A, Imax=5.25A, Iocp min=9.09 DESIGN CURRENT 9A +1.5V
G5603RU1U SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
SUSP

N-CHANNEL DESIGN CURRENT 1.5A +1.5VS

FDS6676AS
VGA_PWROK
SUSP or 0.75VR_EN#

DESIGN CURRENT 1A +0.75VS

G2992F1U

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 3 of 50
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails BTO Option Table
+5VS
Platform SKU CPU PCH
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW Discrete Clarksfield/
+1.8VS HM65
+VSB Huron River (DIS@) Arrandale
power +1.5VS
1 plane +1.05VS
Optimus 1

(OPT@) Arrandale HM65

+0.75VS
+CPU_CORE
+GFX_CORE Function HDMI
+VTT
description HDMI
+3VS_DGPU
State
explain Optimus Discrete CEC

BTO IHDMI@ DHDMI@ CEC@

Function MINI PCI-E SLOT Fingerprint KB Light

S0 description SLOT2 SLOT1 Fingerprint KB Light

O O O O O O
explain WIMAX Fingerprint KB Light
S1
O O O O O O
BTO FP@ KBL@
2 2
S3
O O O O O X
Function BLUE TOOTH SKU LVDS CIR
S5 S4/AC
O O O O X X
description BLUE TOOTH SKU 3D Panel CIR
S5 S4/ Battery only
O O O X X X explain BLUE TOOTH Discrete Optimus Discrete Optimus CIR

S5 S4/AC & Battery BTO BT@ DIS@ OPT@ DIS@ OPT@ CIR@
don't exist
O X X X X X
Function EC

PCH SM Bus Address description

explain KB930QF KB9012QF Trial run phase MP Phase
Power Device HEX Address 930@ 9012@ DBG@ MP@
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3

+3VS WLAN/WIMAX

SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH

+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VS G-Sensor 40 H 0100 0000 b
+3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW
Power Device HEX Address
G3 LOW LOW LOW
+3VL Cap. Sensor Virtual I2C
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 4 of 50
A B C D E
 5 4 3 2 1

JCPUB

100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI Stuff R41 and R42 if do not support eDP
CLK_CPU_DMI 18

MISC
BCLK

CLOCKS
1000P_0402_50V7K 2 1 C487 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#
21 H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# 18
@ +1.05VS_VCCP
120 MHz
1000P_0402_50V7K 2 1 C488 H_PWRGOOD T1 PAD TP_SKTOCC# AN34 SKTOCC# CLK_CPU_DPLL
DPLL_REF_SSCLK A16
A15 CLK_CPU_DPLL# CLK_CPU_DPLL# R42 1 2 1K_0402_5%
DPLL_REF_SSCLK#
D CLK_CPU_DPLL R41 1 D
2 1K_0402_5%
T2 PAD H_CATERR# AL33 CATERR#

THERMAL
H_PECI AN33 R8 H_DRAMRST#
33 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7

DDR3
MISC
+1.05VS_VCCP R450
33,38 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% A5 SM_RCOMP_1 R1438 2 1 25.5_0402_1% Layout Note:Place these
R47 SM_RCOMP[1]
2 1 62_0402_5% H_PROCHOT#
SM_RCOMP[2] A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
R14
22 H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 THERMTRIP#
0_0402_5%
R51 2 1 10K_0402_5% H_PWRGOOD

AP29 XDP_PRDY# PAD T48

PRDY# XDP_PREQ# PAD T49
PREQ# AP27

AR26 XDP_TCK_R
TCK

PWR MANAGEMENT
XDP_TMS_R

JTAG & BPM

TMS AR27
19 H_PM_SYNC H_PM_SYNC AM34 AP30 XDP_TRST#_R
PM_SYNC TRST#
AR28 XDP_TDI_R
TDI XDP_TDO_R
TDO AP26
22 H_PWRGOOD H_PWRGOOD AP33 R36
UNCOREPWRGOOD
1 2 +3VS
1K_0402_5%
AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# 19
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8
C R454 130_0402_5% SM_DRAMPWROK C
AT28 XDP_BPM#0 PAD T3
BPM#[0] XDP_BPM#1 PAD T4
BPM#[1] AR29
AR30 XDP_BPM#2 PAD T8
BUF_CPU_RST# BPM#[2] XDP_BPM#3 PAD T9
AR33 RESET# BPM#[3] AT30
AP32 XDP_BPM#4 PAD T10
BPM#[4] XDP_BPM#5 PAD T45
BPM#[5] AR31
AT31 XDP_BPM#6 PAD T46
+3VALW BPM#[6] XDP_BPM#7 PAD T47
BPM#[7] AR32

+1.5V_CPU
1
C93
0.1U_0402_16V4Z Sandy Bridge_rPGA_Rev0p61 @
1

2
U10 R339
R312 74AHC1G09GW_TSSOP5 200_0402_5%
5

0_0402_5%
2

1 2 1
P

19,33 PM_PWROK B
4 PM_SYS_PWRGD_BUF
O
19 DRAMPWROK 2 A PU/PD for JTAG signals
G

+1.05VS_VCCP
1
3

R340 XDP_TMS_R R28 2 1 51_0402_5%

39_0402_5%
@ XDP_TDI_R R29 2 1 51_0402_5%
R3841 @ 2 0_0402_5%
1 2

XDP_TDO_R R30 2 1 51_0402_5%

D
9,27,36,43 SUSP SUSP 2 Q5 XDP_TCK_R R31 2 1 51_0402_5%
G @
B S 2N7002_SOT23-3 XDP_TRST#_R R32 B
2 1 51_0402_5%
3

FAN Control Circuit

+3VS

1
R3
Buffered Reset to CPU 10K_0402_5%
JFAN
1

2
FANPWM 1
33 FANPWM 2 2
33 FAN_SPEED1 3 3
+3VS +FAN1 4
1 4
C6
0.01U_0402_25V7K ACES_85204-0400N
+5VS @ @
2
1 0.1U_0402_16V4Z
C84
+1.05VS_VCCP
PLT_RST# 21,27,28,29,30,33,34
1A R154
40 mil
2 +FAN1 +5VS
1 2
1

U3 2 0_0603_5% D57
PLT_RST# 1 R69 1 2
OE# 1 2

1
5 75_0402_5% C3 @ 2 1
VCC 10U_0805_10V6K 1SS355TE-17_SOD323-2
R155 1 D86 C4 C379
2
2

IN 43_0402_1%
A BUFO_CPU_RST# 1 2 A
4 1 2 BUF_CPU_RST#

2
OUT BAS16_SOT23-3 10U_0805_10V6K 1000P_0402_50V7K
3 GND
1

74AHC1G125GW_SOT353-5 R209
0_0402_5% Close to Connector
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 5 of 50
5 4 3 2 1
 5 4 3 2 1

PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical

1
impedance = 43 m ohm (4 mils)
R34
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)

2
D J22 PEG_COMP D
PEG_ICOMPI
PEG_ICOMPO J21
DMI_PTX_CRX_N0 B27 H22
19 DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_PTX_CRX_N1 B25
19 DMI_PTX_CRX_N1 DMI_RX#[1]
DMI_PTX_CRX_N2 A25
19 DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_CRX_N[0..15] 13
DMI_PTX_CRX_N3 B24 K33 PCIE_GTX_C_CRX_N0 C520 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N0
19 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
M35 PCIE_GTX_C_CRX_N1 C521 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N1
DMI_PTX_CRX_P0 PEG_RX#[1] PCIE_GTX_C_CRX_N2 C522 .1U_0402_16V7K PCIE_GTX_CRX_N2
19 DMI_PTX_CRX_P0 B28 DMI_RX[0] PEG_RX#[2] L34 1 2
DMI_PTX_CRX_P1 B26 J35 PCIE_GTX_C_CRX_N3 C523 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N3
19 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_PTX_CRX_P2 A24 J32 PCIE_GTX_C_CRX_N4 C524 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N4
19 DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 B23 H34 PCIE_GTX_C_CRX_N5 C525 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N5
19 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
H31 PCIE_GTX_C_CRX_N6 C526 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N6
DMI_CTX_PRX_N0 PEG_RX#[6] PCIE_GTX_C_CRX_N7 C527 .1U_0402_16V7K PCIE_GTX_CRX_N7
19 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2
DMI_CTX_PRX_N1 E22 G30 PCIE_GTX_C_CRX_N8 C528 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N8
19 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 F21 F35 PCIE_GTX_C_CRX_N9 C529 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N9
19 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
DMI_CTX_PRX_N3 D21 E34 PCIE_GTX_C_CRX_N10 C530 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N10
19 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
E32 PCIE_GTX_C_CRX_N11 C531 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N11
DMI_CTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_CRX_N12 C532 .1U_0402_16V7K PCIE_GTX_CRX_N12
19 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2
DMI_CTX_PRX_P1 D22 D31 PCIE_GTX_C_CRX_N13 C533 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N13
19 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]

PCI EXPRESS* - GRAPHICS

DMI_CTX_PRX_P2 F20 B33 PCIE_GTX_C_CRX_N14 C534 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N14
19 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
DMI_CTX_PRX_P3 C21 C32 PCIE_GTX_C_CRX_N15 C535 1 2 .1U_0402_16V7K PCIE_GTX_CRX_N15
19 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_CRX_P[0..15] 13
J33 PCIE_GTX_C_CRX_P0 C536 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P0
PEG_RX[0] PCIE_GTX_C_CRX_P1 C537 .1U_0402_16V7K PCIE_GTX_CRX_P1
PEG_RX[1] L35 1 2
K34 PCIE_GTX_C_CRX_P2 C538 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P2
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_CRX_P3 C539 .1U_0402_16V7K PCIE_GTX_CRX_P3
19 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 1 2
FDI_CTX_PRX_N1 H19 H32 PCIE_GTX_C_CRX_P4 C540 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P4
19 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
FDI_CTX_PRX_N2 E19 G34 PCIE_GTX_C_CRX_P5 C541 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P5
19 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 PCIE_GTX_C_CRX_P6 C542 .1U_0402_16V7K PCIE_GTX_CRX_P6

Intel(R) FDI
19 FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31 1 2
C FDI_CTX_PRX_N4 B21 F33 PCIE_GTX_C_CRX_P7 C543 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P7 C
19 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
FDI_CTX_PRX_N5 C20 F30 PCIE_GTX_C_CRX_P8 C544 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P8
19 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 D18 E35 PCIE_GTX_C_CRX_P9 C545 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P9
19 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_C_CRX_P10 C546 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P10
19 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PCIE_GTX_C_CRX_P11 C547 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P11
PEG_RX[11] PCIE_GTX_C_CRX_P12 C548 .1U_0402_16V7K PCIE_GTX_CRX_P12
PEG_RX[12] D34 1 2
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_C_CRX_P13 C549 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P13
19 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 G19 C33 PCIE_GTX_C_CRX_P14 C550 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P14
19 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_C_CRX_P15 C551 1 2 .1U_0402_16V7K PCIE_GTX_CRX_P15
19 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3 G18
19 FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] 13
FDI_CTX_PRX_P4 B20 M29 PCIE_CTX_GRX_N0 C39 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N0
19 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 C19 M32 PCIE_CTX_GRX_N1 C40 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N1
19 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI_CTX_PRX_P6 D19 M31 PCIE_CTX_GRX_N2 C41 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N2
19 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
FDI_CTX_PRX_P7 F17 L32 PCIE_CTX_GRX_N3 C42 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N3
19 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PCIE_CTX_GRX_N4 C43 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N4
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N5 C44 .1U_0402_16V7K PCIE_CTX_C_GRX_N5
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
19 FDI_FSYNC1 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_N6 C45 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N6
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N7 C46 .1U_0402_16V7K PCIE_CTX_C_GRX_N7
PEG_TX#[7] J30 1 2
19 FDI_INT FDI_INT H20 J28 PCIE_CTX_GRX_N8 C47 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N9 C48 .1U_0402_16V7K PCIE_CTX_C_GRX_N9
PEG_TX#[9] H29 1 2
eDP_COMP signals should be 19 FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N10 C49 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N10
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N11 C50 .1U_0402_16V7K PCIE_CTX_C_GRX_N11
19 FDI_LSYNC1 H17 E29 1 2
shorted near balls and FDI1_LSYNC PEG_TX#[11]
F27 PCIE_CTX_GRX_N12 C52 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] PCIE_CTX_GRX_N13 C51 .1U_0402_16V7K PCIE_CTX_C_GRX_N13
routed with typical PEG_TX#[13] D28 1 2
F26 PCIE_CTX_GRX_N14 C59 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N14
impedance <25m ohm PEG_TX#[14]
E25 PCIE_CTX_GRX_N15 C53 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_N15
R9 EDP_COMP PEG_TX#[15]
+1.05VS_VCCP 1 2 24.9_0402_1% A18 eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] 13
A17 M28 PCIE_CTX_GRX_P0 C60 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P0
R33 eDP_ICOMPO PEG_TX[0]
+1.05VS_VCCP 1 2 10K_0402_5% B16 eDP_HPD PEG_TX[1] M33 PCIE_CTX_GRX_P1 C72 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P1
B PCIE_CTX_GRX_P2 C73 .1U_0402_16V7K PCIE_CTX_C_GRX_P2 B
PEG_TX[2] M30 1 2
L31 PCIE_CTX_GRX_P3 C74 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[3] PCIE_CTX_GRX_P4 C76 .1U_0402_16V7K PCIE_CTX_C_GRX_P4
C15 eDP_AUX PEG_TX[4] L28 1 2
D15 K30 PCIE_CTX_GRX_P5 C75 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P5
eDP_AUX# PEG_TX[5]
eDP

K27 PCIE_CTX_GRX_P6 C78 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P6

PEG_TX[6] PCIE_CTX_GRX_P7 C77 .1U_0402_16V7K PCIE_CTX_C_GRX_P7
PEG_TX[7] J29 1 2
C17 J27 PCIE_CTX_GRX_P8 C62 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P8
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_P9 C61 .1U_0402_16V7K PCIE_CTX_C_GRX_P9
F16 eDP_TX[1] PEG_TX[9] H28 1 2
C16 G28 PCIE_CTX_GRX_P10 C67 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P10
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P11 C66 .1U_0402_16V7K PCIE_CTX_C_GRX_P11
G15 eDP_TX[3] PEG_TX[11] E28 1 2
F28 PCIE_CTX_GRX_P12 C69 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] PCIE_CTX_GRX_P13 C68 .1U_0402_16V7K PCIE_CTX_C_GRX_P13
C18 eDP_TX#[0] PEG_TX[13] D27 1 2
E16 E26 PCIE_CTX_GRX_P14 C71 1 2 .1U_0402_16V7K PCIE_CTX_C_GRX_P14
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P15 C70 .1U_0402_16V7K PCIE_CTX_C_GRX_P15
D16 eDP_TX#[2] PEG_TX[15] D25 1 2
F15 eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61 @

Typ- suggest 220nF. The change in AC capacitor

value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Close to CPU Gen3 (8GT/s)

FDI_INT 1 DIS@ 2
A
R689 1K_0402_5% A
FDI_FSYNC0 1 DIS@ 2
R690 1K_0402_5%
FDI_FSYNC1 1 DIS@ 2
R695 1K_0402_5%
FDI_LSYNC0 1 DIS@ 2
R696 1K_0402_5%
FDI_LSYNC1 1 DIS@ 2
Security Classification Compal Secret Data Compal Electronics, Inc.
R697 1K_0402_5% 2010/09/09 2011/09/09 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 6 of 50
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

JCPUC JCPUD
11 DDR_A_D[0..63]
12 DDR_B_D[0..63]

AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0 11 SB_CLK[0] DDRB_CLK0 12
AA6 DDRA_CLK0# AD2 DDRB_CLK0#
SA_CLK#[0] DDRA_CLK0# 11 SB_CLK#[0] DDRB_CLK0# 12
DDR_A_D0 C5 V9 DDRA_CKE0 DDR_B_D0 C9 R9 DDRB_CKE0
SA_DQ[0] SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDRA_CLK1 DDR_B_D4 SB_DQ[3] DDRB_CLK1
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 11 A9 SB_DQ[4] SB_CLK[1] AE1 DDRB_CLK1 12
D DDR_A_D5 DDRA_CLK1# DDR_B_D5 DDRB_CLK1# D
C6 SA_DQ[5] SA_CLK#[1] AB5 DDRA_CLK1# 11 A8 SB_DQ[5] SB_CLK#[1] AD1 DDRB_CLK1# 12
DDR_A_D6 C2 V10 DDRA_CKE1 DDR_B_D6 D9 R10 DDRB_CKE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6] SB_CKE[1] DDRB_CKE1 12
DDR_A_D7 C3 DDR_B_D7 D8
DDR_A_D8 SA_DQ[7] DDR_B_D8 SB_DQ[7]
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
DDR_A_D16 SA_DQ[15] DDR_B_D16 SB_DQ[15]
K4 SA_DQ[16] SA_CLK[3] AB3 J7 SB_DQ[16] SB_CLK[3] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W10 K10 SB_DQ[18] SB_CKE[3] T10
DDR_A_D19 J1 DDR_B_D19 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDRA_SCS0# DDR_B_D22 SB_DQ[21] DDRB_SCS0#
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# 11 K8 SB_DQ[22] SB_CS#[0] AD3 DDRB_SCS0# 12
DDR_A_D23 K2 AL3 DDRA_SCS1# DDR_B_D23 K7 AE3 DDRB_SCS1#
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[23] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D25 SB_DQ[24] SB_CS#[2]
N10 SA_DQ[25] SA_CS#[3] AH1 N4 SB_DQ[25] SB_CS#[3] AE6
DDR_A_D26 N8 DDR_B_D26 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDRA_ODT0 DDR_B_D29 SB_DQ[28] DDRB_ODT0
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 11 N5 SB_DQ[29] SB_ODT[0] AE4 DDRB_ODT0 12

DDR SYSTEM MEMORY B

DDR_A_D30 DDRA_ODT1 DDR_B_D30 DDRB_ODT1

DDR SYSTEM MEMORY A

N9 SA_DQ[30] SA_ODT[1] AG3 DDRA_ODT1 11 M2 SB_DQ[30] SB_ODT[1] AD4 DDRB_ODT1 12
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR_A_D32 SA_DQ[31] SA_ODT[2] DDR_B_D32 SB_DQ[31] SB_ODT[2]
AG6 SA_DQ[32] SA_ODT[3] AH2 AM5 SB_DQ[32] SB_ODT[3] AE5
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 SA_DQ[33] DDR_B_D34 SB_DQ[33]
AK6 SA_DQ[34] AR3 SB_DQ[34]
DDR_A_D35 AK5 DDR_B_D35 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 11 AN3 SB_DQ[36] DDR_B_DQS#[0..7] 12
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D37 DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 SA_DQ[39] SA_DQS#[2] J3 AP2 SB_DQ[39] SB_DQS#[2] K6
DDR_A_D40 AJ8 M6 DDR_A_DQS#3 DDR_B_D40 AP5 N3 DDR_B_DQS#3
DDR_A_D41 SA_DQ[40] SA_DQS#[3] SB_DQ[40] SB_DQS#[3]
AK8 SA_DQ[41] SA_DQS#[4] AL6 DDR_A_DQS#4 DDR_B_D41 AN9 SB_DQ[41] SB_DQS#[4] AN5 DDR_B_DQS#4
DDR_A_D42 AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[42] SA_DQS#[5] SB_DQ[42] SB_DQS#[5]
AK9 SA_DQ[43] SA_DQS#[6] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[43] SB_DQS#[6] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] 11 SB_DQ[48] DDR_B_DQS[0..7] 12
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 SA_DQ[50] SA_DQS[1] F6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 SA_DQ[52] SA_DQS[3] N6 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 SA_DQ[54] SA_DQS[5] AM9 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 SA_DQ[58] AR14 SB_DQ[58]
DDR_A_D59 AK15 DDR_B_D59 AT14
SA_DQ[59] DDR_A_MA[0..15] 11 SB_DQ[59]
DDR_A_D60 AL14 DDR_B_D60 AT12
SA_DQ[60] SB_DQ[60] DDR_B_MA[0..15] 12
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D61 AN15 AA8 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 SA_DQ[62] SA_MA[1] W1 AR15 SB_DQ[62] SB_MA[1] T7
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] W7 SB_MA[3] T6
V3 DDR_A_MA4 T2 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] V2 SB_MA[5] T4
W3 DDR_A_MA6 T3 DDR_B_MA6
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
11 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 12 DDR_B_BS0 AA9 SB_BS[0] SB_MA[7] R2
B DDR_A_BS1 DDR_A_MA8 DDR_B_BS1 DDR_B_MA8 B
11 DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 12 DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[9]
AD8 DDR_A_MA10 AB7 DDR_B_MA10
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
11 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 12 DDR_B_CAS# AA10 SB_CAS# SB_MA[13] AB10
DDR_A_RAS# AD9 V5 DDR_A_MA14 DDR_B_RAS# AB8 R5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SA_MA[14] 12 DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_WE# AF9 V7 DDR_A_MA15 DDR_B_WE# AB9 R4 DDR_B_MA15
11 DDR_A_WE# SA_WE# SA_MA[15] 12 DDR_B_WE# SB_WE# SB_MA[15]

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @

+1.5V

R466
1

0_0402_5%
1 2 R465
@ 1K_0402_5%

R467
2

Q14 1K_0402_5%
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 SM_DRAMRST# 11,12

2

BSS138_NL_SOT23-3
R464
G
2

4.99K_0402_1%
A A
1

18 DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL
R463 0_0402_5%
1
C140 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K 2010/09/09 2011/09/09 Title
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 7 of 50
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

JCPUF POWER +1.05VS_VCCP Decoupling:

SPEC => 2X 330U (17m ohm), 12X 22U
94A (Quad Core 45W) +1.05VS_VCCP
53A (SV 35W) 8.5A TOP Socket Cavity x 7
D D

AG35 VCC1
AG34 AH13 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC2 VCCIO1
AG33 VCC3 VCCIO2 AH10 1 1 1 1 1 1 1 1 1 1
AG32 AG10 C146 C144 C143 C141 C137 C136 C135 C134 C133 C142
VCC4 VCCIO3
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
2 2 2 2 2 2 2 2 2 2
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 L10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC9 VCCIO8
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 J12 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AF33
VCC12 VCCIO11
J11 1 1 1 1 1 1 1 1 1
+CPU_CORE Decoupling:
VCC13 VCCIO12 C147 C145 C163 C153 C160 C152 C139 C138 C132
AF32 VCC14 VCCIO13 H14
@ @ @ @ @ @ @
4X 330U (6m ohm), 16X 22U, 10X 10U
AF31 VCC15 VCCIO14 H12
AF30
AF29
VCC16 VCCIO15 H11
G14
2 2 2 2 2 2 2 2 2 Bottom Socket Cavity
VCC17 VCCIO16
AF28 G13
PEG AND DDR

VCC18 VCCIO17 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

AF27 VCC19 VCCIO18 G12
+CPU_CORE
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 F11 390U_2.5V_M_R10 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VCC23 VCCIO22
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
AD30
AD29
VCC26
E11
Bottom Socket Cavity x 5 + + C12 +
VCC27 VCCIO25 C10 C11 @ @
AD28 VCC28 VCCIO26 D14
330U_D2_2V_Y 2 2 2 2 2 2 2 2 2 2 2
AD27 VCC29 VCCIO27 D13
2 2 2
AD26 VCC30 VCCIO28 D12
AC35 D11 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
C VCC31 VCCIO29 C
AC34 VCC32 VCCIO30 C14
AC33 C13 390U_2.5V_M_R10
VCC33 VCCIO31
AC32
AC31
VCC34 VCCIO32 C12
C11
Co-Lay with C10
VCC35 VCCIO33
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14 Top Socket Edge
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 A11 +CPU_CORE
VCC41 VCCIO39
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC44
AA31 VCC45
AA30 VCC46 1 1 1 1 1 1 1 1 1
AA29 C159 C151 C130 C129 C124 C123 C122 C121 C125
VCC47
AA28 VCC48
AA27 @
VCC49 2 2 2 2 2 2 2 2 2
AA26
CORE SUPPLY

VCC50
Y35 VCC51
Y34 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC52
Y33 VCC53 +1.05VS_VCCP +1.05VS_VCCP
Y32 VCC54
Y31 VCC55
Y30 VCC56
1

Y29 VCC57
Y28 R70 R68
VCC58 130_0402_5% 75_0402_5%
Y27 VCC59
Y26 VCC60 Top Socket Cavity
V35
2

2
SVID

VCC61 H_CPU_SVIDALRT#
V34 VCC62 VIDALERT# AJ29 1 2 VR_SVID_ALRT# 44
V33 AJ30 H_CPU_SVIDCLK R67 1 2 43_0402_1% +CPU_CORE
VCC63 VIDSCLK VR_SVID_CLK 44
B V32 AJ28 H_CPU_SVIDDAT R63 1 2 0_0402_5% B
VCC64 VIDSOUT VR_SVID_DAT 44
V31 R66 0_0402_5%
VCC65 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
V30 VCC66 Pull high resistor on VR side
V29 VCC67
V28 VCC68 1 1 1 1 1 1 1 1
V27 C158 C150 C128 C127 C120 C118 C119 C117
VCC69
V26 VCC70
U35 VCC71 2 2 2 2 2 2 2 2
U34 VCC72
U33 VCC73
U32 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 +CPU_CORE
VCC79
U26 VCC80
R35 VCC81
R34 VCC82 Bottom Socket Edge
2

R33 VCC83
R32 R64 Close to CPU
VCC84 100_0402_1%
R31 VCC85 +CPU_CORE +CPU_CORE
R30 VCC86
R29
1
SENSE LINES

VCC87 470U_X_2VM_R6M 330U_D2_2V_Y

R28 VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R R65 1 2 0_0402_5% VCCSENSE 44
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R52 1 2 0_0402_5% VSSSENSE 44 1 1 1 1 1
P35 VCC91
P34 + C890 + C2 + C5 + C7 + C9
VCC92
1

P33 VCC93
P32 VCC94 VCCIO_SENSE B10 VCCIO_SENSE VCCIO_SENSE 43
R62
100_0402_1% 2 2 2 2 2
P31 VCC95 VSSIO_SENSE A10
P30 VCC96
VSS_SENSE_VCCIO
2

A A
P29 330U_D2_2V_Y 470U_X_2VM_R6M 330U_D2_2V_Y
2

VCC97 R102 R105

P28 VCC98
P27 0_0402_5% 100_0402_1%
VCC99 @
P26 VCC100
1

+1.05VS_VCCP
Security Classification Compal Secret Data Compal Electronics, Inc.
Close to CPU Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Sandy Bridge_rPGA_Rev0p61 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 8 of 50
5 4 3 2 1
 5 4 3 2 1

+GFX_CORE

+GFX_CORE Decoupling: ESR 10mohm 1

+GFX_CORE
2X 330U (6m ohm), 12X 22U C873 +
560U_2.5V_M_R10

2
+GFX_CORE OPT@
Bottom Socket Edge
Co-lay for Cost Down Plan
2

JCPUG
POWER OPT@
R74
10_0402_1%
Close to CPU

1
SENSE
LINES
470U_X_2VM_R6M AT24 AK35 VCC_AXG_SENSE_R R121 1 OPT@ 2 0_0402_5%
VAXG1 VAXG_SENSE VCC_AXG_SENSE 44
1 1 AT23 AK34 VSS_AXG_SENSE_R R251 1 OPT@ 2 0_0402_5%
D VAXG2 VSSAXG_SENSE VSS_AXG_SENSE 44 D
AT21 VAXG3
2

C112 + C113 + ESR 6mohm AT20 VAXG4

2
R71 +1.5V_CPU
AT18 VAXG5
0_0402_5% @ @ 330U_D2_2VM_R6M AT17 33A +V_SM_VREF should R75
2 2 VAXG6 OPT@ 10_0402_1%
DIS@ AR24 VAXG7 have 20 mil trace width

1
AR23
1

VAXG8 R111 R122

AR21

1
VAXG9 0_0402_5%
AR20 1K_0402_5%

VREF
VAXG10
AR18 VAXG11 2 1
AR17

2
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VAXG12
AP24 VAXG13 SM_VREF AL1 +V_SM_VREF_CNT 2 3 +V_SM_VREF
AP23 VAXG14

1
1 1 1 1 1 1 AP21 1 Q2
C266 C267 C271 C338 C341 C342 VAXG15 R486 C148 @ R252
AP20 VAXG16
AP18 @ AP2302GN-HF_SOT23-3 1K_0402_5%
VAXG17 1

100K_0402_5%

0.1U_0402_16V4Z
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
2 2 2 2 2 2
AP17
AN24
VAXG18 2 +1.5V_CPU Decoupling:

2
VAXG19
Bottom Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AN23 VAXG20
RUN_ON_CPU1.5VS3 1X 330U (6m ohm), 6X 10U
AN21 VAXG21 +1.5V_CPU
Cavity AN20 VAXG22

DDR3 -1.5V RAILS

Bottom Socket Edge AN18 VAXG23 +1.5V_CPU
AN17 VAXG24 5A

GRAPHICS
AM24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VAXG25 VDDQ1
AM23 AF4 1 ESR 6mohm ESR 17mohm
VAXG26 VDDQ2
AM21 VAXG27 VDDQ3 AF1 1 1 1 1 1 1 1
AM20 AC7 C114 C115 C116 C149 C154 C155 + C180
1 1 1 1 1 1 VAXG28 VDDQ4
C343 C344 C345 C346 C347 C348 AM18 AC4 @ + C875
VAXG29 VDDQ5 330U_D2_2VM_R6M 330U_2.5V_M
AM17 VAXG30 VDDQ6 AC1
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ 2 2 2 2 2 2 2
AL24 VAXG31 VDDQ7 Y7
2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4
10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
C Top Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AL21
AL20
VAXG33 VDDQ9 Y1
U7 Co-lay for Cost Down Plan C
VAXG34 VDDQ10
Cavity AL18 VAXG35 VDDQ11 U4
Top Socket Edge AL17
AK24
VAXG36 VDDQ12 U1
P7
VAXG37 VDDQ13
AK23 VAXG38 VDDQ14 P4
AK21 VAXG39 VDDQ15 P1
AK20 VAXG40
AK18 VAXG41
AK17 VAXG42
AJ24
AJ23
VAXG43 +VCCSA Decoupling:
VAXG44
AJ21 VAXG45 1X 330U (6m ohm), 3X 10U
AJ20 VAXG46
AJ18 VAXG47 +VCCSA
VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ17 VAXG48 Bottom Socket Cavity Co-lay for Cost Down Plan
AH24 6A

SA RAIL
VAXG49
AH23 VAXG50 +VCCSA
0 0 0.90 V For Sandy Bridge
AH21 M27 10U_0805_10V6K 10U_0805_10V6K
VAXG51 VCCSA1
AH20 VAXG52 VCCSA2 M26 ESR 17mohm
AH18 VAXG53 VCCSA3 L26 1 2VCCSA_SENSE 0 1 0.80 V
AH17 VAXG54 VCCSA4 J26 1 1 1 1 1 R253 0_0402_5% 1
J25 C100 C447 C476 C477
VCCSA5 + C485 +
VCCSA6 J24 1 0 0.75 V
H26 @ @
VCCSA7 2 2 2 2 330U_D2_2VM_R6M @
VCCPLL Decoupling: VCCSA8 H25
2 C877 2 1 1 0.65 V
1.8V RAIL

+1.8VS
1X 330U (6m ohm), 1X 10U, 2x1U 10U_0805_10V6K 10U_0805_10V6K 330U_2.5V_M_R17

R76
1.2A Bottom Socket Edge
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 H23 VCCSA_SENSE VCCSA_SENSE 42
MISC

0_0805_5% VCCPLL1 VCCSA_SENSE

B A6 VCCPLL2 Unmount C877 for cost down plan B
1 A2 VCCPLL3 1 R95 2 2010/12/23
C185 1 1 1 VCCSA_VID0 0_0402_5% @
@+ C186 C206 C230 C22 VCCSA_VID0
FC_C22
VCCSA_VID1 C24 VCCSAP_VID1 42
1U_0402_6.3V6K
2

2
2 2 2 2
R114 R119
330U_B2_2.5VM_R15M 1U_0402_6.3V6K Sandy Bridge_rPGA_Rev0p61 @ @ Mount PJ30 for cost down plan
10K_0402_5% 10K_0402_5% 2010/12/23 +1.5V_CPU +1.5VS
1

1
PJ30 @
2 2 1 1
+1.5V_CPU +1.5V
JUMP_43X118 +1.5V
Reserve it to
follow CRB 1.0. C213 1 2 0.1U_0402_16V4Z Q33
1 S D 8
C212 1 2 0.1U_0402_16V4Z 2 7
S D

2
1 3 S D 6
C211 1 2 0.1U_0402_16V4Z R449 C179 4 5
470_0805_5% 10U_0805_10V6K G D
C210 1 2 0.1U_0402_16V4Z FDS6676AS_SO8
2 RUN_ON_CPU1.5VS3 1 2 +VSB

3 1
R455 220K_0402_5%

6
Q46B 1
C472 R420 Q46A
SUSP 5 0.1U_0402_25V6 820K_0402_5%
2 SUSP
2 SUSP 5,27,36,43
2N7002DW-T/R7_SOT363-6

2
A 2N7002DW-T/R7_SOT363-6 A

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019B7
5 4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Date: Friday, September 16, 2011
1
Sheet 9 of 50
 5 4 3 2 1

CFG Straps for Processor

JCPUH JCPUI (CFG[17:0] internal pull high to VCCIO)
AT35 VSS1 VSS81 AJ22 Delete Test-padΚT6ΕT5ΕT25ΕT28ΕT27Ε
AT32 VSS2 VSS82 AJ19
AT29 AJ16 T35 F22 T24ΕT23ΕT22ΕT21ΕT19ΕT18ΕT12ΕT11 CFG2
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19 FOR PGRAA LAYOUT LIMITATION

1
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 AJ7 T32 E27 R254
VSS6 VSS86 VSS164 VSS237 JCPUE 1K_0402_1%
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 AJ3 T30 E21 @
VSS8 VSS88 VSS166 VSS239
AT13 AJ2 T29 E18

2
VSS9 VSS89 VSS167 VSS240
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15 RSVD28 L7
D AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 RSVD29 AG7 D
AT4 AH34 T26 E10 T54 PAD CFG0 AK28 AE7
VSS12 VSS92 VSS170 VSS243 CFG1 CFG[0] RSVD30
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AK29 CFG[1] RSVD31 AK2
AR25 AH30 P8 E8 CFG2 AL26 W8
VSS14 VSS94 VSS172 VSS245 T7 PAD CFG3 CFG[2] RSVD32
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AL27 CFG[3]
AR19 AH28 P5 E6 CFG4 AK26 PEG Static Lane Reversal - CFG2 is for the 16x
VSS16 VSS96 VSS174 VSS247 CFG5 CFG[4]
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5 AL29 CFG[5] RSVD33 AT26
AR13 AH25 P2 E4 T15 PAD CFG6 AL30 AM33
VSS18 VSS98 VSS176 VSS249 CFG7 CFG[6] RSVD34
AR10 AH22 N35 E3 AM31 AJ27 1: Normal Operation; Lane # definition matches
AR7
AR4
VSS19
VSS20
VSS21
VSS99
VSS100
VSS101
AH19
AH16
N34
N33
VSS177
VSS178
VSS179
VSS250
VSS251
VSS252
E2
E1
T16 PAD CFG8
CFG9
AM32
AM30
CFG[7]
CFG[8]
CFG[9]
RSVD35
CFG2
* socket pin map definition
AR2 AH7 N32 D35 CFG10 AM28
VSS22 VSS102 VSS180 VSS253 T20 PAD CFG11 CFG[10]
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32 AM26 CFG[11] 0:Lane Reversed
AP31 AG9 N30 D29 T50 PAD CFG12 AN28
VSS24 VSS104 VSS182 VSS255 T51 PAD CFG13 CFG[12]
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26 AN31 CFG[13] RSVD37 T8
AP25 AG4 N28 D20 T52 PAD CFG14 AN26 J16 CFG4
VSS26 VSS106 VSS184 VSS257 T53 PAD CFG15 CFG[14] RSVD38
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17 AM27 CFG[15] RSVD39 H16

1
AP19 AF5 N26 C34 T26 PAD CFG16 AK31 G16
VSS28 VSS108 VSS186 VSS259 CFG17 CFG[16] RSVD40 R255
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31 AN29 CFG[17]
AP13 AF2 L33 C28 1K_0402_1%
VSS30 VSS110 VSS188 VSS261 @
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AP7 AE34 L27 C25

2
VSS32 VSS112 VSS190 VSS263
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23 RSVD41 AR35
AP1 AE32 L8 C10 RSVD1 AJ31 AT34
VSS34 VSS114 VSS192 VSS265 RSVD2 RSVD1 RSVD42
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1 AH31 RSVD2 RSVD43 AT33
AN27 AE30 L5 B22 RSVD3 AJ33 AP35
VSS36 VSS116 VSS194 VSS267 RSVD4 RSVD3 RSVD44
AN25 AE29 L4 B19 AH33 AR34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD4 RSVD45
Embedded Display Port Presence Strap
AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13 AJ26 RSVD5

RESERVED
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
AN10 AD7 K32 B9 1 : Disabled; No Physical Display Port
C
AN7
AN4
VSS42
VSS43
VSS44
VSS122
VSS123
VSS124
AC9
AC8
K29
K26
VSS200
VSS201
VSS202
VSS273
VSS274
VSS275
B8
B7 CPU_RSVD6 B4
SA_DIMM_VREFDQ
RSVD6
RSVD46
RSVD47
B34
A33
* attached to Embedded Display Port
C

AM29 AC6 J34 B5 CPU_RSVD7 D1 A34 CFG4

VSS45 VSS125 VSS203 VSS276 RSVD7 RSVD48
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 SB_DIMM_VREFDQ RSVD49 B35 0 : Enabled; An external Display Port device is
AM22 AC3 H33 B2 C35
VSS47 VSS127 VSS205 VSS278 RSVD50 connected to the Embedded Display Port

1
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32 F25 RSVD8
AM13 AB34 H24 A29 R115 R116 F24
VSS50 VSS130 VSS208 VSS281 1K_0402_1% 1K_0402_1% RSVD9
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26 F23 RSVD10
AM7 AB32 H18 A23 D24 AJ32 CFG6

2
VSS52 VSS132 VSS210 VSS283 RSVD11 RSVD51
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 G25 RSVD12 RSVD52 AK32
AM3 AB30 H13 A3 G24 CFG5
VSS54 VSS134 VSS212 VSS285 RSVD13
AM2 VSS55 VSS135 AB29 H10 VSS213 E23 RSVD14

1
AM1 VSS56 VSS136 AB28 H9 VSS214 D23 RSVD15
AL34 VSS57 VSS137 AB27 H8 VSS215 C30 RSVD16 RSVD53 AH27 RSVD53 R257 R256
AL31 AB26 H7 A31 1K_0402_1% 1K_0402_1%
VSS58 VSS138 VSS216 RSVD17 @ @
AL28 VSS59 VSS139 Y9 H6 VSS217 B30 RSVD18
AL25 Y8 H5 B29

2
VSS60 VSS140 VSS218 RSVD19
AL22 VSS61 VSS141 Y6 H4 VSS219 D30 RSVD20 RSVD54 AN35 CLK_RES_ITP 18
AL19 VSS62 VSS142 Y5 H3 VSS220 B31 RSVD21 RSVD55 AM35 CLK_RES_ITP# 18
AL16 VSS63 VSS143 Y3 H2 VSS221 A30 RSVD22
AL13 VSS64 VSS144 Y2 H1 VSS222 C29 RSVD23
AL10 VSS65 VSS145 W35 G35 VSS223
AL7 VSS66 VSS146 W34 G32 VSS224
AL4 VSS67 VSS147 W33 G29 VSS225 J20 RSVD24
AL2 VSS68 VSS148 W32 G26 VSS226 B18 RSVD25 RSVD56 AT2
AK33 VSS69 VSS149 W31 G23 VSS227 A19 RSVD26 RSVD57 AT1 PCIE Port Bifurcation Straps
AK30 VSS70 VSS150 W30 G20 VSS228
VCCIO_SEL RSVD58 AR1
AK27 VSS71 VSS151 W29 G17 VSS229
AK25 W28 G11 J15 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
AK22
AK19
VSS72
VSS73
VSS74
VSS152
VSS153
VSS154
W27
W26
F34
F31
VSS230
VSS231
VSS232
RSVD27
*10: x8, x8 - Device 1 function 1 enabled ; function 2 B
AK16 U9 F29 B1
VSS75 VSS155 VSS233 KEY disabled
AK13 VSS76 VSS156 U8 CFG[6:5]
AK10 VSS77 VSS157 U6 01: Reserved - (Device 1 function 1 disabled ; function
AK7 VSS78 VSS158 U5 2 enabled)
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Sandy Bridge_rPGA_Rev0p61 @

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @ CFG7

1
R258
1K_0402_1%
@

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

de assertion
CFG7
0: PEG Wait for BIOS for training
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 10 of 50
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+1.5V +1.5V

1
JDDRH
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] 7

DQ0 DQ5 DDR_A_DQS#[0..7] 7

1 1 DDR_A_D1 7 8
C156 C157 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] 7
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_16V4Z

2.2U_0603_6.3V6K
13 VSS VSS 14 DDR_A_MA[0..15] 7
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D
23 DQ9 DQ13 24 D
25 VSS VSS 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
Close to JDDRH.1 29 DQS1 RESET# 30 SM_DRAMRST# 7,12 +1.5V
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36

1
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20 R79
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46

2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48 +VREF_DQA
49 50 DDR_A_D22
VSS DQ22

1
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23 R81
53 DQ19 VSS 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60

2
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

DDRA_CKE0 73 74 DDRA_CKE1
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
C
7 DDR_A_BS2 79 BA2 A14 80 C
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
DDRA_CLK0 101 102 DDRA_CLK1
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7
DDRA_CLK0# 103 104 DDRA_CLK1#
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7
105 VDD VDD 106
DDR_A_MA10 DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 7
DDR_A_BS0 109 110 DDR_A_RAS#
7 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 7
111 VDD VDD 112

1
DDR_A_WE# 113 114 DDRA_SCS0#
7 DDR_A_WE# WE# S0# DDRA_SCS0# 7
DDR_A_CAS# 115 116 DDRA_ODT0 R80
7 DDR_A_CAS# CAS# ODT0 DDRA_ODT0 7
117 118 1K_0402_1%
DDR_A_MA13 VDD VDD DDRA_ODT1
119 A13 ODT1 120 DDRA_ODT1 7
DDRA_SCS1# 121 122

2
7 DDRA_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAA
TEST VREF_CA
127 VSS VSS 128
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37 R82
133 VSS VSS 134
DDR_A_DQS#4 135 136 1K_0402_1%
DDR_A_DQS4 DQS4# DM4
B
137 DQS4 VSS 138 1 1 B
139 140 DDR_A_D38 C161 C162

2
DDR_A_D34 VSS DQ38 DDR_A_D39
141 DQ34 DQ39 142
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

DDR_A_D35 143 144

DQ35 VSS DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154
155 VSS VSS 156 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160 close to JDDRH.126
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 +1.5V
DDR_A_D49 DQ48 DQ52 DDR_A_D53 @ +1.5V +0.75VS
165 DQ49 DQ53 166
167 168 C218 1 + 2 390U_2.5V_M_R10
DDR_A_DQS#6 VSS VSS
169 DQS6# DM6 170
DDR_A_DQS6 171 172 C164 1 2 0.1U_0402_16V4Z C165 1 2 10U_0603_6.3V6M
DQS6 VSS DDR_A_D54 C166 1
173 VSS DQ54 174 2 10U_0603_6.3V6M
DDR_A_D50 175 176 DDR_A_D55 C167 1 2 0.1U_0402_16V4Z
DDR_A_D51 DQ50 DQ55 C168 1
177 DQ51 VSS 178 2 10U_0603_6.3V6M C169 2 1 1U_0402_6.3V6K
179 180 DDR_A_D60 C170 1 2 0.1U_0402_16V4Z
DDR_A_D56 VSS DQ60 DDR_A_D61 C171 1
181 DQ56 DQ61 182 2 10U_0603_6.3V6M C172 2 1 1U_0402_6.3V6K
DDR_A_D57 183 184 C173 1 2 0.1U_0402_16V4Z
DQ57 VSS DDR_A_DQS#7 C174 1
185 VSS DQS7# 186 2 10U_0603_6.3V6M C175 2 1 1U_0402_6.3V6K
187 188 DDR_A_DQS7
DM7 DQS7 C176 1
189 VSS VSS 190 2 10U_0603_6.3V6M C177 2 1 1U_0402_6.3V6K
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63 C178 1
193 DQ59 DQ63 194 2 10U_0603_6.3V6M
R90 1 2 195 196
10K_0402_5% VSS VSS
A 197 SA0 EVENT# 198 A
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA 12,18,27
PM_SMBCLK
0.1U_0402_16V4Z
2.2U_0603_6.3V6K

201 SA1 SCL 202 PM_SMBCLK 12,18,27

1 1 +0.75VS 203 VTT VTT 204 +0.75VS
1

C182
C181 205 206
R91 GND1 BOSS1
207 208
2 2 10K_0402_5% GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
2

FOX_AS0A621-J8RG-7H
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
4019B7
WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 11 of 50
5 4 3 2 1
 A B C D E

+1.5V +1.5V
JDDRL
1 2
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
Reverse Type
DDR_B_D1 7
9
DQ0
DQ1
DQ5
VSS 8
10 DDR_B_DQS#0
DDR3 SO-DIMM B
VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12
1 1 13 VSS VSS 14
C183 C184 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] 7
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0603_6.3V6K

0.1U_0402_16V4Z
19 VSS VSS 20 DDR_B_DQS[0..7] 7
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_D[0..63] 7
1 DQ9 DQ13 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_MA[0..15] 7
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# 7,11
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
Close to JDDRL.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 DDR_B_D20 +1.5V
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 VSS VSS 44

1
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2 R83
47 DQS2 VSS 48
49 50 DDR_B_D22 1K_0402_1%
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54

2
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29 +VREF_DQB
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
VSS DQS3#

1
63 64 DDR_B_DQS3
DM3 DQS3 R84
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30 1K_0402_1%
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 72

2
VSS VSS

DDRB_CKE0 73 74 DDRB_CKE1
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
2
7 DDR_B_BS2 79 BA2 A14 80 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDRB_CLK0 101 102 DDRB_CLK1
7 DDRB_CLK0 CK0 CK1 DDRB_CLK1 7
DDRB_CLK0# 103 104 DDRB_CLK1#
7 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 7
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 7
DDR_B_BS0 109 110 DDR_B_RAS#
7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 7
111 VDD VDD 112

1
DDR_B_WE# 113 114 DDRB_SCS0#
7 DDR_B_WE# WE# S0# DDRB_SCS0# 7
DDR_B_CAS# 115 116 DDRB_ODT0 R86
7 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 7
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDRB_ODT1
119 A13 ODT1 120 DDRB_ODT1 7
DDRB_SCS1# 121 122

2
7 DDRB_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAB
TEST VREF_CA
127 VSS VSS 128
DDR_B_D37 129 130 DDR_B_D32
DQ32 DQ36
1
DDR_B_D36 131 132 DDR_B_D33
DQ33 DQ37 R94
133 VSS VSS 134
DDR_B_DQS#4 135 136 1 1 1K_0402_1%
DDR_B_DQS4 DQS4# DM4 C187 C188
3
137 DQS4 VSS 138 3
139 140 DDR_B_D38
2

VSS DQ38
2.2U_0603_6.3V6K

0.1U_0402_16V4Z

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
153 154 DDR_B_DQS5
DM5 DQS5
DDR_B_D42
155 VSS VSS 156
DDR_B_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_B_D43
157 DQ42 DQ46 158
DDR_B_D47
Close to JDDRL.126 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53 +1.5V
165 DQ49 DQ53 166
167 168 @ +1.5V +0.75VS
DDR_B_DQS#6 VSS VSS C189 1 2 330U_B2_2.5VM_R15M
+
169 DQS6# DM6 170
DDR_B_DQS6 171 172
DQS6 VSS DDR_B_D50 C190 1
173 VSS DQ54 174 2 0.1U_0402_16V4Z C191 1 2 10U_0603_6.3V6M
DDR_B_D54 175 176 DDR_B_D51 C192 1 2 10U_0603_6.3V6M
DDR_B_D55 DQ50 DQ55 C193 1
177 DQ51 VSS 178 2 0.1U_0402_16V4Z
179 180 DDR_B_D60 C194 1 2 10U_0603_6.3V6M C195 2 1 1U_0402_6.3V6K
DDR_B_D56 VSS DQ60 DDR_B_D61 C196 1
181 DQ56 DQ61 182 2 0.1U_0402_16V4Z
DDR_B_D57 183 184 C197 1 2 10U_0603_6.3V6M C198 2 1 1U_0402_6.3V6K
DQ57 VSS DDR_B_DQS#7 C199 1
185 VSS DQS7# 186 2 0.1U_0402_16V4Z
187 188 DDR_B_DQS7 C200 1 2 10U_0603_6.3V6M C201 2 1 1U_0402_6.3V6K
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 C202 1 2 10U_0603_6.3V6M C203 2 1 1U_0402_6.3V6K
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196 C204 1 2 10U_0603_6.3V6M
10K_0402_5% VSS VSS
4 197 SA0 EVENT# 198 4
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA 11,18,27
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK 11,18,27
2.2U_0603_6.3V6K
1 1 1 R99 2 +0.75VS 203 204 +0.75VS
10K_0402_5% VTT VTT
205 GND1 BOSS1 206
C207 C208 207 208
2 2 @ GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2010/09/09 2011/09/09 Title
FOX_AS0A626-U4RN-7F
Issued Date Deciphered Date
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
4019B7
WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 12 of 50
A B C D E
 5 4 3 2 1

B+
JMXMA JMXMB
400mil(10A)
1 PWR_SRC PWR_SRC 2 B+ 163 GND GND 162
3 4 PCIE_GTX_CRX_N2 165 164 PCIE_CTX_C_GRX_N2
PWR_SRC PWR_SRC PCIE_GTX_CRX_P2 PEX_RX2# PEX_TX2# PCIE_CTX_C_GRX_P2
5 PWR_SRC PWR_SRC 6 167 PEX_RX2 PEX_TX2 166
7 PWR_SRC PWR_SRC 8 169 GND GND 168
PCIE_GTX_CRX_N1 PCIE_CTX_C_GRX_N1
9 PWR_SRCE1 E2 PWR_SRC 10
PCIE_GTX_CRX_P1
171 PEX_RX1# PEX_TX1# 170
PCIE_CTX_C_GRX_P1
11 PWR_SRC PWR_SRC 12 1 1 173 PEX_RX1 PEX_TX1 172
13 PWR_SRC PWR_SRC 14 175 GND GND 174
15 16 C16 C15 PCIE_GTX_CRX_N0 177 176 PCIE_CTX_C_GRX_N0
PWR_SRC PWR_SRC PCIE_GTX_CRX_P0 PEX_RX0# PEX_TX0# PCIE_CTX_C_GRX_P0
17 PWR_SRC PWR_SRC 18 10U_0805_25V6K 10U_0805_25V6K 179 PEX_RX0 PEX_TX0 178
+3VS_DGPU 2 2
181 GND GND 180
CLK_PCIE_VGA# 183 182 CLK_REQ_GPU#
18 CLK_PCIE_VGA# PEX_REFCLK# PEX_CLK_REQ#
19 20 CLK_PCIE_VGA 185 184 PLTRST_VGA# PLTRST_VGA# 21
D GND GND 18 CLK_PCIE_VGA PEX_REFCLK PEX_RST# D
Need to confirm MXM VGA_PWROK voltage level 21 22 187 186 VGA_CRT_DATA VGA_CRT_DATA 15
10K_0402_5% @ 2 R58 VGA_PWROK GND GND GND VGA_DDC_DAT VGA_CRT_CLK
1 23 GND GND 24 189 RSVD VGA_DDC_CLK 188 VGA_CRT_CLK 15
25 26 191 190 VGA_CRT_VSYNC VGA_CRT_VSYNC 15
GND GND RSVD VGA_VSYNC VGA_CRT_HSYNC
27 GND GND 28 193 RSVD VGA_HSYNC 192 VGA_CRT_HSYNC 15
29 GND E3 E4 GND 30 195 RSVD GND 194
31 32 197 196 VGA_CRT_R VGA_CRT_R 15
+5VS GND GND RSVD VGA_RED VGA_CRT_G
33 GND GND 34 199 LVDS_UCLK# VGA_GREEN 198 VGA_CRT_G 15
100mil(2.5A, 5VIA) 35 36 201 200 VGA_CRT_B
37
GND GND
38 203
LVDS_UCLK VGA_BLUE
202
VGA_CRT_B 15 CRT
10U_0603_6.3V6M 5V PRSNT_R# VGA_PWROK GND GND
39 5V WAKE# 40 VGA_PWROK 21,22 205 LVDS_UTX3# LVDS_LCLK# 204
41 5V PWR_GOOD 42 207 LVDS_UTX3 LVDS_LCLK 206
1 1 43 44 VGA_PWR_EN 1 2 DIS@ 209 208
C339 5V PWR_EN 20K_0402_1% PR627 SUSP# 17,31,33,36,41,43 GND GND
45 5V RSVD 46 211 LVDS_UTX2# LVDS_LTX3# 210
C18 47 48 2 1 OPT@ 213 212
GND RSVD 150K_0402_1% PR628 DGPU_PWR_EN 21,36 LVDS_UTX2 LVDS_LTX3
49 GND RSVD 50 215 GND GND 214
0.1U_0402_16V4Z 2 2 @ D25
51 GND RSVD 52
ACIN_VGA 2
Resistor for fine tune sequence 217 LVDS_UTX1# LVDS_LTX2# 216
53 GND PWR_LEVEL 54 1 ACIN 19,33,35,39 219 LVDS_UTX1 LVDS_LTX2 218
<BOM Structure> 55 56 221 220
PEX_STD_SW# TH_OVERT# GND GND
57 VGA_DISABLE# TH_ALERT# 58 RB751V40_SC76-2 223 LVDS_UTX0# LVDS_LTX1# 222
VGA_ENVDD 59 60 225 224
14 VGA_ENVDD PNL_PWR_EN TH_PWM LVDS_UTX0 LVDS_LTX1
VGA_ENBKL 61 62 227 226
14 VGA_ENBKL PNL_BL_EN GPIO0 GND GND
VGA_BL_PWM 63 64 229 228
14 VGA_BL_PWM PNL_BL_PWM GPIO1 DP_C_L0# LVDS_LTX0#
65 HDMI_CEC GPIO2 66 231 DP_C_L0 LVDS_LTX0 230
67 68 VGA_SMB_DA2 233 232
DVI_HPD SMB_DAT VGA_SMB_CK2 GND GND VGA_EDP_TX0-
69 LVDS_DDC_DAT SMB_CLK 70 HDMI DP 235 DP_C_L1# DP_D_L0# 234 VGA_EDP_TX0- 14
71 72 SYSTEM 237 236 VGA_EDP_TX0+ VGA_EDP_TX0+ 14
LVDS_DDC_CLK GND DP_C_L1 DP_D_L0
73 GND OEM 74 I2CY_SDA IFPE_AUX- 239 GND GND 238
75 76 241 240 VGA_EDP_TX1-
77
OEM OEM
78 I2CY_SCL IFPE_AUX+ 243
DP_C_L2# DP_D_L1#
242 VGA_EDP_TX1+
VGA_EDP_TX1- 14
VGA_EDP_TX1+ 14
eDP
OEM OEM DP_C_L2 DP_D_L1
C 79 OEM OEM 80 245 GND GND 244 C
81 82 TXC- IFPE_L3- 247 246 VGA_EDP_TX2- VGA_EDP_TX2- 14
OEM GND PCIE_CTX_C_GRX_N15 DP_C_L3# DP_D_L2# VGA_EDP_TX2+
83 GND PEX_TX15# 84 249 DP_C_L3 DP_D_L2 248 VGA_EDP_TX2+ 14
PCIE_GTX_CRX_N15 85 86 PCIE_CTX_C_GRX_P15 TXC+ IFPE_L3+ 251 250
PCIE_GTX_CRX_P15 PEX_RX15# PEX_TX15 GND GND VGA_EDP_TX3-
87 PEX_RX15 GND 88 253 DP_C_AUX# DP_D_L3# 252 VGA_EDP_TX3- 14
89 90 PCIE_CTX_C_GRX_N14 TXD0- IFPE_L2- 255 254 VGA_EDP_TX3+ VGA_EDP_TX3+ 14
PCIE_GTX_CRX_N14 GND PEX_TX14# PCIE_CTX_C_GRX_P14 DP_C_AUX DP_D_L3
91 PEX_RX14# PEX_TX14 92 257 RSVD GND 256
PCIE_GTX_CRX_P14 93 94 TXD0+ IFPE_L2+ 259 258 VGA_EDP_AUX-
PEX_RX14 GND RSVD DP_D_AUX# VGA_EDP_AUX- 14
95 96 PCIE_CTX_C_GRX_N13 261 260 VGA_EDP_AUX
GND PEX_TX13# RSVD DP_D_AUX VGA_EDP_AUX 14
PCIE_GTX_CRX_N13 97 98 PCIE_CTX_C_GRX_P13 TXD1- IFPE_L1- 263 262
PCIE_GTX_CRX_P13 PEX_RX13# PEX_TX13 RSVD DP_C_HPD EDP_HPD
99 PEX_RX13 GND 100 265 RSVD DP_D_HPD 264 EDP_HPD 14
101 102 PCIE_CTX_C_GRX_N12 TXD1+ IFPE_L1+ 267 266
PCIE_GTX_CRX_N12 GND PEX_TX12# PCIE_CTX_C_GRX_P12 RSVD RSVD
103 PEX_RX12# PEX_TX12 104 269 RSVD RSVD 268
PCIE_GTX_CRX_P12 105 106 TXD2- IFPE_L0- 271 270
PEX_RX12 GND PCIE_CTX_C_GRX_N11 RSVD RSVD
PCIE_GTX_CRX_N11
107
109
GND PEX_TX11# 108
110 PCIE_CTX_C_GRX_P11 TXD2+ IFPE_L0+
273
275
RSVD GND 272
274
eDP is supported
PEX_RX11# PEX_TX11 RSVD DP_B_L0#
PCIE_GTX_CRX_P11 111 PEX_RX11 GND 112
PCIE_CTX_C_GRX_N10
277 RSVD DP_B_L0 276 only on IFPD????
113 GND PEX_TX10# 114 279 RSVD GND 278
PCIE_GTX_CRX_N10 115 116 PCIE_CTX_C_GRX_P10 281 280
PCIE_GTX_CRX_P10 PEX_RX10# PEX_TX10 VGA_HDMI_TX2- GND DP_B_L1#
117 PEX_RX10 GND 118 16 VGA_HDMI_TX2- 283 DP_A_L0# DP_B_L1 282
119 120 PCIE_CTX_C_GRX_N9 16 VGA_HDMI_TX2+ VGA_HDMI_TX2+ 285 284
PCIE_GTX_CRX_N9 GND PEX_TX9# PCIE_CTX_C_GRX_P9 DP_A_L0 GND +3VS_DGPU
121 PEX_RX9# PEX_TX9 122 287 GND DP_B_L2# 286
PCIE_GTX_CRX_P9 123 124 16 VGA_HDMI_TX1- VGA_HDMI_TX1- 289 288
PEX_RX9 GND PCIE_CTX_C_GRX_N8 VGA_HDMI_TX1+ DP_A_L1# DP_B_L2
125 GND PEX_TX8# 126 16 VGA_HDMI_TX1+ 291 DP_A_L1 GND 290
PCIE_GTX_CRX_N8 127 128 PCIE_CTX_C_GRX_P8 293 292 VGA_CRT_DATA R39 1 DIS@ 2 4.3K_0402_5%
PCIE_GTX_CRX_P8 PEX_RX8# PEX_TX8 VGA_HDMI_TX0- GND DP_B_L3# VGA_CRT_CLK R38 1 DIS@
129 PEX_RX8 GND 130 HDMI 16 VGA_HDMI_TX0- 295 DP_A_L2# DP_B_L3 294 2 4.3K_0402_5%
131 132 PCIE_CTX_C_GRX_N7 16 VGA_HDMI_TX0+ VGA_HDMI_TX0+ 297 296
PCIE_GTX_CRX_N7 GND PEX_TX7# PCIE_CTX_C_GRX_P7 DP_A_L2 GND
133 PEX_RX7# PEX_TX7 134 299 GND DP_B_AUX# 298 VGA/B already have 4.7K ohm Pull High
PCIE_GTX_CRX_P7 135 136 16 VGA_HDMI_CLK- VGA_HDMI_CLK- 301 300
PEX_RX7 GND PCIE_CTX_C_GRX_N6 VGA_HDMI_CLK+ DP_A_L3# DP_B_AUX
B
137 GND PEX_TX6# 138 16 VGA_HDMI_CLK+ 303 DP_A_L3 DP_B_HPD 302 B
PCIE_GTX_CRX_N6 139 140 PCIE_CTX_C_GRX_P6 305 304 HDMI_HPD_VGA R1431 2 DHDMI@1 0_0402_5%
PEX_RX6# PEX_TX6 GND DP_A_HPD HDMI_HPD 16,20,22
PCIE_GTX_CRX_P6 141 142 VGA_HDMI_DATA 307 306 +3VS_DGPU
PEX_RX6 GND 16 VGA_HDMI_DATA DP_A_AUX# 3V3
143 144 PCIE_CTX_C_GRX_N5 VGA_HDMI_CLK 309 308
GND PEX_TX5# 16 VGA_HDMI_CLK DP_A_AUX 3V3
PCIE_GTX_CRX_N5 145 146 PCIE_CTX_C_GRX_P5 310 40mil(1A)
PCIE_GTX_CRX_P5 PEX_RX5# PEX_TX5 PRSNT_L#
147 PEX_RX5 GND 148
149 150 PCIE_CTX_C_GRX_N4 +3VS_DGPU 311 312
PCIE_GTX_CRX_N4 GND PEX_TX4# PCIE_CTX_C_GRX_P4 GND GND
151 PEX_RX4# PEX_TX4 152
PCIE_GTX_CRX_P4 153 154 JAE_MM70-314-310B1-1
PEX_RX4 GND PCIE_CTX_C_GRX_N3
155 GND PEX_TX3# 156 4.3K_0402_5% 1 2 R43 VGA_HDMI_DATA @
PCIE_GTX_CRX_N3 157 158 PCIE_CTX_C_GRX_P3 4.3K_0402_5% 1 2 R44 VGA_HDMI_CLK
PCIE_GTX_CRX_P3 PEX_RX3# PEX_TX3
159 PEX_RX3 GND 160
161 GND VGA/B already have 4.7K ohm Pull High

JAE_MM70-314-310B1-1
@
+3VS_DGPU

+3VS_DGPU

2
+3VS_DGPU PCIE_GTX_CRX_P[0..15] RV22 RV24
6 PCIE_GTX_CRX_P[0..15]
VGA_PWR_EN 2.2K_0402_5% 2.2K_0402_5%
OPT@ OPT@
2

5
PCIE_GTX_CRX_N[0..15] OPT@
6 PCIE_GTX_CRX_N[0..15]
1

1
RV124 QV1B
2

10K_0402_5% VGA_SMB_CK2 4 3
PCIE_CTX_C_GRX_P[0..15] EC_SMB_CK2 18,33,34,35
@ @ RV118 VGA_SMB_CK2 1 DIS@ 2 EC_SMB_CK2
18 CLK_REQ_VGA# 6 PCIE_CTX_C_GRX_P[0..15]

2
10K_0402_5% OPT@ 2N7002DW-T/R7_SOT363-6 RV35 0_0402_5%
2 1

A QV1A VGA_SMB_DA2 1 DIS@ 2 EC_SMB_DA2 A

2N7002_SOT23-3 PCIE_CTX_C_GRX_N[0..15] VGA_SMB_DA2 RV36 0_0402_5%
G

6 PCIE_CTX_C_GRX_N[0..15] 1 6 EC_SMB_DA2 18,33,34,35

1

DGPU_PWR_EN 2 @ 1 QV3 QV2 @

1

R566 0_0402_5% D CLK_REQ_GPU# 2N7002DW-T/R7_SOT363-6

1 3
2 1 2
D

+3VS_DGPU
R576 0_0402_5% G
2

S 2N7002_SOT23-3
Security Classification Compal Secret Data Compal Electronics, Inc.
3
2

1 @ 2 RV123
RV128 RV110 0_0402_5% 10K_0402_5% 2010/09/09 2011/09/09 Title
10K_0402_5% @
Issued Date Deciphered Date
@ SCHEMATICS,MB A7191
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1

B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 13 of 50
5 4 3 2 1

WWW.AliSaler.Com
 A B C D E F G H

OPTIMUS
+LCD_VDD +3VS +5VS

20 LCD_TXOUT0+ 1 OPT@ 2 LVDS_TXOUT0+ 20 LCD_TZOUT0+ 1 OPT@ 2 LVDS_TZOUT0+

1
R262 0_0402_5% R269 0_0402_5%

1
20 LCD_TXOUT0- 1 OPT@ 2 LVDS_TXOUT0- 20 LCD_TZOUT0- 1 OPT@ 2 LVDS_TZOUT0- R107
R263 0_0402_5% R266 0_0402_5% 150_0603_5% R108 R120
+3VS
20 LCD_TXOUT1+ 1 OPT@ 2 LVDS_TXOUT1+ 20 LCD_TZOUT1+ 1 OPT@ 2 LVDS_TZOUT1+ 100K_0402_5% 100K_0402_5%
R265 0_0402_5% R268 0_0402_5% OPT@ DIS@

2
+5VS
20 LCD_TXOUT1- 1 OPT@ 2 LVDS_TXOUT1- 20 LCD_TZOUT1- 1 OPT@ 2 LVDS_TZOUT1-

2
R264 0_0402_5% R267 0_0402_5%

6
20 LCD_TXOUT2+ 1 OPT@ 2 LVDS_TXOUT2+ 20 LCD_TZOUT2+ 1 OPT@ 2 LVDS_TZOUT2+
R298 0_0402_5% R333 0_0402_5% OPT@ 2 W=80mils W=80mils
1 1
20 LCD_TXOUT2- 1 OPT@ 2 LVDS_TXOUT2- 20 LCD_TZOUT2- 1 OPT@ 2 LVDS_TZOUT2- Q1A C228
R277 0_0402_5% R283 0_0402_5% 2N7002DW-T/R7_SOT363-6 2 0.1U_0402_16V7K DIS@ 2

3
S
20 LCD_TXCLK+ 1 OPT@ 2 LVDS_TXCLK+ 20 LCD_TZCLK+ 1 OPT@ 2 LVDS_TZCLK+ OPT@ C251

1
R297 0_0402_5% R329 0_0402_5% 1
R109 2LCDPWR_GATE
G
Q17 0.1U_0402_16V7K
1 2

3
S
20 LCD_TXCLK- 1 OPT@ 2 LVDS_TXCLK- 20 LCD_TZCLK- 1 OPT@ 2 LVDS_TZCLK- 47K_0402_5% 1 AO3413_SOT23 DIS@ R1446

3
R296 0_0402_5% R307 0_0402_5% LCDPWR_GATE 1 G
Q23
D 2 0_0603_5%

1
1 OPT@ 2 LVDS_EDID_CLK C229 +LCD_VDD AO3413_SOT23
20 LCD_EDID_CLK @
R300 0_0402_5% 0.01U_0402_25V7K W=80mils D

2
2
20 LCD_EDID_DATA 1 OPT@ 2 LVDS_EDID_DATA LCD_ENVDD 5
R299 0_0402_5% Q1B 1
20 UMA_ENVDD 1 OPT@ 2 LCD_ENVDD 2N7002DW-T/R7_SOT363-6 C233

4
R350 0_0402_5% 0.1U_0402_16V4Z +LCD_VDD

2
1 OPT@ 2 EC_ENBKL
20 UMA_ENBKL EC_ENBKL 33 2
R357 0_0402_5% R112
10K_0402_5% W=80mils

1
Close to LVDS Connector Reserve for EMI request

20 PCH_PWM 1 OPT@ 2 1 @ 2 LED_PWM 1 2

R337 0_0402_5% R332 0_0402_5% R78 0_0402_5%
+3VS L55 @
13 VGA_BL_PWM 1 DIS@ 2 2 1 21 USB20_N11 1 1 2 2 USB20_N11_R

2
R349 0_0402_5% D17 RB751V40_SC76-2
R126 2 R1434 1 LVDS_EDID_DATA
2 47K_0402_5% DIS@ 100K_0402_5% 21 USB20_P11 4 3 USB20_P11_R 2
4 3
LCD/PANEL BD. Conn. 2 R1435 1 LVDS_EDID_CLK WCM-2012-900T_0805

1
DIS@ 100K_0402_5%
1 2
R96 0_0402_5%
DISCRETE W=20mils W=20mils 0.1U_0402_16V4Z
+3VS 1 2 +3VS_LVDS_CAM 1 2
R388 0_0603_5% C225
JLVDS
13 VGA_ENVDD 1 DIS@ 2 LCD_ENVDD 1 1 2 2
R356 0_0402_5% USB20_P11_R 3 3 LVDS_TXCLK+ Reserve for eDP panel
EC_ENBKL USB20_N11_R 4 4 LVDS_TXCLK-
D84
13 VGA_ENBKL 1 DIS@ 2 5 5 6 6
R358 0_0402_5% 7 7 +3VS
LVDS_TXOUT0+ 8 8 LVDS_TZCLK+
2 2
9 9 10 10 1 1
LVDS_TXOUT0- 11 11 LVDS_TZCLK- C2521
LVDS_TXOUT1+ 12 12 3 3 DIS@
2
0.1U_0402_16V4Z
13 13 14 14
LVDS_TXOUT1- 15 15 LVDS_EDID_CLK DIS@ 1
Close to LVDS Connector 16 16 AZC199-02SPR7G_SOT23-3 2

5
LVDS_TXOUT2+ 17 17 LVDS_EDID_DATA R103 0_0402_5% U17
LVDS_TXOUT2- 18 18 INT_MIC_CLK
19 19 20 20 1

P
INT_MIC_CLK 31 IN1 VGA_ENBKL 13
21 21 INT_MIC_DATA BKOFF#_R
LVDS_TZOUT0+ 22 22 LCD_ENVDD
INT_MIC_DATA 31 1
D15
2
RB751V40_SC76-2
4 O
23 23 24 24 2
DISCRETE for 3D eDP Panel IN2 BKOFF# 33

G
LVDS_TZOUT0- 25 25 LED_PWM
26 26 OPT@

1
DIS@ LVDS_TZOUT1+ 27 27 +3VS_LVDSDDC DIS@
28 28

3
C880 1 20.1U_0402_16V7K LVDS_TXOUT0+ LVDS_TZOUT1- 29 29 R113 SN74AHC1G08DCKR_SC70-5
13 VGA_EDP_TX0+
DIS@ LVDS_TZOUT2+ 30 30
31 31 32 32 2A 10K_0402_5%
C881 1 20.1U_0402_16V7K LVDS_TXOUT0- LVDS_TZOUT2- 33 33
13 VGA_EDP_TX0-
DIS@ BKOFF#_R 34 34 +LCD_VDD
35 35 36 36 1 1

2
C882 1 20.1U_0402_16V7K LVDS_TXOUT1+ 37 37 OPT@ 1
3 13 VGA_EDP_TX1+
DIS@ 38 38 C226 C227 R146
2
0_0402_5% 3
+LCD_INV 39 39 40 40 +LCD_INV
C883 1 20.1U_0402_16V7K LVDS_TXOUT1- 41 GMD GND 42 0.1U_0402_16V4Z 4.7U_0805_10V4Z
13 VGA_EDP_TX1- 2 2
DIS@ Reserve for LVDS panel
13 VGA_EDP_TX2+
C884 1 20.1U_0402_16V7K LVDS_TXOUT2+ ACES_87242-4001-09
DIS@ @
C885 1 20.1U_0402_16V7K LVDS_TXOUT2-
13 VGA_EDP_TX2-
DIS@
C886 1 20.1U_0402_16V7K LVDS_TXCLK+
13 VGA_EDP_TX3+
DIS@
C887 1 20.1U_0402_16V7K LVDS_TXCLK-
13 VGA_EDP_TX3-
DIS@ B+ 1 R143 2 DIS@ EDP_HPD 13
C888 1 20.1U_0402_16V7K LVDS_EDID_CLK For EMI 0_0402_5%
13 VGA_EDP_AUX
DIS@
C889 1 20.1U_0402_16V7K LVDS_EDID_DATA +LCD_INV B+ +3VS_LVDSDDC 2 R1440 1 OPT@
13 VGA_EDP_AUX- +3VS
L2 0_0603_5%
2 1 1 1 1 1
1 FBMA-L11-201209-221LMA30T_0805

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1 For EMI
C236 C268 C489 C490
Close to LVDS Connector C234 C235 @
2
@
2
@
2
@
2
@
1 1
OPT@
68P_0402_50V8J 0.1U_0402_25V6 C231 C232
2 2 680P_0402_50V7K 0.1U_0402_16V4Z
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 14 of 50
A B C D E F G H

WWW.AliSaler.Com
 A B C D E

CRT CONNECTOR

1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
OPTIMUS DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils

3
1 1 2
1 3 1 1
20 UMA_CRT_R 1 OPT@ 2 CRT_R RB491D_SOT23-3 0.5A_8V_KMC3S050RY
R200 0_0402_5% C237
20 UMA_CRT_G 1 OPT@ 2 CRT_G 0.1U_0402_16V4Z
R204 0_0402_5% CRT_R L3 2
1 2 NBQ100505T-800Y_0402 CRT_R_L @
20 UMA_CRT_B 1 OPT@ 2 CRT_B
R211 0_0402_5% CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
20 UMA_CRT_HSYNC 1 OPT@ 2 CRT_HSYNC
R213 0_0402_5% CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
20 UMA_CRT_VSYNC 1 OPT@ 2 CRT_VSYNC
R235 0_0402_5% JCRT @
20 UMA_CRT_CLK 1 OPT@ 2 CRT_CLK 6 6
R236 0_0402_5% T75 PAD 11 11

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
20 UMA_CRT_DATA 1 OPT@ 2 CRT_DATA R138 R139 R140 CRT_R_L 1 1

150_0402_1%

150_0402_1%

150_0402_1%
R261 0_0402_5% 1 1 1 1 1 1 7 7

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 12
2 2
8
Close to CRT Connector 2 2 2 2 2 2 HSYNC 13
8
13
CRT_B_L 3

2
3
+CRT_VCC 9 9
VSYNC 14 16
14 G
T76 PAD 4 4 G 17
10 10
CRT_DDC_CLK 15 15
5
DISCRETE 5
ALLTO_C10532-11505-L_15P-T

2
13 VGA_CRT_R 1 DIS@ 2 CRT_R 2
R178 0_0402_5% +CRT_VCC
13 VGA_CRT_G 1 DIS@ 2 CRT_G
R181 0_0402_5%
13 VGA_CRT_B 1 DIS@ 2 CRT_B 1 2
R167 0_0402_5% C244 0.1U_0402_16V4Z 2 1
13 VGA_CRT_HSYNC 1 DIS@ 2 CRT_HSYNC R141 10K_0402_5%

5
1
R177 0_0402_5%
1 DIS@ 2 CRT_VSYNC

P
OE#
13 VGA_CRT_VSYNC
R179 0_0402_5% CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
A Y
13 VGA_CRT_CLK 1 DIS@ 2 CRT_CLK +CRT_VCC L6 10_0402_5%

G
R193 0_0402_5% U6
13 VGA_CRT_DATA 1 DIS@ 2 CRT_DATA SN74AHCT1G125GW_SOT353-5

5
1
R194 0_0402_5%

P
OE#
CRT_VSYNC 2 4 D_CRT_VSYNC 1 2 VSYNC
A Y

10P_0402_50V8J

10P_0402_50V8J
L7 10_0402_5%
Close to CRT Connector 1 1

G
U7
SN74AHCT1G125GW_SOT353-5 C245 C246

3
@ @
2 2

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A
CRT_CLK 5 1 6 CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6
Q205B
CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 15 of 50
A B C D E
 5 4 3 2 1

HDMI CEC Controller Address: 0011010X U16

+3VL +3VL 1 11 CEC_INT#

33,38 EC_SMB_CK1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 CEC_INT# 33 +3VL

+3VL 2 12 CEC_TEST 1 CEC@ 2

P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11#

2
R168 4.7K_0402_5%
R162 D9 +3VL +3VL
10K_0402_5% RB751V40_SC76-2 2 CEC@ 1CEC_RST# 3 13 CEC_FSHUPD1 CEC@ 2
CEC@ CEC@ R169 4.7K_0402_5% RESET# P1_4/TXD0 R170 4.7K_0402_5%
CEC_FSHUPD (Pin13)

1 1

1
HDMI_CECIN 2 CEC@ 1CEC_XOUT 4 14 Low= Force to update flash.
R171 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT R166 R164

6
R581 +3VL 4.7K_0402_5% 4.7K_0402_5% Q47

2
CEC@ 27K_0402_5% 5 15 CEC@ CEC@ CEC@ BSH111_SOT23-3
VSS/AVSS P1_2/KI2#/AN10/CMP0_2

G
D Q49A CEC@ CEC@ D
1 2

2
2N7002DW-T/R7_SOT363-6 2 C848 1U_0402_6.3V6K

2
HDMI_CEC 2 CEC@ 1CEC_XIN 6 16 1 2 HDMI_CLK 3 1 HDMI_SCLK
XIN/P4_6 P4_2/VREF

2
R174 47K_0402_5% C263 0.1U_0402_16V4Z
1

D
CEC@
7 17 HDMI_CLK
CEC@ VCC/AVCC P1_1/KI1#/AN9/CMP0_1 HDMI_DATA HDMI_SDATA
3 1
HDMI_CECOUT 1 R163 2 5 Q49B

D
27K_0402_5% 2N7002DW-T/R7_SOT363-6 2 CEC@ 1 8 18 HDMI_DATA Q48
CEC@ R176 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0 BSH111_SOT23-3

4
1

C262 1 CEC@
R165 0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R
100K_0402_5% CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
CEC@
2 HDMI_CECOUT 10 20 EC_SMB_DA1 33,38
2

P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1

R5F211A4C33SP-W4_LSSOP20 CEC@

For DISCRETE
CV296 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC+ VGA_DVI_TXC- 1 @ 2 HDMI_R_CK-
13 VGA_HDMI_CLK+
R157 0_0402_5%
CV293 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC- L8
13 VGA_HDMI_CLK-
1 1 2 2
CV294 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2+ +5VL
13 VGA_HDMI_TX2+ +3VS +3VS_DGPU R145
CV297 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2- 4 3 +HDMI_5V_OUT HDMI_HPD_U 1 2 HDMI_HPD_C
13 VGA_HDMI_TX2- 4 3
2 1K_0402_5%
CV299 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1+ WCM-2012HS-670T_0805 C264 2
13 VGA_HDMI_TX1+

2
VGA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ 0.1U_0402_16V4Z R186 C265
C C

1
CV298 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1- R173 0_0402_5% R453 R452 U9 100K_0402_5% 0.1U_0402_16V4Z
13 VGA_HDMI_TX1- 1
0_0402_5% 0_0402_5%

OE#
CV295 1
13 VGA_HDMI_TX0+ 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0+ IHDMI@ DHDMI@ 2 A Y 4 HDMI_HPD_R
VGA_DVI_TXD0- 1 @ 2 HDMI_R_D0-

1
G
CV300 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0- R175 0_0402_5% IHDMI@ 74AHCT1G125GW_SOT353-5
13 VGA_HDMI_TX0-

1
L9 2 1
20 UMA_HDMI_CLK

3
1 2 R435 0_0402_5% R184 R185
1 2 2.2K_0402_5% 2.2K_0402_5%
DHDMI@

2
4 3 2 1
For Optimus 13 VGA_HDMI_CLK

2
4 3

G
R391 0_0402_5%
WCM-2012HS-670T_0805
VGA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ 3 1 HDMI_SCLK

2
CV308 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC+ R180 0_0402_5%
20 UMA_HDMI_TXC+

D
Q18 +3VL 2 1 2 1 +3VS
CV304 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC- VGA_DVI_TXD1- 1 @ 2 HDMI_R_D1- DHDMI@ BSH111_SOT23-3 R570 R571
20 UMA_HDMI_TXC-
R182 0_0402_5% 13 VGA_HDMI_DATA 2 1 3 1 HDMI_SDATA 100K_0402_5% 2.2K_0402_5%
CV306 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2+ L10 R401 0_0402_5% D55
20 UMA_HDMI_TX2+

D
1 2 HDMI_HPD_R 1 2
1 2 HDMI_HPD 13,20,22
CV302 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2- IHDMI@ Q19
20 UMA_HDMI_TX2-
2 1 BSH111_SOT23-3
20 UMA_HDMI_DATA RB751V40_SC76-2
CV303 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1+ 4 3 R438 0_0402_5%
20 UMA_HDMI_TX1+ 4 3 D53 F2
CV301 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1- WCM-2012HS-670T_0805 +5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
20 UMA_HDMI_TX1-
VGA_DVI_TXD1+ 1 @ 2 HDMI_R_D1+ 1
CV307 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0+ R183 0_0402_5% PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY C259
20 UMA_HDMI_TX0+
CV305 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0- D54 0.1U_0402_16V4Z
20 UMA_HDMI_TX0- 2
VGA_DVI_TXD2- 1 @ 2 HDMI_R_D2- HDMI_R_CK+ 1 DHDMI@2 +5VL 2 1
R187 0_0402_5% R196 499_0402_1%
L11 HDMI_R_CK- 1 DHDMI@2 PMEG2010AEH_SOD123
1 2 R212 499_0402_1% CEC@
1 2 HDMI_R_D1- 1 DHDMI@2
B R199 499_0402_1% B
4 3 HDMI_R_D1+ 1 DHDMI@2 R196 R199
4 3 R214 499_0402_1% 680_0402_5% 680_0402_5%
WCM-2012HS-670T_0805 HDMI_R_D0+ 1 DHDMI@2 IHDMI@ IHDMI@
VGA_DVI_TXD2+ 1 @ 2 HDMI_R_D2+ R207 499_0402_1%
R188 0_0402_5% HDMI_R_D0- 1 DHDMI@2 R212 R215
R210 499_0402_1% 680_0402_5% 680_0402_5%
HDMI_R_D2- 1 DHDMI@2 IHDMI@ IHDMI@
R208 499_0402_1%
HDMI_R_D2+ 1 DHDMI@2 R214 R207
R215 499_0402_1% 680_0402_5% 680_0402_5%

1
D IHDMI@ IHDMI@
+5VS 2 Q24
G 2N7002_SOT23-3 R208 R210
S 680_0402_5% 680_0402_5%
HDMI Connector

3
IHDMI@ IHDMI@

07/10/2010
JHDMI @
Intel DG P.132 HDMI_HPD_C 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16
HDMI_SCLK SDA
15 SCL
14 Reserved
HDMI_CEC 13
HDMI_R_CK- CEC
12 CK- GND 20
11 CK_shield GND 21
HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
9 D0- GND 23
8 D0_shield
HDMI_R_D0+ 7
HDMI_R_D1- D0+
6 D1-
5 D1_shield
A HDMI_R_D1+ 4 A
HDMI_R_D2- D1+
3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
SUYIN_100042MR019S153ZL

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 16 of 50
5 4 3 2 1
 5 4 3 2 1

U2A
CMOS Setting, under DDR Door JCMOS @ PCH_RTCX1 LPC_AD0
2 1 A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 33,34
R292 1 2 PCH_RTCRST# 1 2 C216 15P_0402_50V8J A38 LPC_AD1

LPC
+RTCVCC FWH1 / LAD1 LPC_AD1 33,34
20K_0402_5% Y3 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 33,34

1
10M_0402_5%
C247 1 2 2 1 C37 LPC_AD3
NC OSC FWH3 / LAD3 LPC_AD3 33,34
1U_0402_6.3V6K PCH_RTCRST# D20 RTCRST#

R291
3 4 D36 LPC_FRAME#
NC OSC FWH4 / LFRAME# LPC_FRAME# 33,34
PCH_SRTCRST# G22
32.768KHZ_12.5PF_Q13MC14610002 SRTCRST# +3VS
iME Setting, under DDR Door E36

RTC
2
JME @ SM_INTRUDER# LDRQ0#
2 1 K22 INTRUDER# LDRQ1# / GPIO23 K36
R293 1 2PCH_SRTCRST# 1 2 C205 15P_0402_50V8J
20K_0402_5% PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 2 1
INTVRMEN SERIRQ SERIRQ 33,34
C248 1 2 R136 10K_0402_5%
1U_0402_6.3V6K
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 26
D R286 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 D
31 AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 26

SATA 6G
AP7 SATA_PTX_DRX_N0 +3VS
Integrated SUS 1.05V VRM Enable AZ_SYNC L34
SATA0TXN
AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 26 HDD1
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 26

High - Enable Internal VRs PCH_SPKR T10 AM10 SATA_PRX_C_DTX_N1

32 PCH_SPKR SPKR SATA1RXN SATA_PRX_C_DTX_N1 26
PCH_INTVRMEN (must be always pulled high) AM8 SATA_PRX_C_DTX_P1 SATA_LED# R336 2 1 10K_0402_5%
SATA1RXP SATA_PRX_C_DTX_P1 26
R142 1 2 33_0402_5% AZ_RST# SATA_PTX_DRX_N1
31 AZ_RST_HD# K34 HDA_RST# SATA1TXN AP11
AP10 SATA_PTX_DRX_P1
SATA_PTX_DRX_N1 26 HDD2
SATA1TXP SATA_PTX_DRX_P1 26
CR_WAKE# R334 2 1 10K_0402_5%
+RTCVCC AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
31 AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 26
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 26
R117 1 2 SM_INTRUDER# G34 AH5 SATA_PTX_DRX_N2 PCH_GPIO19 R335 1 2 10K_0402_5%
1M_0402_5% HDA_SDIN1 SATA2TXN
AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 26 ODD
SATA2TXP SATA_PTX_DRX_P2 26
R118 1 2 PCH_INTVRMEN C34

IHDA
330K_0402_5% HDA_SDIN2
+3VS
PCH_SPKR SATA3RXN AB8
+3VALW 2 @ 1 A34 AB10
@ High = Enabled "No Reboot Mode" R273 1K_0402_5% HDA_SDIN3 SATA3RXP
AF3
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) AF1
R276 1K_0402_5% * 31 AZ_SDOUT_HD
R289 1 2 33_0402_5% AZ_SDOUT A36
SATA3TXP +RTCBATT

SATA
HDA_SDO

1
SATA4RXN Y7
SATA4RXP Y5
+3VALW 2010/08/22 R580 1 2 0_0402_5% C36 AD3 D13
33 PWRME_CTRL# HDA_DOCK_EN# / GPIO33 SATA4TXN
Change PWRME_CTRL# AD1 +RTCVCC BAS40-04_SOT23-3
CR_CPPE# CR_CPPE# SATA4TXP
1 2 to HDA_SDO by PCH EDS 29 CR_CPPE# N32 HDA_DOCK_RST# / GPIO13
R560 10K_0402_5% Y3

2
SATA5RXN
SATA5RXP Y1 +3VL
HDA_SDO PCH_JTAG_TCK J3
SATA5TXN AB3
AB1 C486
1
JTAG_TCK SATA5TXP
ME debug mode,
PCH_JTAG_TMS H7 Y11 0.1U_0402_16V4Z

JTAG
this signal has a weak internal pull down T37 PAD JTAG_TMS SATAICOMPO 2
PCH_JTAG_TDI SATAICOMP
*Low = Disable (default)
High = Enable (flash descriptor security overide)
T38 PAD K5 JTAG_TDI SATAICOMPI Y10 1
R279
2
37.4_0402_1%
+1.05VS_VCC_SATA

T39 PAD PCH_JTAG_TDO H1 JTAG_TDO

C SATA3RCOMPO AB12 C
SATA3_COMP
HDA_SYNC SATA3COMPI AB13 1
R280
2
49.9_0402_1%
+1.05VS_SATA3

*This signal has a weak internal pull

H=>On Die PLL is supplied by 1.5V
down
PCH_SPICLK T3 SPI_CLK SATA3RBIAS AH1 RBIAS_SATA3 1 2
R281 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS# Y14 SPI_CS0#
Need to pull high for Huron River platform T1

SPI
AZ_SYNC +3V_SPI SPI_CS1# SATA_LED#
+3VALW 2 1 SATALED# P3 SATA_LED# 35
R284 1K_0402_5%
PCH_SPIDI CR_WAKE#
+5VS 4M Byte V4 SPI_MOSI SATA0GP / GPIO21 V14 CR_WAKE# 29

1 PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 21
2
G

U13
Q21 C494 8 4 BOOT BIOS Strap Bit 0
1 2 AZ_SYNC_R 3 1 0.1U_0402_16V4Z
VCC VSS for EMI COUGARPOINT_FCBGA989~D Q65R1@
31 AZ_SYNC_HD 2
R156 33_0402_5%
S

3 W CLK
1 2 BSS138_NL_SOT23-3 7 HOLD

1
R125 1M_0402_5% 1 @ 2
R285 0_0402_5% CS# 1 R397
S
10_0402_5%
CLK 6 C

2
DI 5 2 DO 1
D Q C86
PCH_SPIDI R572 1 MP@ 2 0_0402_5% DI MX25L3205DM2I-12G SO8 10P_0402_50V8J
PCH_SPICLK R573 1 MP@ 2 0_0402_5% CLK
PCH_SPICS# R574 MP@ 0_0402_5% CS# 2
1 2 Socket: SP07000F500/SP07000H900
PCH_SPIDO R575 1 MP@ 2 0_0402_5% DO

R569 2 MP@ 1 0_0603_5%

+3VS +3V_SPI Please close to U2 PCH
B +5VALW B

For MP phase +5VALW

C249
2 1 2 R418
DBG@ DBG@
8

U51 100K_0402_5% 0.1U_0402_16V4Z 10K_0402_5%

1 1 DBG@ 2 3
P

+5VALW
1

1OE# R227 +
4 2OE# O 1
1

10 EC_ON 2 1
3OE# -
G

13 R217 DBG@ C483 +3VALW

4OE# DBG@ LM393DG_SO8 DBG@
4

PCH_SPIDO 2 3 DO 100K_0402_5% U56A 0.1U_0402_16V4Z

PCH_SPICS# 1A 1B CS# 2
5 6
2

PCH_SPICLK 2A 2B CLK
9 3A 3B 8 D43
PCH_SPIDI 12 11 DI
4A 4B

1
D
3
14 7 +5VALW 1 2 Q37
+3VS VCC GND
1 Change in DVT phase 2 G DBG@
C455 SN74CBTLV3125PWR_TSSOP14 +5VALW S AO3416_SOT23-3
2010/08/25

3
2

1
DBG@ DBG@ DBG@ RB715FGT106_UMD3
0.1U_0402_16V4Z R432 R226 +3VALW +3VALW +3VALW
2 DBG@ DBG@
8

U56B 10K_0402_5% 100K_0402_5%

2
5
P

13,31,33,36,41,43 SUSP# +3V_SPI

1

2
+ R278
7 R363 R330
O 200_0402_5%
6 200_0402_5% 200_0402_5%
-
G

U53 DBG@ 1 @ @ @
EC_ON 1 LM393DG_SO8 C482
33,35 EC_ON
4

1
1OE# DBG@ PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
4 2OE#
Change in DVT phase 10 0.1U_0402_16V4Z
3OE#

2
2
2010/08/25 13 4OE#
R306 R295 R301
2 3 DO 1 2 +5VALW 100_0402_1% 100_0402_1% 100_0402_1%
33,34 KSI7 1A 1B
SPIDO 5 6 CS# @ @ @
A 33,34 KSI3 2A 2B A
SPICS# 9 8 CLK R442 100K_0402_5%
33,34 KSI5

1
3A 3B
1

SPICLK 12 11 DI DBG@
33,34,35 KSI6 4A 4B
SPIDI R443
+3V_SPI 14 7 DBG@ Change in DVT phase
VCC GND 100K_0402_5% PCH_JTAG_TCK
1 2010/08/25 1 2
C456 SN74CBTLV3125PWR_TSSOP14 R355 51_0402_1%
2

DBG@ DBG@
0.1U_0402_16V4Z
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Please close to U2 PCH,and between U2 & U13 Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 17 of 50
5 4 3 2 1
 5 4 3 2 1

U2B +3VALW 2 R232 1 2.2K_0402_5% +3VS

PCIE_PRX_C_LANTX_N1 BG34 2 R260 1 2.2K_0402_5% R400 4.7K_0402_5%
28 PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 EC_LID_OUT# EC_LID_OUT# 33 Q3B R386 4.7K_0402_5%
28 PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN 28 PCIE_PTX_C_LANRX_N1 C498 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32
C497 2 PCIE_PTX_LANRX_P1 PETN1 PCH_SMBCLK PCH_SMBDATA
28 PCIE_PTX_C_LANRX_P1 1 0.1U_0402_16V7K AU32 PETP1 SMBCLK H14 3 4 PM_SMBDATA 11,12,27

2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA Q3A 2N7002DW-T/R7_SOT363-6
27 PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34
27 PCIE_PRX_WLANTX_P2 PERP2
WLAN 27 PCIE_PTX_C_WLANRX_N2 C501 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6 1
PETN2 PM_SMBCLK 11,12,27
C502 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2 AY32

SMBUS
27 PCIE_PTX_C_WLANRX_P2 PETP2
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 7
2N7002DW-T/R7_SOT363-6
27 PCIE_PRX_JETTX_N3 PCIE_PRX_JETTX_N3 BG36
PCIE_PRX_JETTX_P3 PERN3 PCH_SMLCLK0
D 27 PCIE_PRX_JETTX_P3 BJ36 PERP3 SML0CLK C8 D
JET C505 1 2 0.1U_0402_16V7K PCIE_PTX_JETRX_N3 AV34
27 PCIE_PTX_C_JETRX_N3 PETN3
C503 1 2 0.1U_0402_16V7K PCIE_PTX_JETRX_P3 AU34 G12 PCH_SMLDATA0 +3VALW 2 R364 1 2.2K_0402_5% +3VS
27 PCIE_PTX_C_JETRX_P3 PETP3 SML0DATA

29 PCIE_PRX_C_CRTX_N4 PCIE_PRX_C_CRTX_N4 BF36 2 R385 1 2.2K_0402_5%

PERN4

5
29 PCIE_PRX_C_CRTX_P4 PCIE_PRX_C_CRTX_P4 BE36 Q4B
C504 1 PERP4
Card Reader 29 PCIE_PTX_C_CRRX_N4 2 0.1U_0402_16V7K PCIE_PTX_CRRX_N4 AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13 PCH_GPIO74
C868 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_P4 BB34 PCH_SMLDATA1 3 4
29 PCIE_PTX_C_CRRX_P4 PETP4 EC_SMB_DA2 13,33,34,35
E14 PCH_SMLCLK1

PCI-E*
SML1CLK / GPIO58

2
BG37 Q4A 2N7002DW-T/R7_SOT363-6
PERN5 PCH_SMLDATA1
BH37 PERP5 SML1DATA / GPIO75 M16
AY36 PCH_SMLCLK1 6 1
PETN5 EC_SMB_CK2 13,33,34,35
BB36 PETP5 2N7002DW-T/R7_SOT363-6
30 PCIE_PRX_C_USBTX_N6 PCIE_PRX_C_USBTX_N6 BJ38
PCIE_PRX_C_USBTX_P6 PERN6
30 PCIE_PRX_C_USBTX_P6 BG38

Controller
C519 1 PERP6
USB30 30 PCIE_PTX_C_USBRX_N6 2 0.1U_0402_16V7K PCIE_PTX_USBRX_N6 AU36 PETN6 CL_CLK1 M7
C869 1 2 0.1U_0402_16V7K PCIE_PTX_USBRX_P6 AV36
30 PCIE_PTX_C_USBRX_P6 PETP6
Control Link only for support Intel IAMT.

Link
BG40 PERN7 CL_DATA1 T11
BJ40 PERP7
AY40 +3VALW
+3VS PETN7
BB40 PETP7 CL_RST1# P10

R287 1 2 10K_0402_5% CLKREQ_JET# BE38 EC_LID_OUT# R123 1 2 10K_0402_5%

PERN8
BC38 PERP8
R338 1 2 10K_0402_5% CLKREQ_WLAN# AW38 DRAMRST_CNTRL_PCH R228 1 2 1K_0402_5%
PETN8
AY38 PETP8 PCH_GPIO74 R234 1 2 10K_0402_5%
M10 CLK_REQ_VGA# CLK_REQ_VGA# 13
CLK_LAN# PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 R238 1
28 CLK_LAN# Y40 CLKOUT_PCIE0N 2 10K_0402_5%
C
LAN CLK_LAN Y39 C
28 CLK_LAN CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA# PCH_SMLDATA0 R239 1 2 10K_0402_5%
CLKOUT_PEG_A_N CLK_PCIE_VGA# 13

CLOCKS
CLKREQ_LAN# J2 AB38 CLK_PCIE_VGA VGA
28 CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA 13

CLK_WLAN# AB49 AV22 CLK_CPU_DMI# +3VALW

27 CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI @
27 CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
2 1 CLK_REQ_VGA# 2 1
CLKREQ_WLAN# M1 R303 10K_0402_5% R275 10K_0402_5%
27 CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
AM12 CLK_DPLL# T13 PAD
CLKOUT_DP_N / CLKOUT_BCLK1_N CLK_DPLL
CLK_JET# CLKOUT_DP_P / CLKOUT_BCLK1_P AM13 T14 PAD 120 MHz for eDP
27 CLK_JET# AA48 CLKOUT_PCIE2N
JET CLK_JET AA47
27 CLK_JET CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# PCH_CLK_DMI# R242 1 2 10K_0402_5%
CLKREQ_JET# CLKIN_DMI_N PCH_CLK_DMI PCH_CLK_DMI R243 1
27 CLKREQ_JET# V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%

CLKIN_GND1# R244 1 2 10K_0402_5%

CLK_CR# Y37 CLKIN_GND1_NCLKIN_DMI2_N BJ30 CLKIN_GND1# CLKIN_GND1 R245 1 2 10K_0402_5%
29 CLK_CR# CLKOUT_PCIE3N
Card Reader 29 CLK_CR Y36 CLKIN_GND1_PCLKIN_DMI2_P BG30 CLKIN_GND1
CLK_CR CLKOUT_PCIE3P CLK_DOT# R246 1 2 10K_0402_5%
CLKREQ_CR# A8 CLK_DOT R247 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 CLK_DOT#
G24
CLKIN_DOT_96N
E24 CLK_DOT From Clock Gen. CLK_SATA# R248 1 2 10K_0402_5%
CLKIN_DOT_96P CLK_SATA R249 1
Y43 CLKOUT_PCIE4N 2 10K_0402_5%
Y45 CLKOUT_PCIE4P
AK7 CLK_SATA# CLK_14M_PCH R250 1 2 10K_0402_5%
PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_SATA
L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5

CLK_USB30# V45 K45 CLK_14M_PCH

30 CLK_USB30# CLKOUT_PCIE5N REFCLK14IN
USB30 CLK_USB30 V46
B 30 CLK_USB30 CLKOUT_PCIE5P B
+3VALW CLKREQ_USB30# L14 H45 CLK_PCILOOP
For EMI
30 CLKREQ_USB30# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP 21
@
R343 1 210K_0402_5% CLKREQ_LAN# AB42 V47 PCH_X1 CLK_PCILOOP 2 @ 1 2 1
CLKOUT_PEG_B_N XTAL25_IN PCH_X2 R417 10_0402_5% C474 22P_0402_50V8J
Please place under DDR SODIMM. AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
R344 1 210K_0402_5% PCH_GPIO26 10/25
PASSWORD_CLEAR# E6
R345 1 PEG_B_CLKRQ# / GPIO56
210K_0402_5% CLKREQ_CR#
1

JPW Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN

XCLK_RCOMP
R346 1 210K_0402_5% CLKREQ_USB30# @ V40 CLKOUT_PCIE6N
R354 90.9_0402_1%
V42
2

R348 1 OPT@210K_0402_5% PANEL_SEL CLKOUT_PCIE6P

LVDS_SEL T13
R351 1 PCIECLKRQ6# / GPIO45
210K_0402_5% PASSWORD_CLEAR#
V38 K43 CLK_FLEX0 T29 PAD
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

V37 CLKOUT_PCIE7P
F47 PCH_48MCLK T44 PAD
PANEL_SEL CLKOUTFLEX1 / GPIO65 R365 2
K12 PCIECLKRQ7# / GPIO46 1 1M_0402_5%
H47 CLK_FLEX2 T31 PAD
R233 @ CLK_BCLK_ITP# CLKOUTFLEX2 / GPIO66
10 CLK_RES_ITP# 2 1 0_0402_5% AK14 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
Y2
R282 2 @ 1 0_0402_5% CLK_BCLK_ITP AK13 K49 CLK_FLEX3 T33 PAD PCH_X1 1 2 PCH_X2
10 CLK_RES_ITP CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
R584 1 DIS@ 2 10K_0402_5% PANEL_SEL 1 25MHZ_20PF_7A25000012 1
COUGARPOINT_FCBGA989~D Q65R1@ C506 C507
R564 1 2 10K_0402_5% LVDS_SEL
27P_0402_50V8J 27P_0402_50V8J
2 2

A A

LVDS_SEL PANEL_SEL

LVDS_SEL H L PANEL_SEL H L
Security Classification Compal Secret Data Compal Electronics, Inc.
Single Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
Channel (Default) Dual Channel LVDS EDP SCHEMATICS,MB A7191
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 18 of 50

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5 4 3 2 1
 5 4 3 2 1

U2C

6 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 6
6 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 6
6 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 6
6 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 6
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 6
D 6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 D
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 6
6 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 6
2 1 DRAMPWROK 6 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 6
R316 200_0402_5% 6 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
PCH_SUSPWRDN_R DMI3RXP FDI_CTX_PRX_P0
2 1 FDI_RXP0 BG14 FDI_CTX_PRX_P0 6
R218 10K_0402_5% DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
6 DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 6
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
6 DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 6
R220 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 6
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4

DMI
FDI
6 DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 6
R221 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 6
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 6
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
6 DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 6
DMI_PTX_CRX_P2 AY18
6 DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
6 DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT 6
R127 10K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#
2 1 PM_PWROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 R222 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6
R128 10K_0402_5% R130 49.9_0402_1%
2 1 SYS_PWROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
R129 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
R160 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 6

0_0402_5% A18 DSWVREN +RTCVCC

R259 2 DSWVRMEN
1

System Power Management

@
C +3VS PAD T34 SUSACK# C12 E22 PCH_DPWROK DSWVREN R224 2 1 330K_0402_5% C
0.1U_0402_16V4Z SUSACK# DPWROK
1 2 R225 2 @ 1 330K_0402_5%
C250 5 XDP_DBRESET# XDP_DBRESET# K3 B9 EC_SWI#
SYS_RESET# WAKE# EC_SWI# 28,30
5

U12
1 IN1
P

33,44 VGATE
4 SYS_PWROK P12 N3 PCH_GPIO32 DSWVREN must be always pulled high to +RTCVCC
PM_PWROK O SYS_PWROK CLKRUN# / GPIO32
5,33 PM_PWROK 2 IN2
G

DSWVREN - Internal Deep Sleep 1.05V regulator

SN74AHC1G08DCKR_SC70-5 PM_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T17 PAD
*
3

R216 0_0402_5% PWROK SUS_STAT# / GPIO61 HΚEnable

32.768 KHz LΚDisable
L10 N14 CLK_EC
APWROK SUSCLK / GPIO62 CLK_EC 33

DRAMPWROK B13 D10 PM_SLP_S5#

5 DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 33
+3VS
PCH_RSMRST# C21 H4 PM_SLP_S4#
33 PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# 33
PCH_GPIO32 R313 1 2 8.2K_0402_5%
33 PCH_SUSPWRDN 1 2 PCH_SUSPWRDN_R K16 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# F4 PM_SLP_S3#
PM_SLP_S3# 33
R320 0_0402_5%

33 PBTN_OUT# PBTN_OUT# E20 G10 PM_SLP_A# T35 PAD

PWRBTN# SLP_A#

1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T58 PAD +3VALW

+3VALW ACPRESENT / GPIO31 SLP_SUS#
R469 330K_0402_5%
B B
D12 PCH_LOW_BAT# E10 AP14 H_PM_SYNC EC_SWI# R319 1 2 10K_0402_5%
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
13,33,35,39 ACIN 1 2

RB751V40_SC76-2 RI# A10 K14 PCH_GPIO29 PCH_GPIO29 R563 1 @ 2 10K_0402_5%

RI# SLP_LAN# / GPIO29

COUGARPOINT_FCBGA989~D Q65R1@

D16
PM_PWROK 2 1 PCH_RSMRST#

RB751V40_SC76-2
D14
38,40 POK 1 2

RB751V40_SC76-2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 19 of 50
5 4 3 2 1

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 5 4 3 2 1

OPT@ U2D
1 2 UMA_ENBKL UMA_ENBKL J47 AP43
14 UMA_ENBKL L_BKLTEN SDVO_TVCLKINN +3VS
R230 100K_0402_5% UMA_ENVDD M45 AP45
14 UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PWM P45 AM42
14 PCH_PWM L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40

1
14 LCD_EDID_CLK LCD_EDID_CLK T40
LCD_EDID_DATA L_DDC_CLK R271 R272
14 LCD_EDID_DATA K47 L_DDC_DATA SDVO_INTN AP39
AP40 2.2K_0402_5% 2.2K_0402_5%
LCTL_CLK SDVO_INTP IHDMI@ IHDMI@
D T45 L_CTRL_CLK D
LCTL_DATA P39

2
OPT@ L_CTRL_DATA
1 2 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK UMA_HDMI_CLK 16
R219 2.37K_0402_1% AF36 M39
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA 16
T40 PAD
AE48 LVD_VREFH
AE47 AT49 R1432
LVD_VREFL DDPB_AUXN 0_0402_5%
DDPB_AUXP AT47
AT40 HDMI_HPD_UMA 2 1 HDMI_HPD HDMI_HPD_UMA 2 1
DDPB_HPD HDMI_HPD 13,16,22
LCD_TXCLK- AK39 IHDMI@ 100K_0402_5%

LVDS
14 LCD_TXCLK- LVDSA_CLK#
LCD_TXCLK+ AK40 AV42 UMA_HDMI_TX2- R1433
14 LCD_TXCLK+ LVDSA_CLK DDPB_0N UMA_HDMI_TX2- 16
AV40 UMA_HDMI_TX2+
+3VS DDPB_0P UMA_HDMI_TX2+ 16
LCD_TXOUT0- AN48 AV45 UMA_HDMI_TX1-
14 LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N UMA_HDMI_TX1- 16
LCD_TXOUT1- UMA_HDMI_TX1+

Digital Display Interface

AM47 AV46
14 LCD_TXOUT1-
14 LCD_TXOUT2-
LCD_TXOUT2- AK47
LVDSA_DATA#1
LVDSA_DATA#2
DDPB_1P
DDPB_2N AU48 UMA_HDMI_TX0-
UMA_HDMI_TX1+ 16
UMA_HDMI_TX0- 16
HDMI
2 1 LCTL_CLK AJ48 AU47 UMA_HDMI_TX0+
LVDSA_DATA#3 DDPB_2P UMA_HDMI_TX0+ 16
R471 2.2K_0402_5% AV47 UMA_HDMI_TXC-
DDPB_3N UMA_HDMI_TXC- 16
LCD_TXOUT0+ AN47 AV49 UMA_HDMI_TXC+
14 LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P UMA_HDMI_TXC+ 16
2 1 LCTL_DATA LCD_TXOUT1+ AM49
14 LCD_TXOUT1+ LVDSA_DATA1
R472 2.2K_0402_5% LCD_TXOUT2+ AK49
14 LCD_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 OPT@ 1 LCD_EDID_CLK
DDPC_CTRLDATA P42
R223 2.2K_0402_5%
LCD_TZCLK- AF40
14 LCD_TZCLK- LVDSB_CLK#
2 OPT@ 1 LCD_EDID_DATA
14 LCD_TZCLK+
LCD_TZCLK+ AF39 LVDSB_CLK DDPC_AUXN AP47
R229 2.2K_0402_5% AP49
LCD_TZOUT0- DDPC_AUXP R473 2
14 LCD_TZOUT0- AH45 LVDSB_DATA#0 DDPC_HPD AT38 1 100K_0402_5%
2 OPT@ 1 UMA_CRT_CLK
14 LCD_TZOUT1-
LCD_TZOUT1- AH47 LVDSB_DATA#1
C R237 2.2K_0402_5% LCD_TZOUT2- AF49 AY47 C
14 LCD_TZOUT2- LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
2 OPT@ 1 UMA_CRT_DATA
DDPC_1N AY43
R231 2.2K_0402_5% LCD_TZOUT0+ AH43 AY45
14 LCD_TZOUT0+ LVDSB_DATA0 DDPC_1P
LCD_TZOUT1+ AH49 BA47
14 LCD_TZOUT1+ LVDSB_DATA1 DDPC_2N
LCD_TZOUT2+ AF47 BA48
14 LCD_TZOUT2+ LVDSB_DATA2 DDPC_2P
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

OPT@ UMA_CRT_B N48 M43

15 UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
1 2 UMA_CRT_B UMA_CRT_G P49 M36
15 UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
R240 150_0402_1% UMA_CRT_R T49
15 UMA_CRT_R CRT_RED
OPT@
1 2 UMA_CRT_G AT45

CRT
R241 150_0402_1% UMA_CRT_CLK DDPD_AUXN
15 UMA_CRT_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
OPT@ 15 UMA_CRT_DATA UMA_CRT_DATA M40 BH41 R524 2 1 100K_0402_5%
UMA_CRT_R CRT_DDC_DATA DDPD_HPD
1 2
R318 150_0402_1% BB43
UMA_CRT_HSYNC DDPD_0N
15 UMA_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
UMA_CRT_VSYNC M49 BF44
15 UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
DDPD_2N BF42
2 1 CRT_IREF T43 BE42
R311 1K_0402_0.5% DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
COUGARPOINT_FCBGA989~D Q65R1@
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 20 of 50
5 4 3 2 1
 5 4 3 2 1

PLT_RST#

U2E
NV_CE#0 AY7

1
NV_CE#1 AV7
BG26 AU3 R533 +3VS
TP1 NV_CE#2 OPT@
BJ26 TP2 NV_CE#3 BG4 0_0402_5%
BH25 TP3 OPT@ 1 2
BJ16 AT10 C508 0.1U_0402_16V4Z

2
TP4 NV_DQS0

5
BG16 BC8 @ U20
TP5 NV_DQS1 OPT@
AH38 2 1 1

P
D TP6 13,22 VGA_PWROK IN1 D
AH37 AU2 R531 0_0402_5%
TP7 NV_DQ0 / NV_IO0 DGPU_RST# O 4 R5282 1
0_0402_5%
PLTRST_VGA# 13
AK43 TP8 NV_DQ1 / NV_IO1 AT4 2 IN2

G
AK45 TP9 NV_DQ2 / NV_IO2 AT3

1
C18 AT1 SN74AHC1G08DCKR_SC70-5

3
TP10 NV_DQ3 / NV_IO3

2
N30 AY3 OPT@
TP11 NV_DQ4 / NV_IO4 R532 R530
H3 TP12 NV_DQ5 / NV_IO5 AT5
AH12 AV3 1K_0402_5% 100K_0402_5%

NVRAM
TP13 NV_DQ6 / NV_IO6 OPT@ OPT@
AM4 AV1

2
TP14 NV_DQ7 / NV_IO7
AM5 BB1

1
+3VS TP15 NV_DQ8 / NV_IO8
Y13 TP16 NV_DQ9 / NV_IO9 BA3
K24 TP17 NV_DQ10 / NV_IO10 BB5
RP1 L24 BB3
PCH_GPIO4 TP18 NV_DQ11 / NV_IO11
8 1 AB46 TP19 NV_DQ12 / NV_IO12 BB7
7 2 PCI_PIRQC# AB45 BE8 DIS@

RSVD
PCI_PIRQA# TP20 NV_DQ13 / NV_IO13 PLT_RST# PLTRST_VGA#
6 3 NV_DQ14 / NV_IO14 BD4 2 1
5 4 PCH_GPIO2 BF6 R529 0_0402_5%
NV_DQ15 / NV_IO15
8.2K_0804_8P4R_5% B21 AV5
TP21 NV_ALE NV_CLE
M20 TP22 AY1
RP2 AY16 TP23
DF_TVS NV_CLE
8 1 PCH_GPIO52 BG46 AV10
PCH_GPIO53 TP24 NV_RCOMP
7 2
6 3 PCI_PIRQB# AT8
RF_OFF# NV_RB#
5 4
BE28 TP25 NV_RE#_WRB0 AY5
8.2K_0804_8P4R_5% BC30 BA2
TP26 NV_RE#_WRB1
BE32 TP27
RP3 BJ32 AT12
8 1 PCH_GPIO5
PCI_PIRQD#
BC28
TP28
TP29
NV_WE#_CK0
NV_WE#_CK1 BF3 For Optimus
7 2 BE30 TP30
6 3 ODD_DA# BF32
C WL_OFF# TP31 USB20_N0 C
5 4 BG32 TP32 USBP0N C24 USB20_N0 26
AV26 A24 USB20_P0 USB-RIGHT1
TP33 USBP0P USB20_P0 26
8.2K_0804_8P4R_5% BB26 C25 USB20_N1
TP34 USBP1N USB20_N1 26
AU28 B25 USB20_P1 USB-RIGHT2
TP35 USBP1P USB20_P1 26
1 DIS@ 2 DGPU_RST# AY30 C26 USB20_N2
TP36 USBP2N USB20_N2 26
R578 10K_0402_5% AU26 A26 USB20_P2 USB-Left1
TP37 USBP2P USB20_P2 26
1 2 DGPU_PWR_EN AY26 K28
R544 10K_0402_5% TP38 USBP3N
AV28 TP39 USBP3P H28
AW30 EHCI 1 E28 USB20_N4 DMI & FDI Termination Voltage
TP40 USBP4N USB20_N4 32
D28 USB20_P4 BlueTooth
USBP4P USB20_P4 32
1 @ 2 DGPU_PWR_EN C28 USB20_N5
USBP5N USB20_N5 32
R399 1K_0402_5% A28 USB20_P5 IR Emitter Set to VCC when HIGH
USBP5P USB20_P5 32
USBP6N C29 NV_CLE
USBP6P B29
USB port6 and port7 are disabled on HM65 Set to VSS when LOW
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 M28

PCI
PCI_PIRQC# PIRQB# USBP7P USB20_N8
H38 PIRQC# USBP8N L30 USB20_N8 35
PCI_PIRQD# USB20_P8 +1.8VS
G38 PIRQD# USBP8P K30
USB20_N9
USB20_P8 35 Finger Printer
USBP9N G30 USB20_N9 27
DGPU_RST# C46 E30 USB20_P9 WiMax

USB
REQ1# / GPIO50 USBP9P USB20_P9 27

1
PCH_GPIO52 C44 C30
DGPU_PWR_EN REQ2# / GPIO52 USBP10N R324
For Optimus 13,36 DGPU_PWR_EN E40 REQ3# / GPIO54 EHCI 2 USBP10P A30
USB20_N11
USBP11N L32 USB20_N11 14 2.2K_0402_5%
27 RF_OFF# RF_OFF# D47 K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 14
PCH_GPIO53 E42 G32

2
WL_OFF# GNT2# / GPIO53 USBP12N
27 WL_OFF# F46 GNT3# / GPIO55 USBP12P E32
C32 NV_CLE 2 1 H_SNB_IVB# 5
USBP13N R323 1K_0402_5%
USBP13P A32
PCH_GPIO2 G42
ODD_DA#_R PIRQE# / GPIO2
26 ODD_DA# 1 2 G40 PIRQF# / GPIO3
R562 0_0402_5% 1 PCH_GPIO4 C42 C33 USBBIAS 1 2
B PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R535 22.6_0402_1% B
D44 PIRQH# / GPIO5
C473 Within 500 mils
1U_0402_6.3V6K B33
2 PCI_PME# USBRBIAS
T32 PAD K10 PME#
PLT_RST# C6 A14 USB_OC#0 USB-Right
5,27,28,29,30,33,34 PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 26,33
K20 USB_OC#1 USB-Left
OC1# / GPIO40 USB_OC#1 27,30,33 +3VALW
B17 USB_OC#2
22_0402_5% 1 CLK_EC_R H49 OC2# / GPIO41 SLP_CHG_M3
33 CLK_PCI_EC 2 R525 CLKOUT_PCI0 OC3# / GPIO42 C16 SLP_CHG_M3 27
22_0402_5% 1 2 R526 CLK_PCH H43 L16 SLP_CHG_M4
18 CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43 SLP_CHG_M4 27
22_0402_5% 1 2 R527 CLK_SIO J48 A16 USB_OC#5 RP4
34 CLK_PCI_DDR CLKOUT_PCI2 OC5# / GPIO9
2

K42 D14 USB_OC#6 USB_OC#0 4 5

R534 CLKOUT_PCI3 OC6# / GPIO10 USB_OC#7 SLP_CHG_M3
H40 CLKOUT_PCI4 OC7# / GPIO14 C14 3 6
100K_0402_5% SLP_CHG_M4 2 7
USB_OC#1 1 8
COUGARPOINT_FCBGA989~D Q65R1@
1

10K_0804_8P4R_5%

RP5
USB_OC#2 4 5
USB_OC#5 3 6
Boot BIOS Strap USB_OC#6 2 7
USB_OC#7 1 8
RF_OFF# PCH_GPIO19 Boot BIOS Loaction
10K_0804_8P4R_5%
1K_0402_5% 2 @ 1 R537 RF_OFF# LPC
0 0
1K_0402_5% 2 @ 1 R538 PCH_GPIO19 Reserved
PCH_GPIO19 17 0 1
1 0 PCI
A
1 1 SPI * A

1K_0402_5% 2 @ WL_OFF#
A16 Swap Override Strap
1 R536
Low= A16 swap override Enable
Security Classification Compal Secret Data Compal Electronics, Inc.
WL_OFF# 2010/09/09 2011/09/09 Title
* High= A16 swap override Disable Issued Date Deciphered Date
SCHEMATICS,MB A7191
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 21 of 50
5 4 3 2 1
 5 4 3 2 1

@
1 R100 2 +3VS
+3VALW 100K_0402_5% U2F
ODD_EN# 1 2
HDMI_HPD T7 C40 ODD_EN# R106 10K_0402_5%
13,16,20 HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 36
2 1 USB30_SMI# GATEA20 1 2
R390 1K_0402_5% PCH_GPIO1 A42 B41 PCH_WL_BT_LED R548 10K_0402_5%
EC_SMI# TACH1 / GPIO1 TACH5 / GPIO69 KB_RST#
1 2 1 2
R558 10K_0402_5% PCH_GPIO6 H36 C41 LOGO_LED R559 10K_0402_5%
PCH_GPIO12 TACH2 / GPIO6 TACH6 / GPIO70 LOGO_LED
1 2 1 2
R556 10K_0402_5% 33 EC_SCI# EC_SCI# E38 A40 MAXIC_SELECT R436 10K_0402_5%
PCH_GPIO28 TACH3 / GPIO7 TACH7 / GPIO71 PCH_WL_BT_LED
D 1 2 1 2 D
R557 10K_0402_5% 33 EC_SMI# EC_SMI# C10 R110 10K_0402_5%
GPIO8
1 OPT@ 2 3D_DET#
R549 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS USB30_SMI# G2 P4 GATEA20
30 USB30_SMI# GPIO15 A20GATE GATEA20 33
AU16 WL_BT_LED# 35

CPU/MISC
PECI

3
1 @ 2 VGA_PWROK PCH_GPIO16 U2
R579 10K_0402_5% SATA4GP / GPIO16 KB_RST#
1 2 BT_ON#
For Optimus RCIN# P5 KB_RST# 33
Q209B

GPIO
R567 10K_0402_5% VGA_PWROK D40 AY11 H_PWRGOOD 5 PCH_WL_BT_LED
13,21 VGA_PWROK TACH0 / GPIO17 PROCPWRGD H_PWRGOOD 5
1 @ 2 HDMI_HPD
R539 10K_0402_5% BT_DET# T5 AY10 PCH_THRMTRIP# 1 2 2N7002DW-T/R7_SOT363-6
32 BT_DET# H_THERMTRIP# 5

4
PCH_GPIO1 SCLOCK / GPIO22 THRMTRIP# R416 390_0402_5%
1 2
R540 10K_0402_5% E8 T14
BT_DET# GPIO24 / MEM_LED INIT3_3V#
1 2 This signal has weak internal
R542 10K_0402_5% PCH_GPIO27 E16
1 2 ODD_DETECT# GPIO27 pull-up, can't be pulled low
R545 200K_0402_5% PCH_GPIO28 P8
PCH_GPIO6 GPIO28
1 2 NC_1 AH8
R546 10K_0402_5% 27,32 BT_ON# BT_ON# K1
PCH_GPIO16 STP_PCI# / GPIO34
1 2 NC_2 AK11
R577 10K_0402_5% 32 BT_RST# BT_RST# K4
EC_SCI# GPIO35
1 2 NC_3 AH10
R550 10K_0402_5% ODD_DETECT# V8 MAXIC_SELECT 1 2
26 ODD_DETECT# SATA2GP / GPIO36
1 2 CIR_EN# AK10 R124 10K_0402_5%
R551 100K_0402_5% PCH_GPIO37 NC_4
M5 SATA3GP / GPIO37
1 @ 2 ISDBT_DET P37
C R552 10K_0402_5% OPTIMUS_EN# NC_5 C
N2 SLOAD / GPIO38
1 2 PCH_GPIO49
R553 10K_0402_5% CIR_EN# M3 MAXIC_SELECT
SDATAOUT0 / GPIO39
1 DIS@ 2 OPTIMUS_EN#
R555 10K_0402_5% For TV-Tuner use with Japan module ISDBT_DET V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
MAXIC_SELECT H L
PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
1 DIS@ 2 3D_DET#
R554 10K_0402_5% 3D_DET# D6 BH3
@ USB30_SMI# GPIO57 VSS_NCTF_17
2 1 IC TYPE MAX14550E MAX14566B
R437 10K_0402_5% BH47
PCH_GPIO37 VSS_NCTF_18
2 1
R547 10K_0402_5% A4 BJ4
PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
2 1
R402 10K_0402_5% A44 BJ44
ISDBT_DET VSS_NCTF_2 VSS_NCTF_20
1 2
R328 47K_0402_5% A45 BJ45
VSS_NCTF_3 VSS_NCTF_21
2 OPT@ 1 OPTIMUS_EN#

NCTF
R415 10K_0402_5% A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
2 CIR@ 1 CIR_EN#
R405 10K_0402_5% A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

B B
GPIO28 3D_DET#
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
On-Die PLL Voltage Regulator
* H: Enable 3D_DET# H L BE1 VSS_NCTF_11 VSS_NCTF_29 E1

L: Disable BE49 VSS_NCTF_12 VSS_NCTF_30 E49

SKU OPT 3D BF1 VSS_NCTF_13 VSS_NCTF_31 F1

R325 1 @ 2 1K_0402_5% PCH_GPIO28
BF49 VSS_NCTF_14 VSS_NCTF_32 F49

COUGARPOINT_FCBGA989~D Q65R1@

GPIO8
Integrated Clock Chip Enable (Removed) OPTIMUS_EN#
H: Disable
* L: Enable OPTIMUS_EN# H L
R326 1 @ 2 1K_0402_5% EC_SMI#
SKU Discrete Optimus
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 22 of 50
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCP U2G POWER +3VS

PJ31 @ L12
PCH Power Rail Table
1300mA
2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC_R 0.01U_0402_25V7K 10U_0603_6.3V6M 1 2 +VCCA_DAC 2 1 S0 Iccmax
2 1
AC23
VCCCORE[1] 1mA VCCADAC
2 1 R583 1_0603_1% BLM18PG181SN1D_0603 Voltage Rail Voltage Current (A)
VCCCORE[2]

CRT
JUMP_43X118 1 1 1 1 AD21
C274 C269 C275 C289 VCCCORE[3] C512 C288 C286
AD23 VCCCORE[4] VSSADAC U47

VCC CORE
D V_PROC_IO 1.05 0.001 D
AF21 VCCCORE[5]
10U_0603_6.3V6M 1 2
AF23 VCCCORE[6]
2 2 2 2 0.1U_0402_16V7K +3VS
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V5REF 5 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 OPT@ 2
VCCCORE[9] VCCALVDS R541 0_0603_5%
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37 V5REF_SUS 5 0.001
AG29 R424 1 DIS@ 2 0_0402_5%
VCCCORE[12]
AJ23

LVDS
VCCCORE[13] +1.8VS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VCC3_3 3.3 0.266
AJ27 L1 OPT@
VCCCORE[15] +VCCTX_LVDS 0.01U_0402_25V7K
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 1 2
AJ31 1 0.1UH_MLF1608DR10KT_10%_1608 VCCADAC 3.3 0.001
+1.05VS_PCH VCCCORE[17] C256
60mA VCCTX_LVDS[3] AP36
C514 C513 22U_0805_6.3V6M
VCCTX_LVDS[4] AP37 0.01U_0402_25V7K OPT@ OPT@ VCCADPLLA 1.05 0.08
OPT@ 2 C513
AN19 VCCIO[28] 0_0402_5%
This pin can be left as NC if DIS@ VCCADPLLB 1.05 0.08
BJ22 +3VS
PAD T30 VCCAPLLEXP
On-Die VR is enabled (Default)
V33 VCCCORE 1.05 1.3

HVCMOS
VCC3_3[6]
AN16 VCCIO[15]
2
AN17 VCCIO[16]
VCCDMI 1.05 0.042
V34 C272
VCC3_3[7]
1
0.1U_0402_16V7K Change package size only for PGRAA
AN21 VCCIO[17]
VCCIO 1.05 2.925
+VCCAFDI_VRM +1.5VS
AN26 R474
VCCIO[18] 0_0603_5% VCCASW 1.05 1.01
+VCCAFDI_VRM
C
AN27 VCCIO[19] 2925mA VCCVRM[3] AT16 1 2
C
+1.05VS_PCH AP21 +VCCP_VCCDMI R480 +1.05VS_VCCP VCCSPI 3.3 0.02
VCCIO[20] 0_0603_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VCCDSW 3.3 0.002

DMI
AP24 R477 +1.05VS_PCH
1 1 1 1 1

VCCIO
C277 C273 C279 C510 C511 VCCIO[22] 0_0603_5% C276
AP26 AB36 +1.05VS_VCC_DMI 1 2 1U_0402_6.3V6K VCCDFTERM 1.8 0.19
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 20mA VCCIO[1] 2
2 2 2 2 2 1
AT24 VCCIO[24] Change package size only for PGRAA
C270 VCCRTC 3.3 6 uA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
AN33 VCCIO[25]
VCCDFTERM VCCSUS3_3 3.3 0.97
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCPNAND[1]
VCCSusHDA 3.3 / 1.5 0.01

NAND / SPI
BH29 VCC3_3[3] VCCPNAND[2] AG17
2 2
190mA VCCVRM 1.5 0.16
C290 AJ16 C278
VCCPNAND[3]
0.1U_0402_16V7K 0.1U_0402_16V7K
1 +VCCAFDI_VRM 1 VCCCLKDMI 1.05 0.02
AP16 VCCVRM[2]
VCCPNAND[4] AJ17

This pin can be left as NC if PAD T36 BG6 VCCFDIPLL

VCCSSC 1.05 0.095
+3VS
On-Die VR is enabled (Default)
+1.05VS_PCH AP17 VCCIO[27]
VCCDIFFCLKN 1.05 0.055
FDI

VCCSPI V1
20mA
+VCCP_VCCDMI AU20 VCCDMI[2] 1 VCCALVDS 3.3 0.001
B B
C281
COUGARPOINT_FCBGA989~D Q65R1@ 1U_0402_6.3V6K VCCTX_LVDS 1.8 0.06
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 23 of 50
5 4 3 2 1
 5 4 3 2 1

+3VS

L18
1 2 +3VS_VCC_CLKF33
10UH_LB2012T100MR_20% 1 1
C301 C310
This pin can be left as NC if
10U_0603_6.3V6M 1U_0402_6.3V6K On-Die
+3VALW VR is enabled (Default)
2 2 U2J POWER +1.05VS_PCH
T41
2 AD49 VCCACLK VCCIO[29] N26
1
D C324 PAD P26 D
VCCIO[30] C328
0.1U_0402_16V7K T16
1 VCCDSW3_3 3mA 1U_0402_6.3V6K
"@" Avoid leakage @ VCCIO[31] P28
2
2 1 +PCH_VCCDSW V12 T27
C305 0.1U_0402_16V7K DCPSUSBYP VCCIO[32]

VCCIO[33] T29
+3VS_VCC_CLKF33 T38 +3VALW
VCC3_3[5]
This pin can be left as NC if VCCSUS3_3[7] T23
PAD T42 BH23 VCCAPLLDMI2 2
On-Die VR is enabled (Default) 119mA VCCSUS3_3[8] T24 +3VALW +5VALW +3VALW
+1.05VS_PCH AL29 C321
VCCIO[14]
V23 0.1U_0402_16V7K

USB
VCCSUS3_3[9]

2
1
2
+VCCSUS AL24 V24 R512 D8
DCPSUS[3] VCCSUS3_3[10] C332 100_0402_5% RB751V40_SC76-2
1
C300 P24 0.1U_0402_16V7K
1U_0402_6.3V6K VCCSUS3_3[6] 1

1
@ AA19 +PCH_V5REF_SUS
+1.05VS_PCH 2 VCCASW[1]
VCCIO[34] T26 +1.05VS_PCH 1
AA21 VCCASW[2] 1010mA
C326
AA24 1mA M26 +PCH_V5REF_SUS .1U_0402_16V7K
VCCASW[3] V5REF_SUS 2

Clock and Miscellaneous

1 1 AA26 @ Change package size only for PGRAA
C311 C312 VCCASW[4] +VCCA_USBSUS C335 1
DCPSUS[4] AN23 2 1U_0402_6.3V6K
AA27 VCCASW[5]
22U_0805_6.3V6M AN24 +3VALW
2 2 VCCSUS3_3[1]
AA29 VCCASW[6]
22U_0805_6.3V6M
+5VS +3VS
AA31 VCCASW[7]
C C
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
+3VALW
1 1 1
C323 C294 C308 AC27 R490 D7
VCCASW[9] 100_0402_5% RB751V40_SC76-2
N20

PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K VCCSUS3_3[2]
AC29 VCCASW[10] 1
2 2 2 C293
N22

1
VCCSUS3_3[3] 1U_0402_6.3V6K +PCH_V5REF_RUN
AC31 VCCASW[11]
VCCSUS3_3[4] P20 1
+1.05VS_PCH 2
AD29 VCCASW[12]
P22 C304
L21 VCCSUS3_3[5] +3VS 1U_0603_10V6K
AD31 VCCASW[13]
+1.05VS_VCCADPLLA 2
1 2
BLM18PG181SN1D_0603 W21 AA16
L19 VCCASW[14] VCC3_3[1]
+3VS 2
1 2 +1.05VS_VCCADPLLB 1U_0402_6.3V6K W23 W16
BLM18PG181SN1D_0603 VCCASW[15] VCC3_3[8] C313
1U_0402_6.3V6K W24 T34 0.1U_0402_16V7K
VCCASW[16] VCC3_3[4] 1
1 1 1 1
C295 C1207 W26 2 1
C298 C1208 VCCASW[17] C306
0.1U_0402_16V7K +3VS
W29 VCCASW[18]
2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M W31 AJ2
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS_PCH
2
W33 R516
VCCASW[20] C297
VCCIO[5] AF13 2 1
0.1U_0402_16V7K
+VCCRTCEXT 1 0_0805_5%
N16 DCPRTC 1
2 AH13 C329
VCCIO[12] 1U_0402_6.3V6K
+1.05VS_PCH C334 +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
R522 0.1U_0402_16V7K VCCVRM[4] VCCIO[13] 2
+VCCDIFFCLK 1
B 2 1 B

0_0603_5% +1.05VS_VCCADPLLA VCCIO[6] AF14 This pin can be left as NC if

1 BD47

SATA
C337 VCCADPLLA 80mA On-Die VR is enabled (Default)
VCCAPLLSATA AK1 T43 PAD
1U_0402_6.3V6K +1.05VS_VCCADPLLB BF47 +VCCAFDI_VRM
VCCADPLLB 80mA
2 +VCCAFDI_VRM
VCCVRM[1] AF11
+VCCDIFFCLK AF17 +1.05VS_VCC_SATA +1.05VS_PCH
VCCIO[7] R491
AF33 VCCIO[8]
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCC_SATA
R485 +1.05VS_VCCDIFFCLKN
AF34 VCCIO[9] 55mA VCCIO[2] AC16 2
0_0805_5%
1
AG34 VCCIO[11]
2 1 +1.05VS_VCCDIFFCLKN +1.05VS_PCH AC17
VCCIO[3] 1
1 C331
0_0603_5% C320 AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCIO[10] 95mA VCCIO[4]
1 2
C318
2 1U_0402_6.3V6K +VCCSST +1.05VS_PCH
V16 DCPSST
2 2
C299 +1.05VM_VCCSUS T17 T21 +VCCME_22 R509 2 1 0_0603_5%
DCPSUS[1] VCCASW[22]
0.1U_0402_16V7K V19
MISC

1 DCPSUS[2]
+1.05VS_VCCP V21 +VCCME_23 R517 2 1 0_0603_5%
R511 VCCASW[23]
1mA
CPU

+1.05VS_PCH 1 2 0.1U_0402_16V7K +V_CPU_IO BJ8

R521 @ V_PROC_IO +VCCME_21 R520 2
VCCASW[21] T19 1 0_0603_5%
2 1 +1.05VM_VCCSUS 0_0603_5% 1 2 2
+RTCVCC
0_0603_5% C325 C322 C303 +3VALW
1
RTC

C316 4.7U_0603_6.3V6K 0.1U_0402_16V7K A22 10mA P32

HDA

2 1 1
0.1U_0402_16V7K VCCRTC VCCSUSHDA
1U_0402_6.3V6K
2 1 2 2 1
C327 C330 C336 COUGARPOINT_FCBGA989~D Q65R1@ C307
A A
0.1U_0402_16V4Z
1U_0402_6.3V6K 0.1U_0402_16V7K
2 1 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 24 of 50
5 4 3 2 1
 5 4 3 2 1

U2I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
U2H B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
D AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36 D
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
C C
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
B AH36 AW2 D22 G14 B
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D Q65R1@ G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]

COUGARPOINT_FCBGA989~D Q65R1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 25 of 50
5 4 3 2 1
 5 4 3 2 1

SATA Main HDD Conn. SATA ODD Conn Close to JODD

JODDB @
1 1
+5VS SATA_PTX_C_DRX_P2 C378 1 2 0.01U_0402_25V7K
Place closely JHDD1 SATA CONN. 2 2
SATA_PTX_C_DRX_N2 C377 1
SATA_PTX_DRX_P2 17
1.2A 3 3 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 17
4 4
1 1 1 1 5 SATA_PRX_DTX_N2 C376 1 2 0.01U_0402_25V7K
5 SATA_PRX_C_DTX_N2 17
C356 C357 C358 C359 6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
6 SATA_PRX_C_DTX_P2 17
10U_0805_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 7
7 ODD_DETECT#_R
8 8 1 2 ODD_DETECT# 22
2 2 2 2
D 9 9 +5VS_ODD R561 0_0402_5%
D
10 10
11 11 ODD_DA# 21
12 12
GND 13
Close to JHDD1 GND 14

@ JHDD1 ACES_88058-120N
GND 1
2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
A+ SATA_PTX_DRX_P0 17
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N0 17
GND 4
5 SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N0 17
6 SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P0 17
7 JPIO @
GND
22

V33 8 +3VS
USB Board@ Right Side 31 BACK_SENSE
21
20
22
21
20
9 R73 0_0402_5% 19
V33 31 NBA_PLUG 19
10 1 @ 2 18
V33 31 MIC1_R 18
GND 11 31 MIC1_L 17 17
12 L53 16
GND USB20_N0_R 16
GND 13 21 USB20_N0 1 1 2 2 31 HP_L 15 15
V5 14 +5VS 31 HP_R 14 14
V5 15 13 13
16 21 USB20_P0 4 3 USB20_P0_R 12
V5 4 3 USB20_P0_R 12
GND 17 11 11
18 WCM-2012-900T_0805 USB20_N0_R 10
Reserved 10
GND 19 W=60mils @
9 9
20 1 2 1 2 8
V12
V12 21 +5VALW 2.5A +USB_VCCA
For EMI R87 0_0402_5%
+5VL
R149 0_0402_5% USB20_P1_R 7
8
7
22 U14 USB20_N1_R 6
C V12 R77 0_0402_5% @ +5V_IO 6 C
1 GND VOUT 8 2 1 +5VALW 1 2 5 5
23 2 7 C361 1000P_0402_50V7K 1 @ 2 R148 0_0402_5% 4
GND VIN VOUT 4
GND 24 3 VIN VOUT 6 3 3
USB_EN# 4 5 USB_OC#0 21,33 L54 2
EN FLG USB20_N1_R 2
1 21 USB20_N1 1 1 2 2 +USB_VCCA 1 1
SANTA_191001-2 RT9715BGS_SO8 W=60mils
@ C362 ACES_85201-2005N
4.7U_0805_10V4Z USB20_P1_R
2 21 USB20_P1 4 4 3 3
ForEMIrequest
WCM-2012-900T_0805
+5VL +5VALW
1 @ 2
R88 0_0402_5%

680P_0603_50V7K

680P_0603_50V7K

680P_0603_50V7K
1 1 1
C1209 C1210 C1211
2 2 2

ClosetoR149 ClosetoR148

B B

SATA 2nd HDD Conn. USB Board@ Left Side

+USB_VCCC
Q8

S
+USB_VCCC 1 3 +USB_VCCB
@ JHDD2 W=60mils
+5VS 1 AO3413_SOT23
1
2 1 2

G
+5VALW

2
2 R568 100K_0402_5% C428 1
3 3 2 1000P_0402_50V7K
4 4
5 33 USB_EN# USB_EN#
0.01U_0402_25V7K 1 5
17 SATA_PRX_C_DTX_P1 2 C371 SATA_PRX_DTX_P1 6 6 2 @ 1 C389 1 2 0.1U_0402_16V4Z
0.01U_0402_25V7K 1 2 C366 SATA_PRX_DTX_N1 7 R190 0_0402_5%
17 SATA_PRX_C_DTX_N1 7
8 8 L15
0.01U_0402_25V7K 1 2 C365 SATA_PTX_C_DRX_N1 9 JUSB @
17 SATA_PTX_DRX_N1 9
0.01U_0402_25V7K 1 2 C364 SATA_PTX_C_DRX_P1 10 21 USB20_N2 4 3 1
17 SATA_PTX_DRX_P1 10 4 3 VBUS
11 USB20_N2_R 2
11 USB20_P2_R D-
12 12 3 D+
13 GND D11 21 USB20_P2 1 1 2 2 4 GND
Close to JHDD2 14 GND USB20_P2_R 2
5
6
GND
ACES_88058-120N 2 WCM-2012-900T_0805 GND
1 1 7 GND
USB20_N2_R 3 2 @ 1 8
3 R189 0_0402_5% GND
A AZC199-02SPR7G_SOT23-3 ACON_UARBG-4K1926 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019B7
WWW.AliSaler.Com 5 4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3 2
Date: Friday, September 16, 2011
1
Sheet 26 of 50
 A B C D E F G H

WLAN&BT Combo module circuits

Slot 2 Half PCIe Mini Card- JET
BT BT
Slot 1 Half PCIe Mini Card-WLAN/ WiMax on module on module
Enable Disable

+3VALW 2 2 1 1 +3V_WLAN BT_CRTL H L +1.5VS +3VS

PJ27@ JUMP_43X79 J3G
PCIE--JET
+3VS 2 2 1 1 BT_ON# L H 1 1 2 2 2.75A
3 3 4 4
PJ26@ JUMP_43X79 5 6
5 6 +3VS
1 **If +3V_WLAN is +3VS, please 18 CLKREQ_JET# 7 7 8 8 120 mils For SED 1
Short PJ27 for Wimax 9 9 10 10
remove D24 18 CLK_JET# 11 12 0.1U_0402_16V4Z
11 12
Short PJ26 for WLAN 18 CLK_JET 13 13 14 14 1 1 1

1
BT_CTRL 15 16 CM4 CM5 CM6 C255
15 16 47P_0402_50V8J
17 17 18 18

3
19 20 RF_OFF# 0.01U_0402_25V7K @
RF_OFF# 21

2
19 20

6
Q210B PLT_RST# 2 2 2
21 21 22 22
2N7002DW-T/R7_SOT363-6 23 24 4.7U_0805_10V4Z
18 PCIE_PRX_JETTX_N3 23 24
+3V_WLAN
40 mils +1.5VS 22,32 BT_ON# 5 18 PCIE_PRX_JETTX_P3 25 25 26 26
For SED For SED 2 Q210A 27 28
2N7002DW-T/R7_SOT363-6 27 28
29 30

4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 29 30
18 PCIE_PTX_C_JETRX_N3 31 32

1
31 32
1 1 1 1 1 1 18 PCIE_PTX_C_JETRX_P3 33 33 34 34
1

1
5,9,36,43 SUSP 35 35 36 36
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254 37 38
47P_0402_50V8J 47P_0402_50V8J 37 38
+3VS 39 40
2

2
2 2 2 @ 2 2 2 @ 39 40
41 41 42 42
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0603_6.3V6K +3VS 43 44
43 44
45 45 46 46
Change package size only for PGRAA 47 47 48 48

2
G
49 49 50 50
51 51 52 52
+1.5VS +3V_WLAN WLAN_OFF# 1 3
JWLAN WL_OFF# 21
@ 53 54

S
R1443 GND1 GND2
1 1 2 2
0_0402_5% 3 4 Q40 2N7002_SOT23-3 BELLW_80003-1121 @
BT_CTRL 1 3 4
2BT_CTRL_R 5 5 6 6 WLAN_OFF# 1 2 +3V_WLAN
7 8 R582 @ 10K_0402_5%
18 CLKREQ_WLAN# 7 8
9 9 10 10
18 CLK_WLAN# 11 12 Add level shift circuit for WL_OFF# to
11 12
18 CLK_WLAN 13 13 14 14 avoid leakage from WLAN to PCH
2 2
15 15 16 16
17 17 18 18
19 20 WLAN_OFF#
19 20 PLT_RST#
21 21 22 22 PLT_RST# 5,21,28,29,30,33,34
18 PCIE_PRX_WLANTX_N2 23 23 24 24
18 PCIE_PRX_WLANTX_P2 25 25 26 26
27 27 28 28
29 29 30 30 PM_SMBCLK 11,12,18
18 PCIE_PTX_C_WLANRX_N2 31 31 32 32 PM_SMBDATA 11,12,18
18 PCIE_PTX_C_WLANRX_P2 33 33 34 34
35 35 36 36 USB20_N9 21
WLAN/ WiFi 37 37 38 38 USB20_P9 21 WiMax
+3V_WLAN 39 39 40 40
41 42 LED_WIMAX#
41 42 LED_WIMAX# 35
43 43 44 44
45 45 46 46 1 2 +3VS
R16 47 48 RM6 100K_0402_5%
47 48
33 E51_TXD 10_0402_5%2 49 49 50 50
1 2 E51_RXD_R 51 52
33 E51_RXD 51 52
0_0402_5%
R17 53 54 BT_CTRL 1 R327 2 E51_RXD_R
GND1 GND2 1K_0402_5%
Debug card using
BELLW_80003-1121 @
For isolate Intel Rainbow Peak and
Compal Debug Card.

USB Sleep & Charge

3
Auto-Mode 3

Mode3 MAX14566B
CB0 CB1 (CEN#)
SLP_CHG_M4 STATUS
SLP_CHG_M3

0 0 AUTO MODE
Force Dedicated charger mode
0 1 (MODE3)
Pass-Through (USB) Mode:
1 X Connect DP/DM to TDP/TDM

+5VALW 2.5A +USB_VCCB

U15 W=60mils
1 GND VOUT 8 SA00004GV00
2 VIN VOUT 7
3 6 U5
VIN VOUT SLP_CHG_M3 SLP_CHG_M4
30,33 USB_CHG_EN# 4 EN FLG 5 USB_OC#1 21,30,33 21 SLP_CHG_M3 1 CEN CB 8 SLP_CHG_M4 21
USB20_DN1_R 2 7 U2D_DN1
30 USB20_DN1_R DM TDM U2D_DN1 30
RT9715BGS_SO8 1 USB20_DP1_R 3 6 U2D_DP1
30 USB20_DP1_R DP TDP U2D_DP1 30
C383 4 5 +5VALW
@ 4.7U_0805_10V4Z GND VCC
9 GND 1
C892
2 MAX14566BEETA+_TDFN-EP8_2X2~D 0.1U_0402_16V7K
2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 27 of 50
A B C D E F G H

WWW.AliSaler.Com
 A B C D E

UL1
+3V_LAN CL3 to CL6 close to Pin 27,39,47,48
CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 31 +LAN_VDD10 CL7 to CL8 close to Pin 12,42
18 PCIE_PRX_C_LANTX_P1 HSOP LED3/EEDO
LED1/EESK 37
18 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 LL1 1 2
+LAN_REGOUT 1 2 CL3 0.1U_0402_16V4Z
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N 1 2
18 PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
PCIE_PTX_C_LANRX_N1 18 32 RL1 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_16V4Z
18 PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA Layout Note: LL1 must be 1 2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_16V4Z
CLKREQ_LAN# 2 1 16 1 LAN_MDI0+ CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
18 CLKREQ_LAN# CLKREQB MDIP0 2 2
RL19 0_0402_5% 2 LAN_MDI0- 200mil to LL1 CL6 0.1U_0402_16V4Z
PLT_RST# MDIN0 LAN_MDI1+
5,21,27,29,30,33,34 PLT_RST# 25 PERSTB MDIP1 4 1 2
5 LAN_MDI1- CL7 0.1U_0402_16V4Z
1 +3V_LAN CLK_LAN MDIN1 LAN_MDI2+ 1
18 CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2
CLK_LAN# 20 8 LAN_MDI2- CL8 0.1U_0402_16V4Z
18 CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+
RL24 2 @ NC/MDIP3
1 10K_0402_5% CLKREQ_LAN#
NC/MDIN3 11 LAN_MDI3-
LAN_X1 43
RL25 2 @ EC_SWI# CKXTAL1
1 10K_0402_5%
LAN_X2 44 13 +LAN_VDD10 +LAN_EVDD10
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_VDD10
PCH side already have 10K ohm Pull High 29 CL19, CL20,CL21 close to pin 13,29,45, respectively
DVDD10
41 1 2 CL22 close to pin 3, respectively
EC_SWI# DVDD10 LL2 0_0603_5%
19,30 EC_SWI# 28 LANWAKEB CL23,CL24,CL25 close to pin 6,9,41, respectively
RTL8111E 1 1
ISOLATE# 26 27 +3V_LAN 1 2
ISOLATEB DVDD33 CL18 CL17 CL19 0.1U_0402_16V4Z
Pin14 NC DVDD33 39
+3VS 1U_0402_6.3V6K 0.1U_0402_16V4Z 1 2
Pin15 10K ohm PD 2 2 CL20 0.1U_0402_16V4Z
14 NC/SMBCLK AVDD33 12 +3V_LAN
RL21 2 1 10K_0402_5% 15 42 1 2
RL22 1 NC/SMBDATA AVDD33
Pin38 1K ohm Pull-high +3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 CL21 0.1U_0402_16V4Z
1

AVDD33 48 Close to Pin 21 1 2

CL22 0.1U_0402_16V4Z
1K_0402_5% ENSWREG 33 1 2
RL6 ENSWREG CL23 0.1U_0402_16V4Z
EVDD10 21 +LAN_EVDD10
@ 34 +3V_LAN +LAN_VDDREG 1 2
+LAN_VDDREG
2

VDDREG CL24 0.1U_0402_16V4Z

35 VDDREG AVDD10 3 +LAN_VDD10
ISOLATE# 1 2 WOL_EN 6 1 2 1 2
RL433 0_0402_5% AVDD10 LL3 0_0603_5% CL25 0.1U_0402_16V4Z
AVDD10 9 1 1
1 2 46 RSET AVDD10 45
RL5 2.49K_0402_1% CL28 CL29
24 36 +LAN_REGOUT 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RL7 GND REGOUT 2 2
49 PGND 60 mils
15K_0402_5% Sx Enable Sx Disable S0
+3V_LAN
Wake up Wake up
RTL8111E-VL-CGT QFN 48P
2 2
WOL_EN LOW HIGH HIGH

1 1
CL683 CL684
10U_0805_10V6K 10U_0805_10V6K
+3VALW TO +3V_LAN 2 2
YL1 RTL8105E-VC
LAN_X1 1 2 LAN_X2 +3V_LAN
+3VALW
RTL8111E-VB
25MHZ_20PF_7A25000012
PWM Mode
+3VALW
1 1
CL26 CL27 RL4 (Pull High) FOR EMI ISN TEST DEMAND.
27P_0402_50V8J 27P_0402_50V8J
1

2 2 2
RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm
100K_0402_5% @ ENSWREG
@ 0.1U_0402_16V7K
2

1
2

S
@RL432
@ RL432 @ QL51 PJ29
2

G
33 WOL_EN 1 2 2 JUMP_43X79
@
+3V_LAN
1

47K_0402_5% 2 AO3413_SOT23 D
1

@
1

CL482
0.01U_0402_25V7K
1
1
1
CL682
CL681
4.7U_0805_10V4Z
1U_0402_6.3V6K
2 @
LAN Conn.
@ 2 JLAN @
3 3
RJ45_MIDI3- 8 PR4-
RJ45_MIDI3+ 7
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. PR4+
RJ45_MIDI1- 6 PR2-
RJ45_MIDI2- 5 PR3-
RJ45_MIDI2+ 4 PR3+

1
UL4 RJ45_MIDI1+ 3
CL39 1000P_0402_50V7K PR2+ DL1

1
1 24 2 1 1 2 RJ45_MIDI0- 2 AZC199-02SPR7G_SOT23-3
LAN_MDI3- TCT1 MCT1 RL11 75_0402_1% RJ45_MIDI3-_R R392 2 PR1-
2 TD1+ MX1+ 23 10_0402_5% RJ45_MIDI3-

3
LAN_MDI3+ 3 22 RJ45_MIDI3+_R R403 2 10_0402_5% RJ45_MIDI3+ RJ45_MIDI0+ 1
TD1- MX1- CL40 1000P_0402_50V7K PR1+

3
4 TCT2 MCT2 21 2 1 1 2 SHLD1 9
LAN_MDI2- 5 20 RL12 75_0402_1% RJ45_MIDI2-_R R419 2 10_0402_5% RJ45_MIDI2-
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+_R R429 2
6 TD2- MX2- 19 10_0402_5% RJ45_MIDI2+
SHLD2 10
CL41 1000P_0402_50V7K

3
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI1- 8 17 RL13 75_0402_1% RJ45_MIDI1-_R R430 2 10_0402_5% RJ45_MIDI1- SANTA_130451-D

3
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+_R R431 2 RJ45_MIDI1+
9 TD3- MX3- 16 10_0402_5%
CL42 1000P_0402_50V7K AZC199-02SPR7G_SOT23-3

1
10 15 2 1 1 2 DL2
LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0-_R R434 2 RJ45_MIDI0-
11 14 10_0402_5%

1
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+_R R439 2
12 TD4- MX4- 13 10_0402_5% RJ45_MIDI0+

RJ45_GND RJ45_GND 1 2 LANGND

2 2 CL36 1000P_1808_3KV7K 1 1
SUPERWORLD_SWG150401 @ @
4 CL35 @ CL34 CL37 CL38 4
0.1U_0402_16V7K 0.1U_0402_16V7K 180P_0402_50V8J 4.7U_0603_6.3V6K
1 1 Place CL34 colse 2 2
to LAN chip

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 28 of 50
A B C D E
 5 4 3 2 1

+1.8VS_OUT CC3 close to pin 5

CC2 close to CC3
20mil CC1 is near CC3

1000P_0402_50V7K
10U_0805_10V6K

0.22U_0402_6.3V4K

0.1U_0402_16V4Z
1 1 1 1
CC1 CC2 CC3 CC4
CC4 close to pin 10
2 2 2 2

D JMB389C D
+3VS
UC1 +3VS
place near pin 19,20 and 44
CLK_CR#
18 CLK_CR# CLK_CR
3
4
APCLKN APVDD 5
10 40mil CC5
1 2
0.1U_0402_16V4Z 2
D3E mode
18 CLK_CR APCLKP APV18
NC/TAV33 36 1 2
PCIE_PTX_C_CRRX_N4 9 CC6 0.1U_0402_16V4Z CC12
18 PCIE_PTX_C_CRRX_N4 PCIE_PTX_C_CRRX_P4 APRXN RC31 0_0402_5%
18 PCIE_PTX_C_CRRX_P4 8 APRXP DV33 19 1 2 0.1U_0402_16V4Z
CC7 0.1U_0402_16V4Z 1 CPPE#
DV33 20 17 CR_CPPE# 1 2
18 PCIE_PRX_C_CRTX_N4 CC8 1 2 0.1U_0402_16V7K PCIE_PRX_CRTX_N4 11 44
CC9 0.1U_0402_16V7K PCIE_PRX_CRTX_P4 APTXN DV33 +1.8VS_OUT RC6 0_0402_5%
18 PCIE_PRX_C_CRTX_P4 1 2 12 APTXP DV18 18 20mil CC12 close to pin 36
37 17 CR_WAKE# 1 2 SD_CD#
APREXT DV18
2 1 7 APREXT
RC3 12K_0402_1% 12mil 48 XD_SD_MS_D0 +3VS
MDIO0 2 1
47 XD_SD_MS_D1 CC10 CC11 10U_0805_10V6K 2 1
+SDV33_18 MDIO1 XD_SD_MS_D2 RC8 10K_0402_5%
1 2 43 SDDV/MDIO4 MDIO2 46
CC16 2.2U_0603_6.3V6K 39 45 XD_SD_MS_D3 CC11 close to pin18
TXIN/NC MDIO3 SDCMD_MSBS_XDWE# 1 2
MDIO6/4 41 For intenal LDO's usage
CC16 close to pin43 42 SDCLK_MSCLK_XDCE# 0.22U_0402_6.3V4K
MDIO5 XDWP#_SDWP#
24
For internal LDO in SD3.0 JMB389 G/MDIO6
MDIO7 40 XD_CLE Add RC24 and RC17 close to UC1 for xD issue
29 XD_SD_D4 CC10 close to pin37
MDIO8 XD_SD_D5
5,21,27,28,30,33,34 PLT_RST# 1 XRSTN MDIO9 28
2 27 XD_SD_D6
XTEST MDIO10 XD_SD_D7 SDCMD_MSBS_XDWE# XDWE#
MDIO11 26 2 1
25 XD_RE# RC24 22_0402_5%
CPPE# MDIO12 XD_RB#
13 CPPE_N MDIO13 23
XD_CD# 14 22 XD_ALE 2 1 SDCMD_MSBS
CR1_CD2N MDIO14 RC17 22_0402_5%
NC/SPI_SCK 30
C MS_CD# C
15 CR1_CD1N NC/SPI_CSN 33
SD_CD# 16 34
CR1_CD0N NC/SPI_SO
NC/SPI_SI 35
40 mils
+VCC_OUT 17 CR1_PCTLN
+VCC_OUT 6
APGND
NC/GND 31
CR_LEDCON# 21 32 RC13 0_0402_5%
35 CR_LEDCON# CR1_LEDN NC/GND
2 1 XDWP#_SDWP# 38 SDCLK_MSCLK_XDCE# 1 2 SDCLK_MSCLK_XDCE#_R
RC7 10K_0402_5% NC/GND
Confirm sinking 16mA
1 2 XD_RB# 1
RC9 1K_0402_5%
JMB389-LGAZ0A_LQFP48_7X7 @ C475
22P_0402_50V8J
2

5 in 1 Card Reader
B SD_CD# XD_CD# JREAD @ B
+VCC_OUT
40 mils MS-VCC 14 +VCC_OUT
1 1 33 15 SDCLK_MSCLK_XDCE#_R
CC22 CC23 XD_CD# XD-VCC MS-SCLK MS_CD#
34 XD-CD-SW MS-INS 17
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 XD_RB# 1 21 SDCMD_MSBS
@ CC17 CC18 XD_RE# XD-R/B MS-BS XD_SD_MS_D0
2 XD-RE MS-DATA0 19
2 2 SDCLK_MSCLK_XDCE#_R XD_SD_MS_D1
3 XD-CE MS-DATA1 20
10U_0805_10V6K 0.1U_0402_16V4Z XD_CLE 4 18 XD_SD_MS_D2
2 2 XD_ALE XD-CLE MS-DATA2 XD_SD_MS_D3
5 XD-ALE MS-DATA3 16
XDWE# 6
XDWP#_SDWP# XD-WE
7 XD-WP SD-VCC 23 +VCC_OUT
24 SDCLK_MSCLK_XDCE#_R
XD_SD_MS_D0 SD-CLK SDCMD_MSBS
8 XD-D0 SD-CMD 12
XD_SD_MS_D1 9 25 XD_SD_MS_D0
XD_SD_MS_D2 XD-D1 SD-DAT0 XD_SD_MS_D1
26 XD-D2 SD-DAT1 29
XD_SD_MS_D3 27 10 XD_SD_MS_D2
XD_SD_D4 XD-D3 SD-DAT2 XD_SD_MS_D3
28 XD-D4 SD-DAT3 11
XD_SD_D5 30 35 XDWP#_SDWP#
XD_SD_D6 XD-D5 SD-WP-SW SD_CD#
31 XD-D6 SD-CD-SW 36
XD_SD_D7 32 XD-D7

4in1-GND 13
4in1-GND 22
4in1-GND 37
4in1-GND 38

TAITW_R015-211-LM-A_NR

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 29 of 50
5 4 3 2 1
 5 4 3 2 1

+1.5V to +1.05V Transfer +3V 1 RT1

4.7K_0402_5%
2 USB30_POK
Close to U102.D7 Close to U102.P13
+1.5V +3V +1.5V +1.05V +3VA +3VA

10U_0603_6.3V6M
UT2 1A
CT2
1 5 VIN VOUT 3
9 VIN VOUT 4
6 8P_0402_50V8D 8P_0402_50V8D
USB30_POK VCNTL CT6 CT9
7 POK FB 2 2 1
2 RT2 1 1 1 @ 1 1 1 @

1
0.1U_0402_16V7K 0.1U_0402_16V7K

10U_0603_6.3V6M
8 1 10K_0402_1%
+3V EN GND CT4 CT7

CT3
1 U3RXDN1_R 1 @ 2 U3RXDN1_R_L U3TXDN1 1 @ 2 U3TXDN1_L
APL5930KAI-TRG_SO8 RT3 RT4 0_0402_5% RT5 0_0402_5%
2 CT5 2 2 2 CT8 2 2 LT1 LT2
32.4K_0402_1%
Vout=0.8(1+10K/32.4K) 0.01U_0402_25V7K 0.01U_0402_25V7K 4 3 4 3

2
2 4 3 4 3
D 1.042 ~ 1.0469 ~ 1.0519V D
Spec: 0.9975 ~ 1.05 ~ 1.1025 1 2 1 2
1 2 1 2
WCM-2012HS-670T WCM-2012HS-670T
U3RXDP1_R 1 @ 2 U3RXDP1_R_L U3TXDP1 1 @ 2 U3TXDP1_L
+3VALW to +3V Transfer +3VALW RT6 0_0402_5% RT7 0_0402_5%

+3VALW Follow Vendor recommend.

2

2
RT37 CT42 +3V +1.05V
100K_0402_5% CT41 0.1U_0402_16V4Z +3VA
0.1U_0402_16V7K 1 @ 2

3
1 S
RT9 0_0402_5%
1

G
1 2 2 QT1 LT4
RT38 47K_0402_5% 2 AO3413_SOT23 USB20_DN1_R 1 2 USB20_DN1_L
27 USB20_DN1_R 1 2
CT43 D
1
1

D 0.01U_0402_25V7K
2 USB20_DP1_R 4 3 USB20_DP1_L
33,41 SYSON 1 27 USB20_DP1_R 4 3
G
+3V
QT2 S 2N7002_SOT23-3 WCM-2012-900T_0805

D10

H11
E11
E12

K11
K12

P13
3

F13
F14

L10

L13
L14
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
UT1 @

P3

E3
E4
F3

L9

L5

L8
1 2
+3V & +1.05V has power sequence timing: RT10 0_0402_5%
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10
+USB_VCCB
18 CLK_USB30 B2 PECLKP W=80mils
18 CLK_USB30# B1 PECLKN
+3V +3VA 4.7U_0805_10V4Z 0.1U_0402_16V4Z
+3V:200mA U3TXDP2 B6
18 PCIE_PRX_C_USBTX_P6
CT29 2 1 0.1U_0402_16V7K PCIE_PRX_USBTX_P6 D2 PETXP 1
18 PCIE_PRX_C_USBTX_N6
CT30 2 1 0.1U_0402_16V7K PCIE_PRX_USBTX_N6 D1 PETXN +1.05V:800mA U3TXDN2 A6 1 1 1
N8 CT26 + CT31 CT27 CT28
LT3 U2DM2
18 PCIE_PTX_C_USBRX_P6 F2 PERXP
1 2 18 PCIE_PTX_C_USBRX_N6 F1 PERXN U2DP2 P8
BLM18AG601SN1D_2P 2 2 2 2
C
U3RXDP2 B8 C
1
A8 220U_6.3V_M_R15 1000P_0402_50V7K
CT25 U3RXDN2
10U_0603_6.3V6M H2
2 5,21,27,28,29,33,34 PLT_RST# PERSTB
RT12 10_0402_5% 2 USB30_WAKE# K1 G14 OCI2# 1 RT13 2 10K_0402_5% +3V
19,28 EC_SWI# PEWAKEB OCI2B
K2 H13 OCL1#
18 CLKREQ_USB30# PECREQB OCI1B
+3V RT15 1 2 10K_0402_5%
RT16 @1 2 100_0402_1% J2
RT17 AUXDET
+3V 1 2 10K_0402_5% J1 PSEL PPON2 H14 JUSB30 @
USB30_SMI_R H1 J14 USB30PWRON U3TXDP1_L 9
USB30_SMI#_IC 0_0402_5% USB30_SMI#_R SMI PPON1 SSTX+
1 RT18 2 P4 SMIB +USB_VCCB 1 VBUS
U3TXDN1_L 8
+1.05V RT391 USB20_DP1_L SSTX-
+3V 2 10K_0402_5% P5 PONRSTB 3 D+
UPD720200A: B10 U3TX_C_DP1 CT32 1 2 0.1U_0402_16V7K U3TXDP1 7
1SS355TE-17_SOD323-2 U3TXDP1 USB20_DN1_L GND
SMIB Low active 2 D- GND 10
1 1 2 2 SPI_CLK_USB M2 A10 U3TX_C_DN1 CT33 1 2 0.1U_0402_16V7K U3TXDN1 U3RXDP1_R_L 6 11
SPISCK U3TXDN1 SSRX+ GND
1U_0603_10V6K

DT3 SPI_CS_USB# N2 N10 U2D_DN1 4 12

SPISCB U2DM1 U2D_DN1 27 GND GND
CT16 0.1U_0402_16V7K

CT17 0.01U_0402_25V7K

CT18 0.1U_0402_16V7K

CT19 0.01U_0402_25V7K

CT20 0.01U_0402_25V7K

CT21 0.1U_0402_16V7K

CT22 0.01U_0402_25V7K

CT23 0.01U_0402_25V7K

CT24 0.01U_0402_25V7K

CT44

1 2 1 2 2 1 2 2 2 1 SPI_SI_USB N1 U3RXDN1_R_L 5 13 USB_GND

USB30_SMI#_IC SPI_SO_USB SPISI U2D_DP1 SSRX- GND
For UPD720200: M1 SPISO U2DP1 P10 U2D_DP1 27

CT45
SMI high active B12 U3RXDP1_R ACON_TARA4-9K1311 2
U3RXDP1 0_0603_5% 0_0603_5%
1

2 1 2 1 1 2 1 1 1 D 2 U3RXDN1_R RT42
K13 GND U3RXDN1 A12
Q57 2 1 @ 2 USB30_SMI_R K14 GND
RT41
1

.1U_0402_16V7K
@ G RT21 0_0402_5% J13

2
GND
S 2N7002_SOT23-3
3

1 @ 2 USB30_SMI#_R
RT40 0_0402_5% P12 RT22 1 2 1.6K_0402_1%
RREF
U2AVSS N12
C14 GND
U2PVSS N11
+3V D6
U3AVSS
N14 XT1
CLK_48M_USB M14 DT2
XT2 U3TXDP1_L 1 1 109 U3TXDP1_L
DT1
1
CT10 0.01U_0402_25V7K

CT11 0.01U_0402_25V7K

CT12 0.01U_0402_25V7K

CT13 0.01U_0402_25V7K

CT14 0.1U_0402_16V7K

CT15 0.01U_0402_25V7K

2 2 2 2 1 2 U3TXDN1_L 2 2 98 U3TXDN1_L
B B
RT26 P6 USB20_DP1_L 2
100_0402_5% CSEL CSEL=0Κ24MHz XTAL 2
1 1 U3RXDP1_R_L 4 4 77 U3RXDP1_R_L
USB20_DN1_L 3
1 1 1 1 2 1 CSEL=1Κ48MHz Clock P14
3 U3RXDN1_R_L 5 5 66 U3RXDN1_R_L
2

YT1 GND
A1 GND GND P11 AZC199-02SPR7G_SOT23-3
2

2
0_0402_5%

0_0402_5%

1 2 A2 GND GND P9 3 3
A3 GND GND P7
24MHZ_12PF_X5H024000DC1H A4 P2 8
GND GND
12P_0402_50V8J

12P_0402_50V8J

A5 GND GND P1
2

1 1 A7 N13 Change ESD Diode for EMI request YSCLAMP0524P_SLP2510P8-10-9

RT281

RT291

GND GND
0_0402_5%
RT30

@ A9 N9
GND GND
CT37

CT38

A11 GND GND N7

A13 GND GND N3
@ 2 2
A14 M13
1

GND GND
B3 GND GND M12
+3V B4 M11
GND GND
B5 GND GND M10
B7 M9 @
GND GND USB30PWRON RT11 1
B9 GND GND M8 2USB_CHG_EN# USB_CHG_EN# 27,33
B11 M7 0_0402_5%
GND GND
B13 GND GND M6
B14 GND GND M5
C1 M4
Place as close as possibile to C2
GND
GND
GND
GND M3 +3V
C3 L12
UU102.N14 and UU102.M14 C10
GND
GND
GND
GND L11
C11 GND GND L7
L6 10K_0402_5%
GND
+3V 2 RT43 1

5
QT3B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

USB30_SMI#_IC 4 3 USB30_SMI# 22
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

2
2N7002DW-T/R7_SOT363-6 QT3A

+3V OCL1# 1 6 USB_OC#1 21,27,33

A 10K_0402_5% 2N7002DW-T/R7_SOT363-6 A
UPD720200AF1-DAP-SSA-A +3V 2 RT44 1
2

RT32 RT33
47K_0402_5% 10K_0402_5% SPI_CLK_USB 1 RT34 2
0_0402_5%
@ 2
1

UT4
35mA CT39 CT40
2010/10/05 Add Level shift to avoid +3V leakage from +3VALW_PCH
Close to UU37.6
SPI_CS_USB# 1 8 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K
SPI_SO_USB CS# VCC 1
2 7 1 RT35 210K_0402_5%
3
SO
WP#
HOLD#
SCLK 6 SPI_CLK_USB_R
SPI_SI_USB
@ Security Classification Compal Secret Data Compal Electronics, Inc.
4 GND SI 5 Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

MX25L5121EMC-20G SOP 8P SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI_CLK_USB_R 1 RT36 2 SPI_CLK_USB Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0_0402_5% Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 30 of 50
5 4 3 2 1
 5 4 3 2 1

RA2
Speaker Connector
+PVDD1 600 mA 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VALW placement near Audio Codec
1 1 0_0603_5% 1 1
CA57 CA44 RA13
CA56 CA43 SPKL+ 2 1 SPK_L1
0_0603_5% 1
RA20 2 2 2 2 @
+3VS 2 1 0.1U_0402_16V4Z +DVDD_IO 10U_0805_10V6K 10U_0805_10V6K CA19 DA7
FBMH1608HM601-T 10U_0805_10V6K 2 2
2 CA24
1 1 place close to chip 1
CA2 CA1 1 1 1U_0402_6.3V6K 3
0.1U_0402_16V4Z @ @
10U_0805_10V6K +3VS_DVDD CA61 CA20 1 AZ5125-02S_SOT23-3
D place close to chip 2 2
D
RA14 10U_0805_10V6K JSPK
2 SPKL- 2 SPK_L2 SPK_L1
2 1 1 1
RA1 0.1U_0402_16V4Z 0_0603_5% SPK_L2 2
RA15 SPK_R1 2
2 1 35 mA 3
Delete resistor and +3VS
FBMH1608HM601-T 1 1 SPKR+ 2 1 SPK_R1 SPK_R2 4
3
4
+AVDD 0_0603_5% 1
Capcitence for layout concern CA8 CA7 @ DA6 ACES_85204-0400N
10U_0805_10V6K RA3 CA25 2 @
2011/03/10 2 2 68 mA 10U_0805_10V6K 0.1U_0402_16V4Z 2
0_0603_5%
1 +5VALW 10U_0805_10V6K
2 2
CA27
1
3
1 1U_0402_6.3V6K
Ext. Mic/LINE IN @ @ AZ5125-02S_SOT23-3

39

46

25

38
1 1 1 1

9
UA1 CA3 CA4 CA5 CA6 CA26 1
MIC1_LINE1_R_L 1 2 RA16 10U_0805_10V6K

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
CA9 1U_0402_6.3V6K SPKR- 2 SPK_R2
2 1
2 2 2 2 0_0603_5%
place close to chip
MIC1_LINE1_R_R 1 2 10U_0805_10V6K 0.1U_0402_16V4Z
CA10 1U_0402_6.3V6K

CA40
23
24
LINE1_L
LINE1_R
SPK_OUT_L+
SPK_OUT_L-
40
41
SPKL+
SPKL-
Subwoofer Sleep Music Switch Circuit
32 AMP_SUB_S3
2 1 CA30 1U_0402_6.3V6K AMP_SUB_S3
CA41 4.7U_0603_6.3V6K Subwoofer 1 2 14 45 SPKR+ +5VALW
LINE2_L SPK_OUT_R+ SPKR-
2 1 15 44
4.7U_0603_6.3V6K
32 AMP_SUB 1 2
LINE2_R SPK_OUT_R- 0.01U_0402_16V4Z Add circuit to add
CA31 1U_0402_6.3V6K 21 32 RA4 75_0402_1% 2 2
22
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R 33
HP_L 26 AC reference voltage
SW_MIC1_L @ CA21 2 1 SW_MIC1_C_L RA5 75_0402_1% CA36 CA37
HP_R 26
C SW_MIC1_R @ CA22 2
4.7U_0402_6.3V6M
SW_MIC1_C_R
16 MIC2_L 1 1
1U_0402_6.3V4Z
to UA2 C
1 17 MIC2_R
4.7U_0402_6.3V6M
SYNC 10 AZ_SYNC_HD
AZ_SYNC_HD 17 2011/03/10

11
INT_MIC_DATA AZ_BITCLK_HD UA2
14 INT_MIC_DATA 2 GPIO0/DMIC_DATA BCLK 6 AZ_BITCLK_HD 17
1 10 SW_MIC1_R

EP
INT_MIC_CLK_R SW_MIC1_L V+ NO2
3 GPIO1/DMIC_CLK 2 NO1 COM2 9MIC1_LINE1_R_R_SW
5 AZ_SDOUT_HD AZ_SDOUT_HD 17
MONO_IN SDATA_OUT MIC1_LINE1_R_L_SW SUSP#
32 MONO_IN 3 COM1 IN2 8
EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1 4 7
32,33 EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD 17 13,17,33,36,41,43 SUSP# IN1 NC2
RA6 33_0402_5% 5 6
AMP_SUB_S3 2 NC1 GND CA33 1U_0402_6.3V6K
For EMI 1
AZ_RST_HD# 11 47 EAPD NLAS4684MNR2G 1 2 AMP_SUB_S3
17 AZ_RST_HD# RESET# EAPD EAPD 33
CA32 1U_0402_6.3V6K
SPDIFO 48
RA44 CA11 1 2 MONO_IN 12
100K_0402_5% 0.01U_0402_25V7K CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
@ @

1
SENSE_A 13 SENSE A RA888 RA890
MIC2_VREFO 29
For EMI 18 SENSE B 10K_0402_1% 10K_0402_1%
30 +MIC1_VREFO_R CA23 10U_0805_10V6K +5VALW
RA41 MIC1_VREFO_R
1 2 36 28 1 2

2
INT_MIC_CLK_R CA15 CBP LDO_CAP
14 INT_MIC_CLK
FBMA-10-100505-301T 2.2U_0603_6.3V6K 35 27 AC_VREF MIC1_LINE1_R_L 2 1MIC1_LINE1_R_L_SW MIC1_LINE1_R_R_SW 2 1 MIC1_LINE1_R_R
CBN VREF 4.7U_0603_6.3V6K CA38 RA40 CA39 4.7U_0603_6.3V6K
CA47 1 2 0.1U_0603_50V7K 1 +MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% 0_0402_5%
MIC1_VREFO_L JDREF

1
CA28 1 2
CA48 1 2 0.1U_0603_50V7K 27P_0402_50V8J 43 34 CPVEE 1 2 RA889 CA13 RA891
@ PVSS2 CPVEE CA14 2.2U_0603_6.3V6K CA17 @ CA16 8.2K_0402_5% 8.2K_0402_5%
42 PVSS1 1 2
B CA49 1 2 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26
2 1 0.1U_0402_16V4Z
7 37

2
CA50 1 DVSS1 AVSS2
2 0.1U_0603_50V7K 0.1U_0402_16V4Z 2.2U_0603_6.3V6K
+5VALW ALC269Q-VB5-GR _QFN48_7X7
CA51 1 2 0.1U_0603_50V7K place close to chip
DGND AGND Ext.MIC/LINE IN JACK
2 1 For EMI
RA18 10_0603_5% RA42
100K_0402_5% RA33 2 RA31 1 +MIC1_VREFO_R
@ @ CA29 1K_0402_5% 2.2K_0402_5%
AZ_BITCLK_HD 2 1 1 2 @ MIC1_LINE1_R_R 2 1 MIC1_R 26
RA18 Close to UA1 for reduce ripple noise EC_MUTE# RA22 2 1 4.7K_0402_5% 10_0402_5% RA17
10P_0402_50V8J
on 5V power plance MIC1_LINE1_R_L 2 1 MIC1_L 26
(Need confirm with EMI again) 1K_0402_5%
RA32 2 RA29 1 +MIC1_VREFO_L
2.2K_0402_5%

MIC_SENSE
RA43 100K_0402_5%
Sense Pin Impedance Codec Signals Function +3VL

6
2N7002DW-T/R7_SOT363-6
place close to chip QA1A
39.2K PORT-I (PIN 32, 33) Headphone out RA28 100K_0402_5%
33 SM_SENSE# 2
MIC_SENSE 2 1 SENSE_A

3
20K PORT-B (PIN 21, 22) Ext. MIC RA10 20K_0402_1%

1
SENSE A QA1B

A 10K PORT-C (PIN 23, 24) 2N7002DW-T/R7_SOT363-6

5 BACK_SENSE 26 A

26 NBA_PLUG

4
5.1K (PIN 48) RA21 39.2K_0402_1%

39.2K PORT-E (PIN 14, 15) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
SENSE B 20K PORT-F (PIN 16, 17) SCHEMATICS,MB A7191
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B

WWW.AliSaler.Com
10K PORT-H (PIN 20) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4019B7
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 31 of 50
5 4 3 2 1
 5 4 3 2 1

IR Emitter Connector APA3011 Subwoofer Amplifier

DIS@
R150 1 2 0_0402_5% +5VALW

L57 @ 1 1
4 3 USB20_P5_R CA67 CA68
21 USB20_P5 4 3 0.1U_0402_16V4Z
10U_0805_10V6K
USB20_N5_R 2 2 INTSPK_SUB+
21 USB20_N5 1 1 2 2
CA69 UA8
D WCM-2012-900T_0805 2.2N_0603_100V7K 6 1 EC_MUTE# 31,33 D
VDD SHUTDOWN#
1 2 1 2
DIS@ RA48 33K_0402_1% 3 5 INTSPK_SUB+
R144 1 IN+ Vo+
2 0_0402_5%
1 2 4 8 INTSPK_SUB-
RA50 IN- Vo-
CA70 RA49 39K_0402_1%
31 AMP_SUB 1 2 1 2 1 2 2
BYPASS GND 7
8.87K_0402_1% CA71 0.022U_0402_25V7K 9
GND

0.47U_0603_16V7K
0.47U_0603_16V7K

0.1U_0402_16V4Z
1

1
CA73 RA51 @ APA3011XA-TRL_MSOP8
JIR @ 31 AMP_SUB_S3 1 2 2 1 CA72 CA74
+5VS 2 DIS@ 1 +IR_VCC 1 12K_0402_1%

2
R151 0_0603_5% USB20_P5_R 1 0.47U_0603_16V7K 2
2 2
USB20_N5_R 3 5
DIS@ 3 GND
For ESD 4 4 GND 6
Add RC for S3 gain
C399
0.1U_0402_16V4Z ACES_87213-0400G Modify Sub woofer gain & Frequency
D10 2011/03/02 RA50Κbecome 8.87k
USB20_N5_R 2 2
1 1 It will has 17.43db Gain & Frequency between 38.16hz~500hz
USB20_P5_R 3 3

AZC199-02SPR7G_SOT23-3 Sub-woofer Conn. DA3 @ PJDLC05_SOT23-3

2
1
3
JSUB @
INTSPK_SUB+ RA7 1 2 0_0603_5% SPK_SUB+ 1 3
INTSPK_SUB- RA8 1 NC1
1 2 0_0603_5% SPK_SUB- 2 2 NC2 4
C C
ACES_85204-0200N

+3VS

Beep sound Change Page

BlueTooth Interface
EC Beep C396
2

33 EC_BEEP# 1
RA23
2 2010/12/14 0.1U_0402_16V7K

2
47K_0402_5% BT@ @

3
1 S
R398
G
22,27 BT_ON# 1 2 2 0_0603_5%
R362 47K_0402_5% 1
PCI Beep CA35 BT@ C390 D Q28 BT@

1
RA11 0.01U_0402_25V7K AO3413_SOT23
17 PCH_SPKR 1 2 1 2 MONO_IN 31
47K_0402_5% BT@
0.1U_0402_16V4Z 2
+BT_VCC

Change value for Beep (MAX=200mA)

by A51 demand. +BT_VCC
2

2010/08/31 2
RA19 CA34 1
4.7K_0402_5% 100P_0402_50V8J 1 C496
C495 BT@
1 BT@ 0.1U_0402_16V4Z
Change to AGND for
1

4.7U_0805_10V4Z 2
high frequency noise issue 2 Bluetooth Connector
B JBT @ B

1 1
2 2
21 USB20_P4 3 3
21 USB20_N4 4 4
22 BT_RST# BT@ R445 1 2 0_0402_5% BT_RESET# 5 7
5 G1
1 22 BT_DET# 6 6 G2 8
C499 BT@ ACES_87213-0600G

0.1U_0402_16V4Z 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 32 of 50
5 4 3 2 1
 5 4 3 2 1

+3VL R737
+3VL 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 H_PROCHOT# 5,38
44 VR_HOT#
1 1 1 1 2 2 C442

3
C436 1 2

1
C437 C438 C439 C440 C441
For EMI 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z C518
2 2 2 2 1 1 H_PROCHOT#_EC Q6B 47P_0402_50V8J
5

2
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K 2N7002DW-T/R7_SOT363-6

22
33
96

67
9
CLK_PCI_EC U19

4
VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1
R377
10_0402_5% BATT_TEMPA 1 2
@ GATEA20 1 21 KB_LED C445 100P_0402_50V8J
22 GATEA20 GATEA20/GPIO00 PWM0/GPIO0F KB_LED 34
KB_RST# 2 23 EC_BEEP# ACIN_D 1 2
22 KB_RST# EC_BEEP# 32
2
D KBRST#/GPIO01 BEEP#/PWM1/GPIO10 D
1 SERIRQ 3 PWM Output 26 FANPWM C446 100P_0402_50V8J
17,34 SERIRQ SERIRQ# FANPWM0/GPIO12 FANPWM 5
C443 LPC_FRAME# 4 27 ACOFF
17,34 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF 39
22P_0402_50V8J LPC_AD3 5
17,34 LPC_AD3 LPC_AD3/LAD3
@ LPC_AD2 7
2 17,34 LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA
17,34 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA 38
LPC_AD0 10 64 TMPTU1_SXP
17,34 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39 +3VS
LPC & MISC 65 ADP_I TV tuner
ADP_I/AD2/GPI3A ADP_I 38,39
CLK_PCI_EC 12 66 ADP_V
21 CLK_PCI_EC CLK_PCI_EC/PCICLK AD3/GPI3B ADP_V 39 temperature
PLT_RST# 13 AD Input 75 TMPTU2_SXP
5,21,27,28,29,30,34 PLT_RST# PCIRST#/GPIO05 AD4/GPI42
ECRST# 37 76 HDPACT R754 10K_0402_5%
+3VL R378 EC_SCI# EC_RST#/ECRST# AD5/GPI43 HDPACT 34 TMPTU1_SXP
22 EC_SCI# 20 EC_SCI#/GPIO0E 1 2
47K_0402_5% HDPLOCK 38
34 HDPLOCK CLKRUN#/GPIO1D
2 1 ECRST# 68 R757 10K_0402_5%
DAC_BRIG/DA0/GPO3C TMPTU2_SXP
EN_DFAN1/DA1/GPO3D 70 1 2
2 1 DA Output 71 IREF
IREF/DA2/GPO3E IREF 39
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ R758 10K_0402_5%
KSI0/GPIO30 DA3/GPO3F CHGVADJ 39
KSI1 56 H_PROCHOT#_EC 1 2
KSI2 KSI1/GPIO31 @
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_MUTE# 31,32 +3VL
KSI4 59 84 USB_EN#
KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_EN# 26
KSI5 60 85 CAP_INT#
KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C H_PROCHOT#_EC CAP_INT# 35 CEC_INT#
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 2 1
KSI7 62 87 TP_CLK R53 100K_0402_5%
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 35
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 35
KSO1 40 CAP_INT# 1 @ 2
KSO2 KSO1/GPIO21 R172 4.7K_0402_5%
41 KSO2/GPIO22
KSO3 42 97 VGATE
KSO3/GPIO23 SDICS#/GPXIOA00 VGATE 19,44
KSO4 43 98 WOL_EN +5VS
KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 WOL_EN 28
KSO5 PWRME_CTRL#
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/SDIMOSI/GPXIOA02 99
LID_SW#
PWRME_CTRL# 17
45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 LID_SW# 34
KSO7 46 SPI Device I/F TP_CLK 1 2
KSO8 KSO7/GPIO27 R379 4.7K_0402_5%
47 KSO8/GPIO28
KSO9 48 119 EC_SI_SPI_SO TP_DATA 1 2
C KSI[0..7] KSO9/GPIO29 SPIDI/MISO EC_SI_SPI_SO 34 C
KSO10 49 120 EC_SO_SPI_SI R381 4.7K_0402_5%
17,34,35 KSI[0..7] KSO10/GPIO2A SPIDO/MOSI EC_SO_SPI_SI 34
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 34
KSO12 51 128 SPI_CS#
34,35 KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# 34
KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73 CIR_IN
RP7 KSO16 KSO15/GPIO2F GPIO40 EC_PECI
81 KSO16/GPIO48 H_PECI/GPIO41 74
+3VL 1 8 EC_SMB_CK1 KSO17 82 GPIO 89 FSTCHG
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG 39
2 7 EC_SMB_DA1 90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# 35
+3VS 3 6 EC_SMB_CK2 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 34
4 5 EC_SMB_DA2 EC_SMB_CK1 77 92 BATT_CHG_LOW_LED#
16,38 EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 35
EC_SMB_DA1 78 93 PWR_ON_LED# SYSON 1 2
16,38 EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 PWR_ON_LED# 35
2.2K_0804_8P4R_5% EC_SMB_CK2 79 95 SYSON R5 4.7K_0402_5%
13,18,34,35 EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON 30,41
EC_SMB_DA2 80 121 VR_ON
13,18,34,35 EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 44
127 ACIN_D
AC_IN/GPIO59
SM Bus
PM_SLP_S3# 6 100 PCH_RSMRST#
19 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# 19
R1442 SLP_S5# 14 101 EC_LID_OUT# R341 330K_0402_5%
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 18
0_0402_5% EC_SMI# 15 102 EC_ON +3VL 1 2
22 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_ON 17,35
27,30 USB_CHG_EN# 1 2USB_CHG_EN#_R USB_CHG_EN#_R 16 GPIO0A EC_SWI#/GPXIOA06 103 TP_LED
TP_LED 35
ESB_CK 17 104 PM_PWROK
35 ESB_CK GPIO0B ICH_PWROK/GPXIOA07 PM_PWROK 5,19
ESB_DAT 18 GPIO 105 BKOFF# ACIN_D 2 1
35 ESB_DAT GPIO0C BKOFF#/GPXIOA08 BKOFF# 14 ACIN 13,19,35,39
PCH_SUSPWRDN 19 GPO RF_OFF#/GPXIOA09 106 HDPINT
19 PCH_SUSPWRDN SUS_PWR_DN_ACK/GPIO0D HDPINT 34
EAPD 25 107 CAP_RST# D21 RB751V40_SC76-2
31 EAPD INVT_PWM/PWM2/GPIO11 GPXIOA10 CAP_RST# 35
@ FAN_SPEED1 28 108 SA_PGOOD
5 FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 SA_PGOOD 42
1 2 PLT_RST# SM_SENSE# 29
31 SM_SENSE# FANFB1/GPIO15
C819 1U_0402_6.3V6K E51_TXD 30
27 E51_TXD EC_TX/GPIO16
E51_RXD 31 110 CEC_INT# R359 330K_0402_5%
27 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 CEC_INT# 16
@ ON/OFFBTN# 32 112 EC_ENBKL +3VL 1 2
35 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXIOD02 EC_ENBKL 14
1 2 SUSP# PWR_SUSP_LED# 34 114 USB_OC#1 @
35 PWR_SUSP_LED# SUSP_LED#/GPIO19 EAPD/GPXIOD03 USB_OC#1 21,27,30
C820 180P_0402_50V8J NUM_LED# 36 GPI EC_THERM#/GPXIOD04 115 OTP_HW# @
34 NUM_LED# NUM_LED#/GPIO1A
116 SUSP# OTP_HW# 2 1
SUSP#/GPXIOD05 SUSP# 13,17,31,36,41,43 VS_ON 38,40
B 117 PBTN_OUT# B
PBTN_OUT#/GPXIOD06 PBTN_OUT# 19
118 USB_OC#0_R D26 RB751V40_SC76-2
CRY1 @ R991 0_0402_5% CRY1_EC EC_PME#/GPXIOD07
122 XCLK1
CRY2 @ R992 0_0402_5% CRY2_EC 123 124 +EC_V18R
R990 0_0402_5% XCLK0 V18R
Close to EC 19 CLK_EC
AGND
GND
GND
GND
GND
GND

C448 SUSP# R423 2 1 10K_0402_5%

1

1 4.7U_0805_10V4Z
R270 KB930QF-A1_LQFP128_14X14 VR_ON R462 2 1 10K_0402_5%
11
24
35
94
113

69

100K_0402_5% C1206
20P_0402_50V8J
2
2

+3VALW @

2
C818
1
CIR
+5VL
5

U44 0.1U_0402_16V4Z
1 Co-lay KB9012 with KB930
P

19 PM_SLP_S5# IN1

2
4 SLP_S5#
O USB_OC#0_R
19 PM_SLP_S4# 2 IN2 2 930@ 1 USB_OC#0 21,26
R748
G

R741 0_0402_5% 10K_0402_5%

@ SN74AHC1G08DCKR_SC70-5 R389
3

CRY1 1 2 CRY2 1 9012@ 2 H_PECI

1
R475 43_0402_1% U45
10M_0402_5% CIR_IN 1
@ Vout
1 2
R446 0_0402_5% EC_PECI R461 1 930@ 2 43_0402_1% +5VL 1 CIR@ 2 +5VL_CIR 2
H_PECI 5 VCC
R750 100_0805_5%
For Cost reduction need test 1 1 3 GND
R743 1 9012@ 2 0_0402_5% USB_OC#0 C783
1

A C449 @ @ @ C450 U19 4.7U_0805_10V4Z 4 A

GND
18P_0402_50V8J

Y4 CIR@
18P_0402_50V8J
OSC

OSC

2 2 IRM-V538/TR1
CIR@
1 2 E51_TXD
R342 100K_0402_5%
NC

NC

KB930QF-A1_LQFP128_14X14
9012@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
32.768KHZ_12.5PF_Q13MC14610002
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191

WWW.AliSaler.Com
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 33 of 50
5 4 3 2 1
 1 2 3 4 5 6 7 8

Place the PAD under DDR DIMM.

SPI Flash (256KB) Lid SW LPC Debug Port
2 @ 1 +3VS H7 @
+3VL +3VALW
R543 0_0402_5%
2 1 +3VL 6 5
R565 0_0402_5%
1 20mils
C451 U22 930@ 7 4
17,33 SERIRQ PLT_RST# 5,21,27,28,29,30,33

1
930@ 8 4
0.1U_0402_16V4Z VCC VSS R383
2
3 W 47K_0402_5% 17,33 LPC_AD3 8 3 LPC_AD2 17,33
U21
A 7 APX9132ATI-TRL_SOT23-3 A

2
HOLD
17,33 LPC_AD1 9 2 LPC_AD0 17,33
SPI_CS# 1 2 3

GND
33 SPI_CS# S VDD VOUT LID_SW# 33
SPI_CLK 6 10 1
33 SPI_CLK C 17,33 LPC_FRAME# CLK_PCI_DDR 21
1 1

1
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
33 EC_SO_SPI_SI D Q EC_SI_SPI_SO 33

2
C453 C452
W25X10BVSNIG_SO8 0.1U_0402_16V4Z 10P_0402_50V8J DEBUG_PAD R393
2 2 22_0402_5%
For EMI @

1
2
930@ 930@
SPI_CLK 1 2 1 2 C457
R394 100_0402_5% C454 100P_0402_50V8J 22P_0402_50V8J
1 @

For EMI

Keyboard LED JBLG G-Sensor

1 1 +KBV_LED
Q38 2
AO3413_SOT23 2 RG2 @ UG1
+5VS 1 2 3 3
@ R993 0_0603_5% KBL@ 4 +3VS 2 1 +3VS_HDP +3VS_HDP 2 3 VOUTX CG1 1 2 0.033U_0402_16V7K
B
4 Vdd1 Voutx VOUTY CG2 0.033U_0402_16V7K B
GND 5 12 Vdd2 Vouty 5 1 2
S

+3VS 1 2 3 1 +KBV_LED 6 0_0603_5% 7 VOUTZ CG3 1 2 0.033U_0402_16V7K

KBL@ R994 0_0603_5% GND Voutz
1
1

ACES_85201-0405N SELF_TEST 4 10
R587 C836 @ +5VS +3VS_HDP ST NC1
G

6 11
2

10K_0402_5% 0.1U_0402_16V4Z DG1 RB751V40_SC76-2 PD NC2

8 FS NC3 14
KBL@ 2 @
1 2 NC4 15
2 2 16
2

CG12 UG3 NC5

For EMI
1U_0402_6.3V6K CG13 +3VS_HDP 9 1
1U_0402_6.3V6K Rev GND1
Close to JKB 1 VIN VOUT 5 GND2 13
1

D 1 1
2 Q52 KSO16 1 2 2 TSH352TR LGA 16P
33 KB_LED GND CG14
G 2N7002_SOT23-3 C401 100P_0402_50V8J SA00004GB00
S KBL@ KSO17 1 2 3 4 2 1
3

C402 100P_0402_50V8J SHDN# BP

KSO2 1 2 0.22U_0402_6.3V4K
Place UG1 on TOP Layer
C404 100P_0402_50V8J G9191-330T1U_SOT23-5
KSO1
Notice: KB Connector Pin Definition 1
C405
2
100P_0402_50V8J
Reversed with KB Membrane Pin Definition KSO0 1 2
C406 100P_0402_50V8J
KSO4 1 2
KEYBOARD CONN. KSO3
C407
1
100P_0402_50V8J
2
UG5

C408 100P_0402_50V8J 1 11 HDPACT 33

13,18,33,35 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
KSO5 1 2

2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] 17,33,35
KSO14 1 2 SELF_TEST 2 12 RG9
C KSO[0..17] C410 100P_0402_50V8J P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5% C
KSO[0..17] 33,35
KSO6 1 2
C411 100P_0402_50V8J +3VS_HDP RG3 2 1 3 13

1
KSO7 4.7K_0402_5% RESET# P1_4/TXD0
1 2
JKB C412 100P_0402_50V8J
JKB34 1 2 +3VS KSO13 1 2 RG4 2 1GXOUT 4 14 HDPLOCK 33
34 KSO16 R372 300_0402_5% C413 100P_0402_50V8J 4.7K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
33 KSO8 RG10 47K_0402_5%
32 1 2
KSO17 C415 100P_0402_50V8J 5 15 VOUTZ 2 1
31 KSO9 VSS/AVSS P1_2/KI2#/AN10/CMP0_2
30 1 2
C416 100P_0402_50V8J
29 KSO2 KSO10 RG5
28 1 2 2 1GXIN 6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP
KSO1 C417 100P_0402_50V8J 4.7K_0402_5%
27 KSO0 KSO11
26 1 2 1
KSO4 C418 100P_0402_50V8J 7 17 VOUTX CG6
25 KSO3 KSO12 VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z
24 1 2
KSO5 C419 100P_0402_50V8J
23 KSO14 KSO15 RG6 2
22 1 2 2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY
KSO6 C420 100P_0402_50V8J
21 KSO7 KSI7
20 1 2
KSO13 C421 100P_0402_50V8J HDPINT RG7 2 1 1K_0402_5% 9 19
19 KSO8 KSI2 33 HDPINT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
18 1 2
KSO9 C422 100P_0402_50V8J
17 KSO10 KSI3
16 1 2 1 1 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 13,18,33,35
KSO11 C423 100P_0402_50V8J CG8
15 KSO12 KSI4 CG7
14 1 2
KSO15 C424 100P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z R5F211B4D34SP
13 KSI7 KSI0 2 2
12 1 2
KSI2 C425 100P_0402_50V8J
D 11 D
KSI3 KSI5 1 2
10 KSI4 C427 100P_0402_50V8J
9 KSI0 KSI6
8 1 2
KSI5 C429 100P_0402_50V8J
7 KSI6 KSI1
6 1 2
KSI1 C431 100P_0402_50V8J
5
4
JKB4 2 1 +3VS CAPS_LED# 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
CAPS_LED# R376 300_0402_5% C433 100P_0402_50V8J 2010/09/09 2011/09/09 Title
3 CAPS_LED# 33
NUM_LED#
Issued Date Deciphered Date
1 2
2
1
NUM_LED#
NUM_LED# 33
C435 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
ACES_88170-3400 B

WWW.AliSaler.Com 4019B7
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 34 of 50
1 2 3 4 5 6 7 8
 5 4 3 2 1

Power Button 51_ON# 37

Caps Sensor/Light Sensor Conn. Touchpad & Light Pipe Connector

6
For debug JCS
Q7A @
+3VL 2N7002DW-T/R7_SOT363-6 +5VALW 1
SW4 DBG@ 1
17,33 EC_ON 2 +3VL 2 2
1 3 FBMA-11-100505-301T_0402 +3VS 3 JTPL@
3

2
L13 1 2 ESB_DAZ 4 1
33 ESB_DAT

1
R395 R396 L14 1 ESB_CKZ 4 +5VS 1
TOP side 2 4 33 ESB_CK 2 5 5 33 TP_CLK 2 2
10K_0402_5% FBMA-11-100505-301T_0402 CAP_INT# 6 3
33 CAP_INT# 6 33 TP_DATA 3
SMT1-05-A_4P 100K_0402_5% CAP_RST# 7 +3VS 1 R147 2 +3VS_FP 4
6 33 CAP_RST#
5
7 0_0603_5% 1 USB20_N8 4
13,18,33,34 EC_SMB_CK2 8 Finger Printer 21 USB20_N8 5

1
ON/OFFBTN# 8 C484 USB20_P8 5
ON/OFFBTN# 33 13,18,33,34 EC_SMB_DA2 9 9 21 USB20_P8 6 6
10 0.1U_0402_16V4Z TP_LED# 7
SW3 DBG@ 10 FP@ KSI6 7
1 17,33,34 KSI6 8 8
C458 2 KSO0
1 3 11 GND 33,34 KSO0 9 9
D 0.1U_0402_25V6 12 10 D
GND 10

3
BTM side 2 4 @
2
11 GND1
SMT1-05-A_4P ACES_87056-01001-001 2N7002DW-T/R7_SOT363-6 Q7B 12
6
5

GND2
33 TP_LED 5
CVILU_CF20101U0RH-10
For EMI request For EMI D85 FP@

4
+3VS_FP 4 2 USB20_N8
VIN IO1
@ R428 C260 @ USB20_P8 3 1
JPOWER ESB_DAZ IO2 GND
1 2 1 2
PWR_ON_LED# CM1293A-02SR SOT143-4
1 1 100_0402_5% 100P_0402_50V8J
2 2 1 2 +3VALW For ESD
ON/OFFBTN# R22 150_0402_1%
3 3 D83 @ R427 C261 @
4 4 ON/OFFBTN# ESB_CKZ
G1 5 2 1 2 1 2
G2 6 PWR_ON_LED#
1
100_0402_5% 100P_0402_50V8J
3
ACES_85201-0405N
@ YSDA0502C_SOT23-3

Screw Hole
H5 H6 H8 H9 H10 H11 H12 H13
DC-IN LED ACIN 13,19,33,39
WiMAX LED R506
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_3P0
@
H_9P0
@
WIMAX_LED_GND# 1 2 LED_WIMAX# 27

1
2

0_0402_5%

2
@
DC_IN 6 1 R819
+3VS 2 1 6 1 H17 H14 H26 H27
Q209A 10K_0402_5% H_3P3 H_3P3 H_3P6N H_5P0N

5
C 2N7002DW-T/R7_SOT363-6 Q156A @ @ @ @ C
2N7002DW-T/R7_SOT363-6

1
WIMAX_LED_GND# 3 4

Q156B 2N7002DW-T/R7_SOT363-6 MINI CARD -- JET

VGA
H2 H3
H_1P2 H_1P2 H15 H16
@ @ H_3P7 H_3P7
@ @

1
HDD LED SATA_LED# 17
2

CPU
+3VS 2 R404 1 6 1
10K_0402_5% H20 H23 H21 H22
5

Q9A H_4P2 H_4P7 H_4P2x4P7 H_4P2x4P7 MINI CARD -- WLAN

2N7002DW-T/R7_SOT363-6 @ @ @ @
HDD_LED# 3 4 H19

1
H_3P7
Q9B 2N7002DW-T/R7_SOT363-6 @
1 @ 2

1
R50 0_0402_5%

B
PCB Fedical Mark PAD B

FD1 FD2 FD3 FD4

@ @ @ @

LED/B Connector

1
JLED @
ISPD
14 GND 12 12 +3VALW
13 11 +3VS U2 S65R1@ ZZZ
GND 11 WIMAX_LED_GND#
10 10
9 WL_BT_LED#
9 WL_BT_LED# 22
8 DC_IN
8 PWR_ON_LED#
7 7 PWR_ON_LED# 33
6 PWR_SUSP_LED#
6 PWR_SUSP_LED# 33
5 HDD_LED# PCH_HM65-B3 PCB LA-7191P
5 CR_LEDCON#
4 4 CR_LEDCON# 29
3 BATT_FULL_LED#
3 BATT_FULL_LED# 33
2 BATT_CHG_LOW_LED#
2 BATT_CHG_LOW_LED# 33
1 U2 S65R3@ PJP1 45@
1
ACES_85201-1205N

PCH_HM65-B3 PJP1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 35 of 50
5 4 3 2 1
 A B C D E

+5VALW
+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS Unmount below part for cost down plan

0.1U_0402_16V4Z
For ESD 2 2010/12/23
C824
Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS @ +1.5V +1.5VS
1 4.7U_0805_10V4Z

2
4.7U_0805_10V4Z +5VS Vgs=10V,Id=14.5A,Rds=6mohm
1 1 1 1 1 1 R470
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 Q31 @ C463 C464 470_0805_5%

470_0805_5%

470_0805_5%

470_0805_5%
8 1 8 1 For EMI 8 1 @
D S D S D S

2
7 2 7 2 1U_0402_6.3V6K 7 2

1
D S 2 2 R406 D S 2 2 R407 D S 2 2 R408

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 D S 3 6 D S 3 6 D S 3
5 4 5 4 2 2 2 5 4 @
D G 1U_0402_6.3V6K D G C822 C821 C823 D G 1U_0402_6.3V6K

1
1 SI4800BDY_SO8 D 1
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB FDS6676AS_SO8 1 @ 2 +VSB Q190

3 1

3 1

3 1
47K_0402_5% 47K_0402_5% @ @ @ R411 220K_0402_5% SUSP

0.01U_0402_25V7K
0.022U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 1 1 2

6
C466 1 1 1 @

0.1U_0402_25V6
G
C465 R412 Q10A C467 C468 R413 Q11A C469 C470 R414 Q12A S 2N7002_SOT23-3

3
330K_0402_5% Q10B 200K_0402_5% Q11B @ @ 820K_0402_5% @ Q12B
2 2 SUSP 2 2 @ SUSP 2 2 @ SUSP @
2 5 2 5 2 5
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
+3VALW

For S3 CPU Power Saving

2
+5VALW +0.75VS +1.05VS_VCCP
R425
100K_0402_5%

2
R422 R421 R468

1
100K_0402_5% 22_0805_5% 470_0805_5%
0.75VR_EN# 43

1
SUSP
5,9,27,43 SUSP
Q44B

6
42,43 VCCPPWRGD 1 2 0.75VR_EN 5 2N7002DW-T/R7_SOT363-6

6
2 R158 100K_0402_5% 2N7002DW-T/R7_SOT363-6 Q208A 2
Q208B 2N7002DW-T/R7_SOT363-6

4
6
Q44A 5 SUSP 2
2N7002DW-T/R7_SOT363-6 2 Q6A
13,17,31,33,41,43 SUSP#
2N7002DW-T/R7_SOT363-6

1
SUSP 2

1
1
+3VS to +3VS_DGPU +5VS_ODD

+3VS +5VS TO +5VS_ODD

2
+3VALW
R457
470_0805_5%
2

6 1
R433 C491 Vgs=-4.5V,Id=3A,Rds<97mohm +3VS_DGPU
100K_0402_5% 0.1U_0402_16V7K
OPT@ OPT@ Q53A
1

2
1
1

S
R426 Q54
G R104 R458 2 ODD_EN#
3 DGPU_PWR_EN# 1 2 2 0_0805_5% 470_0805_5% 3
DIS@ OPT@ 2N7002DW-T/R7_SOT363-6

1
47K_0402_5% AO3413_SOT23 D +3VS_DGPU +5VS
2
1

3 1
6

OPT@ OPT@
Q206A C492
OPT@ OPT@ 0.01U_0402_25V7K +3VS +5VS
1 Q206B
13,21 DGPU_PWR_EN 2 1
2N7002DW-T/R7_SOT363-6 1 2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN# 2

2
C683 C684 OPT@ C471 Vgs=-4.5V,Id=3A,Rds<97mohm
1

4.7U_0805_10V4Z 1U_0402_6.3V6K R441 0.1U_0402_16V7K

4
@ 2 OPT@ 10K_0402_5%

2
2 1

3
S
R440 Q45 PJ28

2
1
G
22 ODD_EN# 4 3 1 2 2 JUMP_43X79
@ +5VS_ODD

1
47K_0402_5% 2
D

1
Q53B AO3413_SOT23

1
2N7002DW-T/R7_SOT363-6 C217
0.01U_0402_25V7K
1
1
1
C680
C679 1U_0402_6.3V6K
4.7U_0805_10V4Z 2
@ 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019B7
Date: Friday, September 16, 2011 Sheet 36 of 50
A B C D E

WWW.AliSaler.Com
 A B C D

1 2

VIN @ PR1
@PR1
PL1 1K_1206_5%
SINGA_2DW-0005-B03 PF1 SMB3025500YA_2P @PD1
@ PD1
4 DC_IN_S1 1 2 DC_IN_S2 1 2 2 1 N3 1 2
- VIN B+
3 10A_125V_451010MRL RLS4148_LL34-2 @ PR2
@PR2
- 1K_1206_5%

1000P_0402_50V7K

1000P_0402_50V7K

100P_0402_50V8J
100P_0402_50V8J
+ 2
1 2

1
1 1

PC4
PC1

PC2

PC3
+ @ PR3
@ PJP1 1K_1206_5%

1
@PR4
@ PR4 @ PR5
100K_0402_1% 2.2M_0402_5% @ PR38
@PR38
1 2 2 1 511K_0402_1%
VL

2
N1

@PD2
@ PD2

8
RB715F_SOT323-3 @ PU2B
2 5

P
VIN 40 EN0 +
1 7 O
39 ACON 3 - 6 2 1

1
G
2
LM393DG_SO8 @ PR6
@PR6 @PR35
@ PR35

1
PD3 34K_0402_1% 255K_0402_1% @ PC14
@PC14

39

6251VREF
@ PR36
@PR36 1000P_0402_50V7K
RLS4148_LL34-2 @ PC13
@PC13 @ PR7
@PR7 150K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
1

2
@PC16
@ PC16
1000P_0402_50V7K

2
PR8 PR9
PQ4 68_1206_5% 68_1206_5% @PR39
@ PR39

1
D 47K_0402_1%
TP0610K-T1-E3_SOT23-3 @ PQ1 PACIN 39
2 2 1

2
PD4
SSM3K7002FU_SC70-3 G
2 1 N1 3 1
2
BATT+ VS S 2

3
RLS4148_LL34-2
1

1
1

PR10 PC6 N1

1
100K_0402_1% 0.22U_0603_25V7K PC5
2

0.1U_0603_25V7K

8
@PU2A
@ PU2A 2
2

2
+5VALWP
PR11 3

P
1 2 +
35 51_ON# 1 O
22K_0402_1% 2 @ PQ2
@PQ2
-

G
DTC115EUA_SC70-3

3
LM393DG_SO8

4
@ PJ152
2 2 1 1
@ PJ332 JUMP_43X118
+3VALWP 2 2 1 1 +3VALW @ PJ153
@ PJ333 JUMP_43X118 2
3
+1.5VP 2 1 1 +1.5V 3

2 1 (5A,200mils ,Via NO.= 10)

+3VLP 2 1
JUMP_43X39
+3VL
OCP=7.7A
JUMP_43X118 RTC Battery
(7.5A, 300mils ,Via NO.= 15)
(100mA,40mils ,Via NO.= 2) OCP=9.291A
@ PJ352

VL 2
@ PJ353

2 1 1 +5VL
+5VALWP 2 2 1 1 +5VALW - PBJ1 + PR13 PR17
560_0603_5% 560_0603_5%
JUMP_43X118 @ PJ402 2 1 1 2 1 2 +RTCBATT +RTCBATT
JUMP_43X39 2 1
(5A,200mils ,Via NO.= 10) 2 1
OCP=7.9A JUMP_43X118
@ MAXEL_ML1220T10
@ PJ72 @ PJ403
+VSBP 2 2 1 1 +VSB +1.05VS_VCCPP 2 2 1 1 +1.05VS_VCCP
@ PJ182
JUMP_43X39 2 1 JUMP_43X118
+1.8VSP 2 1 +1.8VS
(17A,680mils ,Via NO.=34)
SP093MX0000
(120mA,40mils ,Via NO.= 1) JUMP_43X118
(1.65A,70mils ,Via NO.= 4) OCP=22.731A
@ PJ76 OCP=4.2A
+0.75VSP 2 2 1 1 +0.75VS ACIN
JUMP_43X79
(1A,40mils ,Via NO.= 2) @ PJ452 Precharge detector
+VCCSAP 2 2 1 1 +VCCSA Min. typ. Max.
JUMP_43X118
H-->L 14.42V 14.74V 15.23V
(6A,240mils ,Via NO.= 12)
4
OCP=7.485A L-->H 15.39V 15.88V 16.39V 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev
PGRAA LA-7191P M/B
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 37 of 50
A B C D
 A B C D

PH1 under CPU botten side :

1

PL2
CPU thermal protection at 90 degree C 1

VMB SMB3025500YA_2P
1 2
Recovery at 56 degree C
@ PJP2 PF2
1 BATT_S1 1 2 PL3
1 SMB3025500YA_2P
BATT+
2 2
3 15A_65V_451015MRL 1 2
Rset = 3 * Rtmh
3
4 4 BATT_P4
BATT_P5
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
5 5

1
10 6 EC_SMDA PC8
GND 6 PC7

1
EC_SMCA @ PC15
11
12
GND 7 7
8 PR14 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K

2
GND 8 1K_0402_1%
13 GND 9 9 Rset = 3 * 7.87K = 23.61K ==> 23.7K
SUYIN_200045MR009G171ZR Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K

2
PD6
VL
1

PJSOT24C_SOT23-3

1
PD5 2
PJSOT24C_SOT23-3 1 PR15
3

1
PR16 23.7K_0402_1%
6.49K_0402_1% PC9
2

2
2 1 0.1U_0603_25V7K

2
+3VL

1
PR18 PH1
1

11.3K_0402_1%
2
PR19 PU1 100K_0402_1%_NCP15WF104F03RC 2

1 8

2
1K_0402_1% VCC TMSNS1
2 7
2

GND RHYST1
2

PR22
PR20 PR21 BATT_TEMPA 33 33,40 VS_ON 3 OT1 TMSNS2 6 2 1
PR27 ADP_I 33,39
100_0402_1% 100_0402_1%
4 5 2 1 4.42K_0402_1%
+3VS OT2 RHYST2
1

G718TM1U_SOT23-8 10.2K_0402_1%
EC_SMB_DA1 16,33

1
1
PR28
PR29 10K_0402_1%
5,33 H_PROCHOT#
EC_SMB_CK1 16,33 100K_0402_1%

2
2
1
D
PQ7 2
SSM3K7002FU_SC70-3 G
S

3
Adaptor protection
PQ5 Adaptor Throttling point ADP_I Recovery point ADP_I
TP0610K-T1-E3_SOT23-3
180W 224W 2.34V 172W 1.80V
3 B+ 3 1 +VSBP 3
0.22U_0603_25V7K
100K_0402_1%
1

PC10
1

1
PR23

PC11 @
VL @ 0.1U_0603_25V7K
2

2
2

PR24
2

1 2
PR25 22K_0402_1%
100K_0402_1%
1

D
PR26
1 2 2 PQ6
19,40 POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

@ PC12
.1U_0402_16V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 38 of 50
A B C D
 A B C D

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ208 AO4407AL_SO8
1 8
2 7

1
PC207

PC208

PC209
3 6
5
B+ CHG_B+

2
PQ203 P2 PQ204 P3 PR215 PL201

4
AO4409L_SO8 AO4409L_SO8 0.01_2512_1% 1UH_PH041H-1R0MS_3.8A_20%
8 1 1 8 1 4 2 1 PQ209 AO4407AL_SO8
VIN 7 2 2 7 1 8
6 3 3 6 2 3 CSIN 2 7
5 5 3 6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 5 1

CSIP
VIN

1
PC231

PC232

PC233

4
2
PC211 PR236
1 2
VIN

2
1

5600P_0402_25V7K
200K_0402_1%

0.1U_0603_25V7K

1
1

2
6251VDD
PR210 LDO 5.075V PR226
47K_0402_1% PR212 PR237

2
ACSETIN

PC210
200K_0402_1% 191K_0402_1% 47K_0402_1% PD9

2.2U_0603_6.3V6K
2

PD201 ACOFF
1 2

1 1
1000P_0402_25V8J
PQ210 RB751V-40_SOD323-2 ACSETIN PR238

1
PC212
DTA144EUA_SC70-3 1SS355_SOD323-2 200K_0402_1%

1 1
3

1
2 1
1.26V VIN

1
PC217
2
PR228 PD10
PR227 14.3K_0402_1% PQ215
2 2 1 2

2
PR216 10_1206_5% DTC115EUA_SC70-3

2
10K_0402_1% 1SS355_SOD323-2

2
33 FSTCHG 2 1 PU200
1

1
PC218 PC222

3
1 24 DCIN 2 1 0.1U_0402_25V6
1

VDD DCIN
1

2
0.1U_0603_25V7K
PR213 PR217
2 2 23 ACPRN
PQ211 150K_0402_1% 100K_0402_1% ACSET ACPRN
DTC115EUA_SC70-3 PR229 20_0402_5%
2

2
6251_EN 3 22 1 2 CSON
EN CSON
6

1
D D
PC219
3

5
6
7
8
2 0.047U_0402_16V7K PACIN 2
G 6251VDD 4 21 1 2 CSOP PQ201 G

1
CELLS CSOP AO4466L_SO8 PQ216
PR230 20_0402_5% S

3
2
S PQ212A PC213 SSM3K7002FU_SC70-3 2
1

DMN66D0LDW-7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5%

ICOMP CSIN

2
PC220 4
PQ212B PC214 6800P_0402_25V7K
SB00000EO00 1 2 1
PR218
2 6 19
0.1U_0603_25V7K
1 2
DMN66D0LDW-7_SOT363-6

1
VCOMP CSIP PL202
3

D
10K_0402_1% PR232 2_0402_5% PR235
5 0.01U_0402_25V7K PR219 10UH_FDSD0630-H-100M-P3_3.8A_20% BATT+

3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG 1 4
33,38 ADP_I ICM PHASE
PR211 100_0402_1%

1
5
6
7
8
22K_0402_5% S PC215 2 3
2.39V
4

1 2 1 2 37 8 17 DH_CHG PQ202
37 PACIN 6251VREF VREF UGATE @ PR206
PR220 AO4466L_SO8 0.02_1206_1%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
154K_0402_1% .1U_0402_16V7K PR205 PC205 4.7_1206_5%
33 IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 @
37 ACON

2
CHLIM BOOT

1
0_0603_5% 4
0.01U_0402_25V7K
1

1
0.1U_0603_25V7K

PC202

PC203

PC204
PR222 PD202
1

1
6251VREF
1 2 6251aclim 10 15 6251VDDP
ACLIM VDDP
1

PQ213 RB751V-40_SOD323-2 @PC206

@ PC206
PC216

2
PR221 24K_0402_1%
DTC115EUA_SC70-3 1 2 6251VDD 680P_0603_50V7K

2
3
2
1
ACOFF 2 120K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
33 ACOFF
2

VADJ LGATE
1

2
2

PC221
PR223 12 13 4.7U_0603_6.3V6M

1
GND PGND
100K_0402_1%
3

ISL6251AHAZ-T_QSOP24

PR224
3
33 CHGVADJ 1 2 3

15.4K_0402_1%
2

PR225
31.6K_0402_1% 6251VDD

VIN
1

PR241

1
10K_0402_1%

1
PR240 1 2 ACIN 13,19,33,35
47K_0402_1% PR242
PR246
10K_0402_1%
309K_0402_1%
2

2
PACIN PR247

2
10K_0402_1%

1
1 2 ADP_V 33
PQ214
DTC115EUA_SC70-3

1
ACPRN 2 PR243 PR248 PC223
CP mode CP= 92%*Iada 14.3K_0402_1% 47K_0402_1% .1U_0402_16V7K

2
CC=0.19A~2.3A Iada=0~3.42A(65W) CP=3.147A

2
Vin Detector
3

IREF=0.9133*Icharge Vaclim=0.6221V(65W) PR222=75k, PR223=20k, PR215=0.02

IREF=0.173V~2.1V Iada=0~3.947A(75W) CP=3.63A
High 18.089V
4
VCHLIM need over 88mV Vaclim=1.1V(75W) PR222=24k, PR223=20k, PR215=0.02 4

Low 17.44V
Iada=0~4.737A(90W) CP=4.36A
CHGVADJ=(Vcell-4)*9.445 Vaclim=0.737V(90W) PR222=53.6k, PR223=20k, PR215=0.015 1.26 / 14.3 * 205.3 = 18.089V
Vcell CHGVADJ Iada=0~6.316A(120W) CP=5.81A Security Classification Compal Secret Data Compal Electronics, Inc.
4V 0V Vaclim=1.777V(120W) PR222=8.25k, PR223=26.7k, PR215=0.015 Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

4.2V 1.882V Iada=0~9.47A(180W) CP=8.72A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
Size Document Number Rev

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4.35V 3.2935V Vaclim=1.779V(180W) PR222=24k, PR223=100k, PR215=0.01 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 39 of 50
A B C D
 5 4 3 2 1

2VREF_8205

D D

1
PC363
1U_0603_10V6K

2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2

PR363 PR365
RT8205_B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 RT8205_B+
PJ331
@ JUMP_43X118

ENTRIP1
ENTRIP2
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
B+ 2 2 1 1 +3VLP PR337 PR357
150K_0402_1% 150K_0402_1%
1

1
PC367

PC368

PC369

PC371
PC360 1 2 1 2

1
10U_1206_25V6M PC366
10U_1206_25V6M
2

2
4.7U_0805_10V6K

2
8
7
6
5

5
6
7
8
PU330

1
PQ331 PQ351

PC361

VREF
ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
C AO4466L_SO8 C
25

2
P PAD
4 4
7 VO2 VO1 24 POK 19,38

PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AO4466L_SO8
1
2
3

3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 VBST2 VBST1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 2.2_0603_5% 2.2_0603_5% PL352
UG_3V 10 21 UG_5V
4.7UH_SIL1045R-4R7PF_6.3A_30% DRVH2 DRVH1 4.7UH_SIL1045R-4R7PF_6.3A_30%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 LL2 LL1 20 1 2

LG_3V 12 19 LG_5V
DRVL2 DRVL1
1

8
7
6
5

5
6
7
8

1
SKIPSEL

330U_6.3V_M
PQ332

VREG5
PR356

VCLK
1 PR336

GND
1

EN0
4.7_1206_5%

VIN
4.7_1206_5%
+ 37 EN0 +

PC352
PC332
1 2

1 2
4 PR360 TPS51125ARGER_QFN24_4X4 4

13

14

15

16

17

18
330U_6.3V_M PC336 499K_0402_1%
2 PC356 2
15mohm 680P_0603_50V7K 1 2 PQ352 15mohm
B+ 680P_0603_50V7K
2

2
Ipeak=5A AO4712L_SO8 AO4712L_SO8

100K_0402_5%
1
2
3

3
2
1
1
1
Imax=3.5A VL

PR361
PC362
F=305KHz

1
1U_0402_6.3V6K
PC364
2
B Total Capacitor 330uF 4.7U_0805_10V6K
B

2
ESR 15mohm RT8205_B+ Ipeak=5A

2
Imax=3.5A
F=245KHz
ENTRIP1 ENTRIP2 Total Capacitor 330uF
ESR 15mohm

1
PC365
2VREF_8205
6

D D 0.1U_0603_25V7K

2
2 5
PQ360A G G PQ360B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
S S
1

SB00000EO00
PR370
VL 2 1
100K_0402_1%
1

33,38 VS_ON

PR371
VS 1 2 2
100K_0402_1%
0.01U_0402_16V7K
42.2K_0402_1%

PQ361
1

A A
1

DTC115EUA_SC70-3
PR372

@PC370

3
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B

WWW.AliSaler.Com PGRAA LA-7191P M/B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 40 of 50
5 4 3 2 1
 A B C D

PJ151
1
@ JUMP_43X118 1

2 2 1 1 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC163

PC164
@ PC165
@PC165

5
6
7
8
680P_0402_50V7K

2
PR164 PQ151
255K_0402_1%
1 2

PR155 4
PR160 BST_1.5V 1 2
30,33 SYSON 1 2 2.2_0603_5%
0_0402_5% AO4466L_SO8

3
2
1
1
PL152

15

14
PC160 @

1
PU150 PC155 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP

EN_SKIP

TP

BST
2

2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
3 12 LX_1.5V Ipeak=7.5A
OUT LX

5
6
7
8

1
PR161 PR157
1 2 4 11 1 2 PQ152 PR156 1 Imax=5.25A
+5VALW VCC
VFB=0.75V ILIM +5VALW 4.7_1206_5%
100_0603_5% 20K_0402_1%
+ PC152 Rtrip=20K, OCP=9.291A
5 FB VDD 10
330U_6.3V_M F=315KHz

2
1

PC161 6 9 DL_1.5V 4
PGOOD DL 2 Total Capacitor 660uF,

AGND

PGND
4.7U_0603_6.3V6K

2
ESR 3.42mohm
2

1
PC162 PC156
2
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K AO4712L_SO8 680P_0603_50V7K 2

3
2
1
HW side:

2
C218 390uF 10m @
C189 330uF 15m @
C875 330uF 17m ; C180 330uF 6m @
PR162
1 2
10K_0402_1%
1

PR163
10K_0402_1%
2

PU180
SY8033BDBC_DFN10_3X3 PL182
4

3 3
@ PJ181 1UH_VMPI0703AR-1R0M-Z01_11A_20%
+3VALW 2 1 10 2 LX_1.8V 1 2 +1.8VSP Ipeak=1.308A
PG

2 1 PVIN LX
ILIM = 4A

68P_0402_50V8J
JUMP_43X39 9 3
PVIN LX

1
F=1MHz

680P_0603_50V7K 4.7_1206_5%
1

1
PC187
PC184 8 SVIN Total Capacitor 66uF,

PR186
22U_0805_6.3VAM PR183
ESR ??mohm

22U_0805_6.3VAM
6 FB=0.6Volt 20K_0402_1%

22U_0805_6.3VAM
2

2
FB
5

2
EN

1
NC

NC
TP

PC183
PC182
2
HW side:
FB_1.8V
11

2
PR181

1
1 2 EN_1.8V C256 22uF
PC186
13,17,31,33,36,43 SUSP#

1
0_0402_5%
PR184
2
1

10K_0402_1%
1

@ PR182 PC185@

2
499K_0402_1% 0.1U_0402_10V7K
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 41 of 50
A B C D
 5 4 3 2 1

D D
PJ451
@ JUMP_43X118
VCCSAP_B+ 2 2
B+
1 1

0.1U_0402_25V6
4.7U_0805_25V6-K

4.7U_0805_25V6-K

2200P_0402_50V7K
Ipeak=6A

1
PC463

PC464

PC466
Imax=4.2A

PC465
5
6
7
8
Rtrip=16.5K, OCP=7.485A

2
PR462 F=315KHz
1 2
255K_0402_1%
Total Capacitor 330u
4 ESR=15mohm
PR455
PR460 BST_VCCSAP1 2 PQ451
1 2 AO4466L_SO8
36,43 VCCPPWRGD HW side:

3
2
1
0_0603_5%
0_0402_5%
C877 330uF 17m @; C485 330uF 6m @
1

@ PC460 PL452

15

14
1
.1U_0402_16V7K PU450 PC455 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
BST_VCCSAP-1 1 2 1 2 +VCCSAP

EN_SKIP

TP

BST
2

DH_VCCSAP 0.1U_0603_25V7K
2 TON DH 13

1
PR461 VOUT 3 12 LX_VCCSAP @ PR456 1
OUT LX

5
6
7
8
100_0603_5% PR457
1 2 4 11 1 2 +5VALW 4.7_1206_5% + PC452
+5VALW VCC ILIM
330U_6.3V_M
16.5K_0402_1%

2
FB 5 10 1 2
FB VDD 2
PR471

1
1 2 6 9 PC462 4 @ PC456
+3VS PGOOD DL
1

AGND

PGND
PC461 10K_0402_1% 4.7U_0805_10V6K
DL_VCCSAP 680P_0603_50V7K PR463
4.7U_0603_6.3V6K

2
PQ452 0_0402_5%
2

C G5603RU1U_TQFN14_3P5X3P5 AO4712L_SO8 C
7

3
2
1

2
2

33 SA_PGOOD
@ PR472
10K_0402_1%
PR464
10_0402_5%
1

2 1 VCCSA_SENSE 9

1
PR465
680_0402_1%

2
+3VS

1
PR466 PR467
5.1K_0402_1%

1
9.09K_0402_1%
2

2
PR468
10K_0402_1%
PR469

2
1
D 10K_0402_1%
2 1 2
G
S PR473

.1U_0402_16V7K
3

1
100K_0402_1%
PQ453 C 0_0402_5%

@ PR470
2 1 2

PC470
SSM3K7002FU_SC70-3 VCCSAP_VID1 9
B
E

3
PQ454

1
B B
MMST3904-7-F_SOT323-3

VID1 +VCCSAP

1 0.8V

0 0.9V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title
SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 42 of 50
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
@ PJ75

1
JUMP_43X79

2
D D

2
PU75
1 VIN VCNTL 6 +3VALW
PC261 2 5
GND NC

1
4.7U_0805_6.3V6K

1
3 7 PC264
@ PR282 PR280 VREF NC

2
0_0402_5% 1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
1 2
5,9,27,36 SUSP 9

2
TP
G2992F1U_SO8

.1U_0402_16V7K
PR279
+0.75VSP

1
0_0402_5% D

SSM3K7002FU_SC70-3
PQ260

1K_0402_1%

PC263
1 2 2
36 0.75VR_EN#

1
G

2
S PR281 PC262

3
1
10U_0805_6.3V6M

2
PC260
.1U_0402_16V7K

2
For shortage changed

C @ PJ401 C
1.05VS_B+ 2 1
2 1 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118

1
PC413

PC414

PC415
PR414

5
255K_0402_1%

2
1 2

PQ401
PR410 BST_1.05VS_VCCP 4
0_0402_5% TPCA8065-H_PPAK56-8-5
13,17,31,33,36,41 SUSP# 1 2
1

PC410 PR405 PC405 PL402

15

14

3
2
1
1
@ PU400 2.2_0603_5% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%
.1U_0402_16V7K 1 2BST_1.05VS_VCCP-1 1 2 2 1 +1.05VS_VCCPP
EN_SKIP

TP

BST
2

2 13 DH_1.05VS_VCCP
TON DH

1
5
PR411 3 12 LX_1.05VS_VCCP PR406
100_0603_1% OUT LX PR407 4.7_1206_5% 1
+5VALW 1 2 4 VCC ILIM 11 1 2 +5VALW + PC402

1 2

0_0402_5%
680P_0603_50V7K
5 VFB=0.75V 10 8.87K_0402_1% 1 2 390U_2.5V_M
FB VDD
1

PR420
4
2

PC406
PC411 6 9 PC412 Ipeak=17A
36,42 VCCPPWRGD PGOOD DL
AGND

PGND

4.7U_0603_6.3V6K 4.7U_0805_10V6K
2

2
DL_1.05VS_VCCP PQ402 Imax=11.9A

1
B B
Rtrip=8.87K, OCP=22.731A

3
2
1
G5603RU1U_TQFN14_3P5X3P5 TPCA8057-H_PPAK56-8-5
7

PR415 F=315KHz
1 2 Total Capacitor 1050uF,
+3VS
10K_0402_1% ESR 5.42mohm
2

@ PR416 HW side:
10K_0402_1%
C10 330uF 17m
C11 330uF 17m
1

C12 330uF 17m @

PR412 PR421
4.02K_0402_1% 10_0402_5%
1 2 2 1 VCCIO_SENSE 8
1

PR413
10K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B

WWW.AliSaler.Com PGRAA LA-7191P M/B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 43 of 50
5 4 3 2 1
 5 4 3 2 1

CPU_B+ 1 2 B+

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
@ PC574 @ PR552 PL501
Reserve PC574, PR552

GFX@ PC563

GFX@ PC565
470P_0402_50V7K 4.99K_0402_1% GFX@ PH501 HCB4532KF-800T90_1812

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5
for slow rate

GFX@ PC564
TPCA8065-H_PPAK56-8-5
2 1 2 1 470KB_0402_5%_ERTJ0EV474J

1
PC579

PC578

PC577

PC575

PC576
2 1 2 1 NTCG

GFX@ PQ501
GFX@ PR563 1 2

2
2
3.83K_0402_1% If HW side have add resistor PWR

2
GFX@ PC530 GFX@ PR564 UGATEG 4
GFX@ PR530 1000P_0402_50V7K 27.4K_0402_1% side can remove PR129, PR130
8.06K_0402_1%

1
1
GFX@ PL502
+GFX_CORE

3
2
1
2 1 +GFX_CORE 0.36UH_PCMC104T-R36MN1R17_30A_20%
GFX@ PC556 PHASEG 4 1

330P_0402_50V7K
GFX@ PC531 GFX@ PR532 GFX@ PC532 330P_0402_50V7K @ PR129 GFX@ PC505 1

1
GFX@ PC557

680P_0603_50V7K 4.7_1206_5%
D @ PR531 39P_0402_50V7K 422_0402_1% 680P_0402_50V7K 1 2 10_0402_1% 0.22U_0603_10V7K 3 2 D
VCC_AXG_SENSE 9

5
+

@ PR506
TPCA8057-H_PPAK56-8-5
499K_0402_1% 2 1 2 1 2 1 BOOTG 2 1 2 1 GFX@ PC502

1
390U_2.5V_M
2 1 GFX@ PR505 GFX@ PR570 GFX@ PR571
VSS_AXG_SENSE 9
2

2
2

GFX@ PQ502
2 1 2 1 2 1 0_0603_5% 10K_0402_1% 1_0402_5%

2
GFX@ PC558
GFX@ PC533 GFX@ PR533 GFX@ PR534 1000P_0402_50V7K 2 1 LGATEG 4 GFX@ PH504

2
@ PC506
150P_0402_50V8J 475K_0402_1% 2.8K_0402_1% GFX@ PR572 10K_0402_1%_ERTJ0EG103FA

1
@ PR130 +5VALW 7.5K_0402_1%
10_0402_1% 1 2 1 2 GFX@ PC570
1

+1.05VS_VCCPP @ PR567 .1U_0402_16V7K

3
2
1

2
1

2
GFX@ PR539 GFX@ PC534 24.9K_0402_1% 1 2 1 2

1
45W@ PR568
18.2K_0402_1% 0.047U_0603_16V7K 45W@ PC567 45W@ PR535 GFX@ PR573

2
UGATEG

0_0603_5%
PHASEG
1U_0603_10V6K 2.2_0603_5% 11K_0402_1%

.1U_0402_16V7K

LGATEG
NTCG

BOOTG
ISNG
ISPG
2

1
130_0402_1%
@ PC560

54.9_0402_1%
2 1 1 2 1 2
2

2
PR537
45W@ PU501

1
PR538
ISL6208ACRZ-T_QFN8_3X3 GFX@ PC571 @ PR574

1
5 VCC BOOT3 45W@ PC535 0.047U_0402_16V7K 100_0402_1%
BOOT 1

1
49

48

47

46

45

44

43

42

41

40

39

38

37
0.22U_0603_10V7K 1 2

1
6 8 UGATE3 @PC572
@ PC572
FCCM UGATE

1
GFX@ PC573 470P_0402_50V7K

ISPG
COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

PROG2

BOOTG

UGG

PHG

LGG
GND
8 VR_SVID_DAT PHASE3 0.033U_0402_16V7K
2 7

2
PWM PHASE

45W@ PR569
1 36 BOOT2 GFX@ PR575
8 VR_SVID_ALRT# VWG BOOT2

2
0_0603_5%
3 4 LGATE3 DISEN@ PR576 680_0402_1%
UGATE2 GND LGATE CPU_B+ 0_0402_5%
2 35

2
8 VR_SVID_CLK IMONG UG2 ISNG
PGND 9 +5VALW 2 1

TPCA8065-H_PPAK56-8-5
PHASE2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
3 PGOODG PH2 34

45W@ PC588

45W@ PC587

45W@ PC586
1
SVID_SDA 4 33 35W@ PR561 Connect to +5V can disable GFX portion,
SDA VSSP2

1
45W@ PQ507
0_0402_5%
SVID_ALERT# 5 32 LGATE2 1 2 but PR575 need to be removed.
ALERT# LG2
4

2
SVID_SCLK 6 31 VDDP+ 1 2
SCLK ISL95831CRZ-T_TQFN48_6X6 VDDP +5VALW
33 VR_ON PR540 PR562 45W@ PL505

2.2U_0603_10V6K
C
1 2 7 VR_ON PWM3 30 C
0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
0.047U_0603_16V7K

3
2
1
1
0_0402_5%
45W@ PR542

PC554
19.1K_0402_1%

1 2 8 29 LGATE1
+3VS PGOOD LG1
1

4 1 +CPU_CORE
1
PC561

PR541 9 28

2
IMON VSSP1

680P_0603_50V7K 4.7_1206_5%
35W@ PR542 1.91K_0402_1% Connect to +5V 3 2

PR536
TPCA8057-H_PPAK56-8-5
29.4K_0402_1% 19,33 VGATE 10 27 PHASE1
2

VR_HOT# PH1 disable PWM3

45W@ PQ512
2

10K_0402_1%
11 26 UGATE1
NTC UG1
ISEN3/ FB2

2
1_0402_5%
10K_0402_1%

10K_0402_1%
3.65K_0402_1%
2

45W@ PR586

45W@ PR585

45W@ PR584

PR587

45W@ PR589
12 25 BOOT1 4

PROG1
ISUMN

ISUMP
VW BOOT1
COMP

ISEN2

ISEN1

VSEN
33 VR_HOT#

VDD
RTN

VIN
FB

PC536
Ipeak=98A,

VSUM+ 1

VSUM- 1

1
45W@
43P_0402_50V8J

PU500
13

14

15

16

17

18

19

20

21

22

23

24

3
2
1
Vboot=0V
1

PC537

45W@ PR560

ISEN3

ISEN1

ISEN2
2
1 2 1 2 0_0402_5%
+1.05VS_VCCPP

VDD+
1 2
2

1 2 PR544 PH502 PR559 Ipeak=56A,

3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J 0_0603_5% CPU_B+
@ PR547 2 1 1 2 Vboot=0V
CPU_B+

100U_25V_M

100U_25V_M
TPCA8065-H_PPAK56-8-5
499_0402_1%

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 1

PC580

PC581

PC582
PR545 PC549
+ +

PC568

PC566
27.4K_0402_1% 0.22U_0603_25V7K 35W@ PR560

1
PQ506
4.32K_0402_1%
ISEN3

2
1

PR558
1

PR546 PC539 35W@ PC540 1_0603_5% UGATE2 2 2

ISEN2

ISEN1

2
8.06K_0402_1% 1000P_0402_50V7K 10P_0402_50V8J 2 1
2 1
+5VALW
2

1
2

PC548 PL503

3
2
1
45W@ PC569 1U_0603_10V6K 0.36UH_PCMC104T-R36MN1R17_30A_20%
2

0.22U_0402_6.3V6K PHASE2 4 1
2 1 PR515 +CPU_CORE

680P_0603_50V7K 4.7_1206_5%
VSUM+ 2.2_0603_5% 3 2

PR516
TPCA8057-H_PPAK56-8-5
B PC562 BOOT2 2 1 2 1 B

1
PC541 0.22U_0402_6.3V6K

45W@ PQ508

10K_0402_1%

10K_0402_1%
3.65K_0402_1%
@ PR553 PR548 PC542 VSUM- PR557 PC515
0.022U_0402_16V7K
33P_0402_50V8J 2 1

2
1_0402_5%
11K_0402_1%

10K_0402_1%
499K_0402_1% 499_0402_1% 470P_0402_50V7K 2.61K_0402_1% 0.22U_0603_10V7K
0.33U_0402_10V6K

2
1
@ PC551

PR583

PR581

PR594
PC544 LGATE2

PR580

PR582
1 2 2 1 2 1 2 1 4
1

1
PC550

0.22U_0402_6.3V6K PR556

1 2
PC543 PR549 PR551 2 1

PC516
150P_0402_50V8J 316K_0402_1% 3.65K_0402_1%
2

VSUM+ 1

VSUM- 1

1
2 1 2 1 2 1 PH503
2

3
2
1
10K_0402_1%_ERTJ0EG103FA

ISEN2

ISEN1

ISEN3
2
@ PC559 @ PR550 @ 45W@ PR554
330P_0402_50V7K

680P_0402_50V7K 2K_0402_1% +CPU_CORE 1 2 1.24K_0402_1%

2

2 1 2 1 PC545 2 1 VSUM-
PR131 330P_0402_50V7K CPU_B+
1
PC547

10_0402_1% 2 1
8 VCCSENSE
1

TPCA8065-H_PPAK56-8-5

0.1U_0402_25V6

0.1U_0402_25V6
PC553

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
Reserve PC559, PR550 2 1 2 1

PC583

PC584

PC585
2 1 .1U_0402_16V7K
8 VSSSENSE
2

for slow rate @ PC552 @ PR555

2

1
PQ503

PC589

PC590
@ PC546 330P_0402_50V7K 100_0402_1%
1 2 1000P_0402_50V7K
UGATE1 4

2
PR132
If HW side have add resistor PWR 10_0402_1%
side can remove PR131, PR132 PL504

3
2
1
35W@ PR554 0.36UH_PCMC104T-R36MN1R17_30A_20%
1.47K_0402_1% PHASE1 4 1
PR525 +CPU_CORE

680P_0603_50V7K 4.7_1206_5%
TPCA8057-H_PPAK56-8-5
2.2_0603_5% 3 2

PR526
BOOT1 2 1 2 1
+CPU_CORE +GFX_CORE

45W@ PQ504

10K_0402_1%

10K_0402_1%
3.65K_0402_1%
PQ504 PC525
Iocp=120A, IccMAX=94A Iocp=40A, IccMAX=33A

2
1_0402_5%

10K_0402_1%
TPCA8059-H_PPAK56-8-5 0.22U_0603_10V7K

PR591

PR592

PR593

PR590

PR588
Load line=1.9mohm Load line=3.9mohm 35W@ LGATE1 4
DCR=1.1mohm DCR=1.1mohm

1
A A

PC526
PQ508
quad core TPCA8059-H_PPAK56-8-5

VSUM+ 1

VSUM- 1

1
35W@
3
2
1

ISEN1

ISEN2

ISEN3
+CPU_CORE +GFX_CORE
Iocp=70A, IccMAX=53A Iocp=40A, IccMAX=24A
Load line=1.9mohm Load line=3.9mohm Security Classification Compal Secret Data Compal Electronics, Inc.
DCR=1.1mohm DCR=1.1mohm 2010/09/09 2011/09/09 Title
Issued Date Deciphered Date
dual core SCHEMATICS,MB A7191

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 44 of 50
5 4 3 2 1
 A B C D E

OP!!!!!!!EBUF!!!!!!!!!!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................
EVT --> DVT

1 2010/11/7 P39 change PL201 1.2uH(SH00000B100) to 1uH(SH00000MN00) cost down

2 2010/11/7 P41 change PR157 SD0341622YT to SD034162280 previous P/N is for carPC use
3 2010/11/7 P37 change precharge to unmount reserve precharge
1 4 2010/11/7 P39 change PQ203, PQ204 from AO4407A to AO4409L higher curretn withstanding ability 1

5 2010/11/7 P39 change PR219 from 47K to 100ohm prevent ADP_I from being divided
6 2010/11/7 P37 change PJP3 to PJP1 wrong name
7 2010/11/16 P39 charger pin4 pull high VDD 4 cells design should pull high VDD
8 2010/11/16 P38 change PR27 to 10.2K set adaptor protection power to 224W
9 2010/11/16 P44 change PR551 to 3.65K adjust CPU_CORE loadline
10 2010/11/16 P38 change PD5, PD6 to SCA00000W00 follow ESD team suggestion main source
11 2010/11/16 P39 change PR215=0.01ohm, PR222=24K, PR223=100K change adaptor power to 180W
12 2010/11/19 P44 change PC551 to mount adjust CPU_CORE transient waveform
13 2010/11/19 P44 change PL502, 503, 504, 505 foot print to to solve poor solder issue
MAG_MMD10DZR36MS1_4P
14 2010/11/19 P41 change PL182 to SH00000KS00 original TMP choke is forbidden
15 2010/11/19 P41 mount PR156, PC156; change PR155 to 2.2ohm EMC request
16 2010/11/19 P44 mount PR516, PR526, PR536, PC516, PC526, PC536; EMC request
change PR515, PR525, PR535 to 2.2ohm
17 2010/11/19 P44 add PC589, PC590 0.1uF 0402 EMC request
2 2
18 2010/11/26 P44 PR567 change to 24.9K, unmount set GFX Imax register to 33A
19 2010/11/26 P38 add PL3 bead add design margin for battery current on this bead
20 2010/12/3 P39 mount PC207, PC208, PC209 EMC request

DVT1 --> DVT2

21 2011/1/14 P44 modify PR550 part number to SD034200180 previous part number is wrong
22 2011/1/14 P42 change PR461 to 0603, PC461 to 0603 change to common size
23 2011/1/14 P44 modify PC549 to 25V (SE000005Z80) previous 10V is wrong
24 2011/1/14 P39 modify PQ208, PQ209 to AO4407AL change to L
25 2011/1/14 P44 change PC551 to unmount adjust CPU_CORE transient waveform
26 2011/1/19 P44 change PC571 to 47nF, PC573 to 33nF adjust GFX_CORE transient waveform
27 2011/1/19 P44 change PR534 to 2.8K, PR575 to 680 adjust GFX_CORE loadline and OCP

DVT2 --> PVT

28 2011/2/18 P42 modify PL452 to SH000008U80 can use higher height choke
3 3
29 2011/2/18 P43 modify 1.05V Rtrip PR407 to 7.15K recalculte OCP to 21.3A
30 2011/2/18 P43 modify 1.05V Vout PC402 to 390uF for OVP design reqirement
31 2011/2/18 P39 change PL202 charger choke to 7*7 molding M600 layout replacement requirement
32 2011/2/25 P37 change PJP1 + - pin define for power switch relocation layout replacement
33 2011/3/2 P37 delete GFX_CORE jump PJ502, PJ503 for save space
37 2011/3/7 P40 change PR335 and PR355 to 2.2ohm (boost resistor) EMI request
add 3/5V snubber circuit, PR336, PC336, PR356, PC356

38 2011/3/7 P40 add 0.1uF caps, PC367, PC368, PC369, PC371 at 3/5V B+ EMI request
39 2011/3/10 P44 add 10uF 1206 (PC575, PC576, PC577, PC578, PC579) EMI request
at CPU_B+ and B+

40 2011/3/14 P43 change PR406, PC406(snubber circuit) to mount, to solve enter system hang up issue, reduce 1.05V noise
PR405 to 2.2ohm(Rboost)

PVT --> PreMP

41 2011/4/4 P39 change PR236 : 47K to 200K, PR237 : 10K to 47K design change
4 42 2011/4/20 P41 change PR157 to 20K OCP design change 4

43 2011/4/20 P42 change PR457 to 16.5K OCP design change

44 2011/4/20 P43 change PR407 to 8.87K OCP design change
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B

WWW.AliSaler.Com PGRAA LA-7191P M/B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 16, 2011 Sheet 45 of 50
A B C D E
 5 4 3 2 1

PIR (Product Improve Record)

QHSBB!MB.82:2Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/1!UP!1/2
OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................................
09/13 04 Change RC11 from 22 ohm to 0 ohm For SDXC SDA application
09/13 29 Change R347 to @ and R564 to mount For LVDS dual channel select
09/21 8 Change C890,C891,C894 from 470u to 330u. For cost reduction
09/21 8 Change C10,C11,C12 330u from D2 to OSCON. For cost reduction
09/24 33 Remove R380,R382 For ENE has fixed entry test mode issue.
09/25 35 Add H24 For J3G mini card stand off
09/25 13 Change JP1 to JMXM, JHDD to JHDD1, JODD to JODDB For MXM,HDD,ODD/B Conn.
D 09/26 27 Del Felica schematic For meet PRD D

09/26 32 Add Subwoofer schematic For meet PRD

09/26 31 Del RA11,CA58,CA59,CA60,JA1 For reduce audio schematic
09/26 32 Change UA8 subwoofer amplifier pin6 contact from +5VS to +5VALW For audio sleep & music
09/26 11,12,26,28,30,32 Update JDDRL,JDDRH,JUSB,JHDD1,JHDD2,JODDB,JLAN,JUSB30,JSUB connector For connector list
09/26 28 Del UL3,RL4,RL23,LL1,LL3,CL9,CL13,CL28,CL29 For 1G LAN only
09/26 28 Change UL1,RL23 BOM structure from 8105ELDO@ to 8105E@ For LAN schematic update
09/26 26 Add JHDD2,C363~C366,C371~C374 For LAN schematic update
09/26 32 Add BT schematic For dedicated BT
09/26 35 Delete SW1 and SW4 and update JTPL pin define For move to small board
09/26 35 Update JTPL pin define For small board update
09/26 32 Combine FP and JTPL schematic For small board update
10/12 05 Change Fan Control Circuit For PWM FAN
10/12 06 Change PCIE AC capacitor from 0.22uF to 0.1uF For nVIDIA request
10/12 09 Change R122,R252 from 100 ohm to 1K_0402_5% ohm For Intel Design Guide V1.5 request
10/12 13,14 Remove LVDS Signal from VGA Board, RV125 DIS only support EDP
10/12 14 Mirron JLVDS pin define For Layout Routing
10/12 14 Change R112 from 100K ohm to 10K ohm
10/12 18 Remove R347, Change R228 form 10K ohm to 1K ohm Only support Dual Channel, follow Intel design guide
10/12 22 Remove R444 Only support MAXIM14566B
10/12 23 Remove L22,C509 change to test point T30 On-die VR default support
10/12 23 Remove R483,C280 change to test point T36 On-die VR default support
C 10/12 24 Remove R498 change to test point T41 On-die VR default support C

10/12 24 Remove L20,C302 change to test point T42 On-die VR default support
10/12 24 Remove L17,C296 change to test point T43 On-die VR default support
10/12 26 Reverse JPIO pin define Follow FFC Pin define
10/12 26 Remove SW5 Cancel function test
10/12 26 Direction connection SLP_CHG_M3, SLP_CHG_M4, Remove R1445 Only support MAXIM14566B
10/12 28 Remove LL5, add CL35 For EMI request
10/12 29 Change RC17 from 0 ohm to 22 ohm For xD issue
10/12 31 Remove RA34 Support Sleep & Music function
10/12 32 Remove R361 Pull Up 10K ohm at PCH side
10/12 33 Remove R380,R382 Don't avoid to EC entry ENE test mode
10/12,14 33,34 Change LID +3VALW to +3VL
10/12 22,35 Change Q32,Q51 (single) to Q209 (dual) For cost reduction
10/13 35 Change R22 from 63.4 ohm to 90.9 ohm For Power Board LED request
10/13 34 ADD R393,C457 For EMI request
10/14 13 Remove RV18, Direct connection to MXM connector PCH Side already have option item
10/14 26 Update JHDD2 Connector For connector list
10/14 16,20 Remove HDMI signal from PCH side For support Optimus Huron River 2.0
10/14 22,33 Add CIR BTO@ Reserve to CIR
10/15 13 Add R566 Fine tune vga_clk sequence
10/18 5,10 Remove XDP connector & other component For layout routing request
10/18 30 Change USB3.0 IC from SA000048H10(ES/CS sample) to SA000048H00(QS Sample)
10/18 33 Change R172 to @ Due to the pull high resister will be in Cap sensor board
B B
10/18 34 Reserve power rail +3VL for Hall sensor

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 46 of 48
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

QHSBB!MB.82:2Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/2!UP!1/3
OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................................
10/22 26 Q6 change to always mount
10/22 33,36 Change Q6(single) & Q41(single) to Q6(Dual) For cost reduction
10/25 20 Change R223 & R229 BOM Structure to OPT@ For Optimus
10/25 13 Change C15 & C16 P/NΚSE00000QKN0 B+
10/27 18 Add clear Pass-word function in PASSWORD_CLEAR# (PCH_GPIO56) By Customer demand
10/27 22 Change PCH_GPIO37 pull down R547 value from 100k ohm to 10k ohm By Intel Check list V1.5 demand.
D 10/28 33 Change EC GPXIOD04 from SLP_CHG# to OTP_HW By PWR demand. D

10/28 33 Add D26, R359 for OPT_HW function,Remove R1428, R439 for SLP_CHG#. By PWR demand.
11/1 23 Add net +VCCAFDI_VRM to U2.AP16
11/4 34 Change LID SW power rail to +3VL
11/4 15 Add test point at JCRT pin4, pin11 By CIC demand
11/5 17~25 Change PCH P/N from SA00003P440 to SA00004EE50 By SMT demand
11/5 27 Remove D24 and add Q39 to avoid SUSP# leakage Avoid SUSP# leakage
11/5 27 Add level shift circuit for WL_OFF# Avoid leakage from WLAN to PCH.
11/8 Change P/N from SC1H751H010 to SCS00002G00 For cost reduction
11/9 23 Change R480 from SD002000080 to SD013000080 For layout placement
11/9 24 Change C326 from SE042104K80 to SE076104K80 For layout placement
11/9 23 Change R477 from SD002000080 to SD013000080 For layout placement
11/9 27 Change CM9 from SE053475Z80 to SE107475K80 For layout placement
11/10 23 Add R583 For CRT noise issue
11/10 32 Change Sub-woofer from AGND to DGND For Sub-woofer issue
11/12 18 Add R584 For Panel select
11/16 33 Chagne D26 from always mount to @ Reserve to Power team use
11/16 35 Chagne H21 footprint from 4P7 to 4P2x4P7, H22 footprint from 4P7 to 4P7x5P6 ME drawing
11/17 27 Change Q36(single) & Q39(single) to Q210(Dual) For cost reduction
11/17 26 Change JUSB footprint from SP060004B00 to DC233007P00 For ME request
11/17 35 Reverse JLED Pin define For SB layout request
11/18 35 Add Screw Hole H24 & H25 For ME request
C 11/18 35 Change JLED Connector For ME request C

11/18 28 Add R392,R403,R419,R429,R430,R431,R439,R434 For EMI ISN rsi request

11/18 14 Add D15 for ESD Reserve for DVT test
11/18 23 Change R583 from 0 ohm to 1 ohm For PCH CRT wave line issue
11/22 5 Change D86 P/N from SC100000Y10 to SC100001M00 For PUR suggest
11/22 34 Change UG1 P/N from SA000039900 to SA00004GB00 By IC revision update
11/25 35 Change H22 footprint from H_4P7x5P6 to H_4P2x4P7 For ME drawing
11/25 32 Change CA72 form 2.2uF to 4.7uF For Sub-woofer noise issue
11/25 34 Remove H24,H25 For layout request
11/26 14 Add D15,D17,R337 For EC (Panel) Back light & PWM issue
11/29 10 Add NET NAME at T22,T23,T24,T25,T28
Delete T-PAD at T6ΕT5ΕT25ΕT28ΕT27ΕT24ΕT23ΕT22ΕT21ΕT19ΕT18ΕT12ΕT11 For layout request

11/30 35 Change R404,R819 power plane from +5VS to +3VS For LED issue
11/30 24 Add C1207,C1208 For cost reduction
Change CL37 to 180PF and change BOM to reserved CL38
11/30 28 Change BOM to mounted DL1 and DL2 For EMI request
Change BOM to mounted CL683 and CL684

12/1 35 Change R22 from 90.9 ohm to 150 ohm For LED

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 47 of 50
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

QHSBB!MB.82:2Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/3!UP!1/4
OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................................
12/9 31,32 Add Sleep & Music circuit Modify sleep & music function
12/9 30 Change +1.5V to +1.05V Transfer power plane from +5VALW to +3V Avoid leakage current
12/9 33 Change U44 & C818 to unmount, mount R446 For cost reduction
12/13 18 Change R584 BOM structure from EDP@ to DIS@ For BOM Structure error
12/13 30 Mount LT1,LT2,LT4 For EMI request
12/13 17 Change U13 P/N from SA00003IN00 to SA00003K800 For support Dual and quad SPI.
D 12/14 31 Add Net Name & Sleep-Music Schematic For Subwoofer Sleep-Music funtion D

12/14 31 Add MONO_IN change page symbol For Moving Beep noise Schematic to page 32
12/14 32 Add Beep noise schemtic & MONO_IN change page symbol For Moving Beep noise Schematic to page 32
12/15 31 Change Net Name & Sleep-Music Schematic For Subwoofer Sleep-Music funtion
12/17 31 Modify Net Name & Sleep-Music Schematic & symbol For Subwoofer Sleep-Music funtion
12/20 14 LED_PWM add R126 10K ohm to GND For Samsung panel can not adjust system backlight issue
12/20 14 Change R103 & R332 footprint from 0402 to 0603 For DXF layout co-lay issue
12/21 26 Change JHDD2 P/N to SP010015H00 For SMT assembly issue
12/23 9,36 Need mount PJ30, Unmount +1.5V to +1.5VS part For cost down plan
12/23 19 un mount U12,C250 and mount R259 for cost down purpose For cost down plan
12/23 34 Unmount C836 for cost down purpose. For cost down plan
12/23 9 Unmount C877 for cost down purpose. For cost down plan
12/23 15,16 Change F1 & F2 form 1.1A to 0.5A part For cost down plan
12/23 33 Un-mount R359 EC do not support this function
12/23 34 Change UG1 from TSH35TR to TSH352TR For customer request
12/27 9 Change R74 & R75 from 100 ohm to 10 ohm For Intel Checklist V1.5 updated.
12/27 8 Change C12 P/N from SF000002Z00 to SGA20331E10 For cost down plan
12/30 11 Unmount C218 For cost down plan
12/30 33,34 Add KB9012 can co-lay KB930 circuit use BOM Structure to For cost down plan
control different component for different EC
12/31 14 Change R126 from 10k to 47k Prevent EC pin damage cause MB NG
12/31 9 change CPU GFX Core bulk cap C873 from 330uF to 560uF To prevent Huron-River CPU_CORE PWM IC abnormal shutdown issue
12/31 31 change Net-name from sleep & music switch To prevent S3 subwoofer i-pod noise
C C
12/31 32 Add RA51 & CA73 for S3 subwoofer sleep & music To prevent S3 subwoofer i-pod noise
1/3 21 Add C473 For ESD request
1/4 34 Remove UG4 For customer request
1/5 35 Add H27 For ME request
1/5 24 Unmount C333 & C515, Change L19 & L21 from inductotr to bead For cost down plan
1/10 26 Unmount C426 For cost down plan
1/10 26 Unmount R399, always mount R544 PCBA with dGPU device lose issue now
1/12 8,9 Change C10,C11,C875 from 330uF to 390uF For BOM change
1/13 26 Remove C426 For cost down plan
1/13 26 Remove C363, C372, C373, C374 S/B have part and layout limitation
1/13 26 Remove C352, C353, C354, C355, C360 S/B have part and layout limitation
1/17 21,30 Mount C473,DT2 For ESD request
1/18 19 Mount U12,C250, Unmount R259 Need double confrim this cost down plan
1/18 28 Change LAN chip form 8111E-VB to 8111E-VL For cost down plan
1/19 32 Change RA51 from 20.5K to 12K For Subwoofer noise issue
1/19 14 Change R103 & R332 footprint from 0603 to 0402 For DFX request

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 48 of 50
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

QHSBB!MB.82:2Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/4!UP!1/5
OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................................
1/20 8 Change C2 from 330uF to 470uF & C7,C9 from 470uF to 330uF For Power request
2/8 27,35 Change Wimax@ to always mount For Customer request
2/18 8,9 Remove C391, C351, C350, C349, C215, C214, C221, C223, C209, C131 For Power layout request
C126, C220, C219, C222, C891, C894

2/25 34 Add R993 and R994 for keyboard backlight +3VS and +5VS option For Customer request
3/2 31,32 Modify Audio and subwoofer writing descritption For avoiding confusion
3/3 13,16 Swap HDMI port 0 and port 2 from MXM conn. To meet MXM spec.
D D
3/3 09 Change C875 from SF000002O00 to SF000002Z00. For ME request to avoide ME impact
3/8 13 Un-mount D25 For 3D mark performance low issue on battery mode
3/9 24 Remove C333 and C515 For ME JTPL changing to non-ZIF connector will has ME impact
3/10 26 Add 1pcs C1211 680pF 0603 on +5VALW and close to R148 For EMI request that USB traces of USB/B will couple with Audio traces (165MHz) through FFC cable
Add 2pcs C1209,C1210 680pF 0603 on +5VL and close to R149

3/10 35 Change JTPL from SP01000ZL00 to SP01000YG00 For ME request

3/10 31 Delete RA36, RA39, RA35, RA38, RA30, RA37 Add AC reference voltage circuit for UA2
Add CA38, RA888, RA889, CA13, RA40, RA891, RA890, CA39

3/10 32 Change CA72 package from 0805 to 0603 and add CA74 0402 For tuning subwoofer on-off time
3/10 31 Change CA21, CA22, CA38 and CA39 to 4.7uF 0603 For audio issue
3/10 34 Change R394 from 33ohm to 100ohm, C454 from 33pF to 100pF For EMI request
3/14 17 Change BOM structure of R397 and C86 from un-mount to mount For EMI request about ISN and SPI issue
28 Change CL37 to reserve
3/14 32 Change CA70 and CA73 from 2.2uF to 0.47uF For popo issue
3/15 35 Add PCH HM65 B3 PN

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 49 of 50
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

QHSBB!MB.82:2Q!TDIFNBUJD!DIBOHF!MJTU!SFWJTJPO!DIBOHF;!1/5!UP!2/1
OP!EBUF!!!QBHF!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................................................................................................
4/2 17 Modify clear CMOS jumper's name from JCOMS to JCMOS For jumper naming rule
34 Modify R993 BOM structure from KBL@ to @ and R994 from @ to KBL@ For customer request
32 Change inductors LA4, LA5 (SHI00002T00) to 0ohm RA7,RA8 (SD013000080) For subwoofer current
17 Un-mount R363, R330, R278 and R306, R295, R301 For S5 power saving
31 Add CA40, CA41 and un-mount CA21, CA22 For Audio THD+N fail issue
16 Change HDMI choke L8, L9, L10 and L11 from SM070001310 to SM070001U00 For HDMI eye diagram fail
14 Change D84 PN from SCA00000U10 to SC600001600 For source common
D D
35 Change PCB PN to DAZ0IB00100 For MP use

4/11 31 Change CA21 & CA22 package from 0603 to 0402 For layout request
14 Reserve a AND gate to pull BK_OFF# timing in for eDP panel For Samsung 3D panel white line issue
31 Add 0.1U CA51 to cross on GND and AGND For layout request

4/19 14 Change R103 to 0ohm and BOM structure is DIS@ For Samsung 3D panel white line issue
Change D15 BOM structure to OPT@
13 Change PR628 to 150K ohm For tuning OPT VGA_CORE sequence

4/26 31 Change RA889 and RA891 from 10K to 8.2K For audio performance tuning

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/09 Deciphered Date 2011/09/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A7191
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

WWW.AliSaler.Com
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PGRAA LA-7191P M/B
Date: Friday, September 16, 2011 Sheet 50 of 50
5 4 3 2 1