8 7 6 5 4 3 2 1

The following grounds should be routed back to their respective regulators and then tied directly to the ground plane with one
via: GND_PVSS, GND_MPVSS, GND_TPVSS, and GND_A2VSSN. The other ground pins (GND_AVSSN, GND_A2VSSQ,
GND_TXVSSR GND_TPVSS GND_A2VSSN GND_AVSSN GND_A2VSSQ GND_AVSSQ GND_MPVSS GND_PVSS GND_R2SET GND_RSET GND_RSET, GND_R2SET) should be tied to the ground plane directly through one via as close to the pins as possible
without connecting to anything else. If space is an issue it is possible to use one via for two adjacent pins.
+VDDQ_BUS +5V_BUS +3.3V_BUS
Use 47uF Tant. 16V 20% D size (P/N 4230047600),
800mR Max. ESR and Max. ripple 430mA @ 100kHz
or
+12V_BUS C2 100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700), C5 C8
100uF_6.3V 440mR Max. ESR and Max. ripple 230mA @ 100kHz DNI/47uF_6.3V DNI/47uF_6.3V
or >=6.3V >=6.3V
Biggest footprint 47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600),
C10 place at the AGP connector 760mR Max. ESR and Max. ripple 150mA @ 100kHz
C10 AGP_SBA[7..0]
AGP_SBA[7..0] 2
DNI/10uF_20V
D AGP_ST[2..0] D
AGP_ST[2..0] 2
AGP_C/BE#[3..0]
AGP_C/BE#[3..0] 2
AGP_AD[31..0]
AGP_AD[31..0] 2

MAGP1
A1 B1
AGP_TYPEDET# 12V OVRCNT#
A2 B2
AGP_GC_8X_DET# A3 TYPEDET# 5.0V
B3
GC_DET#/RESEVED 5.0V
A4 B4
USB- USB+
A5 B5
GND GND
A6 B6
2 AGP_INTR# INTA# INTB#
A7 B7 AGP_AGP/PCICLK 2
RST# CLK
A8 B8 AGP_REQ# 2
2 AGP_GNT# GNT# REQ#
A9 B9
2 AGP_WBF# AGP_ST1 VCC3.3 VCC3.3 AGP_ST0
2 AGP_SB_STB# A10 B10
ST1 ST0 AGP_ST2
2 AGP_MB_8X_DET# A11 B11
R83 0R MB_DET#/RESERVED ST2
2 AGP_DBI_HI A12 B12 AGP_RBF# 2
DBI_HI/PIPE# RBF# R86 0R
A13 B13 AGP_DBI_LO 2
+5V_BUS GND GND
A14 B14
AGP_SBA1 WBF# DBI_LO/RESERVED AGP_SBA0
A15 B15
SBA1 SBA0
A16 B16
C11 AGP_SBA3 VCC3.3 VCC3.3 AGP_SBA2
A17 B17
100nF SBA3 SBA2
A18 B18 AGP_SB_STB 2
SB_STB# SB_STB
X7R
14

A19 B19
R3 AGP_SBA5 GND GND AGP_SBA4
A20 B20
100R AGP_SBA7 SBA5 SBA4 AGP_SBA6
1 A21 B21
AGP_RESET# SBA7 SBA6
3 A22 B22
2 AGP_RESET# KEY KEY
2 A23 B23
U6A KEY KEY
A24 B24
R4 SN74ACT86D KEY KEY
A25 B25
7

180R AGP_AD30 KEY KEY AGP_AD31

A26 B26
COMMON AGP_AD28 AD30 AD31 AGP_AD29
A27 B27
AD28 AD29
A28 B28
AGP_AD26 VCC3.3 VCC3.3 AGP_AD27
A29 B29
C AGP_AD24 AD26 AD27 AGP_AD25 C
A30 B30
AD24 AD25
2 AGP_AD_STB1# A31 B31 AGP_AD_STB1 2
GND GND
A32 B32
AGP_C/BE#3 AD_STB1# AD_STB1 AGP_AD23
A33 B33
C/BE3# AD23
A34 B34
AGP_AD22 VDDQ VDDQ AGP_AD21
A35 B35
AGP_AD20 AD22 AD21 AGP_AD19
A36 B36
AD20 AD19
A37 B37
AGP_AD18 GND GND AGP_AD17
A38 B38
AGP_AD16 AD18 AD17 AGP_C/BE#2
A39 B39
AD16 C/BE2#
A40 B40
VDDQ VDDQ
A41 B41 AGP_IRDY# 2
2 AGP_FRAME# FRAME# IRDY#
A42 B42
KEY KEY
A43 B43
KEY KEY
A44 B44
KEY KEY
A45 B45
KEY KEY
A46 B46 AGP_DEVSEL# 2
2 AGP_TRDY# TRDY# DEVSEL#
A47 B47
2 AGP_STOP# STOP# VDDQ
A48 B48
PME# PERR#
A49 B49
2 AGP_PAR GND GND
A50 B50
AGP_AD15 PAR SERR# AGP_C/BE#1
A51 B51
AD15 C/BE1#
A52 B52
AGP_AD13 VDDQ VDDQ AGP_AD14
A53 B53
AGP_AD11 AD13 AD14 AGP_AD12
A54 B54
AD11 AD12
A55 B55
AGP_AD9 GND GND AGP_AD10
A56 B56
AGP_C/BE#0 AD9 AD10 AGP_AD8
A57 B57
C/BE0# AD8
2 AGP_AD_STB0# A58 B58 AGP_AD_STB0 2
VDDQ VDDQ
A59 B59
AGP_AD6 AD_STB0# AD_STB0 AGP_AD7
A60 B60
AD6 AD7
A61 B61
AGP_AD4 GND GND AGP_AD5
A62 B62
AGP_AD2 AD4 AD5 AGP_AD3
A63 B63
AD2 AD3
A64 B64
AGP_AD0 VDDQ VDDQ AGP_AD1
A65 B65
AD0 AD1 AGP_AGPREF
A66 B66
VREFGC VREFCG
B UNIVERSAL_AGP_BUS B

AGP_TYPEDET# For retail, 1K ohm

pull-down causes +VDDQ_BUS
AMD system detects
R19 AGP2X only R88 169R_1%

3
0R
+12V, TYPEDET#
short protection Q9 AGP_AGPTEST
AGP_AGPTEST 2
for OEM (1KR) AGP_VREFGC TEST 1 2N7002E

R89 71.5R_1%

2
+12V_BUS
AGP_GC_8X_DET#
J8

R81 1 AGP_AGPREF R84 DNI/0R Keep stubs short

0R 2 AGP_VREFGC R85 DNI/0R
DNI/CON2
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref

+VDDQ_BUS R_AGP8X
R_AGP8X must be 1%

3
+3.3V_BUS resistor to provide
350mV +/- 5% on Vref
2N7002E R96
U6D TEST 1 Q11 332R_1%
R90 SN74ACT86D +VDDQ_BUS R_AGP8X
47K R95

2
AGP_AGPREFCG 2
3

147R_1% R97 C21

AGP_MB_8X_DET# 13 2N7002E R93 100R_1% 10nF
11 TEST 1 Q10 332R_1%
12
A R92 A
2

R91
1K 147R_1% R94 C19
100R_1% 10nF

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X) (905) 882-2600
Title
R9200L-64TD
Size Document Number Rev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 1 of 14
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AGP_AD[ 31..0] GPIO[1 3..0]

1 AGP_AD[31..0] GPIO[13..0] 7,8
U 1A
AGP _AD0 K27 AJ5 GP IO0
AGP _AD1 AD0 Part 1 of 5 GPIO0 GP IO1
L26 AK4 THE VALUES OF RSET AND R2SET SHOWN IN THE TABLE MAY BE
AGP _AD2 AD1 GPIO1 GP IO2
L25 AJ4 APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING)
AGP _AD3 AD2 GPIO2 GP IO3
L27 AF4 BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI
AGP _AD4 AD3 GPIO3 GP IO4 RSET 499R
M25 AG4 REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR
AGP _AD5 AD4 GPIO4 GP IO5
M26 AH4 R2SET MASS PRODUCTION
AGP _AD6 AD5 GPIO5 GP IO6 715R
N26 AK3
AGP _AD7 AD6 GPIO6 GP IO7
N25 AJ3
AGP _AD8 AD7 GPIO7 GP IO8
R26 AH3
AGP _AD9 AD8 GPIO8 GP IO9
R25 AG3
AGP _AD10 AD9 GPIO9 GP IO10
T26 AF3
AGP _AD11 AD10 GPIO10 GP IO11
D T25 AJ2 D
AGP _AD12 AD11 GPIO11 GP IO12
U26 AH2
AGP _AD13 AD12 GPIO12 GP IO13
U25 AG2
AD13 GPIO13

EXT TMDS / GPIO / ROM

AGP _AD14 U27 AF2 GP IO14
AGP _AD15 AD14 GPIO14 GP IO15 Mem_Strap2 7
V26 AH1 Mem_Strap1 7
AGP _AD16 AD15 GPIO15 GP IO16
M28 AG1 Mem_Strap0 7
AGP _AD17 AD16 GPIO16 ROMC S#
N29 AH5 ROMCS# 8
AGP _AD18 AD17 ROMCSb DVOMO DE
N28 AE10 R1278
AGP _AD19 AD18 DVOMODE
P29 AF5 +VDDC_CT
AGP _AD20 AD19 ZV_LCDDATA0 R986
P28 AE6
AGP _AD21 AD20 ZV_LCDDATA1 10K DNI
R29 AF6
AGP _AD22 AD21 ZV_LCDDATA2
R28 AE7
AGP _AD23 AD22 ZV_LCDDATA3
T28 AG6 24bit-SDR-DVO
AGP _AD24 AD23 ZV_LCDDATA4
V29 AF7
AGP _AD25 AD24 ZV_LCDDATA5
V28 AG8
AGP _AD26 AD25 ZV_LCDDATA6
W29 AF8
AGP _AD27 AD26 ZV_LCDDATA7
W28 AE8
AGP _AD28 AD27 ZV_LCDDATA8
Y29 AE9
AGP _AD29 AD28 ZV_LCDDATA9
Y28 AF9
AGP_C/BE# [3..0] AGP _AD30 AD29 ZV_LCDDATA10
1 AGP_C/BE#[3..0] AA29 AG9
AGP _AD31 AD30 ZV_LCDDATA11 VID/DVO 12
AA28 AK7 DC_Strap1 8
R36 0R AD31 ZV_LCDDATA12 VID/DVO 13
1 AGP_AGP/PCICLK AJ7 DC_Strap2 8
AGP_ C/BE#0 ZV_LCDDATA13 VID/DVO 14
P27 AH8 DC_Strap3 8
AGP_ C/BE#1 C/BEb0 ZV_LCDDATA14 VID/DVO 15
C73 V25 AJ8 DC_Strap4 8
D N I/22pF AGP_ C/BE#2 C/BEb1 ZV_LCDDATA15 VID/DVO 16
M29 AH9 LCDDATA16 7
AGP_ C/BE#3 C/BEb2 ZV_LCDDATA16 VID/DVO 17
T29 AJ9 LCDDATA17 7
C/BEb3 ZV_LCDDATA17 VID/DVO 18
AK9 PAL/NTSC 8
ZV_LCDDATA18 VID/DVO 19
AF29 AH10
PCICLK ZV_LCDDATA19 VID/DVO 20 DC_Strap5 8,13
AG30 AK10 LCDDATA20 7
1 AGP_RESET# RSTb ZV_LCDDATA20
AE29 AJ10
1 AGP_REQ# REQb ZV_LCDDATA21
AG28 AH11
C 1 AGP_GNT# GNTb ZV_LCDDATA22 C
J29 AJ11
1 AGP_PAR PAR ZV_LCDDATA23

PCI/AGP
J28
1 AGP_STOP# STOPb
1 AGP_DEVSEL# K29 AK6
DEVSELb ZV_LCDCNTL0
1 AGP_TRDY# K28 AJ6
TRDYb ZV_LCDCNTL1
1 A G P _IRDY# L29 AH6
IRDYb ZV_LCDCNTL2
1 AGP_FRAME# L28 AH7
FRAMEb ZV_LCDCNTL3
1 AGP_INTR# AF28
INTAb
AE15
NC35
1 AGP_WBF# AF27 AF15
WBFb NC27
1 AGP_RBF# AE16
NC36
1 AGP_AD_STB0 AJ26 AF16
NC19 NC28
1 AGP_AD_STB1 AH25 AG15
NC18 NC37
1 AGP_SB_STB AC29 AH15
RBFb NC29
P25 AH16
AGP_SB A[7..0] AD_STBF0 NC39
1 AGP_SBA[7..0] U29 AH17
AD_STBF1 NC31
AB26 AF17
SB_STBF NC38
AG17
AG P_SBA0 NC30
AE27 AJ17
AG P_SBA1 SBA0 NC22
AD26 AH18
AG P_SBA2 SBA1 NC13
AC25 AK18
AGP2X

AG P_SBA3 SBA2 NC23

AC26 AJ18
AG P_SBA4 SBA3 NC14
AA25 AG19
AG P_SBA5 SBA4 NC24
AA26 AH19
AGP_ ST[2..0] AG P_SBA6 SBA5 NC15
Y25 AJ16
NCS

1 AGP_ST[2..0] SBA6 NC26

AG P_SBA7 Y26 AK16
SBA7/IDSEL NC17
AH20
AGP_ST0 NC25
AD28 AJ20
AGP_ST1 ST0 NC16
AD29 AF11
AGP_ST2 ST1 NC7
AC28 AE12
ST2 NC8

1 AGP_AGPREFCG 1 AGP_SB_STB# AB25 AF10

SB_STBS
AGP4X/8X

B DPLUS S T EREOSYNC TDO TP1 B

1 AGP_AD_STB0# P26 AE11
C20 AD_STBS0 DMINUS VGADDCDATA TDI TP2 O P T ION BOUNDARY
1 AGP_AD_STB1# U28 TP
100nF AD_STBS1 V G ADDCCLK TMS TP3 SCAN WITH TESTEN
H29 AJ13 TMDS_TX0N 14 TP
AGPREF TX0M VS YNC TCK TP4
H28 AH13
TMDS

1 AGP_AGPTEST AGPTEST TX0P TMDS_TX0P 14 TP

AG27 AJ14 TESTEN TRST TP5
TP
1 AGP_MB_8X_DET# AGP8X_DETb TX1M TMDS_TX1N 14
1 AGP_DBI_HI AB28 AH14 TMDS_TX1P 14 TP
DBI_HI TX1P
1 AGP_DBI_LO AB29 AJ15 TMDS_TX2N 14
DBI_LO TX2M
AK15 TMDS_TX2P 14
TP8 R40 715R TX2P
AJ21 AK12 TMDS_TXCN 14
R2SET TXCM
13 A _R/C_DAC2 TP AJ22 AK13 TMDS_TXCP 14
GND_R2SET C_R TXCP
13 A _G/Y_DAC2 AK22
Y_G
AK21 AF13
DAC2

13 A_B/COMP_DAC2 COMP_B DVIDDCCLK D V I D DCCLK 13

12,13 A _ H S YNC_DAC2 AG25 AE13 D V I DDCDATA 13
H2SYNC DVIDDCDATA
13 A _ VSYNC_DAC2 AF25
V2SYNC
AF12 C HARGE_POW 14
R1198 D NI/4.7K HPD
+3.3V_BUS AF23
R1199 D NI/4.7K CRT2DDCCLK
AG24 AK25 A_R_DAC1 11
CRT2DDCDAT R
AJ25 A_G_DAC1 11
G
AK24 A_B_DAC1 11
B
AG29 AH28
SSC

NC34 HSYNC A _ H S YNC_DAC1 11

AH29 AH27 VS YNC
NC33 VSYNC A _ VSYNC_DAC1 11
DAC1

AJ23 R 39 499R TP7

RSET
TP
AJ28
CLK

XTALIN GND_RSET
AJ29
XTALOUT VGADDCDATA
AG26 CRT1DDCDATA 11
VGADDCDATA V G ADDCCLK
AF26 C R T1DDCCLK 11
TESTEN VGADDCCLK
AH26
C1205 27pF TESTEN
A A

Y2
AJ27
STEREOSYNC AUXWIN
AE25
TP10 Some Part Ref's updated to 988 brd
1

27_MHZ TP
3 R1115 RV280
1M ATI Technologies Inc.
R 33 1 Commerce Valley Drive East
2

1K S T EREOSYNC Markham, Ontario

S T EREOSYNC 7
O SC_IN C1206 27pF Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number R ev
C u stom 81-105-L31020 1.0
Date: Thursday, November 20, 2003 Sheet 2 of 14
8 7 6 5 4 3 2 1
 5 4 3 2 1

D D

MEMORY CHANNEL A MEMORY CHANNEL B

QSA[7..0]
9 QSA[7..0]
DQMA#[7..0]
9 DQMA#[7..0]
MAA[13..0]
9 MAA[13..0]
MDA[63..0]
9 MDA[63..0]

U1B U1C
MDA0 G29 B24 MAA0 B6 J2
MDA1 DQA0 Part 2 of 5 AA0 MAA1 DQB0 Part 3 of 5 AB0
G30 A24 C6 K3
MDA2 DQA1 AA1 MAA2 DQB1 AB1
F28 B23 B5 K2
MDA3 DQA2 AA2 MAA3 DQB2 AB2
F30 C23 C5 L3
MDA4 DQA3 AA3 MAA4 DQB3 AB3
E29 B21 B2 L2
MDA5 DQA4 AA4 MAA5 DQB4 AB4
D28 F21 C3 M3
MDA6 DQA5 AA5 MAA6 DQB5 AB5
D29 E21 C2 M2
MDA7 DQA6 AA6 MAA7 DQB6 AB6
D30 F20 D2 N5
MDA8 DQA7 AA7 MAA8 DQB7 AB7
K25 E20 E8 M1
MDA9 DQA8 AA8 MAA9 DQB8 AB8
K26 C21 E7 M5
MDA10 DQA9 AA9 MAA10 DQB9 AB9
J25 B22 D4 N3
MDA11 DQA10 AA10 MAA11 DQB10 AB10
J26 C22 D3 P2
C MDA12 DQA11 AA11 MAA12 DQB11 AB11 C
G28 A25 F6 P6
MDA13 DQA12 AA12 MAA13 DQB12 AB12
G25 C24 F3 P5
MDA14 DQA13 AA13 DQB13 AB13
G26 F5
MDA15 DQA14 DQMA#0 DQB14
G27 E28 G6 A4
MDA16 DQA15 DQMAb0 DQMA#1 DQB15 DQMBb0
C29 H26 D1 E3

MEMORY INTERFACE B
MDA17 DQA16 DQMAb1 DQMA#2 DQB16 DQMBb1
B29 A27 E2 G3
MDA18 DQA17 DQMAb2 DQMA#3 DQB17 DQMBb2
B28 E24 F2 J5
MDA19 DQA18 DQMAb3 DQMA#4 DQB18 DQMBb3
C27 B15 F1 W2
MDA20 DQA19 DQMAb4 DQMA#5 DQB19 DQMBb4
C26 E16 G2 AC3
MEMORY INTERFACE A

MDA21 DQA20 DQMAb5 DQMA#6 DQB20 DQMBb5

B26 C11 H3 W6
MDA22 DQA21 DQMAb6 DQMA#7 DQB21 DQMBb6
C25 E11 H2 AC6
MDA23 DQA22 DQMAb7 DQB22 DQMBb7
B25 J3
MDA24 DQA23 QSA0 DQB23
E26 F29 G4 B4
MDA25 DQA24 QSA0 QSA1 DQB24 QSB0
F25 H25 H6 E5
MDA26 DQA25 QSA1 QSA2 DQB25 QSB1
E25 B27 H5 G1
MDA27 DQA26 QSA2 QSA3 DQB26 QSB2
F24 F23 J6 K6
MDA28 DQA27 QSA3 QSA4 DQB27 QSB3
E23 C15 K5 W1
MDA29 DQA28 QSA4 QSA5 DQB28 QSB4
D22 F16 K4 AD2
MDA30 DQA29 QSA5 QSA6 DQB29 QSB5
F22 B11 L6 V5
MDA31 DQA30 QSA6 QSA7 DQB30 QSB6
E22 F10 L5 AC5
MDA32 DQA31 QSA7 DQB31 QSB7
C17 U2
MDA33 DQA32 RASA# DQB32
B17 A19 RASA# 9 V2 R2
MDA34 DQA33 RASAb DQB33 RASBb
C16 V1
MDA35 DQA34 CASA# DQB34
B16 C18 CASA# 9 V3 T5
MDA36 DQA35 CASAb DQB35 CASBb
C14 W3
MDA37 DQA36 WEA# DQB36
B14 F18 WEA# 9 Y2 T6
MDA38 DQA37 WEAb DQB37 WEBb
C13 Y3
MDA39 DQA38 CSA#0 DQB38
B13 E19 CSA#0 9 AA2 R5
MDA40 DQA39 CSAb0 DQB39 CSBb0
E18 AA3
MDA41 DQA40 CSA#1 DQB40
F17 F19 CSA#1 9 AB2 R6
MDA42 DQA41 CSAb1 DQB41 CSBb1
E17 AB3
MDA43 DQA42 CKEA DQB42
D16 B19 CKEA 9 AC2 R3
MDA44 DQA43 CKEA DQB43 CKEB
F15 AD1
MDA45 DQA44 DQB44
E15 AD3 N1
MDA46 DQA45 DQB45 CLKB0
F14 AE1 N2
MDA47 DQA46 CLKA0 DQB46 CLKB0b
E14 C20 CLKA0 9,10 AE2
MDA48 DQA47 CLKA0 CLKA#0 DQB47
A13 B20 CLKA#0 9,10 U6 T2
MDA49 DQA48 CLKA0b DQB48 CLKB1
C12 U5 T3
B MDA50 DQA49 CLKA1 DQB49 CLKB1b B
A12 B18 CLKA1 9,10 U3
MDA51 DQA50 CLKA1 CLKA#1 DQB50
B12 A18 CLKA#1 9,10 V6 P3
MDA52 DQA51 CLKA1b DQB51 CLKBFB TP12
C10 W5
MDA53 DQA52 DQB52 TP
B10 C19 W4
MDA54 DQA53 CLKAFB TP11 DQB53
C9 Y6
MDA55 DQA54 TP DQB54 +VDDC_CT
B9 Y5
MDA56 DQA55 +VREF DQB55 R51 4.7K
E13 AA6 B7
MDA57 DQA56 DQB56 MEMVMODE R52 DNI/4.7K
F12 B8 AA5 C7
MDA58 DQA57 VREF DQB57 MEMVMODE1
E12 AB6
MDA59 DQA58 DQB58
F11 F26 AB5 G5
MDA60 DQA59 DIMA0 DQB59 DIMB0 R53 R54
E10 F13 AD6 AE3
MDA61 F9
DQA60 ELPIDA DIMA1
AD5
DQB60 ELPIDA DIMB1 4.7K DNI/4.7K
MDA62 E9
DQA61 Vref Voltage AE5
DQB61
C8
MDA63 DQA62 DQB62 MEMTEST
F8 AE4
DQA63 +MVDDQ DQB63
RV280 RV280 R55
47R

Re6 R265
499R_1%

+VREF

Re7 R268
499R_1%
MEMVMODE[1:0] MEMORY IO VOLTAGE

01 2.5V (DDR) Default

10 1.8V (DDR)
Place close to ASIC ball
Use localized Vref on the memory page 11 3.3V (SDR)

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number Rev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 3 of 14
5 4 3 2 1
 5 4 3 2 1

+3.3V_BUS

+VDDC

1
D30
U1D +VDDC 2.4V
P18 AC13 +VDDC
VDDC Part 4 of 5 VDDC
P19 AC15

42
VDDC VDDC

3
U12 AC17
VDDC VDDC
U13 AD13
VDDC VDDC C23
U14 AD15
VDDC VDDC CP9A CP9B CP9C CP9D CP3A CP3B CP3C CP3D CP4A CP4B CP4C CP4D CP2A CP2B CP2C CP2D 10uf
U17 M12

5
VDDC VDDC 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
U18 M13
D VDDC VDDC U1E D
U19 M14
VDDC VDDC
V12 M17 F27 U15
VDDC VDDC At the corner of VDDC plane VSS Part 5 of 5 VSS
V13 M18 F7 U16
VDDC VDDC VSS VSS
V14 M19 G12 U23
VDDC VDDC +VDDC VSS VSS
V17 N12 G16 U4
VDDC VDDC VSS VSS
V18 N13 G21 U8
VDDC VDDC VSS VSS
V19 N14 G24 V15
VDDC VDDC C26 C27 C28 C29 C30 VSS VSS
W12 N17 G9 A10
VDDC VDDC 100nF 100nF 100nF 100nF 100nF VSS VSS
W13 N18 H12 A16
VDDC VDDC VSS VSS
W14
VDDC VDDC
N19 X7R X7R X7R X7R X7R H14
VSS VSS
A2
W17 P12 H16 A22
VDDC VDDC VSS VSS
W18 P13 H18 A29
VDDC VDDC VSS VSS
W19 P14 H21 AA27
VDDC VDDC VSS VSS
P17 H23 AA30
+MVDDQ VDDC +MVDDQ +3.3V_BUS VSS VSS
H27 AB1
VSS VSS
H10 A15 H4 AB23
VDDR1 VDDR1 VSS VSS

2
H13 Memory I/O Power A21 H8 AB24
VDDR1 (1.8V/2.5V/3.3V) VDDR1 VSS VSS
H15 AA7 H9 AB4
VDDR1 VDDR1 C44 VSS VSS
H17 AA8 K1 AB7
VDDR1 VDDR1 CP1A CP1B 100nF VSS VSS
H19 D11 K23 AB8

7
VDDR1 VDDR1 10nF 10nF VSS VSS
H22 D14 K24 AC12
VDDR1 VDDR1 VSS VSS
J1 D17 K30 AC14
VDDR1 VDDR1 VSS VSS
J23 D8 K7 AC16
VDDR1 VDDR1 VSS VSS
J24 V4 K8 AC18
VDDR1 VDDR1 VSS VSS
J27 L4 AC27

I/O POWER
VDDR1 VSS VSS
J4 A28 M15 AC4
VDDR1 VDDR1 VSS VSS

CORE GND
J7 A3 M16 AD12
VDDR1 VDDR1 VSS VSS
J8 A9 M27 AD16
VDDR1 VDDR1 +MVDDQ +MVDDQ VSS VSS
L8 AA1 M30 AD18
VDDR1 VDDR1 VSS VSS
M4 AA4 M7 AD25
VDDR1 VDDR1 VSS VSS

4
N4 AD4 M8 AD30
VDDR1 VDDR1 VSS VSS
N7 B1 N15 AE26
VDDR1 VDDR1 C38 C39 VSS VSS
N8 B30 N16 AE28
VDDR1 VDDR1 CP5A CP5B CP5C CP5D CP6A CP6B CP6C CP6D 10uf 10uf VSS VSS
R1 D10 N23 AG11

5
VDDR1 VDDR1 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF VSS VSS
R4 D19 N24 AG16
VDDR1 VDDR1 VSS VSS
VDDRH0 - CH A Clock Power
VDDRH1 - CH B Clock Power
T4 D20 P15 AG18
VDDR1 VDDR1 VSS VSS
T7 D23 P16 AG21
VDDR1 VDDR1 PLACE DIRECTLY VSS VSS
T8 D26 P4 AG5
C VDDR1 VDDR1 VSS VSS C
D6 UNDERNEATH CHANNEL R12 AG7
VDDR1 +MVDDQ VSS VSS
V7 A & B SECTION OF ASIC. R13 AJ1
VDDR1 VSS VSS
V8 R14 AJ30
VDDR1 +MPVDD VSS VSS
E27 R15 AK2
VDDR1 C32 C33 C34 C35 VSS VSS
F4 G19 R16 AK29
VDDR1 VDDRH0 100nF 100nF 100nF 100nF VSS VSS
G10 N6 R17 B3
VDDR1 VDDRH1 VSS VSS
(VDDR1)

G13
VDDR1
X7R X7R X7R X7R R18
VSS VSS
C1
G15 G18 C51 C52 R19 C28
+3.3V_BUS VDDR1 VSSRH0 100nF 4.7uF VSS VSS
G22 M6 R23 C30
VDDR1 VSSRH1 VSS VSS
G7
VDDR1
X7R >=6.3V R24
VSS VSS
C4
Ceramic R27 D12
VSS VSS
1

MPLL
(1.8V) (1.8V)

A7 R30 D13
D31 MPVDD GND_MPVSS +PVDD +VDDC_CT VSS VSS
A6 R7 D15
+VDDC_CT MPVSS VSS VSS
2.4V R8 D18
VSS VSS

4
AK27 T1 D21
PVDD VSS VSS
PLL

Y23 AK28 T12 D24

2

VDDC18 PVSS VSS VSS

(1.8V)
I/O level shift power

L23 C53 C54 C83 T13 D25

C55 C56 VDDC18 100nF 4.7uF CP1C CP1D 100nF VSS VSS
H20 AC10 T14 D27

5
VDDC18 VDDR4 VSS VSS
DVO Power
(1.8V/3.3V)

X7R >=6.3V X7R

Ext. TMDS/

47uF_6.3V 100nF H11 AC9 10nF 10nF T15 D5

VDDC18 VDDR4 VSS VSS
>=6.3V X7R P8
VDDC18 VDDR4
AD10 Ceramic T16
VSS VSS
D7
Y8 AD9 T17 D9
VDDC18 VDDR4 +3.3V_BUS C1215 GND_PVSS VSS VSS
AC11 AG10 T18 E4
VDDC18 VDDR4 B733 B734 VSS VSS
AC20 AD22 T19 E6
VDDC18 VDDR3 1uF 220 DNI VSS VSS
AC22 W23 V16
VDDR3 VSS VSS
TMDS I/O Power

AC21 W24 V27

VDDR3 VSS VSS
AK19 AD21 W25 V30
NC VDDR3 VSS VSS
GPIO & Ext.

AE19 AC19 +3.3V_BUS +VDDC_CT W26 W15

VDDC18 VDDR3 VSS VSS
AE20 AD19 W7 W16
VDDC18 VDDR3 VSS VSS
(3.3V)

AF20 AD7 W8
+TPVDD NC VDDR3 VSS
AG20 AC8 Y4
NC VDDR3 +VDDQ_BUS VSS
AA23
VDDP +VDDQ_BUS +VDDQ_BUS RV280
AJ19 AA24
C57 C58 NC VDDP
AF18 AB27
NC VDDP

4
4.7uF 100nF AF19 AB30
NC VDDP
>=6.3V X7R AE18
NC VDDP
AC23 C45 C46 C47 C48 C49
Ceramic AE17 AD27 100nF 100nF 100nF 100nF 100nF
NC VDDP
GND_TPVSS AE30 X7R X7R X7R X7R X7R CP8A CP8B CP8C CP8D

5
VDDP
(1.8V)
TMDS PLL

B AH30 10nF 10nF 10nF 10nF B

VDDP
AJ12 J30
TPVDD VDDP
AGP Bus I/O Power

AH12 M23
TPVSS VDDP
M24
AF14
TXVDDR
VDDP
VDDP
N27 Distributed around
(1.5V/3.3V)

+VDDC_CT AE14 N30

TXVDDR VDDP
B16 200R
VDDP
P23
+VDDQ_BUS plane
(1.8V)
TMDS I/O

T23
C59 C60 C77 VDDP
T24
4.7uF DNI/100pF 100nF VDDP
AG14 T27
TXVSSR VDDP
>=6.3V X7R X7R AG13
TXVSSR VDDP
T30
Ceramic AG12 V23
TXVSSR VDDP
V24
+A2VDD VDDP
W27
Analog Display Power, VDDP
AF21 W30
A2VDD VDDP +VDDC_CT
AF22 see table below Y27
C61 C62 +A2VDDQ A2VDD VDDP
22uF_10V 100nF AH21 AH24 B17 200R
A2VDDQ AVDDDI
X7R AF24
AVDD A2VDDDI
AH23
C63 C64 +AVDD AE23 TP9 C65 C66
4.7uF 100nF AVDD TP 100nF 4.7uF
GND_A2VSSN X7R AE21
A2VSSN AVSSQ
AJ24 X7R >=6.3V
C67 C68 AE22 AG23 Ceramic
4.7uF 100nF A2VSSN AVSSDI
AG22 AD24
A2VSSDI AVSSN
GND_A2VSSQ X7R AH22
A2VSSQ AVSSN
AE24
GND_AVSSQ

GND_AVSSN RV280
GND_AVSSN
GND_A2VSSN

GND_A2VSSQ

+AVDDDI
Pin Names +AVDD Matching +A2VDD Matching +A2VDDQ Matching +A2VDDDI Matching
Ground Ground Ground Ground
Voltage 1.8V 2.5V 1.8V 1.8V
A AVSSN A
Usage DAC1 VDD (80mA) (Noisy) A2VSSN A2VSSQ Digital Power for AVSSDI
AVSSQ DAC2 VDD (120mA) (Noisy) DAC2 Band Gap Ref. (Quiet) DAC1 and DAC2 A2VSSDI
DAC1 Band Gap Ref. (Quiet) (Digital)

Board power AVDD sourced from VDDC_CT (1) A2VDD regulated source Source from AVDD thru bead. Source from VDDC_CT
and ground thru bead at least 15 mil trace and A2VSSN return path routed A2VSSQ with sigle via to GND thru bead
option(s) and not longer than 1.5 inch. with at least 15 mil trace and close to the pin. ATI Technologies Inc.
AVSSN and AVSSQ with single not longer than 1.5 inch.
via to GND close to the pin. AVSSN with single via to GND 1 Commerce Valley Drive East
at the regulator. Markham, Ontario
Canada, L3T 7N6
(2) Sourced from VDD thru bead (905) 882-2600
instead of the regulator
Title
R9200L-64TD
Size Document Number Rev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 4 of 14
5 4 3 2 1
 8 7 6 5 4 3 2 1

Cout1 470uF thru hole capacitor (P/N 4051047700)

D Regulator for VDDC (ASIC Core) has 30mR ESR where as 470uF SMT (P/N D

4262047700) capacitor has 150mR ESR. For

Vin = 3.3V AGP current below 4.5A, 1 thru 470uF is enough.
Vout = 1.5V ~ 1.62V
Iout = 4A MAX (load consumption) *** Indicate number of via required for the
Iout = 2.5A MAX (Power rail consumption) connection

+3.3V_BUS

***

2
These dummy resistors are placed
D12 D13 under the diodes to avoid PCB heat
1N5400 1N5400 damage due to hot diodes.

1
C C
R554 R553 R552 R551
*** 0R 0R 0R 0R
C102
1.0uF C101
470uF_16V

***

4
Q21
+12V_BUS MTD3055V +VDDC
+3.3V_BUS 2 3

*** *** **
C106 C106A C107 C107A C108

1
R255 C104 C103
33_0805 1uF_0805 * * 0.1uF D NI D NI 1000uF_10V DNI 10uF_10V

8
R253 **
R254
3 + 1.07K_1% *** ***
1
2 -
R257 U28A 0_0805
COPPER
2

249_1% LM358

4
C105 * SO8 R256
B 1uF REG27 1 3.48K_1% B
* 431L
R258 *
DNI
3

* * VREF125 6

A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title R9200L-64TD
Size Document Number R ev
B 81-105-L31010 1.0
Date: Monday, October 20, 2003 Sheet 5 of 14
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Regulator for VDDC_CT (Core Transform) Regulator for MVDDQ (MEM IO) and VDDR1
and AVDD/A2VDDQ/AVDDDI/A2VDDDI Regulator for MVDDC
TXVDDR, LVDDRx, MPVDD
Vin = 5V
Vin = 3.3V AGP Vin = 3.3V AGP
Vout = 1.8V Vout = 2.5V (TSOP) +3.3V_BUS
Vout = 3.4V 2A MAX SP1
Iout = 350mA + 100mA + 50mA = 500mA MAX Iout = 1200mA MAX 1 2

D
Iout = 600mA MAX (with PVDD/TPVDD) Iout = 1000mA Est. MAX DNI D

Rct1 Rct2 +5V_BUS

1.8V 422R 3240422000 603 U97 AMS1085_TO252

1K 3240100100 603 +MVDDC
1.9V 499R 3240499000 603 Q25 Pin2/4 should be soldered to board for 3 2

ADJ
IN OUT
heat dissipation and a GND fill area. ** ** **
C1035 C1033 C1034 C119
Placed close to C1036 DNI/100nF 330uF_6.3V

1
DNI/22uF_16V 100nF ** ** DNI/22uF_16V
+3.3V_BUS
+MVDDQ
+MVDDQ output **
R958
121_1%
for EMI

4
Q25
MTD3055V
+3.3V_BUS +VDDC_CT 2 3 +MVDDQ C1214 C1037 R960 COPPER
DNI/47uF_6.3V 0.1uF 191_1%
+12V_BUS C127
C130 330uF_6.3V C133

1
REG22 DNI/47uF_6.3V C132 100nF
LT1117CST 100nF C136 X7R
3 2 C126 X7R 100nF R277/.25W
IN OUT 47uF_6.3V 470R Placed close to
ADJ

4
CASE

3
REG23 MRG23
R279
4.75K_1%
+VDDC output for EMI +MVDDQ
SP2
+MVDDC
1

C131 R282 1 431L 4 SC431LC5SK-1 Rq1 1 2

100nF 1.00K
NC
Rct1 1
X7R 1% R281 2 ALT
NC

2K R283
DNI

5
4.64K_1%
Rq2
R278 Rct2
422R
1% 442--->R9200L-128TD

C C

Regulator for PVDD (Core PLLs) Regulator for MPVDD (Memory PLLs) Regulator For TPVDD (TMDS PLLs) Regulator For A2VDD (2nd DACs)
and optional TPVDD (TMDS PLLs)

Vin = 3.3V AGP Vin = 3.3V AGP Vin = +3.3V AGP Vin = +3.3V AGP
Vout = +1.8V Vout = +1.8V Vout = 1.8V Vout = 2.5V A2VDD might not be
TPVDD might not be needed if VDD can
Iout = 25mA MAX (PVDD only) Iout = 10mA MAX Iout = 15mA MAX needed if PVDD can Iout = 150mA MAX provide stable 2.5V
Iout = 30mA MAX (PVDD + TPVDD) provide stable 1.8V

(Optional) (Optional)
B B
+3.3V_BUS +PVDD +VDDC_CT +3.3V_BUS +MPVDD +VDDC_CT +TPVDD +VDDC_CT
+3.3V_BUS +A2VDD
Q2
R284 B23 R285 B24 B25 2N2222
DNI/33R 200R DNI/33R 200R DNI/200R 3 2
PVDD_VDDC18 MPVDD_VDDC18 TPVDD_PVDD

Rvdd R287 Rvdd R288 C139

1
2

DNI/681R DNI/681R TPVDD = TPVDD + LPVDD + TXVDDR 100nF

REG25 1% REG26 1%
1 PVDD 4 MRG25 C1207 1 MPVDD 4 MRG26 C1208 R259
U28B
DNI/AS432S 1 NC SC431LC5SK-1 100nF DNI/AS432S 1 NC SC431LC5SK-1 100nF 0
PVDD R290 2 NC MPVDD R291 2 NC
5 + C138
5 VREF125
DNI/1.5K ALT 1.5K ALT 7 R260 0.1uF
3

Rvdd 1% Rvdd 1% 6 1.02K_1%

PVDD MPVDD Regulator for TPVDD (TMDS PLLs) -
LM358

GND_PVSS GND_MPVSS
3
Vin = 3.3V AGP R261 2N2222
1K_1%
The value of resistor were chosen to reduce failure rate caused by Vout = +1.62V 1 2
possible defective regulators, i.e., 33R are used instead of 47R or Iout = 10mA MAX
51R for more start up current. (3.465V - 1.8V) / 33R = 50.5mA 15mA Estimeatd MAX GND_A2VSSN

805 package resistor are required for sufficient power rating

(0.1W rating). (3.465V - 1.8V) * 50.5mA = 0.085W; therefore,
smaller resistor value would require 1206 package +3.3V_BUS +TPVDD
A2VDD and A2VSSN routed with at least 15
R1325 mil trace and not longer than 1.5 inch.
AVDD/A2VDDQ (1st DAC & 2nd DAC Band Gap) 33R A2VSSN with signle via to GND at the
regulator
+VDDC_CT +AVDD +A2VDDQ Rvdd R1326
2

A REG29 432R_1% A
B27 200R 431L
COMMON 1 TPVDD
B29 200R
COMMON +TPVDD R1327 C1259
1.4K_1% 100nF Some Part Ref's updated to 988 brd
3

Rvdd <Variant Name>

TPVDD
ATI Technologies Inc.
GND_TPVSS 1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600

Title R9200L-64TD
Size Document Number 81-105-L31020 Rev
Custom 1.0
Date: Tuesday, November 25, 2003 Sheet 6 of 14
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

+3.3V_BUS

2,8 GPIO[13..0]
GPIO[13..0] OPTION STRAPS
GPIO0 STRAP G R201 DNI/10K
D NI

R202 10K STRAPS P IN DESCRIPTION DEFAULT

GPIO1 STRAP H R203 DNI/10K

D NI
AGPFBSKEW(1:0) GPIO(1:0) AGP 1x clock feedback phase adjustment wrt refclk(cpuclk) 00
R204 10K 00 - refclk slightly earlier then feedback
D D
01 - refclk 1 tap earlier then feedback (internal pull-down)
GPIO2 STRAP J R205 DNI/10K
D NI 10 - refclk 1 tap later then feedback
11 - refclk 2 taps earlier then feedback clock
R206 10K

GPIO3 STRAP K R207 DNI/10K

D NI X1CLK_SKWE(1:0) GPIO(3:2) Clock phase adjustment between x1 clk and x2clk 00
00 - 0 ta p delay
R208 10K 01 - 1 tap delay (internal pull-down)
10 - 2 taps delay
GPIO11 STRAP L R209 10K 11 - 3 taps delay

R210 DNI/10K
ROMIDCFG(3:0) GPIO(9,13:11) If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type 1100
GPIO12 STRAP M R211 10K 0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
R212 DNI/10K 0100 - reserved
0110 - reserved
GPIO13 STRAP N R213 DNI/10K 1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
R214 10K 1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P05/10 ROM (ST), chip IDis from ROM
GPIO9 STRAP O R215 10K 1100 - Reserved
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
R216 DNI/10K
C C

ID_DISABLE GPIO(8) 0 - Norm al operation 0

GPIO8 STRAP A R217 DNI/10K 1 - Shuts the chip down by not responding to any config cycles
In a system with two graphics chips, one on the motherboard, (internal pull-down)
R218 10K the other on add-in card, the strap can be used to disable one of the two throught a jumper.

GPIO4 STRAP D R219 DNI/10K BUSCFG(2:0) GPIO(6:4) Controls bus type, CLK PLL select, and IDSEL 000
000 - 1.5V BUS -> AG P 4x, PLL clk, IDSEL=AD16
R220 10K 000 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16 (internal pull-down)
001 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD17
GPIO5 STRAP E R221 DNI/10K 001 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
010 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
R222 10K 010 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
011 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
GPIO6 STRAP F R223 DNI/10K 011 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
100 - PCI 66MHz, PLL clk
R224 10K 101 - PCI 33MHz, 3.3v, REF clk
110 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD16
110 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD16
GPIO7 STRAP B R225 DNI/10K 111 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD17
111 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD17
R226 10K Note that for AGP configurations GPIO(4) acts as the IDSEL strap.
B For PCI it acts as the PLL bypass (33 or 66MHz) strap. B

STRAP R R227 DNI/10K

2 LCDDATA16
VGA_DISABLE GPIO(7) 0 - VGA controller capabillit y enabled. 0
R228 10K 1 - The device will not be recognized as the systemis VGA controller.

STRAP S R229 10K

2 LCDDATA17
MULTIFUNC(1:0) LCDDATA(17:16) Multi-function device select 10
R230 DNI/10K 00 - single function device.
01 - two function device. No AGP in either function
10 - two function device. AGP only in function 0
STRAP T R231 10K 11 - two function device. AGP in both functions
2 LCDDATA20
If BUSCFG pin based straps are set to PCI, then AGP will not be enabled in any function.
R232 DNI/10K See AGP function table below for detail on AGP ability claims.

STRAP P R233 DNI/10K VIP_DEVICE LCDDATA(20) Indicates if any slave VIP host devices drove this in low during reset. 0
2 STEREOSYNC
STRAP T 0 - Slave VIP host port devices present
R234 10K 1 - No slave VIP host port devices reporting presence during reset

R235 DNI/10K
2 Mem_Strap0 <Variant Name>
STRAP P INTERRUPT
R236 10K
A LOW ENABLED (DEFAULT) ATI Technologies Inc. A
R237 DNI/10K 1 Commerce Valley Drive East
2 Mem_Strap1
HI GH DISABLED Markham, Ontario
R238 10K Canada, L3T 7N6
(905) 882-2600
R239 DNI/10K
2 Mem_Strap2
Title R9200L-64TD
R240 10K
Size Document Number 81-105-L31020 R ev
B 1.0
Date: Monday, October 20, 2003 Sheet 7 of 14

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

SERIAL EEPROM BIOS

D D
ROMCS#
2 ROMCS#
GPIO[13..0]
2,7 GPIO[13..0]
U11
GPIO9 5 2 GPIO8
D Q
GPIO10 6 C
1 S
+3.3V_BUS
7 HOLD
3 W
8 VCC VSS 4

C80 M25P05-VMN6T
100nF PM25LV512-25SC
X7R

C C

STRAPS P IN DESCRIPTION
Daughter Card Straps +3.3V_BUS
+3.3V_BUS DC_STRAP1 LCDDATA12 Internal TMDS Enabled
0 - Disabled
R582 10K R584 10K 1 - Enabled
R578 DNI/10K R580 10K
R574 10K R576 DNI/10K
DC_STRAP2 LCDDATA13 Video Capture Enabled
B 0 - Disabled B
1 - Enabled
2,13 DC_Strap5 PAL/NTSC 2
2 DC_Strap3 DC_Strap4 2
2 DC_Strap1 DC_Strap2 2 DC_STRAP4 DC_STRAP5 LCDDATA15 LCDDATA19 DAC2 Configuration

0 0 DAC2 Off
R575 DNI/10K R577 10K 0 1 DAC2 On as CRT
R579 DNI/10K R581 DNI/10K 1 0 DAC2 On as TVOUT
R583 DNI/10K R585 DNI/10K 1 1 DAC2 On as TVOUT and CRT

DC_STRAP6 LCDDATA18 TVO Standard Default (Resistor pull-up and switch short to GND)

0 - PAL (on board resistor pull-down and switch closed)

1 -NTSC (on board resistor pull-up)

A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number R ev
B 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 8 of 14
8 7 6 5 4 3 2 1
 5 4 3 2 1

MDA[63..0] M_MDA[63..0]
TERMINATION FOR
MEMORY
3 MDA[63..0] M_MDA[63..0] 10
CLOCK
MDA0 RP117D 4 5 56R M_MDA0
CHANNEL A MDA1
MDA2
MDA3
RP117C
RP117B
RP117A
3
2
6
7
56R
56R
56R
M_MDA1
M_MDA2
M_MDA3
terminations
1 8
MDA4 RP118D 4 5 56R M_MDA4 Change from 1:1 spacing to at least a
MDA5 RP118C 3 6 56R M_MDA5
MDA6 RP118B 2 7 56R M_MDA6 2.5:1 spacing between the pair
MDA7 RP118A 1 8 56R M_MDA7
MDA8 RP119D 5 4 56R M_MDA8 These resistors and caps must be placed to minimize any stubs. These
MDA9 RP119C 6 3 56R M_MDA9 must also be placed after the memory
MDA10 RP119B 7 2 56R M_MDA10
MDA11 RP119A 8 1 56R M_MDA11
D MDA12 RP120A 1 8 56R M_MDA12 D
MDA13 RP120B 2 7 56R M_MDA13
MDA14 RP120C 3 6 56R M_MDA14
MDA15 M_MDA15 3,10 CLKA0
RP120D 4 5 56R
MDA16 RP121D 4 5 56R M_MDA16 M_CLKA0
MDA17 RP121C 3 6 56R M_MDA17
MDA18 RP121B 2 7 56R M_MDA18
MDA19 M_MDA19 M_CLKA0 3,10
RP121A 1 8 56R R797
MDA20 RP122D 4 5 56R M_MDA20 56R
MDA21 RP122C 3 6 56R M_MDA21
MDA22 RP122B 2 7 56R M_MDA22 SERIES Resistors
MDA23 RP122A 1 8 56R M_MDA23
MDA24 RP123A 1 8 56R M_MDA24
MDA25 RP123B 2 7 56R M_MDA25 C778
MDA26 RP123C 3 6 56R M_MDA26 10nF
MDA27 RP123D 4 5 56R M_MDA27 R798
MDA28 RP124D 5 4 56R M_MDA28 For Bi-Directional signals, 56R
MDA29 M_MDA29 3,10 CLKA#0
RP124C 6 3 56R
MDA30 RP124B 7 2 56R M_MDA30 Series resistors should be M_CLKA#0
MDA31 RP124A 8 1 56R M_MDA31
MDA32 RP127A 56R M_MDA32
placed close to the memory
8 1 M_CLKA#0 3,10
MDA33 RP127B 7 2 56R M_MDA33
MDA34 RP127C 6 3 56R M_MDA34
MDA35 RP127D 5 4 56R M_MDA35
MDA36 M_MDA36 3,10 CLKA1
RP128A 8 1 56R
MDA37 RP128B 7 2 56R M_MDA37 M_CLKA1
MDA38 RP128C 6 3 56R M_MDA38
MDA39 RP128D 5 4 56R M_MDA39
MDA40 M_MDA40 M_CLKA1 3,10
RP125D 5 4 56R R799
MDA41 RP125C 6 3 56R M_MDA41 56R
MDA42 RP125B 7 2 56R M_MDA42
MDA43 RP125A 8 1 56R M_MDA43
MDA44 RP126D 5 4 56R M_MDA44
MDA45 RP126C 6 3 56R M_MDA45
MDA46 RP126B 7 2 56R M_MDA46 C779
MDA47 RP126A 8 1 56R M_MDA47 10nF
MDA48 RP129A 8 1 56R M_MDA48 R800
MDA49 RP129B 7 2 56R M_MDA49 56R
C MDA50 M_MDA50 3,10 CLKA#1 C
RP129C 6 3 56R
MDA51 RP129D 5 4 56R M_MDA51 M_CLKA#1
MDA52 RP130A 8 1 56R M_MDA52
MDA53 RP130B 7 2 56R M_MDA53
MDA54 M_MDA54 M_CLKA#1 3,10
RP130C 6 3 56R
MDA55 RP130D 5 4 56R M_MDA55
MDA56 RP131A 1 8 56R M_MDA56
MDA57 RP131B 2 7 56R M_MDA57
MDA58 RP131C 3 6 56R M_MDA58
MDA59 RP131D 4 5 56R M_MDA59
MDA60 RP132D 5 4 56R M_MDA60
MDA61 RP132C 6 3 56R M_MDA61
MDA62 RP132B 7 2 56R M_MDA62
MDA63 RP132A 8 1 56R M_MDA63

QSA[7..0] M_QSA[7..0]
3 QSA[7..0] M_QSA[7..0] 10

QSA0 R759 0R M_QSA0

QSA1 R760 0R M_QSA1
QSA2 R761 0R M_QSA2
Proper Termination of QSA? QSA3 R762 0R M_QSA3
QSA4 R764 0R M_QSA4
QSA5 R763 0R M_QSA5
QSA6 R765 0R M_QSA6
QSA7 R766 0R M_QSA7

M_DQMA#[7..0] DQMA#[7..0]
10 M_DQMA#[7..0] DQMA#[7..0] 3

M_DQMA#0 R775 56R DQMA#0

M_DQMA#1 R776 56R DQMA#1
M_DQMA#2 R777 56R DQMA#2
M_DQMA#3 R778 56R DQMA#3
M_DQMA#4 R780 56R DQMA#4
B M_DQMA#5 R779 56R DQMA#5 B
M_DQMA#6 R781 56R DQMA#6
M_DQMA#7 R782 56R DQMA#7

M_MAA[13..0] MAA[13..0]
10 M_MAA[13..0] MAA[13..0] 3

M_MAA0 RP137A 8 1 0R MAA0

M_MAA1 RP137B 7 2 0R MAA1
M_MAA2 RP137C 6 3 0R MAA2
M_MAA3 RP137D 5 4 0R MAA3
M_MAA4 RP138C 3 6 0R MAA4 For Uni-Directional
M_MAA5 RP138B 2 7 0R MAA5
M_MAA6 RP138A 1 8 0R MAA6 signals, Series
M_MAA7 RP139A 8 1 0R MAA7
M_MAA8 RP139B 0R MAA8
resistors should be
7 2
M_MAA9 RP139C 6 3 0R MAA9 placed close to the
M_MAA10 RP138D 4 5 0R MAA10
M_MAA11 RP139D 5 4 0R MAA11
ASIC
M_MAA12 RP140C 3 6 0R MAA12
M_MAA13 RP140D 4 5 0R MAA13

M_RASA# RP142B 2 7 0R
10 M_RASA# M_CASA# RASA# 3
RP142C 3 6 0R
10 M_CASA# M_WEA# CASA# 3
RP142D 4 5 0R
10 M_WEA# M_CSA#0 WEA# 3
RP142A 1 8 0R
10 M_CSA#0 M_CSA#1 CSA#0 3
RP140A 1 8 0R
10 M_CSA#1 M_CKEA CSA#1 3
RP140B 2 7 0R
10 M_CKEA CKEA 3

A A

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number Rev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 9 of 14

5 4 3 2 1
 8 7 6 5 4 3 2 1

M_DQMA#[7..0]
9 M_DQMA#[7..0] +VREF_U29 Channel A Bottom Down +VREF_U30 Channel A Bottom Up
M_DQMA#0 U29 U30
M_DQMA#1 C418 49 2 M_MDA31 C420 49 2 M_MDA63
M_DQMA#2 100nF VREF DQ0
DQ1
4 M_MDA30 100nF VREF DQ0
DQ1
4 M_MDA62 DDR SDRAM 64Mbit 1Mx16x4
M_DQMA#3 5 M_MDA29 5 M_MDA61
M_DQMA#4 M_MAA0 DQ2 M_MDA28 M_MAA0 DQ2 M_MDA60
29 7 29 7
M_DQMA#5 M_MAA1 A0 DQ3 M_MDA27 M_MAA1 A0 DQ3 M_MDA59
30 8 30 8
M_DQMA#6 M_MAA2 A1 DQ4 M_MDA26 M_MAA2 A1 DQ4 M_MDA58
31 10 31 10
M_DQMA#7 M_MAA3 A2 DQ5 M_MDA25 M_MAA3 A2 DQ5 M_MDA57
32 11 32 11
M_MAA4 A3 DQ6 M_MDA24 M_MAA4 A3 DQ6 M_MDA56
35 13 35 13
M_MAA5 A4 DQ7 M_MDA15 M_MAA5 A4 DQ7 M_MDA47
36 54 36 54
M_MAA6 A5 DQ8 M_MDA14 M_MAA6 A5 DQ8 M_MDA46
37 56 37 56
M_MAA7 A6 DQ9 M_MDA13 M_MAA7 A6 DQ9 M_MDA45
38 57 38 57
M_MAA8 A7 DQ10 M_MDA12 M_MAA8 A7 DQ10 M_MDA44
39 59 39 59
M_MAA9 A8 DQ11 M_MDA11 M_MAA9 A8 DQ11 M_MDA43
40 60 40 60
M_MAA10 A9 DQ12 M_MDA10 M_MAA10 A9 DQ12 M_MDA42 +MVDDQ +MVDDQ
28 62 28 62
D M_MAA11 A10/AP DQ13 M_MDA9 M_MAA11 A10/AP DQ13 M_MDA41 D
41 63 41 63
M_QSA[7..0] A11 DQ14 M_MDA8 A11 DQ14 M_MDA40
9 M_QSA[7..0] 65 65
DQ15 DQ15
M_QSA0 14 14
M_QSA1 NC NC R60 R62
17 17
M_QSA2 M_CLKA0 NC M_CLKA1 NC 5.1K 5.1K
45 19 45 19
M_QSA3 M_CLKA#0 CK NC M_CLKA1# CK NC
46 25 46 25
M_QSA4 M_CKEA CK NC M_CSA#1 M_CKEA CK NC M_CSA#1
44 42 44 42
M_QSA5 CKE NC CKE NC +VREF_U29 +VREF_U30
43 43
M_QSA6 NC +MVDDC NC +MVDDC
50 50
M_QSA7 M_CSA#0 NC M_CSA#0 NC
24 53 24 53
M_RASA#0 CS NC M_RASA#0 CS NC R61 R63
23 23
M_CASA#0 RAS M_CASA#0 RAS 5.1K 5.1K
22 1 22 1
M_WEA# CAS VDD +MVDDQ M_WEA# CAS VDD +MVDDQ
21 18 21 18
WE VDD WE VDD
33 33
VDD VDD
3 3
M_QSA3 VDDQ M_QSA7 VDDQ
16 9 16 9
M_QSA1 LDQS VDDQ M_QSA5 LDQS VDDQ
51 15 51 15
UDQS VDDQ UDQS VDDQ
55 55
VDDQ VDDQ
61 61
M_DQMA#3 VDDQ M_DQMA#7 VDDQ
20 20
M_CLKA0# M_DQMA#1 LDM M_DQMA#5 LDM
3,9 M_CLKA#0 47 34 47 34
M_CLKA1# UDM VSS UDM VSS
3,9 M_CLKA#1 48 48
VSS VSS
66 66
M_MAA13 VSS M_MAA13 VSS
26 6 26 6
M_MAA12 BA0 VSSQ M_MAA12 BA0 VSSQ
27 12 27 12
M_CLKA0 BA1 VSSQ BA1 VSSQ
3,9 M_CLKA0 52 52
M_CLKA1 VSSQ VSSQ
3,9 M_CLKA1 58 58
VSSQ VSSQ
64 64
+MVDDQ VSSQ +MVDDQ VSSQ
1MX16X4 1MX16X4
M_CKEA C566 64MB C569 64MB
9 M_CKEA M_WEA# 100nF U33 100nF U34
9 M_WEA# M_CASA#0 +VREF_U33 49 M_MDA0 +VREF_U34 49 M_MDA32
9 M_CASA# 2 2
M_RASA#0 VREF DQ0 M_MDA1 VREF DQ0 M_MDA33
9 M_RASA# 4 4
M_CSA#0 DQ1 M_MDA2 DQ1 M_MDA34
9 M_CSA#0 5 5
M_CSA#1 M_MAA0 DQ2 M_MDA3 M_MAA0 DQ2 M_MDA35
9 M_CSA#1 29 7 29 7
M_MAA1 A0 DQ3 M_MDA4 M_MAA1 A0 DQ3 M_MDA36
30 8 30 8
C M_MAA2 A1 DQ4 M_MDA5 M_MAA2 A1 DQ4 M_MDA37 C
31 10 31 10
M_MAA3 A2 DQ5 M_MDA6 M_MAA3 A2 DQ5 M_MDA38 +MVDDQ +MVDDQ
32 11 32 11
M_MAA4 A3 DQ6 M_MDA7 M_MAA4 A3 DQ6 M_MDA39
35 13 35 13
M_MAA5 A4 DQ7 M_MDA16 M_MAA5 A4 DQ7 M_MDA48
36 54 36 54
M_MAA6 A5 DQ8 M_MDA17 M_MAA6 A5 DQ8 M_MDA49
37 56 37 56
M_MAA7 A6 DQ9 M_MDA18 M_MAA7 A6 DQ9 M_MDA50
38 57 38 57
M_MAA[13..0] M_MAA8 A7 DQ10 M_MDA19 M_MAA8 A7 DQ10 M_MDA51 R68 R70
9 M_MAA[13..0] 39 59 39 59
M_MAA9 A8 DQ11 M_MDA20 M_MAA9 A8 DQ11 M_MDA52 5.1K 5.1K
40 60 40 60
M_MAA0 M_MAA10 A9 DQ12 M_MDA21 M_MAA10 A9 DQ12 M_MDA53
28 62 28 62
M_MAA1 M_MAA11 A10/AP DQ13 M_MDA22 M_MAA11 A10/AP DQ13 M_MDA54
41 63 41 63
M_MAA2 A11 DQ14 M_MDA23 A11 DQ14 M_MDA55 +VREF_U33 +VREF_U34
65 65
M_MAA3 DQ15 DQ15
M_MAA4 14 14
M_MAA5 NC NC R69 R71
17 17
M_MAA6 M_CLKA0 NC M_CLKA1 NC 5.1K 5.1K
45 19 45 19
M_MAA7 M_CLKA0# CK NC M_CLKA1# CK NC
46 25 46 25
M_MAA8 M_CKEA CK NC M_CSA#1 M_CKEA CK NC M_CSA#1
44 42 44 42
M_MAA9 CKE NC CKE NC
43 43
M_MAA10 NC +MVDDC NC +MVDDC
50 50
M_MAA11 M_CSA#0 NC M_CSA#0 NC
24 53 24 53
M_MAA12 M_RASA#0 CS NC M_RASA#0 CS NC
23 23
M_MAA13 M_CASA#0 RAS M_CASA#0 RAS
22 1 22 1
M_WEA# CAS VDD +MVDDQ M_WEA# CAS VDD +MVDDQ
21 18 21 18
WE VDD WE VDD
33 33
VDD VDD
3 3
M_QSA0 VDDQ M_QSA4 VDDQ
16 9 16 9
M_QSA2 LDQS VDDQ M_QSA6 LDQS VDDQ
51 15 51 15
UDQS VDDQ UDQS VDDQ
55 55
VDDQ VDDQ
61 61
M_DQMA#0 VDDQ M_DQMA#4 VDDQ
20 20
M_DQMA#2 LDM M_DQMA#6 LDM
47 34 47 34
UDM VSS UDM VSS
48 48
VSS VSS
66 66
M_MAA13 VSS M_MAA13 VSS
26 6 26 6
M_MAA12 BA0 VSSQ M_MAA12 BA0 VSSQ
27 12 27 12
BA1 VSSQ BA1 VSSQ
52 52
VSSQ VSSQ
58 58
VSSQ VSSQ
64 64
B VSSQ VSSQ B
1MX16X4 1MX16X4
64MB 64MB
9 M_MDA[63..0]
Channel A Top Down Channel A Top Up

Put 1 1uF cap per power pin of memory

+MVDDQ +MVDDC +MVDDQ +MVDDC

C572 C573 C574 C575 C576 C577 C578 C579 C580 C581
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF

+MVDDQ +MVDDC +MVDDQ +MVDDC

2 capacitors SHOULD BE
PLACED CLOSE TO THE DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AND DQM ACCORDINGLY
REFERENCE LAYER C592 C593 C594 C595 C596 C597 C598 C599 C600 C601
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS
CHANGE OF CLOCKS FOR
EMI REDUCE.
All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed
A A
per memory chip. As close to the pin as possible.
Place as many as possible.
+MVDDC +MVDDQ +MVDDQ <Variant Name>
Some Part Ref's updated to 988 brd
ATI Technologies Inc.
C231 C232 C235 C221 C222 C223 C224 C237 C238 C239 C240 C243 1 Commerce Valley Drive East
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title R9200L-64TD
Size Document Number Rev
C 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 10 of 14

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

OPTIONAL ESD/HOTPLUG PROTECTION DIODES +5V_BUS

+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS +5V_BUS +5V_BUS +5V_BUS F1

PRIMARY CRT BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1
750mA
Resettable fuse

2
D NI D3 D NI D2 D NI D1 D NI D4 D NI D5 D NI D8 D NI D9 +5V_DIN 14
3 3 3 3 3 3 3
Place close to ASIC

1
+5 V_DIN_CNCR

J4
B7 1 2 82nH B8 1 2 82nH 1
2 A_R_DAC1 R
B9 1 2 82nH B10 1 2 82nH 2
2 A_G_DAC1 G
B11 1 2 82nH B12 1 2 82nH 3
2 A_B_DAC1 B
11
DDCDATA_DAC1_R MS0 DDC2_MONID0
12
MS1 DDC2_MONID1(SDA)
4
DDCCLK_DAC1_R MS2 DDC2_MONID2
15
B6 26R MS3
9 DDC2_MONID3(SCL)
A_HSYNC_DAC1_R NC
13
R1258 R1259 R1260 HS
14
75.0R 75.0R 75.0R A_ VSYNC_DAC1_R VS
5
VSS
6
C404 C408 C412 C413 C409 C405 C414 C410 C406 VSS
7
DNI/5pF C402 VSS
8
DNI/3.3pF DNI/3.3pF DNI/3.3pF 5pF 5pF 5pF DNI/5pF DNI/5pF 68pF VSS
10
Change these inductors VSS

2
C C736 C737 C738 C739 16 C
D NI D NI D NI D NI Close to CASE
to 0R for EMI B15 B14 B13
Connector
DNI/82nH DNI/82nH DNI/82nH Header 2x8

1
GND_CHASSIS

GND_CHASSIS Place close to CONNECTOR

+3.3V_BUS +5V_BUS
1

R416 R400
B52
4.7K 6.8k
2 3 DDCDATA_DAC1_5V R520 33R DDCDATA_DAC1_R
2 CRT1DDCDATA
BSN20 0_0805
+3.3V_BUS Q3 +5V_BUS
1

R417 R399
B53
4.7K 6.8k
2 3 DDCCLK_DAC1_5V R521 33R DDCCLK_DAC1_R
2 CRT1DDCCLK
BSN20 0_0805
Q4

B B54 B
2 A_HSYNC_DAC1 5
6 A_ HSYNC_DAC1_B R885 51R A_HSYNC_DAC1_R
4 0_0805
U6B
SN74ACT86D

B55
10
8 A _VSYNC_DAC1_B R884 51R A_ VSYNC_DAC1_R
9 0_0805
2 A_VSYNC_DAC1
U6C
SN74ACT86D

R411 0R
805
R412 0R Three on top side, three at
805 the bottom, spreaded high,
R413 0R middle and low vertically
805
R414 0R
805
R415 0R
805
R418 0R
805

GND_CHASSIS

A A

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number R ev
C 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 11 of 14

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Place Resistors close to ASIC.

13 A_Y_DAC2 A_Y_DAC2 L20 1.8uH A_Y_DAC2_F Add alternate part for 7 pin Svideo
D D
6071001500
R1257 C550 C551 C m3
75.0R 82pF 82pF
Place near connector TV Out (SVHS)
GND_CHASSIS 0R leaves footprint for Ferrite
Beads if req'd for EMI J6
6 +12V

A_Y_DAC2_F R519 0R A _Y_DAC2_DIN 5 Y

13 A_C_DAC2 A_C_DAC2 L21 1.8uH A_C_DAC2_F A_C_DAC2_F R1266 0R A_C_DAC2_DIN 7 C
A_COMP_DAC2_F R1267 0R A_COMP_DAC2_DIN PIN7 6 SDA
R308 DNI/330R PIN5 4 SCK
R1256 C552 C553
82pF 82pF C m4 PIN1
75.0R Rx PIN2
1 G ND
2 G ND

GND_CHASSIS
Rcx C435 10 CASE
DNI/470pF 11 CASE
DNI 12 CASE
C Connector_DIN_Miniature_Circular_7_Pin C

13 A_COMP_DAC2 A_COMP_DAC2 L22 1.8uH A_COMP_DAC2_F

R1255 C554 C555 C m5

75.0R 82pF 82pF

GND_CHASSIS
GND_CHASSIS
+5V_BUS

HSync to Connector Rx = 330R, Rcx = 470pF, Ux INSTALL

C18
DNI/100nF
X7R HSync NOT Connected Rx = DNI, Rcx = 0R, Ux = DNI

5
1
4 A_HSYNC_DAC2_B
2,13 A_ HSYNC_DAC2 2
U3
DNI/TC7SZ08FU

3
B B

Ux

<Variant Name>

ATI Technologies Inc.

A A
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
R9200L-64TD
Size Document Number Rev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 12 of 14

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS +5V_BUS +5V_BUS +5V_BUS

SECONDARY CRT BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1

2
D N I D75 D N I D76 D N I D77 D N I D71 D N I D72 D N I D73 D N I D74

3 3 3 3 3 3 3
D D
Place close to connector DVI1

1
L71 1 2 82nH A_R_DAC2_F1 L74 1 2 82nH A_R_D VI-I A_R_DVI-I 14
L72 1 2 82nH A_G_DAC2_F2 L75 1 2 82nH A_G _DVI-I A_G_DVI-I 14
L73 1 2 82nH A_B_DAC2_F3 L76 1 2 82nH A_B_DVI-I A_B_DVI-I 14
DDCDATA_DVI-I_R DDCDATA_DVI-I_R 14
DDCCLK_D VI-I_R DDCCLK_DVI-I_R 14
A_HSYNC_DVI-I_R A_HSYNC_DVI-I_R 14
A_VSYNC_D VI-I_R A_VSYNC_DVI-I_R 14
C451 C452 C453 C454 C455 C456
DNI/3.3pF DNI/3.3pF DNI/3.3pF 5pF 5pF 5pF C457 C458 C459
DNI/5pF
DNI/5pF
DNI/5pF
R451 75.0R C740 C741 C742 C743
R452 75.0R D NI D NI D NI D NI

2
R453 75.0R

L80 L81 L82

DNI/82nH DNI/82nH DNI/82nH

To DVI1

1
C C

2 A_R/C_DAC2
GND_CHASSIS
2 A_G/Y_DAC2
2 A_B/COMP_DAC2

+5V_BUS

C735
+3.3V_BUS +5V_BUS
100nF

1
U96 R454 R455
R458 B56
1 16 4.7K 6.8k
2,8 DC_Strap5 SEL VCC
2 4 2 3 DDCDATA_DVI-I_R
1A0 YA 2 DVIDDCDATA
A_B_DAC2 3 7 BSN20 0_0805
1A1 YB Q71
5 9
A_G_DAC2 1B0 YC 33R
6 12
1B1 YD
11 13
1C0 1D1
10 14
1C1 1D0
15 8
E GND +3.3V_BUS +5V_BUS
PI5V330

1
A_R_DAC2 R456 R457
TO J6 2 DVIDDCCLK
4.7K
2 3
6.8k
R459 B57
DDCCLK_D VI-I_R
BSN20 0_0805
A_C_DAC2 Q72 33R
A_C_DAC2 12
A_Y_DAC2 A_Y_DAC2 12
B B
A_COMP_DAC2 A_COMP_DAC2 12

10 R460 51R B58

2,12 A_HSYNC_DAC2
8 A_HSYNC_DVI-I_R
9 0_0805
U 7C
SN74ACT86D
B59
13 R461 51R
11 A_VSYNC_D VI-I_R
12 0_0805
2 A_VSYNC_DAC2
U 7D
SN74ACT86D

+5V_BUS

14
SN74ACT86D
C1216 1 U7A
3
0.1uF 2

7
A MODIFY A

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
R9200L-64TD
Size Document Number R ev
Custom 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 13 of 14

8 7 6 5 4 3 2 1
 5 4 3 2 1

INSTALL TERMINATION RESISTORS CLOSE TO ASIC INSTALL TERMINATION RESISTORS CLOSE TO CONNECTOR PRIMARY DVI-I CONNECTOR
DVI1
D D
M1 CASE
R1269 330R R1268 DNI/330R M3
TMDS CASE
2 TMDS_TX2N 1 TMDS Data2-
2 TMDS_TX2P 2 TMDS Data2+
3 TMDS Data2/4 Shield
4 TMDS Data4-
5 TMDS Data4+
DDCCLK_DVI-I 6
DDCDATA_DVI-I DDC Clock
7 DDC Data
R1271 330R R1270 DNI/330R 8
TMDS Analog VSYNC
2 TMDS_TX1N 9 TMDS Data1-
2 TMDS_TX1P 10 TMDS Data1+
11 TMDS Data1/3 Shield
12 TMDS Data3-
13 TMDS Data3+
B732 26R 14
11 +5V_DIN +5V Power
15 GND (for +5V)
R1273 330R R1272 DNI/330R 16
TMDS Hot Plug Detect
2 TMDS_TX0N 17 TMDS Data0-
2 TMDS_TX0P 18 TMDS Data0+
19 TMDS Data0/5 Shield
20 TMDS Data5-
21 TMDS Data5+
R1275 330R R1274 DNI/330R 22
C TMDS Clock Shield C
TMDS 23
2 TMDS_TXCP TMDS Clock+
2 TMDS_TXCN 24 TMDS Clock-
13 A_VSYNC_DVI-I_R
13 A_R_DVI-I C1 Analog Red
13 A_G_DVI-I C2 Analog Green
13 A_B_DVI-I C3 Analog Blue
13 A_HSYNC_DVI-I_R C4 Analog HYNC
C5 Analog GND
C6 Analog GND
C1209 M4
1.0uF CASE
M2 CASE
DVI_A/D

R1276 20K
2 CHARGE_POW
GND_CHASSIS GND_CHASSIS

1
J7
D78 1
2.4V R1277 R
13 DDCCLK_DVI-I_R 2 G
100K 3
TMDS B
11

2
13 DDCDATA_DVI-I_R MS0
12 MS1
B 4 MS2 B
15 MS3
IF HOT PLUG DETECT IS NOT REQUIRED 9 NC
REMOVE ALL THIS LOGIC EXCEPT 13 HS
FOR 100K PULL DOWN 14 VS
5 VSS
6 VSS
7 VSS
8 VSS
10 VSS
16 CASE
17 CASE
Slim_Connector_DB15_Female_VGA_Blue
GND_CHASSIS

<Variant Name>

A ATI Technologies Inc. A

1 Commerce Valley Drive East

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
R9200L-64TD
Size Document Number R ev
B 81-105-L31020 1.0
Date: Monday, October 20, 2003 Sheet 14 of 14

5 4 3 2 1