<Variant Name> 5 4 3 2 1

Title Schematic No. Date:

PCI-E RV370 128M TSOP VO-SV/DI 105-A260xx-00C Wednesday, March 24, 2004

Rev
REVISION HISTORY 2
D D
Sch Date REVISION DESCRIPTION
Rev
0 00A 2003-09-10 PRELIMINARY BASED ON 105-A181xx-00A and 105-A200xx-00
- Use 402 R and C footprints as preferred
- (pg1) Add 0R bypass for PERST#, and use XOR spared gate for buffer
- (pg1) Keep only 1 100uF decoupling for +12V_BUS
- (pg1) Connect B3 of edge connector directly to +12V_BUS
- (pg2) Remove oscillator and change crystal to surface mount
- (pg2) Hard pull-down on TEST_Y/MCLK
- (pg2) Remove thermal interrupt, no provision for speed controlled fan
- (pg2) Remove redundant TPs
- (pg2) Pull-up on DVPCNTL_[3:0], remove RageTheater capture ports (VID/DVO[7:0])
- (pg2) DVOMode pull-up to 1.8V, set to 12-bit DVO (1.8V DVO I/O signalling)
- (pg3) Memory interface based on A198, remove Channel B
- (pg4) Remove power-up diodes
- (pg5, 6, 7) Redesigned power regulators
C
- (pg8, 9) Channel A only Series-Terminated TSOP interface (based on A200) C
- (pg11, 12, 13) Front-end based on Low-Profile VGA/DVI + VO design (based on A200)
2003-09-22 - (pg5) Add RC snubber circuit on switching regulator
- (pg7) Add R124 for power dissipation
2003-10-16 - (pg14) Add MT2, second mounting hole
- (pg6 and 7) Remove R817, option for sharing REG8 and REG9, due to layout concerns
- (pg4) Add C979..C985 On request of EMI team. These are for decoupling ajacent planes.
- (pg6) Make RP2 dual footprint with 0402 Caps C986..C989. Created a similar circuit using RP195 and C990..C993. The RP can be used to short +MVDDQ and +MVDDC, and the
caps can be used to decouple the planes.
- (pg6) Add C973..C978 Decoupling caps. These are placed accross +MVDDQ/+MVDDC plane splits
- (pg11) Remove R994..R996 stitching GND to Chassis GND.

1 00B 2003/11/14 - (Layout) Change to 6-layer PCB

- (Layout) Change PCIE test points
- (pg1) Change PCIE test points, add 3.3V_BUS polymer cap, add R1244
- (pg2) Add R23 for DVO pull-down
- (pg4) Add B15 for +3.3V_BUS VDDR4 alternate, change PCIE regulators filter from 100nF to 1uF
- (pg5) Add stand-alone +PCIE_VDDR, +PCIE_PVDD12 and +PCIE_PVDD18 regulators, improve power sequence circuit
- (pg5) Add R315 and R316 to select +12V_BUS or +5V for boot circuit, change R368 footprint to 603
B
- (pg6) Add C314 and C315 for MVDDC and MVDDQ, 1.8V from PCIE_PVDD18 B
- (pg7) Remove R124, add polymer cap for PCIE_PVDD18, add +PCIE_VDDR and +PCIE_PVDD12 tied option and single package FET for +PCIE_VDDR
- (pg14) Add fan connector

2 00C 2004/03/05 - (pg02, 10) Fix pull-up +VDD_DVO to +VDDR4

- (Layout) TVO filters move close to connector
- (pg04) Remove CP2, 3, 4, 5, 6 and 8 for dual footprint manufacturing issues (Capacitor packs sharing with 402 footprints)
- (Layout) Components using the same foot print. (remove MC2)
- (pg06) Remove C986, C987, C988, C989, C990, C991, C992 and C993
- (pg06) Add C800 for options
- (pg11) +5V supply with current limiting for VESA DDC spec, remove F1, B21
- (pg05) Remove dual-packaged MOSFET
- (Layout/EMI) C507, C508, C509, R513, R514, R515 (added), L60, L61 and L62 connect to digital Gnd instead of chassis Gnd.

A A

5 4 3 2 1
 8 7 6 5 4 3 2 1

PCI-EXPRESS EDGE CONNECTOR GND_MPVSS GND_TPVSS GND_A2VSSN GND_AVSSQ GND_RSET

+12V_BUS +3.3V_BUS +3.3V_BUS
GND_AVSSN GND_PVSS GND_TXVSSR GND_A2VSSQ GND_R2SET
USE 47uF TANTALUM
C5 C8 C2
100uF_16V 100uF_16V 47uF_16V CAPACITOR OR HIGHER NOTE: THIS IS A DRAWING. THESE
DNI
>=6.3V
DNI
>=6.3V
DNI
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE

D D

+12V_BUS
+12V_BUS
+3.3V_BUS
+3.3V_BUS

MPCIE1
B1 A1 PRESENCE
+12V#B1 PRSNT1#A1
B2 A2
+12V#B2 +12V#A2 0R R1244 DNI
B3 A3
RSVD#B3 +12V#A3 +5V
B4 A4 402
GND#B4 GND#A4 JTAG_TCK
B5
SMCLK JTAG2
A5 RP194A 8 1 0R DNI A_VSYNC_DAC1 (2,11)
B6
SMDAT JTAG3
A6 JTAG_TDI RP194B 7 2 0R DNI CRT1DDCDATA (2,11)
B7 A7 JTAG_TDO RP194C 6 3 0R DNI C972
JTAG_TRST# GND#B7 JTAG4 JTAG_TMS RP194D SCL (2)
(2,11) A_HSYNC_DAC1
R1008 0R 402 B8
+3.3V#B8 JTAG5
A8 5 4 0R DNI CRT1DDCCLK (2,11)
100nF
DNI B9 A9 402

14
JTAG1 +3.3V#A9 SN74ACT86D
B10 A10
3.3Vaux +3.3V#A10 PERST# U6A
B11 A11 1
TP28 WAKE# PERST# TP26 R3 100R
Mechanical Key 3
PERST#_buf (2)
B12 A12 2
RSVD#B12 GND#A12 TP27
B13 A13
(2) PETp0_GFXRp0 GND#B13 REFCLK+ PCIE_REFCLKP (2) R4
B14 A14
(2) PETn0_GFXRn0 PETp0 REFCLK- PCIE_REFCLKN (2)

7
B15 A15 180R
TP30 PRESENT_NULL PETn0 GND#A15 PERp0 C607
B16 A16 402
TP29 GND#B16 PERp0 PERn0 100nF C608 GFXTp0_PERp0 (2)
B17 A17
PRSNT2#B17 PERn0 100nF GFXTn0_PERn0 (2)
B18 A18
(2) PETp1_GFXRp1 GND#B18 GND#A18
B19 A19
(2) PETn1_GFXRn1 TP32 PETp1 RSVD#A19 R64 0R
B20 A20 402
PETn1 GND#A20 PERp1
B21
GND#B21 PERp1
A21 C617
GFXTp1_PERp1 (2) DNI
TP31 B22 A22 PERn1 100nF C618
(2) PETp2_GFXRp2 GND#B22 PERn1 100nF GFXTn1_PERn1 (2)
C B23 A23 C
(2) PETn2_GFXRn2 TP34 PETp2 GND#A23
B24 A24
PETn2 GND#A24 PERp2 C626
B25 A25
TP33 GND#B25 PERp2 PERn2 100nF C627 GFXTp2_PERp2 (2)
B26 A26
(2) PETp3_GFXRp3 GND#B26 PERn2 100nF GFXTn2_PERn2 (2)
B27 A27
(2) PETn3_GFXRn3 PETp3 GND#A27
B28 A28
PETn3 GND#A28 PERp3 C631
B29 A29
TP36 TP35 PRESENT_NULL GND#B29 PERp3 PERn3 100nF C632 GFXTp3_PERp3 (2)
B30 A30
RSVD#B30 PERn3 100nF GFXTn3_PERn3 (2)
B31 A31
PRSNT2#B31 GND#A31
B32 A32
(2) PETp4_GFXRp4 GND#B32 RSVD#A32
B33 A33
(2) PETn4_GFXRn4 TP38 PETp4 RSVD#A33
B34 A34
PETn4 GND#A34 PERp4 C611
B35 A35
TP37 GND#B35 PERp4 PERn4 100nF C612 GFXTp4_PERp4 (2)
B36 A36
(2) PETp5_GFXRp5 GND#B36 PERn4 100nF GFXTn4_PERn4 (2)
B37 A37
(2) PETn5_GFXRn5 TP40 PETp5 GND#A37
B38 A38
PETn5 GND#A38 PERp5 C622
B39 A39
TP39 GND#B39 PERp5 PERn5 100nF C623 GFXTp5_PERp5 (2)
B40 A40
(2) PETp6_GFXRp6 GND#B40 PERn5 100nF GFXTn5_PERn5 (2)
B41 A41
(2) PETn6_GFXRn6 TP42 PETp6 GND#A41
B42 A42
PETn6 GND#A42 PERp6 C621
B43 A43
TP41 GND#B43 PERp6 PERn6 100nF C630 GFXTp6_PERp6 (2)
B44 A44
(2) PETp7_GFXRp7 GND#B44 PERn6 100nF GFXTn6_PERn6 (2)
B45 A45
(2) PETn7_GFXRn7 PETp7 GND#A45
B46 A46
TP44 PRESENT_NULL PETn7 GND#A46 PERp7 C605
B47 A47
TP43 GND#B47 PERp7 PERn7 100nF C606 GFXTp7_PERp7 (2)
B48 A48
PRSNT2#B48 PERn7 100nF GFXTn7_PERn7 (2)
B49 A49
(2) PETp8_GFXRp8 GND#B49 GND#A49
B50 A50
(2) PETn8_GFXRn8 TP46 PETp8 RSVD#A50
B51 A51
PETn8 GND#A51 PERp8 C615
B52 A52
TP45 GND#B52 PERp8 PERn8 100nF C616 GFXTp8_PERp8 (2)
B53 A53
(2) PETp9_GFXRp9 GND#B53 PERn8 100nF GFXTn8_PERn8 (2)
B54 A54
(2) PETn9_GFXRn9 TP48 PETp9 GND#A54
B55 A55
PETn9 GND#A55 PERp9 C624
B56 A56
TP47 GND#B56 PERp9 PERn9 100nF C625 GFXTp9_PERp9 (2)
B57 A57
(2) PETp10_GFXRp10 GND#B57 PERn9 100nF GFXTn9_PERn9 (2)
B58 A58
(2) PETn10_GFXRn10 TP50 PETp10 GND#A58
B59 A59
PETn10 GND#A59 PERp10 C633
B60 A60
B
TP49 GND#B60 PERp10 PERn10 100nF C634 GFXTp10_PERp10 (2) B
B61 A61
(2) PETp11_GFXRp11 GND#B61 PERn10 100nF GFXTn10_PERn10 (2)
B62 A62
(2) PETn11_GFXRn11 TP52 PETp11 GND#A62
B63 A63
PETn11 GND#A63 PERp11 C609
B64 A64
TP51 GND#B64 PERp11 PERn11 100nF C610 GFXTp11_PERp11 (2)
B65 A65
(2) PETp12_GFXRp12 GND#B65 PERn11 100nF GFXTn11_PERn11 (2)
B66 A66
(2) PETn12_GFXRn12 TP54 PETp12 GND#A66
B67 A67
PETn12 GND#A67 PERp12 C619
B68 A68
TP53 GND#B68 PERp12 PERn12 100nF C620 GFXTp12_PERp12 (2)
B69 A69
(2) PETp13_GFXRp13 GND#B69 PERn12 100nF GFXTn12_PERn12 (2)
B70 A70
(2) PETn13_GFXRn13 TP56 PETp13 GND#A70
B71 A71
PETn13 GND#A71 PERp13 C628
B72 A72
TP55 GND#B72 PERp13 PERn13 100nF C629 GFXTp13_PERp13 (2)
B73 A73
(2) PETp14_GFXRp14 GND#B73 PERn13 100nF GFXTn13_PERn13 (2)
B74 A74
(2) PETn14_GFXRn14 TP58 PETp14 GND#A74
B75 A75
PETn14 GND#A75 PERp14 C603
B76 A76
TP57 GND#B76 PERp14 PERn14 100nF C604 GFXTp14_PERp14 (2)
B77 A77
(2) PETp15_GFXRp15 GND#B77 PERn14 100nF GFXTn14_PERn14 (2)
B78 A78
(2) PETn15_GFXRn15 PETp15 GND#A78
B79 A79
PRESENCE PETn15 GND#A79 PERp15 C613
B80 A80
TP59 GND#B80 PERp15 PERn15 100nF C614 GFXTp15_PERp15 (2)
B81 A81
PRSNT2#B81 PERn15 100nF GFXTn15_PERn15 (2)
B82 A82
RSVD#B82 GND#A82
x16 PCIe

SYMBOL LEGEND

DNI DO NOT
INSTALL

# ACTIVE
LOW

A DIGITAL A
GROUND

ANALOG
GROUND

<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title PCI-E RV370 128M TSOP VO-SV/DI
Size
C
Document Number 105-A260xx-00C Rev
2
Date: Wednesday, March 24, 2004 Sheet 1 of 15
8 7 6 5 4 3 2 1
 5 4 3 2 1

GPIO[6..0]
GPIO[6..0] (10) BOUNDARY SCAN TEST ACCESS
U1A
AH30 AJ5 GPIO0
(1) PETp0_GFXRp0 PCIE_RX0P Part 1 of 6 GPIO_0 GPIO1 A_HSYNC_DAC1 TP1 TRST/
(1) PETn0_GFXRn0
AG30 PCIE_RX0N GPIO_1 AH5
AG29 AJ4 GPIO2 SCL TP2 TDO
(1) PETp1_GFXRp1 PCIE_RX1P GPIO_2 GPIO3 CRT1DDCDATA TP3 TDI
(1) PETn1_GFXRn1
AF29 PCIE_RX1N GPIO_3 AK4
AE29 AH4 GPIO4 CRT1DDCCLK TP4 TMS
(1) PETp2_GFXRp2 PCIE_RX2P GPIO_4 GPIO5 A_VSYNC_DAC1 TP5 TCK
(1) PETn2_GFXRn2
AE30 PCIE_RX2N GPIO_5 AF4
AD30 AJ3 GPIO6 GPIO[13..8] TESTEN TP8
(1) PETp3_GFXRp3 PCIE_RX3P GPIO_6 GPIO[13..8] (10)
(1) PETn3_GFXRn3
AD29 PCIE_RX3N GPIO_7 AK3
AC29 AH3 GPIO8
D (1) PETp4_GFXRp4 PCIE_RX4P GPIO_8 GPIO9 D
(1) PETn4_GFXRn4
AB29 PCIE_RX4N GPIO_9 AJ2
AB30 AH2 GPIO10
(1) PETp5_GFXRp5 PCIE_RX5P GPIO_10 GPIO11
(1) PETn5_GFXRn5
AA30 PCIE_RX5N GPIO_11 AH1
GPIO12
DEBUG BUS ACCESS
(1) PETp6_GFXRp6
AA29 PCIE_RX6P GPIO_12 AG3
Y29 AG1 GPIO13
(1) PETn6_GFXRn6 PCIE_RX6N GPIO_13 VID/DVO16 TESTOUT(0)
W29 AG2
(1) PETp7_GFXRp7 PCIE_RX7P GPIO_14 VID/DVO17 TESTOUT(1)
W30 AF3 Mem_Strap1 (10)
(1) PETn7_GFXRn7 PCIE_RX7N GPIO_PWRCNTL VID/DVO18 TESTOUT(2)
V30 AF2 Mem_Strap0 (10)
(1) PETp8_GFXRp8 PCIE_RX8P GPIO_MEMSSIN +VDDR4 VID/DVO19 TP17 TESTOUT(3)
V29
(1) PETn8_GFXRn8 PCIE_RX8N DVOMODE R22 10K 402 VID/DVO20 TESTOUT(4)
U29 AE10
(1) PETp9_GFXRp9 PCIE_RX9P DVOVMODE R23 10K 402 VID/DVO21 TP19 TESTOUT(5)
T29
(1) PETn9_GFXRn9 PCIE_RX9N VID/DVO22 TP20 TESTOUT(6)
T30 AH6
(1) PETp10_GFXRp10 PCIE_RX10P DVPDATA_0 VID/DVO23 TP21 TESTOUT(7)
R30 AJ6
(1) PETn10_GFXRn10 PCIE_RX10N DVPDATA_1 GPIO10 TESTOUT(8)
R29 AK6
(1) PETp11_GFXRp11 PCIE_RX11P DVPDATA_2 GPIO11 TESTOUT(9)
P29 AH7 Pull-up to 1.8V

DVO / EXT TMDS / GPIO

(1) PETn11_GFXRn11 PCIE_RX11N DVPDATA_3 GPIO12 TESTOUT(10)
N29 AK7
(1) PETp12_GFXRp12 PCIE_RX12P DVPDATA_4 GPIO13 TESTOUT(11)
(1) PETn12_GFXRn12
N30
PCIE_RX12N DVPDATA_5
AJ7 12bit-DVO mode for SDR
M30 AH8
(1) PETp13_GFXRp13
M29
PCIE_RX13P DVPDATA_6
AJ8 Ext. TMDS 1.8V DVO I/O
(1) PETn13_GFXRn13 PCIE_RX13N DVPDATA_7
L29 AH9
(1) PETp14_GFXRp14 PCIE_RX14P DVPDATA_8
K29 AJ9
(1) PETn14_GFXRn14 PCIE_RX14N DVPDATA_9
K30 AK9
(1) PETp15_GFXRp15 PCIE_RX15P DVPDATA_10
J30 AH10
(1) PETn15_GFXRn15 PCIE_RX15N DVPDATA_11
AE6
DVPDATA_12
AG6
DVPDATA_13 VID/DVO14
AF26 AF6 SVHS/YPrPbb (13)
(1) GFXTp0_PERp0 PCIE_TX0P DVPDATA_14
AE26 AE7
(1) GFXTn0_PERn0 PCIE_TX0N DVPDATA_15 VID/DVO16

PCI Express
AC25 AF7 LCDDATA16 (10)
(1) GFXTp1_PERp1 PCIE_TX1P DVPDATA_16 VID/DVO17
AB25 AE8 LCDDATA17 (10)
(1) GFXTn1_PERn1 PCIE_TX1N DVPDATA_17 VID/DVO18
AC27 AG8
(1) GFXTp2_PERp2 PCIE_TX2P DVPDATA_18 VID/DVO19
AB27 AF8
(1) GFXTn2_PERn2 PCIE_TX2N DVPDATA_19 VID/DVO20
AC26 AE9 VHAD0 (10)
(1) GFXTp3_PERp3 PCIE_TX3P DVPDATA_20 VID/DVO21 +VDDR4
AB26 AF9
(1) GFXTn3_PERn3 PCIE_TX3N DVPDATA_21 VID/DVO22 P1
Y25 AG10
(1) GFXTp4_PERp4 PCIE_TX4P DVPDATA_22 VID/DVO23 PLUG
W25 AF10
(1) GFXTn4_PERn4 PCIE_TX4N DVPDATA_23
Y27
(1) GFXTp5_PERp5 PCIE_TX5P
W27 AJ10 OPT
(1) GFXTn5_PERn5 PCIE_TX5N DVPCNTL_0 +3.3V_BUS R584
C Y26 AK10 C
(1) GFXTp6_PERp6 PCIE_TX6P DVPCNTL_1 10K
W26 AJ11
(1) GFXTn6_PERn6 PCIE_TX6N DVPCNTL_2 R43 10K
U25 AH11 1 402
(1) GFXTp7_PERp7 PCIE_TX7P DVPCNTL_3
T25 402 2
(1) GFXTn7_PERn7 PCIE_TX7N
U27 AG4 3
(1) GFXTp8_PERp8 PCIE_TX8P VREFG
T27
(1) GFXTn8_PERn8 PCIE_TX8N +3.3V_BUS JU2
U26
(1) GFXTp9_PERp9 PCIE_TX9P

4
T26 AH15 Header_3_Pin_1X3 R585
(1) GFXTn9_PERn9 PCIE_TX9N NC#AH15 10K SW1A
P25 AH16
(1) GFXTp10_PERp10 PCIE_TX10P NC#AH16 R35 ALT DIP_SWX2
N25 AJ16
(1) GFXTn10_PERn10 PCIE_TX10N NC#AJ16 1K
P27 AJ17 402
(1) GFXTp11_PERp11 PCIE_TX11P NC#AJ17

1
(1) GFXTn11_PERn11
N27
PCIE_TX11N NC#AJ18
AJ18 402 Both resistors and
P26 AK18 capacitor close to ASIC
(1) GFXTp12_PERp12 PCIE_TX12P NC#AK18
N26 AJ20
(1) GFXTn12_PERn12 PCIE_TX12N NC#AJ20 C16 R34
L25 AJ21
(1) GFXTp13_PERp13 PCIE_TX13P NC#AJ21 100nF 1K
K25 AK19
(1) GFXTn13_PERn13 PCIE_TX13N NC#AK19
L27 AJ19 402 402
(1) GFXTp14_PERp14 PCIE_TX14P NC#AJ19
K27 AG16
(1) GFXTn14_PERn14 PCIE_TX14N NC#AG16
L26 AG17
(1) GFXTp15_PERp15 PCIE_TX15P NC#AG17
K26 AF16
(1) GFXTn15_PERn15 PCIE_TX15N NC#AF16
AF17
NC#AF17
AE18
NC#AE18
AF27 AE19
(1) PCIE_REFCLKP PCIE_REFCLKP NC#AE19
AE27 AF19
(1) PCIE_REFCLKN PCIE_REFCLKN NC#AF19
AF20
+PCIE_VDDR R1009 150R 402 AC23 NC#AF20
AG19
R1010 100R 402 AB24 PCIE_CALRP NC#AG19
AG20
R1011 10K 402 AB23 PCIE_CALRN NC#AG20
PCIE_CALI
AE12
R1089 10K 402 AE25 NC#AE12
AG12
PCIE_TEST NC#AG12
AD24 AK13 TMDS_TX0N (12)
PWRGD_MASK TX0M
AD25 AJ13 TMDS_TX0P (12)
(1) PERST#_buf PWRGD TX0P
TX1M AJ14 TMDS_TX1N (12)
AJ15 TMDS_TX1P (12)
R40 715R TX1P
GND_R2SET AH21 AK15 TMDS_TX2N (12)
R2SET TX2M
TP6
402
TX2P AK16 TMDS_TX2P (12)
+3.3V_BUS AJ22 AJ12
B (13) A_R/C_DAC2 C_R_PR TXCM TMDS_TXCN (12) B
(13) A_G/Y_DAC2 AK21 AK12 TMDS_TXCP (12)
Y_G TXCP
TMDS

(13) A_B/COMP_DAC2 AK22

COMP_B_PB
DDC2CLK AE13
R45 R46 AJ24 AE14
H2SYNC DDC2DATA
DAC2

4.7K 4.7K AK24 V2SYNC

402 402 AF12 HPD (12)
HPD1
(1) SCL AG22
DDC3CLK
AG23 AK27 A_R_DAC1 (11)
DDC3DATA R
AJ27 A_G_DAC1 (11)
G
AJ23 AJ26 A_B_DAC1 (11)
NC#AJ23 B
AH24 AJ25 A_HSYNC_DAC1
NC#AH24 HSYNC A_HSYNC_DAC1 (1,11)
AK25 A_VSYNC_DAC1 (1,11)
C71 15PF VSYNC
AH28
XTALIN R39 499R +3.3V_BUS
402
RSET AH26 GND_RSET
1

DAC1

AJ29 402 TP7

Y1 R32 XTALOUT
AG25 CRT1DDCDATA (1,11)
27_MHZ 1.0M TESTEN AH27 DDC1DATA R65
TESTEN DDC1CLK AF24 CRT1DDCCLK (1,11)
5023270000 402 E8 4.7K
TEST_YCLK
2

C72 15PF B6 AG24 AUXWIN 402

R33 TEST_MCLK GPIO__AUXWIN
402 AF25 PLLTEST
OPTION 1: Crystal Circuit 1K
CLK
THERM

402 AH25 AF11

STEREOSYNC DPLUS TP11
DMINUS AE11 TP12

+3.3V_BUS

RV370GL
+3.3V_BUS R27 R44
MY1 220R 10K
4 3 402
VCC OUT
C18 2 1
100nF GND E/D +3.3V_BUS R28 R29
402 27.000MHz 130R 0R
5015270000 402
A A

OPTION 2: Oscillator Circuit

IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS <Variant Name>
TO ADDRESS ANY LAYOUT NOISE RELATED
SIGNAL DAMPING REQUIREMENTS ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 2 of 15
5 4 3 2 1
 1 2 3 4 5 6 7 8

QSA[7..0]
(8) QSA[7..0]
DQMA#[7..0]
(8) DQMA#[7..0]
MAA[14..0]
(9) MAA[14..0]

MDA[63..0]
(8) MDA[63..0]
U1C
U1B D7 N5
A MDA0 MAA0 DQB_0 Part 3 of 6 MAB_0 A
H28 E22 F7 M1
MDA1 DQA_0 Part 2 of 6 MAA_0 MAA1 DQB_1 MAB_1
H29 B22 E7 M3
MDA2 DQA_1 MAA_1 MAA2 DQB_2 MAB_2
J28 B23 G6 L3
MDA3 DQA_2 MAA_2 MAA3 DQB_3 MAB_3
J29 B24 G5 L2
MDA4 DQA_3 MAA_3 MAA4 DQB_4 MAB_4
J26 C23 F5 M2
MDA5 DQA_4 MAA_4 MAA5 DQB_5 MAB_5
H25 C22 E5 M5
MDA6 DQA_5 MAA_5 MAA6 DQB_6 MAB_6
H26 F22 C4 P6
MDA7 DQA_6 MAA_6 MAA7 DQB_7 MAB_7
G26 F21 B5 N3
MDA8 DQA_7 MAA_7 MAA8 DQB_8 MAB_8
G30 C21 C5 K2
MDA9 DQA_8 MAA_8 MAA9 DQB_9 MAB_9
D29 A24 A4 K3
MDA10 DQA_9 MAA_9 MAA10 DQB_10 MAB_10
D28 C24 B4 J2
MDA11 DQA_10 MAA_10 MAA11 DQB_11 MAB_11
E28 A25 C2 P5
MDA12 DQA_11 MAA_11 MAA12 DQB_12 MAB_12
E29 E21 D3 P3
MDA13 DQA_12 MAA_12 MAA13 DQB_13 MAB_13
G29 B20 D1 P2
MDA14 DQA_13 MAA_13 MAA14 DQB_14 MAB_14
G28 C19 D2
MDA15 DQA_14 MAA_14 DQB_15
F28 G4 E6
MDA16 DQA_15 DQMA#0 DQB_16 DQMBb_0
G25 J25 H6 B2
MDA17 DQA_16 DQMAb_0 DQMA#1 DQB_17 DQMBb_1
F26 F29 H5 J5
MDA18 DQA_17 DQMAb_1 DQMA#2 DQB_18 DQMBb_2
E26 E25 J6 G3
MDA19 DQA_18 DQMAb_2 DQMA#3 DQB_19 DQMBb_3
F25 A27 K5 W6
MDA20 DQA_19 DQMAb_3 DQMA#4 DQB_20 DQMBb_4
E24 F15 K4 W2
MDA21 DQA_20 DQMAb_4 DQMA#5 DQB_21 DQMBb_5
F23 C15 L6 AC6
MDA22 DQA_21 DQMAb_5 DQMA#6 DQB_22 DQMBb_6
E23 C11 L5 AD2
MDA23 DQA_22 DQMAb_6 DQMA#7 DQB_23 DQMBb_7
D22 E11 G2
MDA24 DQA_23 DQMAb_7 DQB_24
B29 F3 F6
MDA25 DQA_24 QSA0 DQB_25 QSB_0
C29 J27 H2 B3
MDA26 DQA_25 QSA_0 QSA1 DQB_26 QSB_1
C25 F30 E2 K6
MDA27 DQA_26 QSA_1 QSA2 DQB_27 QSB_2
C27 F24 F2 G1
MDA28 DQA_27 QSA_2 QSA3 DQB_28 QSB_3
B28 B27 J3 V5
MDA29 DQA_28 QSA_3 QSA4 DQB_29 QSB_4
B25 E16 F1 W1
MDA30 DQA_29 QSA_4 QSA5 DQB_30 QSB_5
C26 B16 H3 AC5
MDA31 DQA_30 QSA_5 QSA6 DQB_31 QSB_6
B26 B11 U6 AD1
MDA32 DQA_31 QSA_6 QSA7 DQB_32 QSB_7
F17 F10 U5
MDA33 DQA_32 QSA_7 DQB_33
E17 U3 R2
MDA34 DQA_33 RASA# DQB_34 RASBb
D16 A19 RASA# (9) V6
MDA35 DQA_34 RASAb DQB_35
F16 W5 T5
MDA36 DQA_35 CASA# DQB_36 CASBb
E15 E18 CASA# (9) W4
MDA37 DQA_36 CASAb DQB_37
F14 Y6 T6
B MDA38 DQA_37 WEA# DQB_38 WEBb B
E14 E19 WEA# (9) Y5
MDA39 DQA_38 WEAb DQB_39
F13 U2 R5
MDA40 DQA_39 CSA#0 DQB_40 CSBb_0
C17 E20 CSA#0 (9) V2
MDA41 DQA_40 CSAb_0 DQB_41
B18 V1 R6
MDA42 DQA_41 DQB_42 CSBb_1
B17 F20 V3
MDA43 DQA_42 CSAb_1 DQB_43
B15 W3 R3
MDA44 DQA_43 CKEA DQB_44 CKEB
C13 B19 CKEA (9) Y2
MDA45 DQA_44 CKEA DQB_45
B14 Y3 N1
MDA46 DQA_45 DQB_46 CLKB0
C14 AA2 N2
MDA47 DQA_46 CLKA0 DQB_47 CLKB0b
C16 B21 CLKA0 (8,9) AA6
MDA48 DQA_47 CLKA0 CLKA#0 DQB_48
A13 C20 CLKA#0 (8,9) AA5 T2
DQA_48 CLKA0b DQB_49 CLKB1

MEMORY INTERFACE
MDA49 A12 +MVDDQ AB6 T3
DQA_49 DQB_50 CLKB1b
MEMORY INTERFACE

MDA50 C12 C18 CLKA1 AB5

DQA_50 CLKA1 CLKA1 (8,9) DQB_51
MDA51 B12 A18 CLKA#1 AD6
DQA_51 CLKA1b CLKA#1 (8,9) DQB_52
MDA52 C10 R56 AD5 E3
MDA53 DQA_52 100R DQB_53 DIMB_0
C9 AE5 AA3
MDA54 DQA_53 DQB_54 DIMB_1
B9 402 AE4
MDA55 DQA_54 DQB_55
B10 B7 AB2
MDA56 DQA_55 MVREFD DQB_56
E13 AB3 AF5 ROMCS# (10)
MDA57 DQA_56 DQB_57 ROMCSb +VDDC_CT
E12 B8 AC2
MDA58 DQA_57 MVREFS C153 R57 DQB_58 R51 4.7K
E10 AC3 C6 402
MDA59 DQA_58 100nF 100R DQB_59 MEMVMODE_0 R52 4.7K
F12 AD3 C7 402
DQA_59 DQB_60 MEMVMODE_1
MDA60 F11
DQA_60 DIMA_0
D30 402 402 AE1
DQB_61 DNI
MDA61 E9 B13 AE2 C8
MDA62 DQA_61 DIMA_1 DQB_62 MEMTEST
F9 AE3
MDA63 DQA_62 DQB_63 R53 R54
F8
DQA_63 +MVDDQ RV370GL R55 4.7K 4.7K DNI

B
RV370GL 47R 402 402
A

402
R58
100R LAYOUT NOTE: SOME OF THE RESISTORS R51-54 MAY BE
402
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING

C154 R59
MEMORY CHANNEL B
MEMORY CHANNEL A 100nF
402
100R
402
VDDR1 MEMVMODE_0 MEMVMODE_1
C C

1.8V GND +VDDC_CT

PLACE C351/152 VERY CLOSE TO ASIC
R56/57/58/59 CLOSE TO ASIC AS WELL 2.5V +VDDC_CT GND

2.8V +VDDC_CT +VDDC_CT

D D

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 3 of 15
1 2 3 4 5 6 7 8
 5 4 3 2 1

+VDDC

C24
10uf +VDDC

U1F
U1D
+MVDDQ P17 Part 6 of 6 M16
Part 4 of 6 VDDC#P17 VSS#M16
T7 AC13 P18 N16
VDDR1#T7 VDDC#AC13 +VDDC VDDC#P18 VSS#N16
R4 AC15 P19 N15
VDDR1#R4 VDDC#AC15 VDDC#P19 VSS#N15
R1 AC17 U12 P15
D VDDR1#R1 VDDC#AC17 +VDDC VDDC#U12 VSS#P15 D
N8 AD13 U13 P16
VDDR1#N8 VDDC#AD13 C26 C27 C28 C29 C30 VDDC#U13 VSS#P16
N7 AD15 U14 R18
VDDR1#N7 VDDC#AD15 100nF 100nF 100nF 100nF 100nF VDDC#U14 VSS#R18
M4 U17 R17
VDDR1#M4 VDDC#U17 VSS#R17
L8 402 402 402 402 402 U18 R16
VDDR1#L8 VDDC#U18 VSS#R16
K23 H11 U19 R15
VDDR1#K23 VDD15#H11 VDDC#U19 VSS#R15
K24 H20 V19 R14
VDDR1#K24 VDD15#H20 VDDC#V19 VSS#R14
L23 M23 V18 R13
+MVDDQ VDDR1#L23 VDD15#M23 VDDC#V18 VSS#R13
J8 P8 V17 R12

CENTER ARRAY
VDDR1#J8 VDD15#P8 VDDC#V17 VSS#R12
J7 Y23 V14 T13
VDDR1#J7 VDD15#Y23 +VDDC VDDC#V14 VSS#T13
J4 Y8 V13 T14
C38 VDDR1#J4 VDD15#Y8 +VDDC_CT VDDC#V13 VSS#T14
J1 AC11 V12 T15
10uf VDDR1#J1 VDD15#AC11 VDDC#V12 VSS#T15
H10 AC20 N18 W15
VDDR1#H10 VDD15#AC20 C20 C21 C22 C23 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 VDDC#N18 VSS#W15
H13 N17 V16
VDDR1#H13 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VDDC#N17 VSS#V16
H15 N14 V15
VDDR1#H15 VDDC#N14 VSS#V15
H17 AC8 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 W17 U15
VDDR1#H17 VDDR3#AC8 VDDC#W17 VSS#U15
T8 AC19 W18 U16
VDDR1#T8 VDDR3#AC19 VDDC#W18 VSS#U16
V4 AC21 W12 T19
VDDR1#V4 VDDR3#AC21 VDDC#W12 VSS#T19
V7 AC22 W13 T18
+MVDDQ VDDR1#V7 VDDR3#AC22 VDDC#W13 VSS#T18
V8 AD7 W14 T17
VDDR1#V8 VDDR3#AD7 +3.3V_BUS VDDC#W14 VSS#T17
AA1 AD19 N13 T16
VDDR1#AA1 VDDR3#AD19 VDDC#N13 VSS#T16
AA4 AD21 N19
C32 C33 C35 C31 C74 C75 C94 C95 C96 C97 VDDR1#AA4 VDDR3#AD21 +VDDR4 +3.3V_BUS VDDC#N19
AA7 M19 W16
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF VDDR1#AA7 VDDC#M19 VDDCI#W16
AA8 M18 M15
VDDR1#AA8 +3.3V_BUS +VDDC_CT VDDC#M18 VDDCI#M15
402 402 402 402 402 402 402 402 402 402 A3 AC9 M12 R19
VDDR1#A3 VDDR4#AC9 B15 VDDC#M12 VDDCI#R19
A9 AC10 N12 T12
VDDR1#A9 VDDR4#AC10 C70 C69 200R VDDC#N12 VDDCI#T12
A15 AD9 M13
VDDR1#A15 VDDR4#AD9 4.7uF 100nF ALT: 0R VDDC#M13
A21 AD10 M14 W19
VDDR1#A21 VDDR4#AD10 C44 C46 C45 C47 C48 C49 VDDC#M14 VDDC#W19
A28 AG7 402 P12 M17
VDDR1#A28 VDDR4#AG7 100nF 100nF 100nF 100nF 100nF 100nF VDDC#P12 VDDC#M17
B1 P13 P14
VDDR1#B1 VDDC#P13 VDDC#P14
B30 D9 402 402 402 402 402 402
VDDR1#B30 NC#D9
D26 D13
VDDR1#D26 NC#D13 RV370GL
D23 D19
VDDR1#D23 NC#D19
D20 D25
VDDR1#D20 NC#D25
D17 E4
VDDR1#D17 NC#E4
D14 T4
VDDR1#D14 NC#T4
D11 AB4
VDDR1#D11 NC#AB4
D8
VDDR1#D8
C D5 C
VDDR1#D5 These caps are footprint-shared alternate
E27 AG26
+TPVDD VDDR1#E27 PCIE_VDDR_12#AG26 of capacitor array
F4 AG27
VDDR1#F4 PCIE_VDDR_12#AG27 U1E
G7 AG28
VDDR1#G7 PCIE_VDDR_12#AG28 +PCIE_VDDR
G10 AJ30
C50 C43 C58 C73 VDDR1#G10 PCIE_VDDR_12#AJ30 Part 5 of 6
G13 AK29 A2 AB8
10uf 2.2uF 2.2uF 100nF VDDR1#G13 PCIE_VDDR_12#AK29 VSS#A2 VSS#AB8
G15 A10 AB7
VDDR1#G15 VSS#A10 VSS#AB7

4
OPT ALT: ALT: 402 G19 A16 AB1
100nF 100nF VDDR1#G19 +PCIE_PVDD_12 VSS#A16 VSS#AB1
G22 N23 A22 AC4
GND_TPVSS VDDR1#G22 PCIE_PVDD_12#N23 C99 C98 C37 CP9A CP9B CP9C CP9D C39 C40 C76 C77 VSS#A22 VSS#AC4
G27 N24 A29 AC12
+1.8V VDDR1#G27 PCIE_PVDD_12#N24 1.0uF 1.0uF 1.0uF 10nF 10nF 10nF 10nF 100nF 100nF 100nF 100nF VSS#A29 VSS#AC12
H22 P23 C1 AC14
VDDR1#H22 PCIE_PVDD_12#P23 VSS#C1 VSS#AC14

5
H19 402 402 402 402 C3 AD16
VDDR1#H19 VSS#C3 VSS#AD16
AD4 C28 AC16
B11 VDDR1#AD4 VSS#C28 VSS#AC16
N4 T23 C30 AC18
200R +TXVDDR_PINS VDDR1#N4 PCIE_PVDD_18#T23 VSS#C30 VSS#AC18
U23 D27 AD18
ALT: 0R PCIE_PVDD_18#U23 +PCIE_PVDD_18 VSS#D27 VSS#AD18
V23 D24 AK2
PCIE_PVDD_18#V23 VSS#D24 VSS#AK2

4
W23 D21 AJ1
C59 C60 C81 PCIE_PVDD_18#W23 VSS#D21 VSS#AJ1
D18
4.7uF 100nF 100nF C968 C969 CP10A CP10B CP10C CP10D C41 C42 C78 C79 VSS#D18
+1.8V 402 402 1.0uF 1.0uF 10nF 10nF 10nF 10nF 100nF 100nF 100nF 100nF
D15
D12
VSS#D15 CORE GND
VSS#D12

5
AE15 AF18 402 402 402 402 D6
GND_TXVSSR NC#AE15 NC#AF18 VSS#D6
AE16 AG15 D4 K28
B14 NC#AE16 NC#AG15 VSS#D4 PCIE_VSS#K28
AE17 AG18 D10 L28
200R +A2VDDQ NC#AE17 NC#AG18 VSS#D10 PCIE_VSS#L28
AF15 AH17 F27 M24
ALT: 0R NC#AF15 NC#AH17 VSS#F27 PCIE_VSS#M24
G9 M25
VSS#G9 PCIE_VSS#M25

4
AH19 AH18 G12 M26
C63 C64 NC#AH19 NC#AH18 VSS#G12 PCIE_VSS#M26
G16 M27
4.7uF 100nF C970 C971 CP11A CP11B CP11C CP11D C55 C56 C57 C61 VSS#G16 PCIE_VSS#M27
AH13 AH12 G18 M28
TPVDD TPVSS 1.0uF 1.0uF 10nF 10nF 10nF 10nF 100nF 100nF 100nF 100nF VSS#G18 PCIE_VSS#M28
402 G21 N28
VSS#G21 PCIE_VSS#N28

5
AF13 AH14 GND_TPVSS 402 402 402 402 G24 P28
GND_A2VSSQ TXVDDR#AF13 TXVSSR#AH14 VSS#G24 PCIE_VSS#P28
AF14 AG13 H27 R23
+A2VDD TXVDDR#AF14 TXVSSR#AG13 VSS#H27 PCIE_VSS#R23
AG14 H23 R24
+MVDDQ TXVSSR#AG14 VSS#H23 PCIE_VSS#R24
AVDD/A2VDDQ (1st & 2nd GND_TXVSSR
H21
VSS#H21 PCIE_VSS#R25
R25
F18 F19 H18 R26
DAC Band Gap) - 200mA C62 N6
VDDRH0 VSSRH0
M6 H16
VSS#H18 PCIE_VSS#R26
R27
100nF VDDRH1 VSSRH1 VSS#H16 PCIE_VSS#R27
H14 R28
+1.8V VSS#H14 PCIE_VSS#R28
402 AE20 AH20 H12 T24
GND_A2VSSN A2VDD#AE20 A2VSSN#AH20 VSS#H12 PCIE_VSS#T24
AF21 AG21 H9 T28
B A2VDD#AF21 A2VSSN#AG21 +3.3V_BUS VSS#H9 PCIE_VSS#T28 B
H8 U28
B13 GND_A2VSSN VSS#H8 PCIE_VSS#U28
AF23 AF22 H4 V24
A2VDDQ A2VSSQ VSS#H4 PCIE_VSS#V24
200R +AVDD CAPS C979..C985 are J23
VSS#J23 PCIE_VSS#V25
V25
ALT: 0R AH23 AH22 GND_A2VSSQ J24 V26
AVDD AVSSN C979 +VDDC accross Plane Splits VSS#J24 PCIE_VSS#V26
AD12 V27
C67 C68 GND_AVSSN TP9 VSS#AD12 PCIE_VSS#V27
AD22 AG5 V28
4.7uF 100nF AVSSQ VSS#AG5 PCIE_VSS#V28
AG9 W24
VSS#AG9 PCIE_VSS#W24
402 AE23
VDD1DI I/O POWER VSS1DI
AE24
100nF
They are not required AG11
VSS#AG11 PCIE_VSS#W28
W28
AE22 GND_AVSSQ They should be populated R7 Y28
GND_AVSSN +1.8V VDD2DI VSS#R7 PCIE_VSS#Y28
AE21 C980 P4 AA23
VSS2DI +Vout_Switcher only if EMI issues are M7
VSS#P4 PCIE_VSS#AA23
AA24
found. VSS#M7 PCIE_VSS#AA24
AK28 AJ28 M8 AA25
B12 PVDD PVSS VSS#M8 PCIE_VSS#AA25
L4 AA26
200R +VDDOI_PINS GND_PVSS VSS#L4 PCIE_VSS#AA26
A7 A6 K1 AA27
ALT: 0R MPVDD MPVSS 100nF VSS#K1 PCIE_VSS#AA27
K7 AA28
GND_MPVSS VSS#K7 PCIE_VSS#AA28
C981 K8 AB28
C66 C65 RV370GL +MVDDQ VSS#K8 PCIE_VSS#AB28
R8 AC28
4.7uF 100nF VSS#R8 PCIE_VSS#AC28
T1 AD26
VSS#T1 PCIE_VSS#AD26
402 W8 AD27
VSS#W8 PCIE_VSS#AD27
W7 AD28
100nF VSS#W7 PCIE_VSS#AD28
U8 AE28
VSS#U8 PCIE_VSS#AE28
C982 U4 AF28
+12V_BUS_F1 VSS#U4 PCIE_VSS#AF28
Y4 AH29
VSS#Y4 PCIE_VSS#AH29

RV370GL
100nF
+MVDDQ

C983
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
+PVDD +VDDC
PLACED CLOSE TO THE POWER/GND PINS
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
C54 C53
4.7uF 100nF 100nF
402
C984 +MVDDC
A A
GND_PVSS

100nF

C985 <Variant Name>

ATI Technologies Inc.

+MPVDD 1 Commerce Valley Drive East
100nF
Markham, Ontario
Canada, L3T 7X6
C52 C51 (905) 882-2600
4.7uF 100nF
402 Title
PCI-E RV370 128M TSOP VO-SV/DI
GND_MPVSS Size Document Number Rev
C 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 4 of 15
5 4 3 2 1
 8 7 6 5 4 3 2 1

*** Indicate number of power via required for the connection

Regulator for VDDC (ASIC Core)

Part NOTES
Vout = 1.2V ~ 1.3V
MAX1954 Do not install Cc1, Rc1
+12V_BUS
Alt. 1: Separate MOSFETs
ALT. 1: MAXIM REGULATOR Q24
High current path
ISL6522 Install Cc1, Rc1
+VDDC_S B17
R351 0R 4 5 60R
D +5V +12V_BUS D
402 3 6 *** ***
2 7 ***
1 8 C301 Part Vout R1 R2
470UF
R315 R316 IRF7413A C150 *** 0.019R @ 100kHz
0R 0R 10uF 3.5mm LS
MAX1954 1.2V 1.00K 1% 2.00K 1%
ATI P/N 3240100100 ATI P/N 3240200100
C151 ISL6522
1.0uF
must be low impedance L21 2.2uH +Vout_Switcher 0.8V Ref 1.3V 1.00K 1% 1.6K 1%
+PW_VDDC_M ATI P/N 3240100100 ATI P/N 3240162100
+VDDC_S R15 *** ** **
U41 1R C325 C321 C323 C324
2

R314 +PW_VDDC_HGD Q22 10nF 470uF_10V 22uF_16V 22uF_16V

D1 510K
1
ILIM HSD DH
8
must be low impedance Cc1 *** ** **
RB501V-40 2 6 +PW_VDDC_LGD 4 5 C152 OPT OPT
COMP DL 2.2nF
C148 C149
3 6
R254
R1
3 5 2 7
FB IN
1

470pF 27pF 4 1 8 1.5K R353

+VDDC_B GND 1.00K
402 9
LX IRF7413A
Rc1 1%
10 7
BST PGND
C147 MAX1954EUB 0.8V Ref
100nF
603 VDDC_FB
X7R
+12V_BUS
5%
ALT. 2: INTERSIL REGULATOR +12V_BUS_F1 R2
R357 10K
+VDDC_S R99 R356
MU31 C143 2.2R 2K
R358 51K 1 14 0.22uF 1%
R359 3K RT VCC
2 13
OCSET PVCC C115
3 12
SS LGATE +VDDC_B 100nF
4 11
C C104 COMP PGND C
5 10 603
22nf C111 FB BOOT
6 9 X7R
33pF EN UGATE
7 8 5%
GND PHASE
C312 ISL6522CB
10nF
402
R368

ISL6522CB : SOIC
15K_1%
402

+Vout_Switcher +VDDC +VDDC

RP1A 1 8 0R ***
RP1B 2 7 0R C322
RP1C 3 6 0R 470uF_10V
RP1D 4 5 0R ***

+Vout_Switcher +PCIE_VDDR
L6 1.8uH
ALT: 0R

+Vout_Switcher +PCIE_PVDD_12
L7 1.8uH
ALT: 0R

B B

Circuit to hold PCI-E voltage low and wait for +VDDC for proper power sequence

+3.3V_BUS

R153
100K
402
VDDC_GOOD_PU (7)
3

R396
2

100R CMPT3904
+VDDC Rq3 Rq4 +VDDC +12V_BUS 402 Q29

+1.3V 1.5K 2.4K R395

VDDC_GOOD (7)
3

+1.2V 1.5K 3K 20K

Rq3 R393 CMPT3904 402 1
3

1.50K Q28
A 1 R397 A
2

100R CMPT3904
Rq4 R394 402 Q27
2

3.01K

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 5 of 15
8 7 6 5 4 3 2 1
 5 4 3 2 1

Place caps very Alt. regulator for +MVDDC

+12V_BUS
close to power pin Vout = 2.5V ~ 2.6V
Iout = 500mA MAX
C13 C12
+3.3V_BUS 100nF 100nF
603
X7R
603
X7R +MVDDC +3.3V_BUS
Voltage Req. Rm1 Rm2
R811 5% 5%
3.34V 4.32K 2.55K
33R

4
2.5V_REF2 U81A [-0.04V/+0.04V]

2
1.25V_REF2 R101 1K 3 +
3

C800 402 1 1 Q31 1 4 MQ31 3.45V 4.32K 2.43K

REG9 10uF_6.3V 2 CMPT3904 BCP68 +Vout_Switcher
-
D LM324M D
TL431CDBVR 4 200mA, SOT-23 1A SOT-223
[-0.04V/+0.04V]

3
NC
1 150mW MAX 350mW MAX

11
R812 L12 2.5V 1K 3240100100 1K 3240100100
NC
2
100R ALT 1.8uH
5

1% R1 +VDDC_CT ALT: 0R
402 5260002100
[-0.03V/+0.03V]
1.25V_REF2 R102 432R 1.5V
R813 Rx1 CMPT3904: 40V 200mA C302 150mA MAX
100R R103 MMBT2222: 40V 600mA 10uF_6.3V G_MVDDC +12V_BUS
1% R2 2.15K ALT
402
Rx2 C138
100nF +MVDDC
+3.3V_BUS 603 R949
Rails derived from +VDDR4 X7R 750R
+PCIE_PVDD_18 +1.8V +VDDR4 +MPVDD +PVDD +TPVDD 5% /.25W

3
U81B +AVDD: 10mA MAX R958

2
1.25V_REF2 R105 1K 5 REG33 MREG33 1.0K Rm1
+
Voltage Req. R1 R2 402 7 1 4 Q32 L4 L8 L9 L10 L11 +A2VDDQ: 20mA MAX 1 AS432S 4 SC431LC5SK-1 1%
6 BCP68 1.8uH 1.8uH 1.8uH 1.8uH 1.8uH 1 402
NC
-
0.8V 150R 71.5R LM324M 1A SOT-223 ALT: 0R ALT: 0R ALT: 0R ALT: 0R ALT: 0R +VDDOI_PINS: 20mA MAX 2
NC

3
350mW MAX ALT 5260002100 5260002100 5260002100 5260002100

5
P/N 3240150000 P/N 324075R500 R106 681R <ATIPartNumbers> 5260002100 +TXVDDR_PINS: 20mA MAX R960
402 1.0K Rm2
1.25V 75R 75R DNI 3160681000 1.8V +VDDR4: 90mA MAX TOTAL 1%
P/N 3240075000 603 P/N 3240075000 603 R107 Rx1 C303 402
P/N 316075R000 402 P/N 316075R000 402 0R 175mA MAX 10uF_6.3V +MPVDD: 10mA MAX
1.5V 49.9R 75R Rx2 +PVDD: 25mA MAX
P/N 3240075000 603
P/N 3240049900 P/N 316075R000 402 +TPVDD: 50mA MAX
Alt regulator for +MVDDQ
1.8V 54.9R 140R Vout = 2.5V ~ 2.6V
P/N 3240054900 P/N 3240140000 +3.3V_BUS +3.3V_BUS
Iout = 200mA MAX
1.84V 49.9R 140R MQ33

7
8
C C

P/N 3240049900 P/N 3240140000 2.5V_REF2 R109 1K U81C

4 5 Voltage Req. Rq1 Rq2
10 + 3 6
402 8 G_MVDDC 2 Q33A 2 7 1.8V 681R 3240681000 1.5K 3230015200
Voltage Req. Rx1 for 1.25V Ref Rx2 for 1.25V Ref 9 -
BSO4804 1 8 2.5V ~ 2.6V
LM324M +MVDDC [-0.09V/+0.18V]

1
1.5 432R 2.15K IRF7201 +MVDDC: 500mA MAX
R110 0R ALT
2.5V 1K 3240100100 1K 3240100100
P/N 3240432000 P/N 3240215100 402 +MVDDC and +MVDDQ: 700mA MAX
8A continuous @ 25'C 5.8A continuous @ 70'C
Ry1 *** 2.6V 4.75K 3240475100 4.32K 3240432100
1.6V 432R 1.5K R111 6.4A continuous @ 70'C 58A pulse drain current @ 25'C C314 C304 CONSIDER HEATSINK ON FET
4.99K 32A pulse drain current @ 25'C RDS(on) MAX = 50mR@Vgs=4.5V,Id=3.7A 10uF_6.3V 470uF_10V
DNI RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A 550mW MAX
P/N 3240432000 P/N 3240150100 402
3160499100 275mW MAX
***

1.7V 432R 1.21K Ry2 G_MVDDQ +12V_BUS

P/N 3240432000 P/N 3240121100

1.8175V 681R 1.5K C136
P/N 3240681000 603 +3.3V_BUS 100nF +MVDDQ
P/N 3160681000 402 P/N 3240015200 603 R277
X7R 750R

5
6
5% /.25W

3
Voltage Req. Ry1 for 2.5V Ref Ry2 for 2.5V Ref R279 Rq1
2.5V_REF2 R113 1K 12 +
U81D REG34 MREG34 1.0K
3.3V 1.07K 3.32K 402 14 G_MVDDQ 4 Q33B 1 AS432S 4 SC431LC5SK-1 1%
13 -
BSO4804 NC
1 402
P/N 3240107100 P/N 3240332100 LM324M <ATIPartNumbers> +MVDDQ 2
NC

3
R283

5
2.7V 301R (402, 1%) 3.32K R114 301R 2.5V ~ 2.6V 1.0K Rq2
402 200mA MAX 1%
3160301000 8A continuous @ 25'C
P/N 3160301000 P/N 3240332100 R115
DNI 6.4A continuous @ 70'C C315
***
C305
402

0R
Ry1 32A pulse drain current @ 25'C 10uF_6.3V 470uF_10V
2.65V 301R (402, 1%) 4.99K (402, 1%) RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
402 ***
+MVDDQ +MVDDC
P/N 3160301000 P/N 3160499100 Ry2 275mW MAX

B
2.5V 0R DNI Place caps across
B
P/N 3230000000 603 C973 +MVDDQ and +MVDDC
P/N 3150000000 402 Plane Splits

100nF Alt regulator for +VDDC_CT

If +MVDDQ and +MVDDC
C974
are shorted, then these Vout = 1.5V
Rt1 Rt2
caps should be populated Iout = 150mA MAX
+MVDDQ +MVDDC with 0R Resistors.
RP2A 0R 100nF
RP2B
1 8
0R
1.52V 432R 3240432000 2.15K
2 7
RP2C 3 6 0R 3160432000 3160215100 C975
RP2D 4 5 0R 1.61V 432R 3240432000 1.5K 3230015200 +3.3V_BUS REG31 +VDDC_CT
+MVDDQ +MVDDC 1.5K 3160150100 LT1117CST
RP195A 0R 100nF
RP195B
1 8
0R
1.69V 432R 3240432000 1.21K 3240121100 3
IN OUT
2
2 7 C976

ADJ
RP195C 3 6 0R 4
RP195D 0R CASE R294
4 5 1.718V 562R 3240562000 1.5K 3230015200 1.0K
1.5K 3160150100

1
1%
100nF
1.75V 604R 3160604000 1.5K 3230015200 R293
402

1.5K 3160150100 C977

200R
1.8V 604R 3160604000 1.37K 3160137100 1%

100nF
Need at least a 4.7uF
C978 output cap for stability
Alt. regulator for +PVDD Alt regulator for +MPVDD Alt. regulator for +TPVDD
Vout = 1.8V Vout = 1.8V Vout = 1.65V ~ 1.85V 100nF
Iout = 30mA MAX Iout = 10mA MAX Iout = 20mA MAX
A A

+3.3V_BUS +PVDD +3.3V_BUS +MPVDD +3.3V_BUS +TPVDD

R284 R285 R286

33R 75R 56R

ATI Technologies Inc.

2

R287 Rt1 REG32 R288 Rt1 REG39 R289 Rt1 1 Commerce Valley Drive East
REG40 681R AS432S 681R AS432S 604R Markham, Ontario
AS432S
1 1% 402 4 MREG40 1 1% 402 4 MREG32 1 1% 402 4 MREG39 Canada, L3T 7X6
1 NC SC431LC5SK-1 1 NC SC431LC5SK-1 1 NC SC431LC5SK-1 (905) 882-2600
R290 2 NC R291 2 NC R292 2 NC

1.5K Rt2 1.5K Rt2 1.37K Rt2 Title PCI-E RV370 128M TSOP VO-SV/DI
3

1% 402 1% 402 1% 402

Size Document Number Rev
GND_PVSS GND_MPVSS GND_TPVSS Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 6 of 15
5 4 3 2 1
 8 7 6 5 4 3 2 1

Place caps very +12V_BUS

close to power pin

C15 C14
100nF 100nF +Vout_Switcher
603 603

Alt. regulator for +A2VDD

X7R X7R
5% 5%

4
U82A Q35
D 1.2V_REF R117 1K 3 +
Vout = 2.5V D
+3.3V_BUS 1 4 5
Iout = 120mA MAX
402
2 - 3 6
LM324M 2 7
R814 1 8

11
33R +3.3V_BUS +A2VDD
2.5V_REF IRF7413A 1.3V 2.5V
ALT +VDDC
3

8A MAX 120mA
REG8 R118 0R REG35
TL431CDBVR 4 402 MIGHT NEED HEATSINK ON FET 1
VIN VOUT
5
9.6A continuous @ 70'C C306 +A2VDD +MVDDC
Rx1
NC
1
R815 96A pulse drain current @ 25'C 10uF_6.3V
NC
2

GND
324R R119 ALT RDS(on) MAX=18mR@Vgs=4.5V,Id =6.0A ALT
R1 3
SHDN BYPASS
4
5

1% 10K L5
402
DNI Rx2 1.8uH 2.5V

2
1.2V_REF ALT: 0R C139
100nF
R816 402
301R R2
1%
402 GND_A2VSSN

+3.3V_BUS
+A2VDD and GND_A2VSSN routed with at least 15 mil
trace and not longer than 1.5 inch.

2
1.2V_REF R121 1K 12 U82D
+
Q36
14 1 4
Alt. regulator for PCIE_PVDD_18
402
13 -
BCP68
LM324M +PCIE_PVDD_18
Vout = 1.85V
1A SOT-223

3
350mW MAX
R122 681R <ATIPartNumbers> +PCIE_PVDD_18: 1.8V 500mA MAX
Iout = 500mA MAX
Rx1 C308 MC308
R123 10uF_6.3V 470uF
1.50K
C +3.3V_BUS +PCIE_PVDD_18 C
Rx2 MREG36
LT1117CST
3 2
IN OUT

ADJ
4
CASE R296
1.50K

1
1%

Optional when +Vout_Switcher is above 1.2V R295

681R
1% 402
+Vout_Switcher 8A continuous @ 25'C

Need at least a 4.7uF

output cap for stability
5
6
MQ37

1.2V_REF R125 1K 5 +
U82B 4 5
402 7 4 Q37B 3 6
6 BSO4804 R128 402 Q37_PIN2 2 7
-
LM324M 0R +PCIE_VDDR +PCIE_VDDR: 1.2V 1300mA MAX
1 8
Regulator for +5V
3

ALT
R126 0R IRF7413A
402 Vout = 5V
6.4A continuous @ 70'C
R127
Rx1 32A pulse drain current @ 25'C C309 Iout = 20mA MAX
10K ALT 2W power dissipation @ 25'C 10uF_6.3V C160 MC160 C161 C162
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A 100uF_16V 470uF 22uF 22uF
DNI 402
Rx2
RP111A 1 8 0R +12V_BUS +5V
+Vout_Switcher RP111B 2 7 0R
RP111C 3 6 0R
RP111D 4 5 0R Multi footprint R1042
220R
7
8

U82C
1206, 1/4W Multi-footprint
B 1.2V_REF R129 1K 10 B
+

3
402 8 MR128 Q37_PIN2 2 Q37A R1040 C917 MC917
9 -
0R BSO4804 REG29 R1 1.0K 10uF_6.3V 10uf
LM324M 402 +PCIE_PVDD_12 TL431CDBVR 4 1%
1

DNI ALT
NC
1 402
R130 0R R1041
NC
2
402 +PCIE_PVDD_12: 1.2V 250mA MAX R2 1.0K

5
8A continuous @ 25'C 1%
R131
Rx1 6.4A continuous @ 70'C C310 402
10K ALT 32A pulse drain current @ 25'C 33uF
DNI 402 2W power dissipation @ 25'C ALT
RDS(on) MAX=28.2mR@Vgs=4.5V,Id =6.7A
Rx2

+PCIE_PVDD_12 +3.3V_BUS +PCIE_PVDD_18

+3.3V_BUS
+3.3V_BUS +PCIE_VDDR
REG38 REG37
MAX1935ETA MAX1935ETA
1 8 1 8
IN OUT IN OUT
3
6

MREG37 2 7 2 7
R141 C163 IN2 OUT7 R151 C166 IN2 OUT7 R154
1 5
VCNTL
TAB

2.15K IN VOUT 1.0uF 1.0K 1.0uF 6.81K Part Vout R1 R2

4 6 402 4 6 402
R145 0R SHDN SET C165 SHDN SET C167
(5) VDDC_GOOD 402
4
REFEN GND
2
R143
R1 10uf
R1 10uf
RT9173ACL5 1K 3 5 3 5 MAX1935 1.2V 1.00K 1% 402 2.00K 1% 402
R142 POK GND R152 POK GND R155
402
TH_GND9
9
TH_GND9
9 ATI P/N 3160100100 ATI P/N 3160200100
1.24K C157 10 2K 10 5.49K 0.8V Ref
1.0uF TH_GND10 TH_GND10
11 402 11 402
A TH_GND11 TH_GND11 A
R2 R2 1.79V 6.81K 1% 5.49K 1% 402
ATI P/N 3160681100 ATI P/N 3160549100

R144 0R
(5) VDDC_GOOD_PU 402
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600

Title PCI-E RV370 128M TSOP VO-SV/DI

Size Document Number 105-A260xx-00C Rev
Custom 2
Date: Wednesday, March 24, 2004 Sheet 7 of 15
8 7 6 5 4 3 2 1
 5 4 3 2 1

MDA[63..0] M_MDA[63..0]
(3) MDA[63..0] M_MDA[63..0] (9)
CLOCK
MDA0 RP122A 56R M_MDA0
terminations
8 1
MDA1 RP122B 7 2 56R M_MDA1
MDA2 RP122C 6 3 56R M_MDA2
MDA3 RP122D 5 4 56R M_MDA3
MDA4 RP118B 2 7 56R M_MDA4
D MDA5 RP118C 3 6 56R M_MDA5 D
MDA6 RP118A 1 8 56R M_MDA6
MDA7 RP118D 4 5 56R M_MDA7
MDA8 RP120B 7 2 56R M_MDA8
MDA9 RP119B 2 7 56R M_MDA9
MDA10 RP119A 1 8 56R M_MDA10
MDA11 RP119C 3 6 56R M_MDA11
MDA12 RP120D 5 4 56R M_MDA12
MDA13 RP120A 8 1 56R M_MDA13
MDA14 RP120C 6 3 56R M_MDA14
(3,9) CLKA0
MDA15 RP119D 4 5 56R M_MDA15
MDA16 RP121D 5 4 56R M_MDA16 M_CLKA0
MDA17 RP121C 6 3 56R M_MDA17
MDA18 RP121B 7 2 56R M_MDA18
M_CLKA0 (3,9)
MDA19 RP121A 8 1 56R M_MDA19 R797
MDA20 RP117A 1 8 56R M_MDA20 56R
MDA21 RP117B 56R M_MDA21
MDA22 RP117C
2
3
7
6 56R M_MDA22 SERIES Resistors
MDA23 RP117D 4 5 56R M_MDA23
MDA24 RP123B 7 2 56R M_MDA24
MDA25 RP123A 8 1 56R M_MDA25 C778
MDA26 RP124B 2 7 56R M_MDA26 10nF
MDA27 RP123D 5 4 56R M_MDA27 R798
MDA28 RP123C 6 3 56R M_MDA28 For Bi-Directional signals, 56R
(3,9) CLKA#0
MDA29 RP124A 1 8 56R M_MDA29
MDA30 RP124D 4 5 56R M_MDA30 Series resistors should be M_CLKA#0
MDA31 RP124C 3 6 56R M_MDA31 placed close to the memory
MDA32 RP127C 6 3 56R M_MDA32
M_CLKA#0 (3,9)
MDA33 RP127B 7 2 56R M_MDA33
MDA34 RP127A 8 1 56R M_MDA34
MDA35 RP127D 5 4 56R M_MDA35
(3,9) CLKA1
MDA36 RP128D 5 4 56R M_MDA36
MDA37 RP128C 6 3 56R M_MDA37 M_CLKA1
MDA38 RP128A 8 1 56R M_MDA38
MDA39 RP128B 7 2 56R M_MDA39
M_CLKA1 (3,9)
MDA40 RP125B 7 2 56R M_MDA40 R799
MDA41 RP125A 8 1 56R M_MDA41 56R
MDA42 RP125C 6 3 56R M_MDA42
C MDA43 RP126A 8 1 56R M_MDA43 C
MDA44 RP126D 5 4 56R M_MDA44
MDA45 RP126C 6 3 56R M_MDA45
MDA46 RP126B 7 2 56R M_MDA46 C779
MDA47 RP125D 5 4 56R M_MDA47 10nF
MDA48 RP131A 8 1 56R M_MDA48 R800
MDA49 RP131C 6 3 56R M_MDA49 56R
(3,9) CLKA#1
MDA50 RP131B 7 2 56R M_MDA50
MDA51 RP131D 5 4 56R M_MDA51 M_CLKA#1
MDA52 RP132B 7 2 56R M_MDA52
MDA53 RP132D 5 4 56R M_MDA53
M_CLKA#1 (3,9)
MDA54 RP132C 6 3 56R M_MDA54
MDA55 RP132A 8 1 56R M_MDA55
MDA56 RP129B 2 7 56R M_MDA56
MDA57 RP129C 3 6 56R M_MDA57
MDA58 RP130D 5 4 56R M_MDA58
MDA59 RP129A 1 8 56R M_MDA59
MDA60 RP129D 4 5 56R M_MDA60
MDA61 RP130B 7 2 56R M_MDA61
MDA62 RP130C 6 3 56R M_MDA62
MDA63 RP130A 8 1 56R M_MDA63

QSA[7..0] M_QSA[7..0]
(3) QSA[7..0] M_QSA[7..0] (9)

QSA0 R759 0R M_QSA0

QSA1 R760 0R M_QSA1
QSA2 R761 0R M_QSA2
QSA3 R762 0R M_QSA3
QSA4 R764 0R M_QSA4
QSA5 R763 0R M_QSA5
QSA6 R765 0R M_QSA6
QSA7 R766 0R M_QSA7

M_DQMA#[7..0] DQMA#[7..0]
B (9) M_DQMA#[7..0] DQMA#[7..0] (3) B

M_DQMA#0 R775 56R DQMA#0 For Uni-Directional

M_DQMA#1 R776 56R DQMA#1
M_DQMA#2 R777 56R DQMA#2 signals, Series
M_DQMA#3 R778 56R DQMA#3 resistors should be
M_DQMA#4 R780 56R DQMA#4
M_DQMA#5 R779 56R DQMA#5 placed close to the
M_DQMA#6 R781 56R DQMA#6 ASIC
M_DQMA#7 R782 56R DQMA#7

M_MAA[14..0] MAA[14..0]
(3,9) M_MAA[14..0] MAA[14..0] (3,9)

M_MAA0 MAA0
M_MAA1 MAA1
M_MAA2 MAA2
M_MAA3 MAA3
M_MAA4 MAA4
M_MAA5 MAA5
M_MAA6 MAA6
M_MAA7 MAA7
M_MAA8 MAA8
M_MAA9 MAA9
M_MAA10 MAA10
M_MAA11 MAA11
M_MAA12 MAA12
M_MAA13 MAA13
M_MAA14 MAA14

M_RASA#
(3,9) M_RASA# RASA# (3,9)
M_CASA#
(3,9) M_CASA# CASA# (3,9)
M_WEA#
(3,9) M_WEA# WEA# (3,9)
M_CSA#0
(3,9) M_CSA#0 CSA#0 (3,9)
M_CKEA
(3,9) M_CKEA CKEA (3,9)
A A

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 8 of 15

5 4 3 2 1
 8 7 6 5 4 3 2 1

+MVDDQ +MVDDQ

M_DQMA#[7..0]
(8) M_DQMA#[7..0]
C206 Channel A Bottom Down C216 Channel A Bottom Up
M_DQMA#0 100nF 402 U29 100nF 402 U30
M_DQMA#1 C287 +VREF_U29 49 2 M_MDA13 C289 +VREF_U30 49 2 M_MDA41
M_DQMA#2 100nF VREF DQ0 M_MDA8 100nF VREF DQ0 M_MDA40
4 4
M_DQMA#3 DQ1 M_MDA14 DQ1 M_MDA42
402 5 402 5
M_DQMA#4 M_MAA0 DQ2 M_MDA12 M_MAA0 DQ2 M_MDA47
29 7 29 7
M_DQMA#5 M_MAA1 A0 DQ3 M_MDA15 M_MAA1 A0 DQ3 M_MDA43
30 8 30 8
M_DQMA#6 M_MAA2 A1 DQ4 M_MDA11 M_MAA2 A1 DQ4 M_MDA46
31 10 31 10
M_DQMA#7 M_MAA3 A2 DQ5 M_MDA9 M_MAA3 A2 DQ5 M_MDA45
32 11 32 11
M_MAA4 A3 DQ6 M_MDA10 M_MAA4 A3 DQ6 M_MDA44
35 13 35 13
M_MAA5 A4 DQ7 M_MDA25 M_MAA5 A4 DQ7 M_MDA48
36 54 36 54
M_MAA6 A5 DQ8 M_MDA24 M_MAA6 A5 DQ8 M_MDA50
37 56 37 56
M_MAA7 A6 DQ9 M_MDA28 M_MAA7 A6 DQ9 M_MDA49
38 57 38 57
M_MAA8 A7 DQ10 M_MDA27 M_MAA8 A7 DQ10 M_MDA51
39 59 39 59
D M_MAA9 A8 DQ11 M_MDA30 M_MAA9 A8 DQ11 M_MDA55 D
40 60 40 60
M_MAA10 A9 DQ12 M_MDA31 M_MAA10 A9 DQ12 M_MDA52
28 62 28 62
M_MAA11 A10/AP DQ13 M_MDA26 M_MAA11 A10/AP DQ13 M_MDA54
41 63 41 63
M_QSA[7..0] A11 DQ14 M_MDA29 A11 DQ14 M_MDA53
(8) M_QSA[7..0] 65 65
DQ15 DQ15
M_QSA0 14 14
M_QSA1 NC NC +MVDDQ +MVDDQ
17 17
M_QSA2 M_CLKA0 NC#17 M_CLKA1 NC#17
45 19 45 19
M_QSA3 M_CLKA#0 CK NC#19 M_CLKA1# CK NC#19
46 25 46 25
M_QSA4 M_CKEA CK NC#25 M_MAA14 M_CKEA CK NC#25 M_MAA14
44 42 44 42
M_QSA5 CKE NC#42 CKE NC#42
43 43
M_QSA6 NC#43 +MVDDC NC#43 +MVDDC R60 R62
50 50
M_QSA7 M_CSA#0 NC#50 M_CSA#0 NC#50 4.7K 4.7K
24 53 24 53
M_RASA#0 CS NC#53 M_RASA#0 CS NC#53
23 23 402 402
M_CASA#0 RAS M_CASA#0 RAS
22 1 22 1
M_WEA# CAS VDD +MVDDQ M_WEA# CAS VDD +MVDDQ +VREF_U29 +VREF_U30
21 18 21 18
WE VDD#18 WE VDD#18
33 33
VDD#33 VDD#33
3 3
M_QSA1 VDDQ M_QSA5 VDDQ R61 R63
16 9 16 9
M_QSA3 LDQS VDDQ#9 M_QSA6 LDQS VDDQ#9 4.7K 4.7K
51 15 51 15
UDQS VDDQ#15 UDQS VDDQ#15
55 55 402 402
VDDQ#55 VDDQ#55
61 61
M_DQMA#1 VDDQ#61 M_DQMA#5 VDDQ#61
20 20
M_CLKA0# M_DQMA#3 LDM M_DQMA#6 LDM
(3,8) M_CLKA#0 47 34 47 34
M_CLKA1# UDM VSS UDM VSS
(3,8) M_CLKA#1 48 48
VSS#48 VSS#48
66 66
M_MAA13 VSS#66 M_MAA13 VSS#66
26 6 26 6
M_MAA12 BA0 VSSQ#6 M_MAA12 BA0 VSSQ#6
27 12 27 12
M_CLKA0 BA1 VSSQ#12 BA1 VSSQ#12
(3,8) M_CLKA0 52 52
M_CLKA1 VSSQ VSSQ
(3,8) M_CLKA1 58 58
VSSQ#58 +MVDDQ VSSQ#58
64 64
+MVDDQ VSSQ#64 VSSQ#64
4MX16X4 4MX16X4
M_CKEA C226 <3RD PART FIELD> C236 <3RD PART FIELD>
(3) M_CKEA
M_WEA# 100nF 402 U33 100nF 402 U34
(3) M_WEA#
M_CASA#0 C288 +VREF_U33 49 2 M_MDA23 C290 +VREF_U34 49 2 M_MDA63
(3) M_CASA# VREF DQ0 VREF DQ0
M_RASA#0 100nF 4 M_MDA22 100nF 4 M_MDA61
(3) M_RASA# DQ1 DQ1
M_CSA#0 402 5 M_MDA21 402 5 M_MDA62
C (3) M_CSA#0 DQ2 DQ2 C
M_MAA0 29 7 M_MDA20 M_MAA0 29 7 M_MDA58
M_MAA1 A0 DQ3 M_MDA19 M_MAA1 A0 DQ3 M_MDA60
30 8 30 8
M_MAA2 A1 DQ4 M_MDA18 M_MAA2 A1 DQ4 M_MDA57
31 10 31 10
M_MAA3 A2 DQ5 M_MDA17 M_MAA3 A2 DQ5 M_MDA56
32 11 32 11
M_MAA4 A3 DQ6 M_MDA16 M_MAA4 A3 DQ6 M_MDA59
35 13 35 13
M_MAA5 A4 DQ7 M_MDA7 M_MAA5 A4 DQ7 M_MDA38
36 54 36 54
M_MAA6 A5 DQ8 M_MDA5 M_MAA6 A5 DQ8 M_MDA39
37 56 37 56
M_MAA7 A6 DQ9 M_MDA4 M_MAA7 A6 DQ9 M_MDA37
38 57 38 57
M_MAA[14..0] M_MAA8 A7 DQ10 M_MDA6 M_MAA8 A7 DQ10 M_MDA36 +MVDDQ +MVDDQ
(3) M_MAA[14..0] 39 59 39 59
M_MAA9 A8 DQ11 M_MDA0 M_MAA9 A8 DQ11 M_MDA34
40 60 40 60
M_MAA0 M_MAA10 A9 DQ12 M_MDA1 M_MAA10 A9 DQ12 M_MDA33
28 62 28 62
M_MAA1 M_MAA11 A10/AP DQ13 M_MDA2 M_MAA11 A10/AP DQ13 M_MDA32
41 63 41 63
M_MAA2 A11 DQ14 M_MDA3 A11 DQ14 M_MDA35
65 65
M_MAA3 DQ15 DQ15 R68 R70
M_MAA4 14 14 4.7K 4.7K
M_MAA5 NC NC
17 17 402 402
M_MAA6 M_CLKA0 NC#17 M_CLKA1 NC#17
45 19 45 19
M_MAA7 M_CLKA0# CK NC#19 M_CLKA1# CK NC#19 +VREF_U33 +VREF_U34
46 25 46 25
M_MAA8 M_CKEA CK NC#25 M_MAA14 M_CKEA CK NC#25 M_MAA14
44 42 44 42
M_MAA9 CKE NC#42 CKE NC#42
43 43
M_MAA10 NC#43 +MVDDC NC#43 +MVDDC R69 R71
50 50
M_MAA11 M_CSA#0 NC#50 M_CSA#0 NC#50 4.7K 4.7K
24 53 24 53
M_MAA12 M_RASA#0 CS NC#53 M_RASA#0 CS NC#53
23 23 402 402
M_MAA13 M_CASA#0 RAS M_CASA#0 RAS
22 1 22 1
M_MAA14 M_WEA# CAS VDD +MVDDQ M_WEA# CAS VDD +MVDDQ
21 18 21 18
WE VDD#18 WE VDD#18
33 33
VDD#33 VDD#33
3 3
M_QSA2 VDDQ M_QSA7 VDDQ
16 9 16 9
M_QSA0 LDQS VDDQ#9 M_QSA4 LDQS VDDQ#9
51 15 51 15
UDQS VDDQ#15 UDQS VDDQ#15
55 55
VDDQ#55 VDDQ#55
61 61
M_DQMA#2 VDDQ#61 M_DQMA#7 VDDQ#61
20 20
M_DQMA#0 LDM M_DQMA#4 LDM
47 34 47 34
UDM VSS UDM VSS
48 48
VSS#48 VSS#48
66 66
M_MAA13 VSS#66 M_MAA13 VSS#66
26 6 26 6
M_MAA12 BA0 VSSQ#6 M_MAA12 BA0 VSSQ#6
27 12 27 12
BA1 VSSQ#12 BA1 VSSQ#12
52 52
B VSSQ VSSQ B
58 58
VSSQ#58 VSSQ#58
64 64
VSSQ#64 VSSQ#64
4MX16X4 4MX16X4
<3RD PART FIELD> <3RD PART FIELD>
(8) M_MDA[63..0]
Channel A Top Down Channel A Top Up

Put 1 1uF cap per power pin of memory

+MVDDQ +MVDDC +MVDDQ +MVDDC

C572 C573 C574 C575 C576 C577 C578 C579 C580 C581
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
402 402 402 402 402 402 402 402 402 402

+MVDDQ +MVDDC +MVDDQ +MVDDC DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AND DQM ACCORDINGLY
AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS
C592 C593 C594 C595 C596 C597 C598 C599 C600 C601
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
402 402 402 402 402 402 402 402 402 402
All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed
A A
per memory chip. As close to the pin as possible.

+MVDDC +MVDDQ

ATI Technologies Inc.

1 Commerce Valley Drive East
C229 C231 C232 C235 C221 C222 C223 C224 C237 C238 C239 C243 Markham, Ontario
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Canada, L3T 7X6
402 402 402 402 402 402 402 402 402 402 402 402
(905) 882-2600
Title PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 9 of 15
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

GPIO[6..0]
GPIO[6..0] (2)
GPIO0
OPTION STRAPS GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6 GPIO[13..8]
GPIO[13..8] (2)
+3.3V_BUS GPIO8
GPIO9
GPIO10
GPIO11
GPIO0 R201 10K DESKTOP GPIO12
D GPIO13 D
R202 10K MOBO
GPIO1 R203 10K DESKTOP
STRAPS PIN DESCRIPTION ASIC DEFAULT
R204 10K MOBO
STRAP_B_PTX_PWRS_ENB GPIO0 Tansmitter Power Savings Enable 0
0: 50% Tx output swing for mobile mode
GPIO2 R205 10K DNI 1: full Tx output swing

R206 10K

STRAP_B_PTX_DEEMPH_EN GPIO1 Transmitter De-emphasis Enable 0

0: Tx de-emphasis disabled for mobile mode
GPIO3 R207 10K Tumwater 1: Tx de-emphasis enabled

R208 10K Grantsdale

PCIE_MODE(1:0) GPIO(3:2) 00: PCI Express 1.0A mode (Grantsdale) 00
01: Kyrene-compatible mode
10: PCI Express 1.0 mode (Tumwater)
GPIO4 R219 10K 11: PCI Express 1.0A mode and short-circuit internal loopback mode
(Rx connected directly to Tx of PHY)
R220 10K DNI
GPIO5 R221 10K DNI STRAP_B_PTX_IEXT GPIO4 Transmitter Extra Current 0
0: normal mode
R222 10K 1: extra current in Tx output stage - potential power savings for mobile mode

GPIO6 R223 10K DNI

R224 10K

GPIO11 R209 10K DNI

STRAP_FORCE_COMPLIANCE GPIO5 Force chip to go to Compliance state quickly for Tester purposes 0
C R210 10K C
0: normal operational mode
1: compliance mode
GPIO12 R211 10K DNI
R212 10K

GPIO13 R213 10K STRAP_B_PPLL_BW GPIO6 PLL Bandwidth 0

0: full PLL Bandwidth
R214 10K DNI 1: reduced PLL bandwidth

GPIO9 R215 10K

R216 10K DNI STRAP_DEBUG_ACCESS GPIO8 Strap to set the debug muxes to bring out DEBUG signals 0
even if registers are inaccessible.

GPIO8 R217 10K DNI

R218 10K

ROMIDCFG(3:0) GPIO(9,13:11) If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
(2) Mem_Strap0
R235 10K DNI 0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
R236 10K 1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
(2) Mem_Strap1
R237 10K DNI 1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
R238 10K 1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM

VIP_DEVICE DVPDATA_20 Indicates if any slave VIP host devices drove this in low during reset.
(VHAD0 net) 0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset

B +VDDR4 B

STRAP P INTERRUPT

(2) LCDDATA16
R227 10K DNI LOW ENABLED (DEFAULT)

R228 10K HIGH DISABLED

(2) LCDDATA17
R229 10K DNI +3.3V_BUS

R250 10K DNI R230 10K SERIAL EEPROM 512K

MEMORY TYPE STRAPS
3

(2) VHAD0
R231 10K DNI R91
SW1B 10K
DIP_SWX2 R232 10K Mem_Strap0 Mem_Strap1
ROM_SO
(2) GPIO8
2

SAM 0 0
U11
INF 1 0 SI/A16 5 2
(2) GPIO9 D Q
HYN 0 1 SCK/WEb 6
(2) GPIO10 C
ELPIDA 1 1 CSb 1
(3) ROMCS# S
HOLD1 7
+3.3V_BUS HOLD
3
W
8 4
VCC VSS
C80 M25P05-AVMN6T
100nF

A A

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 10 of 15
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V +5V +5V +5V

PRIMARY CRT BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1 BAT54SLT1

2
D55 D56 D57 D51 D52 D53 D54

3 3 3 3 3 3 3

1
A_R_DVI-I (12) +5V_VESA
A_G_DVI-I (12)
A_B_DVI-I (12)
MJ2
Pr L51 82nH L54 68nH 1
(2) A_R_DAC1 R
Y L52 82nH L55 68nH 2
(2) A_G_DAC1 G
Pb L53 82nH L56 68nH 3
(2) A_B_DAC1 B
11
DDCDATA_DAC1_R MS0 DDC2_MONID0
12
MS1 DDC2_MONID1(SDA)
4
DDCCLK_DAC1_R MS2 DDC2_MONID2
15
MS3
9 DDC2_MONID3(SCL)
A_HSYNC_DAC1_R NC
13
A_VSYNC_DAC1_R HS
14
VS
5
VSS
6
C407 C408 C409 VSS#6
7
C441 VSS#7
8
R401 75.0R C401 C402 C403 C404 C405 C406 5pF 5pF 5pF 68pF VSS#8
10
R402 75.0R 3.3pF 3.3pF 3.3pF 3.3pF 3.3pF 3.3pF VSS#10
C R403 75.0R 402 402 402 402 402 402 Close to 16
17
CASE C
CASE#17
402 L60 L61 L62
Connector
82nH 82nH 82nH
Place close to ASIC DB15F_slim_RA

6050003000 Old Slim-VGA connector

6052003000 New horizontally aligned Slim-VGA connector
GND_CHASSIS

Place close to CONNECTOR

+5V
+3.3V_BUS
1

R404 R405
4.7K 6.8K
402 2 3 402 DDCDATA_DAC1_5V R415 33R 402 DDCDATA_DAC1_R DB15 pin Standard VGA DDC1 Host DDC2B or DDC2AB Host DDC1/2 Display
(1,2) CRT1DDCDATA DDCDATA_DVI-I_R (12)
BSN20 DDC2B+ Host
Q51 +5V 11 Monitor ID bit 0 Monitor ID bit 0 Monitor ID bit 0 Monitor ID bit 0 Optional
+3.3V_BUS 12 Monitor ID bit 1 Data from display SDA SDA SDA
4 Monitor ID bit 2 Monitor ID bit 2 Monitor ID bit 2 Monitor ID bit 2 Optional
15 Monitor ID bit 3 Open SCL SCL SCL
1

R406 R407 +5V +5V +5V

4.7K 6.8K 9 N/C 50mA min 50mA min 300mA min Optional
402 2 3 402 DDCCLK_DAC1_5V R416 33R 402 DDCCLK_DAC1_R Mechanical Key 1A max 1A max 1A max
(1,2) CRT1DDCCLK DDCCLK_DVI-I_R (12)
BSN20 Hardware
Q52 Support No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

(1,2) A_HSYNC_DAC1 5
B 6 A_HSYNC_DAC1_B R413 51R A_HSYNC_DAC1_R B
A_HSYNC_DVI-I_R (12)
4
U6B
SN74ACT86D

10
8 A_VSYNC_DAC1_B R414 51R A_VSYNC_DAC1_R A_VSYNC_DVI-I_R (12)
(1,2) A_VSYNC_DAC1 9
U6C
SN74ACT86D

13
11
12
U6D
SN74ACT86D

R991 0R
805
R992 0R
805 Three on top side, three at
R993 0R the bottom, spreaded high,
805 middle and low vertically
R997 0R
805
R998 0R
805
R999 0R
805
A A

GND_CHASSIS

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 11 of 15
8 7 6 5 4 3 2 1
 5 4 3 2 1

PRIMARY DVI-I CONNECTOR

INSTALL TERMINATION RESISTORS CLOSE TO ASIC
+5V_VESA J2
M1
R601 330R CASE

(2) TMDS_TX2N
402 1
D TMDS Data2- D
(2) TMDS_TX2P 2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
DDCCLK_DVI-I TMDS Data4+
6
DDCDATA_DVI-I DDC Clock
7
R602 330R DDC Data
8
Analog VSYNC
(2) TMDS_TX1N
402 9
TMDS Data1-
(2) TMDS_TX1P 10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
R603 330R GND (for +5V)
16
Hot Plug Detect
(2) TMDS_TX0N
402 17
TMDS Data0-
(2) TMDS_TX0P 18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
R604 330R TMDS Data5+
22
TMDS Clock Shield
(2) TMDS_TXCP
402 23
TMDS Clock+
(2) TMDS_TXCN 24
TMDS Clock-
(11) A_VSYNC_DVI-I_R
(11) A_R_DVI-I Pr C1
Analog Red
(11) A_G_DVI-I Y C2
Analog Green
(11) A_B_DVI-I Pb C3
Analog Blue
(11) A_HSYNC_DVI-I_R C4
Analog HYNC
C5
Analog GND
(11) DDCCLK_DVI-I_R LAYOUT NOTE: MAY REMOVE R605-R608 IF THERE'S NO SPACE! C6
Analog GND#C6

(11) DDCDATA_DVI-I_R M2
CASE#M2
DVI_A/D

+3.3V_BUS C510
68pF
DNI
C C

R605 R606
20K 20K
402 402
R608 20K
(2) HPD 402

3
1

Q25 1 GND_CHASSIS GND_CHASSIS

D121 CMPT3904

3
2.5V R609

2
DNI 100K Q26 1 R607 20K
402 CMPT3904 402
2

B +12V_BUS B

+5V_VESA
Normal +5V regulated operation
Req = 120.8R R911 R912 R913 R914 R915
This circuit provide upto 58mA
Use 604R, 1206, 1/4W 220R 220R 220R 220R 220R
Multi-footprint
If Iload > 58mA, +5V will drop
3

R901 C901 MC901

REG19 1.0K 10uF_6.3V 4.7uF If Vout is shorted
TL431CDBVR 4 1%
1 402
Current across each Rx is 12V/604R = 20mA
NC

R902
NC
2
1.0K Power dissipated by each Rx is 20mA x 12V = 238mW
5

1%
402
Each Rx are rated 250mW (1/4W)

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 12 of 15
5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

Place Resistors close to ASIC.

A_Y_DAC2
(2) A_G/Y_DAC2
L91
1.8uH
R504 C501 C502
75.0R 82pF 82pF +3.3V_BUS
402 402 402
Place near connector TV Out (SVHS)
0R leaves footprint for Ferrite R578
Beads if req'd for EMI 10K J6
402 R377 0R PIN6 6
(2) SVHS/YPrPbb 402 +12V
A_Y_DAC2_F R519 0R 402 A_Y_DAC2_DIN 3
A_C_DAC2 A_C_DAC2_F R520 0R A_C_DAC2_DIN Y-OUT
(2) A_R/C_DAC2
402 4
L92 A_COMP_DAC2_F R521 0R A_COMP_DAC2_DIN PIN7 C-OUT
402 7
1.8uH PIN5 Comp_out
5
R505 C503 C504 SYNC
C 75.0R 82pF 82pF PIN1 1 C
C507 C508 C509 PIN2 GND
402 402 402 2
82pF 82pF 82pF GND#2
402 402 402 8
R515 R513 R514 CASE
9
0R 220R 220R CASE#9
10
CASE#10
Connector_DIN_Miniature_Circular_7_Pin
A_COMP_DAC2 GND_CHASSIS
(2) A_B/COMP_DAC2
L93
1.8uH
R506 C505 C506
75.0R 82pF 82pF
402 402 402
The 7-pin MiniDIN footprint allows one of the two MiniDINs:
- 7-pin Svideo/Composite MiniDIN P/N 6071001500
- 4-pin Svideo MiniDIN P/N 6070001000

MJ6
Jack_Phono_RCA
PIN7 1

3
B B

GND_CHASSIS

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 13 of 15
8 7 6 5 4 3 2 1
 5 4 3 2 1

DVI/VGA SCREWS MISC. BOARD PARTS

ASSY1
ASSY7 REF5
SCREW
JACKSCREW
ANTISTATIC ATI LOGO
BAG LABEL

6_X_11 ATI_LOGO_LABEL
D ASSY2 D

SCREW
JACKSCREW

ASSY8
BLANK
LABEL
+12V_BUS

9050005900;9050005900;9050005900;9050005900

H101 H100
1
2

JU1

heatsink HEATSINK
7120005800 7120005100

Spring push-pin
MH101 MH100

HEATSINK HEATSINK
7120002700 7120008000

ITW push-pin
C ATX Brackets LP Brackets C

ASSY10 ASSY14

BRACKET BRACKET
DVI ATX DVI LP

NO TABS, DVI LP, NO TABS, DVI

8020032600

ASSY11 ASSY15

BRACKET BRACKET

DVI+MiniDIN ATX DVI+MiniDIN LP

TOP TAB (LP), DIN, DVI LP, TOP TAB, DIN, DVI
8020033000

MT1
MT_Hole_0.136_in. ASSY16 MASSY16

BRACKET Slim-VGA LP BRACKET Slim-VGA LP

Slim-VGA ATX

80200329D0 is removed due to missing symbol LP VGA LP, DUAL TABS, Slim VGA
80200328F0
6052003000 New horizontally aligned Slim-VGA connector 6052003000 New horizontally aligned Slim-VGA connector 6050003000 Old Slim-VGA connector
GND_CHASSIS
ASSY13 ASSY17 MASSY17

BRACKET BRACKET BRACKET

MT2
B MT_Hole_0.136_in. Slim-VGA+MiniDIN ATX Slim-VGA+MiniDIN LP Slim-VGA+MiniDIN LP B

Vid Out Slim VGA LP VID OUT VGA LP, DUAL TABS, DIN, Slim VGA

6052003000 New horizontally aligned Slim-VGA connector 6052003000 New horizontally aligned Slim-VGA connector 6050003000 Old Slim-VGA connector

GND_CHASSIS

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
PCI-E RV370 128M TSOP VO-SV/DI
Size Document Number Rev
Custom 105-A260xx-00C 2
Date: Wednesday, March 24, 2004 Sheet 14 of 15
5 4 3 2 1
 5 4 3 2 1

MEMORY CHANNEL A

D D

TSOP 16Mx16 Memory

MEMORY TERMINATIONS A

MEM A
CLOCK
C C
PRIMARY CRT
DAC1 LOGIC

STRAPS
DVI Connector
TMDS TMDS Terminations
Slim-VGA DB15
BIOS ROM CONN

B B
POWER
REGULATION RV370
TVOUT
DAC2 TVOUT Filters
CONN

AGP

A A

<Variant Name>

PCI-Express REFERENCE RESTRICTION ATI Technologies Inc.

DESIGN NOTICE 1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
THESE SCHEMATICS ARE THESE SCHEMATICS CONTAIN (905) 882-2600
SUBJECT TO MODIFICATION INFORMATION WHICH IS PROPRIETARY
AND DESIGN IMPROVEMENTS. TO AND IS THE PROPERTY OF ATI, AND Title
PLEASE CONTACT ATI FIELD MAY NOT BE USED, REPRODUCED OR PCI-E RV370 128M TSOP VO-SV/DI
APPLICATION ENGINEERING DISCLOSED IN ANY MANNER WITHOUT Size Document Number Rev
BEFORE USING THE INFOR- EXPRESSED WRITTEN PERMISSION B 105-A260xx-00C 2
MATION CONTAINED HEREIN. FROM ATI. Date: Wednesday, March 24, 2004 Sheet 15 of 15
5 4 3 2 1