Ati Agp r300 128mb Bga Dvii Vga Vo Rev 11 SCH

<Core Design> 8 7 6 5 4 3 2 1
Title Schematic No. Date:

AGP R300 128MB BGA DVII VGA VO 105-942XX-30_11 Tuesday, October 01, 2002
Rev
REVISION HISTORY 11
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
6 11 07/26/02 PRODUCTION RELEASE IIII
PCB silkscreen update only. No schematic changes.
7 12 08/19/02 PRODUCTION RELEASE IV

PCB silkscreen update only. No schematic changes.
1. Rev letter changed from 109-94200-11 to 109-94200-12
2. Remove CGND flood on L1 and L6 for MJ4.18
8 20 08/24/02 PRODUCTION RELEASE V

Sheet 1: Added traces to hijack circuit (sheet 24), AGP_TRDY#_R, and AGP_STOP#_R. Removed R12.
Sheet 6: Added R938 and R939 for selection of either 12V or 5V for Vtt regulator.
Sheet 7: Added R936 and R937 for selection of either 12V or 5V for MVDDC regulator.
C
Sheet 8: Added R934 and R935 for selection of either 12V or 5V for MVDDQ regulator. C
Sheet 24: Added Hijack Circuit to compensate for R300 cold boot issues.
9 30A 09/06/02 PROTOTYPE IV

Sheet 1: Added C1127.
Sheet 2: Added trace 8X_DET# to hijack circuit (sheet 24).
Sheet 6: Added C762 to Vc pin of Vtt regulator.
Sheet 7: Added C763 to 12V for MVDDC regulator. Added R954 and C764 to low gate of Q8B.
Sheet 8: Added C765 to Vc pin of MVDDQ regulator.
Sheet 24: Changed Hijack Circuit to compensate for R300 cold boot issues.
10 30B 09/18/02 PROTOTYPE V

PCB silkscreen update. Changed some component location in order to shorten the AGP_CLK lentgh after R946 resistor. No schematic changes.
11 30 09/26/02 PRODUCTION RELEASE VI

Sheet 6: Added R1552 between pins 2 and 3 of VDDC regulator.
B B
A A
8 7 6 5 4 3 2 1
<Core Design> 8 7 6 5 4 3 2 1
Title Schematic No. Date:

AGP R300 128MB BGA DVII VGA VO 105-942XX-30_11 Tuesday, October 01, 2002
Rev
REVISION HISTORY 11
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A PROTOTYPE I.i.
1 00B PROTOTYPE I.i.i.

BASED ON 109-94200-00A.
Sheet 2: Added C731 to input 2 of U2 to provide RC circuit for RESET.
Sheet 3: Added MOSFET Q19 to AGPREF pin of the ASIC to disconnect VREF from the motherboard during RESET time.
Replaced values for R39 (180R) and R40 (68R)
Sheet 4: Added C738 to TPVDD.
Sheet 6: Added header JU2 , capacitor C101, C739,C737 for external +5V power source, B18 connected to external +5V, added C732 to the output of the core regulator.
Added R910, R911.
Replaced values for Q3, Q4, L1, L2, R76, R89, R77, R90, C86, C92.
Removed diodes D4, D5.
Sheet 7: Added C734, and C736. Replaced internal +12V with external 12V. Replaced C120 with the bigger value 470uF. Removed C123, C124. Removed resistor R112 from U48-6 to 12V, that is not used. Added option to short one diode in D6
with R112. Added diode D24 to provide +12v power to MVDDC regulator when external power is not connected.
C C
Sheet 8: Regulator circuit for VDDC_CT replaced with one regulator. Changed source voltage for PVDD, and TPVDD regulators from +5V to +3.3V.
Sheet 9: Added resistors for selection between 4MX32 and 8MX32 memories.
Sheet 10: Added resistors for selection between 4MX32 and 8MX32 memories.
Sheet 11: Connected address lines MAA14 and MAB14 .
Sheet 12: Connected address lines MAC14 and MAD14 .
Sheet 13: Added MAA14, MAB14 as chip selects for Hynix 8MX32 memory.
Sheet 14: Added MAC14, MAD14 as chip selects for Hynix 8MX32 memory.
Sheet 15: Added circuit for detection of external power supply connection.
Sheet 16: Added fail-safe circuit for fan control, and connected internal thermistor from ASIC, VTERM1 is connected through the 0R resistor, R912, to have an option to use A11. Removed 3-pin
header.
Sheet 21: Added pull down resistor R877 on VSYNC_DAC2 for TVout filter enable.
Sheet 22: Added resistor R878 on connector J7. Removed MOSFET switch, and replaced with demultiplexer U96. Added also resistors to bridge the demultiplexer.
Sheet 23: Change GPIO used for Si168 reset to DVALID.
2 00C 06/28/2002 PROTOTYPE I.i.i.I
BASED ON 109-94200-00B.
B
Sheet 3: Replaced Q2 and Q1 with different type 2N7002E. B
Sheet 6: Added capacitors C740, C742 to the drains of the Q3A and Q5A. Added diode D25 to the second phase of the core regulator. Changed resistors values R94, and R98.
Sheet 7: Added capacitors C743, C744, C745, C746 and C747. Changed values for R114 and R117.
Sheet 8: Added capacitors C748. Changed values for R124, R131, R130, R126, R143, R139 and C133.
Sheet 9: Changed value for R138 to 75R.
Sheet10: Changed value for R774 to 75R.
Sheet19: Changed values for R800 and R803 to 0R. Replaced L11, L13, and L15 with R26, R27 and R28 respectively 0R. Added capacitors for HSYNC and VSYNC C749, and
C750.
Sheet20: Added capacitors at HSYNC and VSYNC, at C751, C752.
Sheet21: Added R29, R30, R31 and R32.
Sheet22: Added R925, R926, R927 to remove stubs when VO is used on HDH. Added R928, R929, and R930 to short DMUX (U96) when no VO is installed on the main board. Added R931, R932, and R933 to short DMUX (U96) when
no second VGA is installed.
Sheet23: Removed resistors R805 and R807.
PRODUCTION RELEASE
3 00 07/08/2002
Sheet 6: Replaced diode D25 with Scottkey diode. C91 replaced with 10MM footprint, better quality part.
A A
PRODUCTION RELEASE II
4 10 07/10/2002
Sheet 2: Removed series resistors R7 on AGP_SBSTB#, R9 on AGP_ADSTB1#, and R16 on AGP_ADSTB0#. Added instead pull-up 10K resistors to +VDDQ_BUS with the same designators.
PRODUCTION RELEASE III

5 01 07/19/2002 Adjusted trace on AGP to give clearance for fingers. Remove N625 declaration. Changed soldermask requirement to red.
8 7 6 5 4 3 2 1
5 4 3 2 1
MEMORY CHANNEL A B MEMORY CHANNEL C D
D D
DDR 4M XSHT32
13
(BGA) DDR 4M XSHT32
14
(BGA)
MEMORY TERMINATIONS A B MEMORY TERMINATIONS C D

SHT 11 SHT 12
VGA1
PRIMARY CRT DB15
MA/B[14..0] MDA/B[63..0] QSA/B[7..0]CS0A/B# DQMA/B[0..7] MC/D[14..0]MDC/D[63..0]QSC/D[7..0]C S0C/D# DQMC/D[0..7]
CASA/B#RASA/B# WEA/B# CKEA/BCLKA/B01 CLKA/B01# CASC/D#RASC/D# WEA/B# CKEC/DCLKC/D01CLKC/D01# LOGIC CONN
SHEET 19 SHT 19
MEM A B MEM C D
DAC1 R G B HSY VSY DDC1DATA DDC1CLK
C C
STRAPS
SHT 15
DVI-I1
T MDS TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
INTEG TMDS CONN
LOGIC SHT 18
BIOS ROMCS# ROM

SHT 17
TVO
R300 DVO DVO, VIP Host, VIP Data
External
FAN SHEET 3, 4, 5, 09, 10 VIP HDH
power
SHT 16
SHT 23
Y/R C/G COMP/B H2SYNC CRT2DDCDATA CRT2DDCCLK V2SYNC
B B
POWER VDDC VDDC18 VDD VTT VDDQ
PVDD TPVDD MPVDD
REGULATION A2VDD Vref
SHT 6,7,8 TVOUT TVout
D
DAC2 LOGIC
E SHT 22
CONN
M
GPIO U
SEL
AGP X SECONDARY
CRT LOGIC
SHT 22 SHT 19
AD31..0 CBE3..0 CPUCLK STOP# PAR REQ#

IR DY# GNT# TR DY# DEVSEL# RESET#
FRAME# CLK INTR SUSPEND# SERR#
AGPREF SBA[7..0] ST2..0 SB_STB SB_STB#
+3.3V +5V +12V AD_STB1 AD_STB1# AD_STB0 AD_STB0# RBF#
A A
<Core Design>
AGP BUS REFERENCE RESTRICTION ATI Technologies Inc.

2X/4X/8X DESIGN NOTICE 1 Commerce Valley Drive East
Markham, Ontario
SHT 2 Canada, L3T 7X6
THESE SCHEMATICS ARE THESE SCHEMATICS CONTAIN (905) 882-2600
SUBJECT TO MODIFICATION INFORMATION W HICH IS PROPRIETARY
AND DESIGN IMPROVEMENTS. TO AND IS THE PROPERTY OF ATI, AND Title
PLEASE CONTACT ATI FIELD MAY NOT BE USED, REPRODUCED OR AGP R300 128MB BGA DVII VGA VO
APPLICATION ENGINEERING DISCLOSED IN ANY MANNER W ITHOUT Size Document Number Rev
BEFORE USING THE INFOR- EXPRESSED WRITTEN PERMISSION B 105-942XX-30_11 11
MATION CONTAINED HEREIN. FROM ATI. Date: Tuesday, October 01, 2002 Sheet 1 of 25
5 4 3 2 1
8 7 6 5 4 3 2 1
2X/4X/8X AGP BUS +12V_BUS +5V_BUS +3.3V_BUS
C1 C2 C3
GND_MPVSS GND_TPVSS GND_A2VSSN GND_AVSSQ GND_RSET 100uF 16V 100uF 16V 100uF 16V
GND_TVVSSN ALU
GND_AVSSN GND_PVSS GND_TXVSSR GND_A2VSSQ GND_R2SET
NOTE: THIS IS A DRAWING. THESE

AGP_C/BE#[3..0]
D GROUNDS MUST BE MANUALLY AGP_C/BE#[3..0] (3) D
AGP_AD[31..0]
CONNECTED TO THE GROUND PLANE AGP_AD[31..0] (3)
AGP_SBA[7..0]
AGP_SBA[7..0] (3)
AGP_ST[2..0]
AGP_ST[2..0] (3)
+12V_BUS
(3) AGP_INTR#
+3.3V_BUS TYDET R1 0R G ND_TY +3.3V_BUS
+VDDQ_BUS +5V_BUS
MAGP1 +VDDQ_BUS
A1 12V OVRCNT# B1
TYDET A2 B2
AGP_GC_8X_DET# TYPEDET# 5.0V
A3 GC_DET#/RESEVED 5.0V B3
R2 0R A4 B4
G ND_TY A5 USB- USB+
GND GND B5
A6 INTA# INTB# B6
AGP_RST# A7 B7 AGP_AGPCLK_R R3 0R
RST# CLK AGP_AGPCLK (3,24)
(3) AGP_GNT# A8 GNT# REQ# B8 AGP_REQ# (3)
A9 VCC3.3 VCC3.3 B9
AGP_ST1 A10 B10 AGP_ST0 C4
R4 0R ST1 ST0 AGP_ST2 10pF
(3) AGP_MB_8X_DET# A11 MB_DET#/RESERVED ST2 B11
R5 0R AGP_DBI_HI_R A12 B12 DNI
(3) AGP_DBI_HI DBI_HI/PIPE# RBF# AGP_RBF# (3)
A13 B13 AGP_DBI_LO_R R6 0R
(3) AGP_WBF# GND GND AGP_DBI_LO (3)
A14 WBF# DBI_LO/RESERVED B14
+VDDQ_BUS AGP_SBA1 A15 B15 AGP_SBA0
R7 8K2 SBA1 SBA0
A16 VCC3.3 VCC3.3 B16
AGP_SBA3 A17 B17 AGP_SBA2
AGP_SBSTB#_R SBA3 SBA2 AGP_SBSTB_R R8 0R
(3) AGP_SBSTB# A18 SB_STB# SB_STB B18 AGP_SBSTB (3)
C A19 B19 C
AGP_SBA5 GND GND AGP_SBA4
A20 SBA5 SBA4 B20
AGP_SBA7 A21 B21 AGP_SBA6
SBA7 SBA6
A22 KEY KEY B22
A23 KEY KEY B23
A24 KEY KEY B24
A25 KEY KEY B25
AGP_AD30 A26 B26 AGP_AD31
+VDDQ_BUS AGP_AD28 AD30 AD31 AGP_AD29
A27 AD28 AD29 B27
A28 VCC3.3 VCC3.3 B28
R9 8K2 AGP_AD26 A29 B29 AGP_AD27
AGP_AD24 AD26 AD27 AGP_AD25
A30 AD24 AD25 B30
AGP_ADSTB1#_R A31 B31 AGP_ADSTB1_R R10 0R
(3) AGP_ADSTB1# GND GND AGP_ADSTB1 (3)
A32 AD_STB1# AD_STB1 B32
AGP_C/BE#3 A33 B33 AGP_AD23
C/BE3# AD23
A34 VDDQ VDDQ B34
A36 AD20 AD19 B36
A37 GND GND B37
AGP_AD16 AD18 AD17 AGP_C/BE#2
A39 AD16 C/BE2# B39
A40 VDDQ VDDQ B40
(3) AGP_FRAME# A41 FRAME# IRDY# B41 AGP_IRDY# (3)
A42 KEY KEY B42
A43 KEY KEY B43
A44 KEY KEY B44
(24) AGP_TRDY#_R A45 KEY KEY B45
DNI R13 0R AGP_TRDY#_R A46 B46 AGP_DEVSEL#_R
(3,24) AGP_TRDY# DNI R15 TRDY# DEVSEL# AGP_DEVSEL#_R (3,24)
0R AGP_STOP#_R A47 B47
(3,24) AGP_STOP# STOP# VDDQ
(24) AGP_STOP#_R A48 PME# PERR# B48
B AGP_PAR_R A49 B49 B
GND GND
A50 PAR SERR# B50
AGP_AD15 A51 B51 AGP_C/BE#1
(3) AGP_PAR AD15 C/BE1#
A52 VDDQ VDDQ B52
+VDDQ_BUS AGP_AD11 AD13 AD14 AGP_AD12
A54 AD11 AD12 B54
A55 GND GND B55
R16 8K2 AGP_AD9 A56 B56 AGP_AD10
AGP_C/BE#0 AD9 AD10 AGP_AD8
A57 C/BE0# AD8 B57
AGP_ADSTB0#_R A58 B58 AGP_ADSTB0_R R17 0R
(3) AGP_ADSTB0# VDDQ VDDQ AGP_ADSTB0 (3)
A59 AD_STB0# AD_STB0 B59
AD6 AD7
A61 GND GND B61
A63 AD2 AD3 B63
A64 VDDQ VDDQ B64
AGP_VREFGC AD0 AD1
(3,24) AGP_VREFGC A66 VREFGC VREFCG B66 AGP_AGPREF (3)
UNIVERSAL AGP BUS
C1127
+5V_BUS 1.0uF
SYMBOL LEGEND
C5 R19
100nF 10K DNI DO NOT
INSTALL
14
A U2A A
1 AGP_RST# # ACTIVE
R22 100R 3 LOW
(3,9,10,23,24) AGP_RESET# <Core Design>
2 PW GOOD_VDDC (6) ATI Technologies Inc.
DIGITAL
74ACT08MTC DNI G ROUND 1 Commerce Valley Drive East
7
Markham, Ontario
DNI R854 R25 ANALOG Canada, L3T 7X6
180R 180R C731 G ROUND (905) 882-2600
100nF
Title AGP R300 128MB BGA DVII VGA VO
Size Document Number 105-942XX-30_11 Rev
B 11
Date: Tuesday, October 01, 2002 Sheet 2 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U42A
D PART 1 OF 8 D
AV39 Y36 AGP_AD0
(2,24) AGP_AGPCLK PCICLK AD0
A Y37 AGP_AD1
AD1 AGP_AD2
(2) AGP_GNT# AP38 AA36
AU39
GNT# G AD2
AA37 AGP_AD3
(2) AGP_REQ# REQ# AD3
AM39 P AB36 AGP_AD4
(2) AGP_RBF# RBF# AD4
AU37 AB37 AGP_AD5
(2) AGP_INTR# INTA# / AD5
AP35 AC36 AGP_AD6
(2,9,10,23,24) AGP_RESET# RST# AD6
(2) AGP_WBF# AM36 WBF# P AD7 AD37 AGP_AD7
AG35 AF37 AGP_AD8
PLACE
(2) AGP_FRAME#
AE35
FRAME# C AD8
AG36 AGP_AD9
(2,24) AGP_TRDY# TRDY# AD9
CLOSE TO
(2) AGP_IRDY# AH35 IRDY#
I AD10 AG37 AGP_AD10
THE ASIC AD35 AH36 AGP_AD11
(2,24) AGP_DEVSEL#_R DEVSEL# AD11
PIN AB35 AH37 AGP_AD12
(2,24) AGP_STOP# STOP# AD12
(2) AGP_PAR AA35 PAR
I AD13 AJ36 AGP_AD13
AGPREFCG AG34 AK37 AGP_AD14
AGP_C/BE#[3..0] AGPREF N AD14 AGP_AD15
(2) AGP_C/BE#[3..0] AL36 AGPTEST AD15 AK36
T AD16 Y39 AGP_AD16
AGP_C/BE#0 AF36 AB39 AGP_AD17
C14 AGP_C/BE#1 CBE#0 E AD17 AGP_AD18
AL37 CBE#1 AD18 AA38
100nF AGP_C/BE#2 AA39 R AC39 AGP_AD19
AGP_ST[2..0] AGP_C/BE#3 CBE#2 AD19 AGP_AD20
(2) AGP_ST[2..0] AD38 CBE#3 F AD20 AB38
AD39 AGP_AD21
AGP_ST0 A AD21 AGP_AD22
AP39 ST0 AD22 AC38
AGP_ST1 AN39 C AE39 AGP_AD23
AGP_SBA[7..0] AGP_ST2 ST1 AD23 AGP_AD24
(2) AGP_SBA[7..0] AN38 ST2 AD24 AG39
E AG38 AGP_AD25
AGP_SBA0 AD25 AGP_AD26
AT37 SBA0 AD26 AH39
AGP_SBA1 AT38 AH38 AGP_AD27
AGP_SBA2 SBA1 AD27 AGP_AD28
AT39 SBA2 AD28 AJ39
C AGP_SBA3 AR39 AJ38 AGP_AD29 C
AGP_SBA4 SBA3 AD29 AGP_AD30
AP36 SBA4 AD30 AK39
AGP_SBA5 AP37 AK38 AGP_AD31 AGP_AD[31..0]
SBA5 AD31 AGP_AD[31..0] (2)
AGP_SBA6 AN36
AGP_SBA7 SBA6
AN37 SBA7
AL38 AGP_DBI_HI
DBI_HI AGP_DBI_HI (2)
AGP_SBSTB AR38 AGP 8X DBI_LO AL39 AGP_DBI_LO
(2) AGP_SBSTB SB_STBF AGP_DBI_LO (2)
AGP_SBSTB# AR37
(2) AGP_SBSTB# SB_STBS
AGP_ADSTB0 AE37 AL35 AGP_MB_8X_DET#
(2) AGP_ADSTB0 AD_STBF0 AGP8X_DET# AGP_MB_8X_DET# (2)
AGP_ADSTB0# AD36
(2) AGP_ADSTB0# AD_STBS0
AGP_ADSTB1 AF39
(2) AGP_ADSTB1 AD_STBF1
AGP_ADSTB1# AE38
(2) AGP_ADSTB1# AD_STBS1
AP33 TEST_AGPCLK TP1
TEST_AGPCLK
R300
DNI +VDDQ_BUS
R895 0R
(2) AGP_AGPREF
R39 169R
3
Q19
3
NDS335N
(2,9,10,23,24) AGP_RESET# 1
TEST 1
2
AGPREFCG 2N7002E
2
Q2 R40 71.5R
B B
+3.3V_BUS +VDDQ_BUS
(24) 8X_DET#
R18 R20
47K 3.32K
3
U2B
AGP_MB_8X_DET# 4
(2) AGP_MB_8X_DET#
6 TEST 1
+5V_BUS 5 2N7002E
R21 1.47K AGP_VREFGC
AGP_VREFGC (2,24)
2
74ACT08MTC Q1
R23
1K R24 C6
1.02K
10nF
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X) *
A <Core Design> A
ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Size Document Number Rev
B 105-942XX-30_11 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VID[7..0]
(15,23) VID[7..0]
U42B
PART 2 OF 8
V ID0 AW35 AV29
VID0 TXCM TXCM (18)
V ID1 AV35 V AW29
VID1 TXCP TXCP (18)
V ID2 AU35 AV30
VID2 I TX0M TX0M (18)
Video Capture & Test

V ID3 AT35 AW30
VID3 TX0P TX0P (18)
V ID4 AW34 D AV31
VID4 TX1M TX1M (18)
TMDS / Flat Panel

V ID5 AV34 AW31
V ID6 AU34
VID5 E TX1P
AV32
TX1P (18)
+TPVDD +VDDC_CT
VID6 TX2M TX2M (18)
V ID7 AT34 VID7
O TX2P AW32 TX2P (18) Ba1
AW36 B3 DNI
(23) CLK_VIDCLK VPCLK0
(15,23) D VALID AU36 DVALID TPVDD AW28
APPLICATION TVOVMODE DVOVMODE
(15) PSYNC AV36 PSYNC
& TPVSS AV28 C16 Bead
D AT29 1uF 1uF C17 C18 D
TVout w/ Rage Theatre 0V X R43 1K TESTEN TXVDDR C738 C15 100pF 100nF 22uF 16V
AT36 TESTEN TXVDDR AT28
ext 24b DDR TMDS VDDC18 VDDC18 TP7 M TXVSSR AU28 R44
ext 12b DDR TMDS&TVout 0V VDDC18 TP27 AW21 AU29 Rk 0R
24b SDR TMDS 0V 0V TP28 TVOCLKO U TXVSSR DNI
AV21 TVOCLKI TXVSSR AU30
(22,23) TVO0
TVO0 AW19 TVODATA0
L TXVDDR GND_TPVSS +VDDC_CT
TVO1 AV19 AR31 Ba2
(23) TVO1
TVO2 TVODATA1 T HPD1 HPD1 (18)
B4
(22,23) TVO2 AU19 TVODATA2 HPD2 AR33 HPD2 (23)
+VDDC_CT
(23) TVO3
TVO3 AT19 I
TVO4 TVODATA3 C19 Bead
(23) TVO4 AW20 TVODATA4 M DDC1DATA AU32 CRT1DDCDATA (20)
DNI R45 0R TVO5 AV20 AU31 C20 C21
DNI
(23) TVO5 TVODATA5 E DDC1CLK CRT1DDCCLK (20)
R46 0R TVO6 AU20 22uF 16V 100pF 100nF
(15) TVO6 TVODATA6
TVO7 TP2
DAC / VGA
(15) TVO7 AT20 TVODATA7 D AUXWIN AP31
R47 0R TVO8 AU21 AT30
(15) TVO8 TVODATA8 I VSYNC V SYNC_DAC1 (20)
R48 0R AT21 AT31
TVODATA9 HSYNC HSYNC_DAC1 (20)
AR19 A AP32 GND_TXVSSR
TVOVMODE STEREOSYNC STEREOSYNC (22)
R AW24 R_DAC1 (20)
AT18 DVOVMODE G AW23 G_DAC1 (20)
(23) CLK_DVOCLK0 AW17 DVOCLK0 B AW22 B_DAC1 (20)
TVOut, DVOut & ROM

(23) CLK_DVOCLK1 AV17 DVOCLK1
(23) DVOCNTL0 AU15 DVOCNTL0 AVDD AV23
DVO[11..0] AV15 AV24
(23) DVO[11..0] (23) DVOCNTL1 DVOCNTL1 AVDD
(23) DVOCNTL2 AW15 DVOCNTL2 AVSSN AR24
DVO0 AT15 AT24
DVO1 AR15 DVODATA0 AVSSN TP33
DVODATA1 AVSSQ AU22
DVO2 AW16 TP34
DVO3 AV16 DVODATA2 R52 499R +3.3V_BUS +3.3V_BUS
Note1 : PVSS, and MPVSS go to ground plane directly through their own DVODATA3 RSET AV22
DVO4 AU16 AV33 GND_AVSSQ Ba3 +VDDC_CT
dedicated via. No connection with other VSS.. DVODATA4 VIPCLK CLK_VIPCLK (23) B5
DVO5 R53 R54 +AVDD
VIP Host
AT16 DVODATA5 VPHCTL AW33 VPHCTL (23)
Note2 : Separate vias for AVSSQ (A2VSSQ), and AVSSN (A2VSSN) to DVO6 AU17 AU33 GND_RSET 4.7K 4.7K
C DVODATA6 VHAD0 VHAD0 (15,23) C
ground plane. DVO7 AT17 AT33 1uF
DVODATA7 VHAD1 VHAD1 (23)
DVO8 AR17 Ra9 Ra10 C23 Bead
DVO9 AW18 DVODATA8 SCL C22 C24
Note3 : AVDD/AVSSN power need to use a pair of short traces (20mil at DVODATA9 SCL AR27 SCL (23)
DVO10 AV18 AR28 S DA DNI 100nF 22uF 16V
least) and direct to link to AVDD & AVSSN balls, the ground return point DVODATA10 SDA S DA (23)
DVO11 AU18
should be near the ground trace start point. DVODATA11
AW38 R300_XOUT
XTALOUT
XTALI 2C
AV38 R300_XIN GND_AVSSN
XTALIN +PVDD B6 +VDDC_CT
Note4: Rset resistor ground point should link to AVSSQ trace, or have via (15,17) ROMSCK AP30 ROMSCK Ba4
AP29 AW37 DNI
at resistor directly to ground plane. (15,17) ROMSO ROMSO PVDD
AR29 AV37 1uF
(15,17) ROMSI ROMSI PVSS
Note5 : Populate Ra9 and Ra10 only if they are not populated on page ROMCS# AR30 C26 C27 200R
(15,17) ROMCS# ROMCS#
24 or 25 or 31 or 32. C7 +MPVDD C25 100nF
MPVDD GND_MPVSS DNI 22uF 16V
MPVSS C6
TP3 TEST_MCLK F9 TEST_MCLK
PLL
AV25 R55 715R TP35
TP4 TEST_YCLK R2SET GND_PVSS
G6 TEST_YCLK
AW27 +A2VDD
C-R R/C_DAC2 (22)
AW26 GND_R2SET
Y-G G /Y_DAC2 (22)
AW25 1uF
COMP_B B/COMP_DAC2 (22)
AR32 C32
H2SYNC HSYNC_DAC2 (21)
AT32 C31 C33
V2SYNC V SYNC_DAC2 (21)
+VDDC_CT DNI 100nF 22uF 16V
DAC2
+VDDDI B7
DDC2CLK AR34 CRT2DDCCLK (21)
+ VDDDI AR35
DDC2DATA CRT2DDCDATA (21)
AV26 GND_A2VSSN
1uF C28 Bead A2VDD
A2VDD AV27
C30 22uF 16V + VDDDI AU23 AT25 +VDDC_CT
C29 100nF +VDD2DI AU27 VDD1DI A2VSSN B9
VDD2DI A2VSSN AU26 Ba5
+A2VDDQ
AU24 AU25 1uF
B VSS1DI A2VDDQ C38 C39 Bead B
AT26 VSS2DI A2VSSQ AT27
+VDDC_CT C37 100nF
+VDD2DI B8 R300 22uF 16V
+VDD2DI Crystal Circuit
1uF C34 Bead DNI C40 DNI R56 0R R300_XIN GND_A2VSSQ
1
C36 22uF 16V 10pF DNI DNI +MPVDD Ba6 B10 +VDDC_CT
C35 100nF MY1 Ra1 R57 +MPVDD DNI
27 MHZ 1M R65 1uF 1 uF 1uF
Ra4 0R
C41 DNI R58 0R R59 0R R300_XOUT C45 C46 200R
2
10pF Ra8 C42 C43 C44 100nF

DNI GND_MPVSS DNI DNI DNI 22uF 16V
GND_MPVSS
CLOCK SOURCE SELECTION

Oscillator Circuit
XTAL/OSC. INSTALL NOT INSTALL
Ra1,Ra4 Ra8
CRYSTAL Crystal Circuit(27M) Oscillator circuit +3.3V_BUS Y1
R300 alone 8 5 R63 107R
C47 VDD OUT
Ra1 = 0R Ra4,Ra8
OSC (OPTION 1) Oscillator circuit(27M) Crystal Circuit 4 GND E/D 1
100nF +3.3V_BUS
OSC (OPTION 2) Ra4,Ra8 Ra1 27.000MHz
Oscillator circuit(27M) Crystal Circuit R66
DEFAULT 150R
A A
<Core Design> ATI Technologies Inc.

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
B 105-942XX-30_11 11
8 7 6 5 4 3 2 1
5 4 3 2 1
+MVDDQ +VDDC_CT
+3.3V_BUS
Da1
+ VDDC +VDDC_CT
REGULATOR
+5V_BUS
FOR
DNI DVO/TVO(+1.8V) C50 Diodes Da1
100nF
and Da2 are
D
DNI needed to +3.3V_BUS D
+VTVO/DVO
protect ASIC
during power Da2
ramping.
DNI
+VDDC
1%
DNI
1
1% DNI DNI CP1A
10nF
8
USE ONLY IF TVO OR DVO MODES ARE 1.8V
CP2C
C61
C 10 uf C
PLACE DIRECTLY
UNDERNEATH ASIC
AT THE OPPOSITE
CORNER OF THE
VDDC FEED.
(16) VTERM2
+VDDQ_BUS PLACE DIRECTLY UNDERNEATH
VDDP SECTION OF ASIC.
USE 47uF
4
TANTALUM
CAPACITOR OR C65 CP5B CP5C CP5D C675
HIGHER 10 uf 10nF 10nF 10nF
100nF
5
+3.3V_BUS
(16) VTERM1
3
CP11A CP11C
C67 10nF 10nF
22uF 16V
6
+MVDDQ
C68
+3.3V_BUS 47uF 6.3V
B B
4
PLACE DIRECTLY
UNDERNEATH CP8A CP8B CP8D
CHANNELS A C70 10nF 10nF 10nF
AND B 10 uf
5
+VDDTVO
2
PLACE DIRECTLY
UNDERNEATH CP9B
CHANNELS C C73 10nF
AND D 10 uf
7
+VDDDVO
2
CP13A CP13B
+VDDQ_BUS 10nF 10nF
7
+VDDTVO +3.3V_BUS
B12 200R
+VTVO/DVO
DNI
A A
<Core Design>

+VDDDVO +3.3V_BUS
Markham, Ontario
+VTVO/DVO Canada, L3T 7X6
DNI (905) 882-2600
Title AGP R300 128MB BGA DVII VGA VO VIP
Custom 105-942XX-30_11 11
5 4 3 2 1
8 7 6 5 4 3 2 1
Layout Guide Lines for switching regulators

+3.3V_BUS
CORE REGULATOR VDDC B16
1) Feedback trace from the voltage divider resistors to the controller as short as possible.
***
2) Trace from VIN to Qb1 should be in the same layer, with no via, width no less than 2MM
60R
+5V_BUS 3) VIN_SOURCE should be a 2-3" snaked trace (with at least 6 bends.) The trace width
should be 2 MM.
R72 4) Components with " ** " should have two vias on each pad
PW
2.2R C76 5) Components with " *** " should have three vias on each pad.
D R873 0R C740 470uF 6.3V D
DNI 6) Connections indicated by bold thick line are high current path. Short, thick traces (at
PW GOOD_VDDC (2)
1.0uF least 30 mil) should be used.
7
8
R910 R911 Q3A
C77 1nf R71 5.1R 2 +VDDC

100K 100K
FDS6898A L1 1.5uH
5 1
+12V_BUS DNI DNI 1 2
6
U43 Q3B *** *** ***
1 20 DNI C80 DNI C81 DNI C82 *** **
R73 R1552 56R VREF GND C85 R76 51.1R R77 150R R78 C10 * C11 * C12 * C732 C84
2 19 R79 5.1R 4 511R 470uF 22uF 16V
2.2R +IN2 PWRGD 1nF C86 2.2uF 470uF 470uF 10V 470uF 470uF 10V 470uF 470uF 10V
1% **
3 18 FDS6898A *** *** *** ***
3
-IN2 -IN1
Rb1
4 VCC SS/ENA 17 Rb5 DNI
Rb9 R80 0R Rb4 Cb4
C87 R81 0R 5 16 R82 0R
1uF CL2- CL1- DUAL FOOTPRINT DUAL FOOTPRINT DUAL FOOTPRINT
Rb10
R83 0R 6 15 R84 0R R85 100R
CL2+ CL1+ C88 0.22uF
7 BST2 BST1 14 Rb6
C89 10nF PW1 B18 +5VEXT R87
8 13 60R 2.43K
DH2 DH1
C90
DNIRb7 Rb8 DNI C91 Bb1
1%
9 DL2 DL1 12
7
8
1uF R74 R75 C741 470uF Rb2
33K 100K 10 11 1.0uF Q4A
C PGND BSTC C
Cb1 Cb2 R88 5.1R 2 Part VDDC Rb1 Rb2
DNI DNI SC1175CSW
C78 C79 Alternate part IRU3047 FDS6898A L2 1.5uH
5 1
2.2nF 150pF 1 2 1.2V 110R 1% DNI
6
SC1175
Q4B
R89 51.1R R90 150R IRU3047 1.5V 511R 1% 2.43k 1%
R91 5.1R 4
C92 2.2uF
FDS6898A
3
C93 Part INSTALL DO NOT INSTALL
10nF
Rb4, Rb6, Rb9, Rb10, Cb4 Rb7, Rb8, Rb5, Cb1,
R92 100R SC1175 Cb2, Db2, Db1
+5V_BUS
D25
Rb7, Rb8, Rb5, Cb1, Cb2 Rb4, Rb6, Rb9, Rb10, Cb4
Regulator for VTT Termination *** B19 PW1 1 2 DNI +3.3V_BUS
HEADER 1X4 RA
IRU3047 Db1, Db2
60R 1
MBRS340T3 +12VEXT
JUb2 2
+PW_VTT
3
+12V_BUS J U2 4 +5VEXT
C739 C737
+12V_BUS C1128 C101 Part VTT Rb11 Rb12 Rb13
+5V_BUS C94 22uF 16V C1129 22uF 16V
C742 470uF 6.3V 2.2uF
DNI 6.8uF 25V 6.8uF 25V 0.9V 47.5K 1% DNI 75K 1%
B R938 R939 1.0uF B
0R 0R IRU3037
7
8
1.25V 0R DNI DNI

Alternative 1 Q5A
+VTT
C95 U44 2 0.9V 1.07K 1% 8.45K 1% DNI
100nF 2 5 R93 10R STS8DNF3LL L3 3.3uH IRU3037A
Vcc HDrv
1 2
51
6
BOOT 6 *** ** ** ISL6522CB 1.25V 576R 1% 1.02K 1% DNI

Vc Q5B C97
DNI
R94 C7 C98 C99
SS_VTT 8 SS 3 4 Cb5 C100 825R 22uF 16V 22uF 16V 1.40V 825R 1% 1.0K 1% DNI
C102 2.2nF LDrv STS8DNF3LL 10nF 1% 470uF 470uF 10V **
COMP_VTT
7 Comp DNI *** **
3
C103 Rb11
C762 Rb14 R95
150nF 100nF R96 4 1 1.5K DUAL FOOTPRINT
27K GND Fb +MPVDD
IRU3037ACS DNI
Alternate part R97 1.40K
IRU3037CS Part INSTALL DO NOT INSTALL
Rb13
R98
1.10K IRU3037 Alternative1 Cb5, Rb14,
1% IRU3037A Alternative2
DNI
R99 10K Rb12
DNI ISL6522CB Alternative2 Alternative1
DNI U45
R100 51K 1 14
A +PW_VTTR101 3K RT VCC A
2 OCSET PVCC 13
DNI SS_VTT 3 12
COMP_VTT 4
SS LGATE
11
* C10, C11, C12, and C7 are the alternate surface
C104 33pF COMP PGND BOOT
5 FB BOOT 10 mount components for C80, C81, C82, C97 <Core Design> ATI Technologies Inc.
6 9
DNI DNI 7
EN UGATE
8
respectively. 1 Commerce Valley Drive East
C105 GND PHASE
Markham, Ontario
10nF ISL6522CB Alternative 2 Canada, L3T 7X6
(905) 882-2600
R102 15K
DNI
B 105-942XX-30_11 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+12V_BUS MVDDC Switching Regulator for

D Memory Core for 128M D
configuration
C763
220nF
D24
1
D6 1 2
BAT54SLT1 +12V_BUS
3 C121 100nF S3AB
+12V_BUS
+5V_BUS B21
***
R112 +PW_VDD C8 is an alternate surface
+12VEXT *
2
DNI 0R
mount component for C122.
R936 R937
0R 0R C744 C745 C120 60R
7
8
Q8A 180uF 16V
220nF 220nF
2 +MVDDC
U48 DNI STS8DNF3LL
C743 C119 2 5 R113 10R L5 2.2uH
5 1
220nF 220nF Vcc HDrv
1 2
6
BOOT1 6 Q8B ***
Vc C8
** ***
R114 DNI C122 C736
SS_VDD C764 10nF
Cd1 C125 C746 * 470uF 10V 470uF
8 SS LDrv 3 4
STS8DNF3LL 10nF 1% 10uF 470uF
C734 C126 COMP_VDD 7 R954 1.33K ** DNI *** ***
3
DNI Comp
C 1 uF 2.2nF 10K R115 C
C127 DNI R116
Rd4 1.5K
Rd1
4 GND Fb 1
27K DUAL FOOTPRINT
22nf DNI IRU3037ACS
Alternate part IRU3037CS
Alternative 1 R117
499R
1% Layout Guide Lines for VDD switching regulator

R118 10K
Rd2
The same rules apply as for VDDC regulator.
DNI C747 1nf
R120 51K U49
1 RT VCC 14
+PW_VDD R121 3K 2 13
SS_VDD OCSET PVCC
3 SS LGATE 12
COMP_VDD 4 11
C128 33pF COMP PGND BOOT1
5 FB BOOT 10
6 EN UGATE 9
7 GND PHASE 8
C129 Part MVDDC Rd1 Rd2
10nF ISL6522CB
R122 15K
IRU3037 2.5V 1.21K 1.21K
Alternative 2 1% 1%
IRU3037A 2.55K 1.21K

B 2.5V B
1% 1%
ISL6522CB
IRU3037A 1.33K 499R

2.9V 1% 1%
ISL6522CB
Part INSTALL DO NOT INSTALL
IRU3037 Alternative1 Cd1, Rd4, Alternative2

IRU3037A
ISL6522CB Alternative2 Alternative1
A A
<Core Design>
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600

B 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
+5V_BUS
*** B22
Regulator for MVDDQ (Memory I/O) +1.8V Regulator for VDDC_CT (Core Transform)
60R
+PW_VDDQ
D +12V_BUS +3.3V_BUS D
+5V_BUS C130
C748 470uF 6.3V C13 is an alternate surface
+12V_BUS DNI * mount component for C136.
R934 R935 1.0uF B23
7
8
0R 0R 60R REG2 +VDDC_CT
LT1117CST
Alternative 1 Q9A 3 2
C133 +MVDDQ IN OUT
2
ADJ
U50 STS8DNF3LL C134 C135 4 C131 C132
100nF R123 10R L6 3.3uH 22uF 16V 100nF CASE 100nF 100uF 16V
2 5
5 1
Vcc HDrv R130
1 2
1
6
BOOT2 6 *** 1.33K
Vc Q9B *
C13 C136 ** C137 ** C138 1%
R124 DNI
SS_VDDQ 8 3 4 Ce1 C140 4.99K
SS LDrv STS8DNF3LL 10nF 470uF 470uF 10V 22uF 16V** 22uF 16V
1%
C765 C141 COMP_VDDQ7 *** ** R126
3
Comp 562R
Re4
100nF 2.2nF Re8 R127 1%
C142 R128 4 1 1.5K
27K GND Fb DUAL FOOTPRINT
150nF IRU3037ACS
Alternate part IRU3037CS
Re5
R131
2K
1%
C DNI R132 10K

Alternative 2 C
U51 DNI
DNI R133 51K 1 14
+PW_VDDQ R134 3K RT VCC
2 OCSET PVCC 13
DNI SS_VDDQ 3 12
COMP_VDDQ SS LGATE
4 COMP PGND 11 REGULATOR
C143 33pF 5 10 BOOT2 Part MVDDQ Re4 Re5 +3.3V_BUS
DNI FB BOOT FOR
6 EN UGATE 9
DNI 7 8 USE ONLY IF VDD IS +3.3V A2VDD(+2.5V)
C144 GND PHASE
10nF ISL6522CB B24
IRU3037 2.5V 1.21K 1.21K 200R
R135 15K +A2VDD
1% 1%
REG3
1 VIN VOUT 5
IRU3037A 2.55K 1.21K
2.5V 1% 1% 1 uF
GND
ISL6522CB 3 SHDN BYPASS 4 1 uF
C145 C146
2.5V
2
IRU3037A 4.99K 2.0K C147
2.8V 1% 1% 470pF
ISL6522CB DNI
Part INSTALL DO NOT INSTALL

6 8 1R 1.5K GND_A2VSSN GND_A2VSSN
IRU3037 1.8V 1% 1%
IRU3037 Alternative1 Ce1, Re8, Alternative2
IRU3037A
B B
IRU3037A 1.87K 1.5K
ISL6522CB Alternative2 Alternative1 1.8V 1% 1%
ISL6522CB
REGULATOR
FOR PVDD
+3.3V_BUS
(+1.8V)
B25 200R
R139
18R +PVDD
REGULATOR REGULATOR
3
FOR FOR TPVDD R140
+5V_BUS +3.3V_BUS AS432S 681R REG4
MVDD(+1.8V) (+1.8V) 1 1% 4
B26 200R B27 200R NC
SC431LC5SK-1
1
MREG4 R141 2 NC
1.50K
5
R142 R143 1%
47R
+MPVDD 18R +TPVDD
GND_PVSS
2
R144 R145
AS432S 681R REG5 AS432S 681R REG6
A 1 1% 4 1 1% 4 A
NC
SC431LC5SK-1 NC
SC431LC5SK-1
1 1
MREG5 R146 2 NC MREG6 R147 2 NC
1.50K 1.50K <Core Design>

3
1% 1%
Markham, Ontario
GND_MPVSS GND_TPVSS Canada, L3T 7X6
(905) 882-2600

B 11
8 7 6 5 4 3 2 1
5 4 3 2 1
R-300
MEMORY CHANNELS A and B
MAA8X R883 0R MAA8 MAB8X R885 0R MAB8
MAA9X R884 0R MAB9X R886 0R
R880 0R R882 0R
R879 0R MAA9 R881 0R MAB9
D D
MAB[14..0]
MAA[14..0] (11,13) MAB[14..0]
(11,13) MAA[14..0]
MDA[63..0] (11) MDB[63..0]
(11) MDA[63..0]
U42D
U42C MDB0 E25 C18 MAB0
MDA0 MAA0 MDB1 DQB0 Part 4 of 8 MAB0 MAB1
R35 DQA0 MAA0 H36 D25 DQB1 MAB1 C19
MDA1 R36 Part 3 of 8 J37 MAA1 MDB2 C25 E19 MAB2
MDA2 DQA1 MAA1 MAA2 MDB3 DQB2 MAB2 MAB3
R37 DQA2 MAA2 J35 D24 DQB3 MAB3 D20
MDA3 P36 K36 MAA3 MDB4 D23 C20 MAB4
N36 DQA4 MAA4 K37 E22 DQB5 MAB5 D19
MDA5 M35 J36 MAA5 MDB6 D22 D18 MAB6
M36 DQA6 MAA6 H35 C22 DQB7 MAB7 B18
MDA7 M37 H37 MAA7 MDB8 B26 D17 MAB8X MAB8
MDA8 DQA7 MAA7 MAA8X MAA8 MDB9 DQB8 MAB8 MAB9X MAB9
P38 DQA8 MAA8 G36 A26 DQB9 MAB9 C21
MDA9 P39 L37 MAA9X MAA9 MDB10 B25 D21 MAB10
N38 DQA10 MAA10 L36 A25 DQB11 MAB11 E21
MDA11 N39 L35 MAA11 MDB12 B23 A18 MAB12
L38 DQA12 MAA12 G35 A23 DQB13 MAB13 C17
MDA13 L39 G37 MAA13 MDB14 B22 E17 MAB14
MDA14 DQA13 MAA13 MAA14 MDB15 DQB14 MAB14
K38 DQA14 MAA14 G34 A22 DQB15 DQMB#[7..0] (11)
MDA15 K39 MDB16 E29
DQA15 DQMA#[7..0] (11) DQB16
MDA16 W35 MDB17 D29 C24 DQMB#0
MDA17 DQA16 DQMA#0 MDB18 DQB17 DQMB#0 DQMB#1
W36 DQA17 DQMA#0 P37 C29 DQB18 DQMB#1 B24
MDA18 W37 M38 DQMA#1 MDB19 D28 C28 DQMB#2
C MDA19 DQA18 DQMA#1 DQMA#2 MDB20 DQB19 DQMB#2 DQMB#3 C
V36 DQA19 DQMA#2 V37 D27 DQB20 DQMB#3 B29
MDA20 U36 U38 DQMA#3 MDB21 E26 B13 DQMB#4
MDA21 DQA20 DQMA#3 DQMA#4 MDB22 DQB21 DQMB#4 DQMB#5
T35 DQA21 DQMA#4 C38 D26 DQB22 DQMB#5 C14
MDA22 T36 C36 DQMA#5 MDB23 C26 B8 DQMB#6
MDA23 DQA22 DQMA#5 DQMA#6 MDB24 DQB23 DQMB#6 DQMB#7
T37 DQA23 DQMA#6 B34 B31 DQB24 DQMB#7 C10 QSB[7..0] (11)
MDA24 W38 C32 DQMA#7 MDB25 A31
MDA25 DQA24 DQMA#7 QSA[7..0] (11) MDB26 DQB25 QSB0
MEMORY INTERFACE B
W39 DQA25 B30 DQB26 QSB0 E23
MDA26 V38 N35 QSA0 MDB27 A30 A24 QSB1
MDA27 DQA26 QSA0 QSA1 MDB28 DQB27 QSB1 QSB2
V39 DQA27 QSA1 M39 B28 DQB28 QSB2 E27
MDA28 T38 U35 QSA2 MDB29 A28 A29 QSB3
MEMORY INTERFACE A

T39 DQA29 QSA3 U39 B27 DQB30 QSB4 A13
MDA30 R38 B39 QSA4 MDB31 A27 E13 QSB5
R39 DQA31 QSA5 E35 B15 DQB32 QSB6 A8
MDA32 E38 A34 QSA6 MDB33 A15 E9 QSB7
MDA33 DQA32 QSA6 QSA7 MDB34 DQB33 QSB7
D39 DQA33 QSA7 E31 B14 DQB34
MDA34 D38 MDB35 A14 D16 RASB#
DQA34 DQB35 RASB# RASB# (11,13)
MDA35 C39 F39 RASA# MDB36 B12
DQA35 RASA# RASA# (11,13) DQB36
MDA36 B38 MDB37 A12 A16 CASB#
DQA36 DQB37 CASB# CASB# (11,13)
MDA37 A38 E39 CASA# MDB38 B11
DQA37 CASA# CASA# (11,13) DQB38
MDA38 B37 MDB39 A11 B16 WEB#
DQA38 DQB39 WEB# WEB# (11,13)
MDA39 A37 F36 WEA# MDB40 E15
DQA39 WEA# WEA# (11,13) DQB40
MDA40 E37 MDB41 D15 B17 CSB#
DQA40 DQB41 CSB# CSB# (11,13)
MDA41 D37 F37 CSA# MDB42 C15
DQA41 CSA# CSA# (11,13) DQB42
MDA42 E36 MDB43 D14 A17 CKEB
MDA43 DQA42 CKEA MDB44 DQB43 CKEB
D36 DQA43 CKEA F38 D13 DQB44
MDA44 D35 MDB45 E12 A20
DQA44 DQB45 CLKB0 M_CLKB0 (11,13)
MDA45 E34 MDB46 D12 B21
DQA45 DQB46 CLKB0# M_CLKB#0 (11,13)
MDA46 D34 MDB47 C12
MDA47 DQA46 MDB48 DQB47
C34 DQA47 CLKA0 H39 M_CLKA0 (11,13) B10 DQB48 CLKB1 B19 M_CLKB1 (11,13)
MDA48 B36 J38 MDB49 A10 A19
B DQA48 CLKA0# M_CLKA#0 (11,13) DQB49 CLKB1# M_CLKB#1 (11,13) B
MDA49 A36 MDB50 B9
B35 DQA50 CLKA1 G38 M_CLKA1 (11,13) A9 DQB51
MDA51 A35 G39 MDB52 B7
DQA51 CLKA1# M_CLKA#1 (11,13) DQB52
MDA52 B33 +MVDDQ MDB53 A7
A33 DQA53 B6 DQB54
MDA54 B32 MDB55 A6
MDA55 DQA54 R137 MDB56 DQB55
A32 DQA55 E11 DQB56
MDA56 E33 75.0R MDB57 D11
D33 DQA57 C11 DQB58
MDA58 C33 G24 MDB59 D10 A21 R710 0R
DQA58 VREF2 DQB59 DIMB0 DIMB0 (13)
MDA59 D32 MDB60 D9 E16 R711 0R
DQA59 DQB60 DIMB1 DIMB1 (13)
MDA60 D31 J39 R708 0R MDB61 E8
DQA60 DIMA0 DIMA0 (13) C148 DQB61 Only for BGA Elpida memory
MDA61 E30 F34 R709 0R MDB62 D8
DQA61 DIMA1 DIMA1 (13) DQB62
MDA62 D30 C149 R138 MDB63 C8
MDA63 DQA62 Only for BGA Elpida memory 10uF 16V 100nF 75.0R DQB63
C30 DQA63 R300
R300
B - size
+MVDDQ +MVDDQ
C727 C728
100nF 100nF
5
TC7SZ08FU TC7SZ08FU
CKEA 1 CKEB 1
A 4 M_CKEA 4 M_CKEB <Core Design> A
M_CKEA (11,13) M_CKEB (11,13)
AGP_RESET# 2 AGP_RESET# 2
(2,3,10,23,24) AGP_RESET#
U89 U90 ATI Technologies Inc.
3

Markham, Ontario
Canada, L3T 7X6
DNI DNI (905) 882-2600
R855 0R R856 0R
Title
AGP R300 128MB BGA DVII VGA VO
B 105-942XX-30_11 11
5 4 3 2 1
5 4 3 2 1
R-300
MEMORY CHANNELS C and D
MAD8X R906 0R MAD8
MAD9X R908 0R
MAC8X R905 0R MAC8 R890 0R
MAC9X R907 0R R888 0R MAD9
R889 0R
R887 0R MAC9
D D
MAD[14..0]
(12,14) MAD[14..0]
MAC[14..0]
(12,14) MAC[14..0] (12) MDD[63..0]
U42F
(12) MDC[63..0]
MDD0 AJ4 AT3 MAD0
U42E MDD1 DQD0 Part 6 of 8 MAD0 MAD1
AJ3 DQD1 MAD1 AT6
MDC0 G4 N2 MAC0 MDD2 AK5 AR4 MAD2
MDC1 DQC0 Part 5 of 8 MAC0 MAC1 MDD3 DQD2 MAD2 MAD3
G3 DQC1 MAC1 N5 AK4 DQD3 MAD3 AP3
MDC2 H5 M2 MAC2 MDD4 AL3 AR6 MAD4
MDC3 DQC2 MAC2 MAC3 MDD5 DQD4 MAD4 MAD5
H4 DQC3 MAC3 M4 AM5 DQD5 MAD5 AR3
MDC4 J4 M3 MAC4 MDD6 AM4 AT5 MAD6
J3 DQC5 MAC5 M1 AN5 DQD7 MAD7 AU5
MDC6 K4 N4 MAC6 MDD8 AJ2 AU2 MAD8X MAD8
MDC7 DQC6 MAC6 MAC7 MDD9 DQD8 MAD8 MAD9X MAD9
K3 DQC7 MAC7 N1 AJ1 DQD9 MAD9 AP4
MDC8 D2 P4 MAC8X MAC8 MDD10 AK2 AN3 MAD10
MDC9 DQC8 MAC8 MAC9X MAC9 MDD11 DQD10 MAD10 MAD11
D1 DQC9 MAC9 L3 AK1 DQD11 MAD11 AN4
MDC10 E2 L4 MAC10 MDD12 AM2 AU4 MAD12
E1 DQC11 MAC11 L5 AM1 DQD13 MAD13 AU1
MDC12 G2 P5 MAC12 MDD14 AN2 AV4 MAD14
MDC13 DQC12 MAC12 MAC13 MDD15 DQD14 MAD14
G1 DQC13 MAC13 P3 AN1 DQD15 DQMD#[7..0] (12)
MDC14 H2 P6 MAC14 MDD16 AE4
MDC15 DQC14 MAC14 MDD17 DQD16 DQMD#0
H1 DQC15 DQMC#[7..0] (12) AE3 DQD17 DQMD#0 AK3
MDC16 C5 MDD18 AF5 AL2 DQMD#1
MDC17 DQC16 DQMC#0 MDD19 DQD18 DQMD#1 DQMD#2
C4 DQC17 DQMC#0 H3 AF4 DQD19 DQMD#2 AF3
MDC18 D5 F2 DQMC#1 MDD20 AG3 AF2 DQMD#3
C MDC19 DQC18 DQMC#1 DQMC#2 MDD21 DQD20 DQMD#3 DQMD#4 C
D3 DQC19 DQMC#2 E4 AH5 DQD21 DQMD#4 AV7
MDC20 E6 B3 DQMC#3 MDD22 AH4 AU8 DQMD#5
MDC21 DQC20 DQMC#3 DQMC#4 MDD23 DQD22 DQMD#5 DQMD#6
F5 DQC21 DQMC#4 T2 AJ5 DQD23 DQMD#6 AV12
MDC22 F4 V3 DQMC#5 MDD24 AD2 AU12 DQMD#7
MDC23 DQC22 DQMC#5 DQMC#6 MDD25 DQD24 DQMD#7 QSD[7..0] (12)
G5 DQC23 DQMC#6 AA2 AD1 DQD25
MDC24 B5 AB3 DQMC#7 MDD26 AE2 AL4 QSD0
MEMORY INTERFACE
MDC25 DQC24 DQMC#7 QSC[7..0] (12) MDD27 DQD26 QSD0 QSD1
A5 DQC25 AE1 DQD27 QSD1 AL1
MDC26 B4 J5 QSC0 MDD28 AG2 AG4 QSD2
MEMORY INTERFACE
MDC27 DQC26 QSC0 QSC1 MDD29 DQD28 QSD2 QSD3

A4 DQC27 QSC1 F1 AG1 DQD29 QSD3 AF1
MDC28 A2 E3 QSC2 MDD30 AH2 AW7 QSD4
B1 DQC29 QSC3 A3 AH1 DQD31 QSD5 AR9
MDC30 C2 T1 QSC4 MDD32 AV5 AW12 QSD6
C1 DQC31 QSC5 W4 AW5 DQD33 QSD7 AR13
MDC32 P2 AA1 QSC6 MDD34 AV6
MDC33 DQC32 QSC6 QSC7 MDD35 DQD34 RASD#
P1 DQC33 QSC7 AC4 AW6 DQD35 RASD# AW4 RASD# (12,14)
MDC34 R2 MDD36 AV8
MDC35 DQC34 RASC# MDD37 DQD36 CASD#
R1 DQC35 RASC# R4 RASC# (12,14) AW8 DQD37 CASD# AW2 CASD# (12,14)
MDC36 U2 MDD38 AV9
MDC37 DQC36 CASC# MDD39 DQD38 W ED#
U1 DQC37 CASC# T4 CASC# (12,14) AW9 DQD39 WED# AW3 W ED# (12,14)
MDC38 V2 MDD40 AT7
MDC39 DQC38 W EC# MDD41 DQD40 CSD#
V1 DQC39 WEC# T5 W EC# (12,14) AU7 DQD41 CSD# AV3 CSD# (12,14)
D
MDC40 U4 MDD42 AR8
MDC41 DQC40 CSC# MDD43 DQD42 CKED
U3 DQC41 CSC# R3 CSC# (12,14) AT8 DQD43 CKED AV1
C
MDC42 V5 MDD44 AT9

MDC43 DQC42 CKEC MDD45 DQD44
V4 DQC43 CKEC R5 AR10 DQD45 CLKD0 AR1 M_CLKD0 (12,14)
MDC44 W3 MDD46 AT10 AP2
DQC44 DQD46 CLKD0# M_CLKD#0 (12,14)
MDC45 Y5 K1 MDD47 AU10
DQC45 CLKC0 M_CLKC0 (12,14) DQD47
MDC46 Y4 J2 MDD48 AV10 AT2 +MVDDQ
DQC46 CLKC0# M_CLKC#0 (12,14) DQD48 CLKD1 M_CLKD1 (12,14)
MDC47 AA5 MDD49 AW10 AT1
DQC47 DQD49 CLKD1# M_CLKD#1 (12,14)
MDC48 W2 L2 MDD50 AV11
B DQC48 CLKC1 M_CLKC1 (12,14) DQD50
MDC49 W1 L1 MDD51 AW11 R773 B
DQC49 CLKC1# M_CLKC#1 (12,14) DQD51
MDC50 Y2 MDD52 AV13 75.0R
MDC51 DQC50 MDD53 DQD52
Y1 DQC51 AW13 DQD53 VREF1 AC6
MDC52 AB2 MDD54 AV14
MDC53 DQC52 MDD55 DQD54
AB1 DQC53 AW14 DQD55
MDC54 MDD56 C150 C151
AC2 DQC54 AR11 DQD56 DIMD0 AP1
MDC55 AC1 MDD57 AT11 AR7 100nF R774
MDC56 DQC55 MDD58 DQD57 DIMD1 10uF 16V 75.0R
AA4 DQC56 AU11 DQD58
MDC57 AA3 MDD59 AT12 E7 MEMMODE0
MDC58 DQC57 MDD60 DQD59 MEMVMODE0 MEMMODE1
AB5 DQC58 AT13 DQD60 MEMVMODE1 F7
MDC59 AB4 J1 R712 0R MDD61 AR14
DQC59 DIMC0 DIMC0 (14) DQD61
MDC60 AC3 U5 R713 0R MDD62 AT14 F24
DQC60 DIMC1 DIMC1 (14) DQD62 MEMTEST
MDC61 AD5 MDD63 AU14
MDC62 DQC61 Only for Elpida DQD63
AD4 DQC62
MDC63 AE5 memory R300 R166
DQC63 47R
R300 Only for Elpida
memory
R714 0R
D IMD0 (14)
+MVDDQ +MVDDQ +VDDC_CT R715 0R
D IMD1 (14)
MEMMODE0 R164 4.7K
MEMVMODE[1:0] MEMORY IO VOLTAGE MEMMODE1 R165 4.7K
C729 C730
100nF 100nF 01 2.5V (DDR)
R167 R168
4.7K 4.7K
5
TC7SZ08FU TC7SZ08FU 10 1.8V (DDR)

CKEC 1 CKED 1
4 M_CKEC 4 M_CKED
A M_CKEC (12,14) M_CKED (12,14) 11 3.3V (SDR) A
AGP_RESET# 2 AGP_RESET# 2
(2,3,9,23,24) AGP_RESET# <Core Design>
U91 U92

3

DNI DNI Markham, Ontario
R857 0R R858 0R Canada, L3T 7X6
(905) 882-2600
Title
B 105-942XX-30_11 11
5 4 3 2 1
8 7 6 5 4 3 2 1
MDA[63..0] MDB[63..0]
MAA[14..0]
MDA0 M_MDA[63..0] MDB0 M_MDB[63..0]

MDA1 MDB1
MDA2 MDB2
MDA3 MDA0 M_MDA0 MDB3 MDB0 M_MDB0
D MDA11 MDA8 M_MDA8 MDB11 MDB8 M_MDB8 D
C MDA41 MDA38 M_MDA38 MDB41 MDB38 M_MDB38 C
MDA52 MDA49 M_MDA49 MDB52 MDB49 M_MDB49 DQMA#0 M_DQMA#0
MAA0 MDA61 M_MDA61 MDB61 M_MDB61 DQMB#0 M_DQMB#0
MAA3 DQMB#3 M_DQMB#3
MAA4 MAA0 M_MAA0 DQMB#4 M_DQMB#4
MAA5 MAA1 M_MAA1 DQMB#5 M_DQMB#5
MAA6 MAA2 M_MAA2 WEB# DQMB#6 M_DQMB#6
B MAA7 MAA3 M_MAA3 RASB# DQMB#7 M_DQMB#7 B
MAA8 MAA4 M_MAA4 CASB#
MAA9 MAA5 M_MAA5
MAA10 MAA6 M_MAA6 CSB#
MAA11 MAA7 M_MAA7
MAA12 MAA8 M_MAA8
MAA13 MAA9 M_MAA9
MAA10 M_MAA10
MAA11 M_MAA11
DQMA#0 MAA12 M_MAA12
DQMA#1 MAA13 M_MAA13 DQMB#0
DQMA#2 DQMB#1
DQMA#3 WEA# DQMB#2
DQMA#4 RASA# DQMB#3
DQMA#5 CASA# DQMB#4
DQMA#6 DQMB#5
DQMA#7 CSA# DQMB#6
DQMB#7
WEB# QSB0
WEA# CASB# QSB1
CASA# RASB# QSB2
RASA# CSB# QSB3
CSA# QSB4
M_CLKB0 QSB5
QSA0 M_CLKB#0 QSB6
QSA1 M_CLKB1 QSB7
A QSA2 M_CLKB#1 A
QSA3
QSA4 QSB0 M_QSB0
QSA0 M_QSA0 QSA5 QSB1 M_QSB1
QSA3 M_QSA3 QSB4 M_QSB4
QSA7 M_QSA7
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MDC[63..0] MDD[63..0]
MDC[63..0] (10) MDD[63..0] (10)
+VTT
+VTT MAC[14..0] MAD[14..0]
MAC[14..0] (10,14) MAD[14..0] (10,14)
+MVDDQ RP91A 1 8 56R MDC0 M_MDC[63..0] RP136A 1 8 56R MDD0 M_MDD[63..0]
M_MDC[63..0] (14) M_MDD[63..0] (14)
RP91B 2 7 56R MDC1 RP136B 2 7 56R MDD1
RP91C 3 6 56R MDC2 +MVDDQ RP136C 3 6 56R MDD2
C180 RP91D 4 5 56R MDC3 MDC0 RP111A 8 1 47R M_MDC0 RP136D 4 5 56R MDD3 MDD0 RP160A 8 1 47R M_MDD0
100nF RP92A 1 8 56R MDC4 MDC1 RP111B 7 2 47R M_MDC1 RP137A 1 8 56R MDD4 MDD1 RP160B 7 2 47R M_MDD1
RP92B 2 7 56R MDC5 MDC2 RP111C 6 3 47R M_MDC2 C181 RP137B 2 7 56R MDD5 MDD2 RP160C 6 3 47R M_MDD2 Differential CLOCK termination
RP92C 3 6 56R MDC6 MDC3 RP111D 5 4 47R M_MDC3 100nF RP137C 3 6 56R MDD6 MDD3 RP160D 5 4 47R M_MDD3
RP92D 4 5 56R MDC7 MDC4 RP112A 8 1 47R M_MDC4 RP137D 4 5 56R MDD7 MDD4 RP161A 8 1 47R M_MDD4 Either Rp or Rg1,Rg2, Rg3, Rg4, Cg1, Cg2 should be
RP93A 1 8 56R MDC8 MDC5 RP112B 7 2 47R M_MDC5 RP138A 1 8 56R MDD8 MDD5 RP161B 7 2 47R M_MDD5 mounted. Differential termination should be placed close
RP93B
RP93C
2 7 56R
56R
MDC9
MDC10
MDC6
MDC7
RP112C
RP112D
6 3 47R
47R
M_MDC6
M_MDC7
Vtt RP138B
RP138C
2 7 56R
56R
MDD9
MDD10
MDD6
MDD7
RP161C
RP161D
6 3 47R
47R
M_MDD6
M_MDD7
to the memory.
3 6 5 4 3 6 5 4
D
C182
RP93D
RP94A
4
1
5
8
56R
56R
MDC11
MDC12
MDC8
MDC9
RP113A
RP113B
8
7
1
2
47R
47R
M_MDC8
M_MDC9 TERMINATION C183
RP138D
RP139A
4
1
5
8
56R
56R
MDD11
MDD12
MDD8
MDD9
RP162A
RP162B
8
7
1
2
47R
47R
M_MDD8
M_MDD9
M_CLKC1
R834
M_CLKC0
R835
D
100nF RP94B 2 7 56R MDC13 MDC10 RP113C 6 3 47R M_MDC10 100nF RP139B 2 7 56R MDD13 MDD10 RP162C 6 3 47R M_MDD10 Rg1 Rg3
RP94C
RP94D
3 6 56R
56R
MDC14
MDC15
MDC11
MDC12
RP113D
RP114A
5 4 47R
47R
M_MDC11
M_MDC12
for DDR RP139C
RP139D
3 6 56R
56R
MDD14
MDD15
MDD11
MDD12
RP162D
RP163A
5 4 47R
47R
M_MDD11
M_MDD12
56R Cg1 56R Cg2
4 5 8 1 4 5 8 1
RP95A 1 8 56R MDC16 MDC13 RP114B 7 2 47R M_MDC13 RP140A 1 8 56R MDD16 MDD13 RP163B 7 2 47R M_MDD13 C715 10nF C716 10nF
+MVDDQ RP95B 2 7 56R MDC17 MDC14 RP114C 6 3 47R M_MDC14 +MVDDQ RP140B 2 7 56R MDD17 MDD14 RP163C 6 3 47R M_MDD14
RP95C 3 6 56R MDC18 MDC15 RP114D 5 4 47R M_MDC15 RP140C 3 6 56R MDD18 MDD15 RP163D 5 4 47R M_MDD15 Rg2 R224 Rg4 R223
RP95D 4 5 56R MDC19 MDC16 RP115A 8 1 47R M_MDC16 RP140D 4 5 56R MDD19 MDD16 RP164A 8 1 47R M_MDD16
C184 RP96A 8 1 56R MDC20 MDC17 RP115B 7 2 47R M_MDC17 C185 RP141A 8 1 56R MDD20 MDD17 RP164B 7 2 47R M_MDD17 56R 56R
100nF RP96B 7 2 56R MDC21 MDC18 RP115C 6 3 47R M_MDC18 100nF RP141B 7 2 56R MDD21 MDD18 RP164C 6 3 47R M_MDD18 M_CLKC#1 M_CLKC#0
RP96C 6 3 56R MDC22 MDC19 RP115D 5 4 47R M_MDC19 RP141C 6 3 56R MDD22 MDD19 RP164D 5 4 47R M_MDD19
RP97A 1 8 56R MDC24 MDC21 RP116B 7 2 47R M_MDC21 RP142A 1 8 56R MDD24 MDD21 RP165B 7 2 47R M_MDD21
RP97B 2 7 56R MDC25 MDC22 RP116C 6 3 47R M_MDC22 RP142B 2 7 56R MDD25 MDD22 RP165C 6 3 47R M_MDD22
C186 RP97D 4 5 56R MDC27 MDC24 RP117A 8 1 47R M_MDC24 C187 RP142D 4 5 56R MDD27 MDD24 RP166A 8 1 47R M_MDD24
100nF RP98A 1 8 56R MDC28 MDC25 RP117B 7 2 47R M_MDC25 100nF RP143A 1 8 56R MDD28 MDD25 RP166B 7 2 47R M_MDD25
RP98B 2 7 56R MDC29 MDC26 RP117C 6 3 47R M_MDC26 RP143B 2 7 56R MDD29 MDD26 RP166C 6 3 47R M_MDD26 Differential CLOCK termination
RP98D 4 5 56R MDC31 MDC28 RP118A 8 1 47R M_MDC28 RP143D 4 5 56R MDD31 MDD28 RP167A 8 1 47R M_MDD28 Either Rpp or Rg5,Rg6, Rg7, Rg8, Cg3, Cg4 should be
RP99A 8 1 56R MDC32 MDC29 RP118B 7 2 47R M_MDC29 +MVDDQ RP144A 8 1 56R MDD32 MDD29 RP167B 7 2 47R M_MDD29 mounted. Differential termination should be placed close
+MVDDQ RP99B 7 2 56R MDC33 MDC30 RP118C 6 3 47R M_MDC30 RP144B 7 2 56R MDD33 MDD30 RP167C 6 3 47R M_MDD30 to the memory.
RP99D 5 4 56R MDC35 MDC32 RP119A 1 8 47R M_MDC32 C188 RP144D 5 4 56R MDD35 MDD32 RP168A 1 8 47R M_MDD32 M_CLKD1 M_CLKD0
C189 RP100A 1 8 56R MDC36 MDC33 RP119B 2 7 47R M_MDC33 100nF RP145A 8 1 56R MDD36 MDD33 RP168B 2 7 47R M_MDD33 R836 R837
100nF RP100B 2 7 56R MDC37 MDC34 RP119C 3 6 47R M_MDC34 RP145B 7 2 56R MDD37 MDD34 RP168C 3 6 47R M_MDD34 Rg5 Rg7
RP100C 3 6 56R MDC38 MDC35 RP119D 4 5 47R M_MDC35 RP145C 6 3 56R MDD38 MDD35 RP168D 4 5 47R M_MDD35 56R Cg3 56R Cg4
RP101A 8 1 56R MDC40 MDC37 RP120B 2 7 47R M_MDC37 RP146A 1 8 56R MDD40 MDD37 RP169B 2 7 47R M_MDD37 C717 10nF C718 10nF
C RP101B 7 2 56R MDC41 MDC38 RP120C 3 6 47R M_MDC38 RP146B 2 7 56R MDD41 MDD38 RP169C 3 6 47R M_MDD38 C
RP101C 6 3 56R MDC42 MDC39 RP120D 4 5 47R M_MDC39 RP146C 3 6 56R MDD42 MDD39 RP169D 4 5 47R M_MDD39 Rg6 R226 Rg8 R225
C190 RP101D 5 4 56R MDC43 MDC40 RP121A 1 8 47R M_MDC40 C191 RP146D 4 5 56R MDD43 MDD40 RP170A 1 8 47R M_MDD40
100nF RP102A 8 1 56R MDC44 MDC41 RP121B 2 7 47R M_MDC41 100nF RP147A 8 1 56R MDD44 MDD41 RP170B 2 7 47R M_MDD41 56R 56R
RP102B 7 2 56R MDC45 MDC42 RP121C 3 6 47R M_MDC42 RP147B 7 2 56R MDD45 MDD42 RP170C 3 6 47R M_MDD42 M_CLKD#1 M_CLKD#0
RP103A 1 8 56R MDC48 MDC45 RP122B 2 7 47R M_MDC45 RP148A 1 8 56R MDD48 MDD45 RP171B 2 7 47R M_MDD45
+MVDDQ RP103B 2 7 56R MDC49 MDC46 RP122C 3 6 47R M_MDC46 +MVDDQ RP148B 2 7 56R MDD49 MDD46 RP171C 3 6 47R M_MDD46
M_DQMC#[7..0] (14)
C192 RP104A 1 8 56R MDC52 MDC49 RP123B 2 7 47R M_MDC49 C193 RP149A 1 8 56R MDD52 MDD49 RP172B 2 7 47R M_MDD49
100nF RP104B 2 7 56R MDC53 MDC50 RP123C 3 6 47R M_MDC50 100nF RP149B 2 7 56R MDD53 MDD50 RP172C 3 6 47R M_MDD50
RP104C 3 6 56R MDC54 MDC51 RP123D 4 5 47R M_MDC51 RP149C 3 6 56R MDD54 MDD51 RP172D 4 5 47R M_MDD51 DQMC#0 R227 47R M_DQMC#0
RP104D 4 5 56R MDC55 MDC52 RP124A 1 8 47R M_MDC52 RP149D 4 5 56R MDD55 MDD52 RP173A 1 8 47R M_MDD52 DQMC#1 R228 47R M_DQMC#1
RP105A 1 8 56R MDC56 MDC53 RP124B 2 7 47R M_MDC53 RP150A 8 1 56R MDD56 MDD53 RP173B 2 7 47R M_MDD53 DQMC#2 R229 47R M_DQMC#2
RP105B 2 7 56R MDC57 MDC54 RP124C 3 6 47R M_MDC54 RP150B 7 2 56R MDD57 MDD54 RP173C 3 6 47R M_MDD54 DQMC#3 R230 47R M_DQMC#3
RP105C 3 6 56R MDC58 MDC55 RP124D 4 5 47R M_MDC55 RP150C 6 3 56R MDD58 MDD55 RP173D 4 5 47R M_MDD55 DQMC#4 R231 47R M_DQMC#4
M_MAC[14..0] (10,14)
RP105D 4 5 56R MDC59 MDC56 RP125A 1 8 47R M_MDC56 RP150D 5 4 56R MDD59 MDD56 RP174A 1 8 47R M_MDD56 DQMC#5 R232 47R M_DQMC#5
C194 RP106A 1 8 56R MDC60 MDC57 RP125B 2 7 47R M_MDC57 C195 RP151A 8 1 56R MDD60 MDD57 RP174B 2 7 47R M_MDD57 DQMC#6 R233 47R M_DQMC#6
100nF RP106B 2 7 56R MDC61 MDC58 RP125C 3 6 47R M_MDC58 100nF RP151B 7 2 56R MDD61 MDD58 RP174C 3 6 47R M_MDD58 DQMC#7 R234 47R M_DQMC#7
M_DQMD#[7..0] (14)
MDC61 RP126B 2 7 47R M_MDC61 MDD61 RP175B 2 7 47R M_MDD61
MDC62 RP126C 3 6 47R M_MDC62 RP153D 4 5 56R MAD0 MDD62 RP175C 3 6 47R M_MDD62 DQMD#0 R235 47R M_DQMD#0
+MVDDQ RP108D 4 5 56R MAC0 MDC63 RP126D 4 5 47R M_MDC63 +MVDDQ RP154A 8 1 56R MAD1 MDD63 RP175D 4 5 47R M_MDD63 DQMD#1 R236 47R M_DQMD#1
RP109A 8 1 56R MAC1 RP153C 3 6 56R MAD2 DQMD#2 R237 47R M_DQMD#2
RP108C 3 6 56R MAC2 MAC0 M_MAC0 RP152C 6 3 56R MAD3 DQMD#3 R238 47R M_DQMD#3
RP107C 6 3 56R MAC3 MAC1 M_MAC1 C196 RP152B 7 2 56R MAD4 W ED# DQMD#4 R239 47R M_DQMD#4
M_WED# (10,14)
C197 RP107B 7 2 56R MAC4 MAC2 M_MAC2 100nF RP153B 2 7 56R MAD5 RASD# DQMD#5 R240 47R M_DQMD#5
B M_RASD# (10,14) B
100nF RP108B 2 7 56R MAC5 MAC3 M_MAC3 RP154B 7 2 56R MAD6 CASD# DQMD#6 R241 47R M_DQMD#6
M_CASD# (10,14)
RP109B 7 2 56R MAC6 MAC4 M_MAC4 RP155B 2 7 56R MAD7 DQMD#7 R242 47R M_DQMD#7
M_MAD[14..0] (10,14)
RP110B 2 7 56R MAC7 MAC5 M_MAC5 RP155A 1 8 56R MAD8 CSD#
M_CSD# (10,14)
RP110A 1 8 56R MAC8 MAC6 M_MAC6 RP153A 1 8 56R MAD9 MAD0 M_MAD0
RP108A 1 8 56R MAC9 MAC7 M_MAC7 C198 RP152D 5 4 56R MAD10 MAD1 M_MAD1
C199 RP107D 5 4 56R MAC10 MAC8 M_MAC8 100nF RP152A 8 1 56R MAD11 MAD2 M_MAD2
100nF RP107A 8 1 56R MAC11 MAC9 M_MAC9 RP154C 6 3 56R MAD12 MAD3 M_MAD3
RP109C 6 3 56R MAC12 MAC10 M_MAC10 RP154D 5 4 56R MAD13 MAD4 M_MAD4
RP109D 5 4 56R MAC13 MAC11 M_MAC11 RP155D 4 5 56R MAD14 MAD5 M_MAD5
RP110D 4 5 56R MAC14 MAC12 M_MAC12 M_CKED MAD6 M_MAD6
M_CKED (10,14)
MAC13 M_MAC13 R243 56R DQMD#0 +VTT MAD7 M_MAD7
R244 56RDQMC#0 MAC14 M_MAC14 R245 56R DQMD#1 R838 56R R839 10K MAD8 M_MAD8
R246 56RDQMC#1 W EC# R247 56R DQMD#2 MAD9 M_MAD9
M_WEC# (10,14)
R248 56RDQMC#2 RASC# R249 56R DQMD#3 MAD10 M_MAD10
M_RASC# (10,14)
R250 56RDQMC#3 CASC# R251 56R DQMD#4 MAD11 M_MAD11
M_CASC# (10,14)
+MVDDQ R252 56R DQMC#4 CSC# +MVDDQ R253 56R DQMD#5 MAD12 M_MAD12
M_CSC# (10,14)
R254 56R DQMC#5 R255 56R DQMD#6 MAD13 M_MAD13
R256 56R DQMC#6 R257 56R DQMD#7 MAD14 M_MAD14
C200 R258 56R DQMC#7 M_CKEC C201
M_CKEC (10,14)
100nF +VTT 100nF
QSD[7..0] (10)
R840 56R R841 10K
DQMD#[7..0] (10)
RP156B 7 2 56R W ED# QSD0
DQMC#[7..0] (10) W ED# (10,14)
RP132B 7 2 56R W EC# RP156C 6 3 56R CASD# QSD1
W EC# (10,14) CASD# (10,14) M_QSD[7..0] (14)
RP132C 6 3 56R CASC# C202 RP155C 3 6 56R RASD# QSD2
CASC# (10,14) M_QSC[7..0] (14) QSC[7..0] (10) RASD# (10,14)
C203 RP110C 3 6 56R RASC# 100nF RP156A 8 1 56R CSD# QSD3
RASC# (10,14) CSD# (10,14)
100nF RP132A 8 1 56R CSC# QSD4
CSC# (10,14)
QSC0 R783 56R M_CLKD0 QSD5
M_CLKD0 (10,14)
R784 56R M_CLKC0 QSC1 R785 56R M_CLKD#0 QSD6
M_CLKC0 (10,14) M_CLKD#0 (10,14)
Rp R786 56R M_CLKC#0 QSC2 Rpp R787 56R M_CLKD1 QSD7
A M_CLKC#0 (10,14) M_CLKD1 (10,14) <Core Design> A
R788 56R M_CLKC1 QSC3 R789 56R M_CLKD#1
M_CLKC1 (10,14) M_CLKD#1 (10,14)
R790 56R M_CLKC#1 QSC4
M_CLKC#1 (10,14)
QSC5 R742 56R QSD0 R261 47R M_QSD0 ATI Technologies Inc.
R734 56R QSC0 R262 47R M_QSC0 QSC6 R743 56R QSD1 R263 47R M_QSD1 1 Commerce Valley Drive East
R735 56R QSC1 R264 47R M_QSC1 QSC7 R744 56R QSD2 R265 47R M_QSD2 Markham, Ontario
R736 56R QSC2 R266 47R M_QSC2 R745 56R QSD3 R267 47R M_QSD3 Canada, L3T 7X6
R737 56R QSC3 R268 47R M_QSC3 +MVDDQ R746 56R QSD4 R269 47R M_QSD4 (905) 882-2600
+MVDDQ R738 56R QSC4 R270 47R M_QSC4 R747 56R QSD5 R271 47R M_QSD5
R739 56R QSC5 R272 47R M_QSC5 R748 56R QSD6 R273 47R M_QSD6 Title
R740 56R QSC6 R274 47R M_QSC6 RP132D 5 4 56R C204 R749 56R QSD7 R275 47R M_QSD7 AGP R300 128MB BGA DVII VGA VO
C205 R741 56R QSC7 R276 47R M_QSC7 100nF Size Document Number Rev
100nF C206 B
105-942XX-30_11 11
C207 RP156D 5 4 56R 22uF Date: Tuesday, October 01, 2002 Sheet 12 of 25
22uF
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(11) M_DQMA#[7..0] 64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels A and B - rank 1
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3 U52 U53 U54 U55
M_DQMA#4 M_MAA12 M3 A7 M_MDA8 M_MAA12 M3 A7 M_MDA47 M_MAB12 M3 A7 M_MDB8 M_MAB12 M3 A7 M_MDB39
M_DQMA#5 M_MAA13 BA0 DQ31 M_MDA9 M_MAA13 BA0 DQ31 M_MDA46 M_MAB13 BA0 DQ31 M_MDB9 M_MAB13 BA0 DQ31 M_MDB38
L4 BA1 DQ30 B8 L4 BA1 DQ30 B8 L4 BA1 DQ30 B8 L4 BA1 DQ30 B8
M_DQMA#6 A8 M_MDA10 A8 M_MDA45 A8 M_MDB10 A8 M_MDB37
M_DQMA#7 M_MAA11 DQ29 M_MDA11 M_MAA11 DQ29 M_MDA44 M_MAB11 DQ29 M_MDB11 M_MAB11 DQ29 M_MDB36
(11) M_DQMB#[7..0] L6 A11 DQ28 A9 L6 A11 DQ28 A9 L6 A11 DQ28 A9 L6 A11 DQ28 A9
M_MAA10 K5 B12 M_MDA12 M_MAA10 K5 B12 M_MDA43 M_MAB10 K5 B12 M_MDB12 M_MAB10 K5 B12 M_MDB35
M_MAA9 A10 DQ27 M_MDA13 M_MAA9 A10 DQ27 M_MDA42 M_MAB9 A10 DQ27 M_MDB13 M_MAB9 A10 DQ27 M_MDB34
L7 A9 DQ26 C11 L7 A9 DQ26 C11 L7 A9 DQ26 C11 L7 A9 DQ26 C11
M_DQMB#0 M_MAA8 M10 C12 M_MDA14 M_MAA8 M10 C12 M_MDA41 M_MAB8 M10 C12 M_MDB14 M_MAB8 M10 C12 M_MDB33
D M_DQMB#1 M_MAA7 A8/AP DQ25 M_MDA15 M_MAA7 A8/AP DQ25 M_MDA40 M_MAB7 A8/AP DQ25 M_MDB15 M_MAB7 A8/AP DQ25 M_MDB32 D
M9 A7 DQ24 D12 M9 A7 DQ24 D12 M9 A7 DQ24 D12 M9 A7 DQ24 D12
M_DQMB#2 M_MAA6 M8 J2 M_MDA16 M_MAA6 M8 J2 M_MDA55 M_MAB6 M8 J2 M_MDB16 M_MAB6 M8 J2 M_MDB55
M_DQMB#3 M_MAA5 A6 DQ23 M_MDA17 M_MAA5 A6 DQ23 M_MDA54 M_MAB5 A6 DQ23 M_MDB17 M_MAB5 A6 DQ23 M_MDB54
L8 A5 DQ22 J1 L8 A5 DQ22 J1 L8 A5 DQ22 J1 L8 A5 DQ22 J1
M_DQMB#4 M_MAA4 M7 H1 M_MDA18 M_MAA4 M7 H1 M_MDA53 M_MAB4 M7 H1 M_MDB18 M_MAB4 M7 H1 M_MDB53
M6 A3 DQ20 H2 M6 A3 DQ20 H2 M6 A3 DQ20 H2 M6 A3 DQ20 H2
M_DQMB#6 M_MAA2 L5 F1 M_MDA20 M_MAA2 L5 F1 M_MDA51 M_MAB2 L5 F1 M_MDB20 M_MAB2 L5 F1 M_MDB51
M5 A1 DQ18 F2 M5 A1 DQ18 F2 M5 A1 DQ18 F2 M5 A1 DQ18 F2
M_MAA0 M4 E1 M_MDA22 M_MAA0 M4 E1 M_MDA49 M_MAB0 M4 E1 M_MDB22 M_MAB0 M4 E1 M_MDB49
(11) M_QSA[7..0] A0 DQ17 A0 DQ17 A0 DQ17 A0 DQ17
E2 M_MDA23 E2 M_MDA48 E2 M_MDB23 E2 M_MDB48
DQ16 M_MDA0 DQ16 M_MDA39 DQ16 M_MDB0 DQ16 M_MDB47
B3 NC DQ15 E11 B3 NC DQ15 E11 B3 NC DQ15 E11 B3 NC DQ15 E11
M_QSA0 B10 E12 M_MDA1 B10 E12 M_MDA38 B10 E12 M_MDB1 B10 E12 M_MDB46
M_QSA1 NC DQ14 M_MDA2 NC DQ14 M_MDA37 NC DQ14 M_MDB2 NC DQ14 M_MDB45
G3 NC DQ13 F11 G3 NC DQ13 F11 G3 NC DQ13 F11 G3 NC DQ13 F11
M_QSA2 G10 F12 M_MDA3 G10 F12 M_MDA36 G10 F12 M_MDB3 G10 F12 M_MDB44
K11 NC DQ11 H11 K11 NC DQ11 H11 K11 NC DQ11 H11 K11 NC DQ11 H11
M_QSA4 K12 H12 M_MDA5 K12 H12 M_MDA34 K12 H12 M_MDB5 K12 H12 M_MDB42
M_QSA5 +MVDDQ NC DQ10 M_MDA6 +MVDDQ NC DQ10 M_MDA33 +MVDDQ NC DQ10 M_MDB6 +MVDDQ NC DQ10 M_MDB41
L2 NC DQ9 J11 L2 NC DQ9 J11 L2 NC DQ9 J11 L2 NC DQ9 J11
M_QSA6 M_MAA14 L3 J12 M_MDA7 M_MAA14 L3 J12 M_MDA32 M_MAB14 L3 J12 M_MDB7 M_MAB14 L3 J12 M_MDB40
M2 NC DQ7 D1 M2 NC DQ7 D1 M2 NC DQ7 D1 M2 NC DQ7 D1
C1 M_MDA25 C1 M_MDA62 C1 M_MDB25 C1 M_MDB62
(11) M_QSB[7..0] DQ6 DQ6 DQ6 DQ6
R277 C2 M_MDA26 R278 C2 M_MDA61 R279 C2 M_MDB26 R280 C2 M_MDB61
4.99K DQ5 M_MDA27 4.99K DQ5 M_MDA60 4.99K DQ5 M_MDB27 4.99K DQ5 M_MDB60
L12 MCL DQ4 B1 L12 MCL DQ4 B1 L12 MCL DQ4 B1 L12 MCL DQ4 B1
M_QSB0 A4 M_MDA28 A4 M_MDA59 A4 M_MDB28 A4 M_MDB59
M_QSB1 DQ3 M_MDA29 DQ3 M_MDA58 DQ3 M_MDB29 DQ3 M_MDB58
M12 VREF DQ2 A5 M12 VREF DQ2 A5 M12 VREF DQ2 A5 M12 VREF DQ2 A5
M_QSB2 R281 C208 B5 M_MDA30 R282 C209 B5 M_MDA57 R283 C210 B5 M_MDB30 R284 C211 B5 M_MDB57
M_QSB3 DIMA0 DQ1 M_MDA31 DIMA1 DQ1 M_MDA56 DIMB0 DQ1 M_MDB31 DIMB1 DQ1 M_MDB56
L9 RFU DQ0 A6 L9 RFU DQ0 A6 L9 RFU DQ0 A6 L9 RFU DQ0 A6
M_QSB4 4.99K 4.99K 4.99K 4.99K
M_QSB5 100nF K8 B2 100nF K8 B2 100nF K8 B2 100nF K8 B2
M_QSB6 RFU VDDQ RFU VDDQ +MVDDQ RFU VDDQ RFU VDDQ
VDDQ B4 VDDQ B4 VDDQ B4 VDDQ B4
M_QSB7 M_CLKA#0 L11 B6 +MVDDQ M_CLKA#1 L11 B6 M_CLKB#0 L11 B6 +MVDDQ M_CLKB#1 L11 B6 +MVDDQ
CLK VDDQ CLK VDDQ CLK VDDQ CLK VDDQ
C M_CKEA M_CSA# M1 B9 M_CSA# M1 B9 M_CSB# M1 B9 M_CSB# M1 B9 C
(9,11) M_CKEA CS VDDQ CS VDDQ CS VDDQ CS VDDQ
M_WEA# B11 B11 B11 B11
(9,11) M_WEA# VDDQ VDDQ VDDQ VDDQ
M_CASA# M_RASA# L1 D2 M_RASA# L1 D2 M_RASB# L1 D2 M_RASB# L1 D2
(9,11) M_CASA# RAS VDDQ RAS VDDQ RAS VDDQ RAS VDDQ
M_RASA# D11 D11 D11 D11
(9,11) M_RASA# VDDQ VDDQ VDDQ VDDQ
M_CSA# M_CASA# K1 E3 M_CASA# K1 E3 M_CASB# K1 E3 M_CASB# K1 E3
(9,11) M_CSA# CAS VDDQ CAS VDDQ CAS VDDQ CAS VDDQ
M_CLKA0 E10 E10 E10 E10
(9,11) M_CLKA0 VDDQ VDDQ VDDQ VDDQ
M_CLKA1 M_WEA# K2 F3 M_WEA# K2 F3 M_WEB# K2 F3 M_WEB# K2 F3
(9,11) M_CLKA1 WE VDDQ WE VDDQ WE VDDQ WE VDDQ
M_CLKA#0 F10 F10 F10 F10
(9,11) M_CLKA#0 VDDQ VDDQ VDDQ VDDQ
M_CLKA#1 M_DQMA#1 A11 H3 M_DQMA#5 A11 H3 M_DQMB#1 A11 H3 M_DQMB#4 A11 H3
(9,11) M_CLKA#1 DM3 VDDQ DM3 VDDQ DM3 VDDQ DM3 VDDQ
M_CKEB H10 H10 H10 H10
(9,11) M_CKEB VDDQ VDDQ VDDQ VDDQ
M_WEB# M_DQMA#2 G2 J3 M_DQMA#6 G2 J3 M_DQMB#2 G2 J3 M_DQMB#6 G2 J3
(9,11) M_WEB# DM2 VDDQ DM2 VDDQ DM2 VDDQ DM2 VDDQ
M_CASB# J10 J10 J10 J10
(9,11) M_CASB# VDDQ VDDQ +MVDDC VDDQ VDDQ
M_RASB# M_DQMA#0 G11 C6 M_DQMA#4 G11 C6 M_DQMB#0 G11 C6 M_DQMB#5 G11 C6
(9,11) M_RASB# DM1 VDD DM1 VDD DM1 VDD +MVDDC DM1 VDD +MVDDC
M_CSB# C7 C7 C7 C7
(9,11) M_CSB# VDD +MVDDC VDD VDD VDD
M_CLKB0 M_DQMA#3 A2 D3 M_DQMA#7 A2 D3 M_DQMB#3 A2 D3 M_DQMB#7 A2 D3
(9,11) M_CLKB0 DM0 VDD DM0 VDD DM0 VDD DM0 VDD
M_CLKB1 D10 D10 D10 D10
(9,11) M_CLKB1 VDD VDD VDD VDD
M_CLKB#0 M_CLKA0 L10 K3 M_CLKA1 L10 K3 M_CLKB0 L10 K3 M_CLKB1 L10 K3
(9,11) M_CLKB#0 CLK VDD CLK VDD CLK VDD CLK VDD
M_CLKB#1 K6 K6 K6 K6
(9,11) M_CLKB#1 VDD VDD VDD VDD
M_CKEA M11 K7 M_CKEA M11 K7 M_CKEB M11 K7 M_CKEB M11 K7
CKE VDD CKE VDD CKE VDD CKE VDD
VDD K10 VDD K10 VDD K10 VDD K10
Only for DIMA0 A3 A3 A3 A3
BGA (9) DIMA0 VSSQ VSSQ VSSQ VSSQ
DIMA1 A10 A10 A10 A10
Elpida (9) DIMA1 VSSQ VSSQ VSSQ VSSQ
DIMB0 M_QSA1 A12 C3 M_QSA5 A12 C3 M_QSB1 A12 C3 M_QSB4 A12 C3
memory (9) DIMB0 DQS3 VSSQ DQS3 VSSQ DQS3 VSSQ DQS3 VSSQ
DIMB1 C4 C4 C4 C4
(9) DIMB1 VSSQ VSSQ VSSQ VSSQ
M_QSA2 G1 C5 M_QSA6 G1 C5 M_QSB2 G1 C5 M_QSB6 G1 C5
DQS2 VSSQ DQS2 VSSQ DQS2 VSSQ DQS2 VSSQ
VSSQ C8 VSSQ C8 VSSQ C8 VSSQ C8
M_QSA0 G12 C9 +MVDDQ M_QSA4 G12 C9 +MVDDQ M_QSB0 G12 C9 M_QSB5 G12 C9
(9,11) M_MAA[14..0] DQS1 VSSQ DQS1 VSSQ DQS1 VSSQ DQS1 VSSQ
M_MAA0 M_QSA3 A1 D5 M_QSA7 A1 D5 M_QSB3 A1 D5 M_QSB7 A1 D5
M_MAA1 DQS0 VSSQ C679 DQS0 VSSQ C680 DQS0 VSSQ DQS0 VSSQ
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
B M_MAA2 E4 10uF E4 10uF E4 E4 +MVDDQ B
M_MAA3 VSSQ +MVDDC VSSQ +MVDDQ VSSQ +MVDDC +MVDDC VSSQ
VSSQ E9 VSSQ E9 VSSQ E9 VSSQ E9
M_MAA4 F4 F4 F4 F4
M_MAA5 VSSQ VSSQ VSSQ VSSQ C681
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
M_MAA6 G4 C214 G4 C212 G4 C682 C213 G4 10uF
M_MAA7 VSSQ 10uF VSSQ 22uF 16V VSSQ 10uF 10uF VSSQ
E5 TH GND VSSQ G9 E5 TH GND VSSQ G9 E5 TH GND VSSQ G9 E5 TH GND VSSQ G9
M_MAA8 E6 H4 E6 H4 E6 H4 E6 H4
M_MAA9 TH GND VSSQ TH GND VSSQ TH GND VSSQ TH GND VSSQ
E7 TH GND VSSQ H9 E7 TH GND VSSQ H9 E7 TH GND VSSQ H9 E7 TH GND VSSQ H9
M_MAA10 E8 J4 +MVDDC E8 J4 E8 J4 E8 J4
M_MAA11 TH GND VSSQ TH GND VSSQ TH GND VSSQ TH GND VSSQ
F5 TH GND VSSQ J9 F5 TH GND VSSQ J9 F5 TH GND VSSQ J9 F5 TH GND VSSQ J9
M_MAA12 F6 F6 F6 F6
M_MAA13 TH GND C683 TH GND TH GND TH GND
F7 TH GND VSS D4 F7 TH GND VSS D4 F7 TH GND VSS D4 F7 TH GND VSS D4
M_MAA14 F8 D6 10uF F8 D6 F8 D6 F8 D6
(9,11) M_MAB[14..0] TH GND VSS TH GND VSS +MVDDQ TH GND VSS TH GND VSS
G5 TH GND VSS D7 G5 TH GND VSS D7 G5 TH GND VSS D7 G5 TH GND VSS D7
M_MAB0 G6 D9 G6 D9 G6 D9 G6 D9
M_MAB1 TH GND VSS TH GND VSS TH GND VSS TH GND VSS
G7 TH GND VSS J5 G7 TH GND VSS J5 G7 TH GND VSS J5 G7 TH GND VSS J5
M_MAB2 G8 J6 G8 J6 G8 J6 G8 J6
M_MAB3 TH GND VSS TH GND VSS C215 TH GND VSS TH GND VSS
H5 TH GND VSS J7 H5 TH GND VSS J7 H5 TH GND VSS J7 H5 TH GND VSS J7
M_MAB4 H6 J8 H6 J8 10uF H6 J8 H6 J8
H7 TH GND VSS K4 H7 TH GND VSS K4 H7 TH GND VSS K4 H7 TH GND VSS K4
M_MAB6 H8 K9 H8 K9 H8 K9 H8 K9
M_MAB8 1Mx32x4 1Mx32x4 1Mx32x4 1Mx32x4
M_MAB9
M_MAB10
M_MAB11 M_MDA[63..0]
(11) M_MDA[63..0]
M_MAB12
M_MAB13 M_MDB[63..0]
(11) M_MDB[63..0]
M_MAB14
A +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC <Core Design> A

C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 C232 C233 C234 C235
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
+MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC
C236 C237 C238 C239 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249 C250 C251 C252 C253 C254 C255 B 105-942XX-30_11 11
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Date: Tuesday, October 01, 2002 Sheet 13 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(12) M_DQMC#[7..0] 64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels C and D - rank1
M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3 U56 U57 U58 U59
M_DQMC#4 M_MAC12 M3 A7 M_MDC8 M_MAC12 M3 A7 M_MDC47 M_MAD12 M3 A7 M_MDD8 M_MAD12 M3 A7 M_MDD47
M_DQMC#5 M_MAC13 BA0 DQ31 M_MDC9 M_MAC13 BA0 DQ31 M_MDC46 M_MAD13 BA0 DQ31 M_MDD9 M_MAD13 BA0 DQ31 M_MDD46
L4 BA1 DQ30 B8 L4 BA1 DQ30 B8 L4 BA1 DQ30 B8 L4 BA1 DQ30 B8
M_DQMC#6 A8 M_MDC10 A8 M_MDC45 A8 M_MDD10 A8 M_MDD45
M_DQMC#7 M_MAC11 DQ29 M_MDC11 M_MAC11 DQ29 M_MDC44 M_MAD11 DQ29 M_MDD11 M_MAD11 DQ29 M_MDD44
(12) M_DQMD#[7..0] L6 A11 DQ28 A9 L6 A11 DQ28 A9 L6 A11 DQ28 A9 L6 A11 DQ28 A9
M_MAC10 K5 B12 M_MDC12 M_MAC10 K5 B12 M_MDC43 M_MAD10 K5 B12 M_MDD12 M_MAD10 K5 B12 M_MDD43
M_MAC9 A10 DQ27 M_MDC13 M_MAC9 A10 DQ27 M_MDC42 M_MAD9 A10 DQ27 M_MDD13 M_MAD9 A10 DQ27 M_MDD42
L7 A9 DQ26 C11 L7 A9 DQ26 C11 L7 A9 DQ26 C11 L7 A9 DQ26 C11
M_DQMD#0 M_MAC8 M10 C12 M_MDC14 M_MAC8 M10 C12 M_MDC41 M_MAD8 M10 C12 M_MDD14 M_MAD8 M10 C12 M_MDD41
D M_DQMD#1 M_MAC7 A8/AP DQ25 M_MDC15 M_MAC7 A8/AP DQ25 M_MDC40 M_MAD7 A8/AP DQ25 M_MDD15 M_MAD7 A8/AP DQ25 M_MDD40 D
M9 A7 DQ24 D12 M9 A7 DQ24 D12 M9 A7 DQ24 D12 M9 A7 DQ24 D12
M_DQMD#2 M_MAC6 M8 J2 M_MDC16 M_MAC6 M8 J2 M_MDC55 M_MAD6 M8 J2 M_MDD16 M_MAD6 M8 J2 M_MDD55
M_DQMD#3 M_MAC5 A6 DQ23 M_MDC17 M_MAC5 A6 DQ23 M_MDC54 M_MAD5 A6 DQ23 M_MDD17 M_MAD5 A6 DQ23 M_MDD54
L8 A5 DQ22 J1 L8 A5 DQ22 J1 L8 A5 DQ22 J1 L8 A5 DQ22 J1
M_DQMD#4 M_MAC4 M7 H1 M_MDC18 M_MAC4 M7 H1 M_MDC53 M_MAD4 M7 H1 M_MDD18 M_MAD4 M7 H1 M_MDD53
M6 A3 DQ20 H2 M6 A3 DQ20 H2 M6 A3 DQ20 H2 M6 A3 DQ20 H2
M_DQMD#6 M_MAC2 L5 F1 M_MDC20 M_MAC2 L5 F1 M_MDC51 M_MAD2 L5 F1 M_MDD20 M_MAD2 L5 F1 M_MDD51
M5 A1 DQ18 F2 M5 A1 DQ18 F2 M5 A1 DQ18 F2 M5 A1 DQ18 F2
M_MAC0 M4 E1 M_MDC22 M_MAC0 M4 E1 M_MDC49 M_MAD0 M4 E1 M_MDD22 M_MAD0 M4 E1 M_MDD49
(12) M_QSC[7..0] A0 DQ17 A0 DQ17 A0 DQ17 A0 DQ17
E2 M_MDC23 E2 M_MDC48 E2 M_MDD23 E2 M_MDD48
DQ16 M_MDC0 DQ16 M_MDC39 DQ16 M_MDD0 DQ16 M_MDD39
B3 NC DQ15 E11 B3 NC DQ15 E11 B3 NC DQ15 E11 B3 NC DQ15 E11
M_QSC0 B10 E12 M_MDC1 B10 E12 M_MDC38 B10 E12 M_MDD1 B10 E12 M_MDD38
M_QSC1 NC DQ14 M_MDC2 NC DQ14 M_MDC37 NC DQ14 M_MDD2 NC DQ14 M_MDD37
G3 NC DQ13 F11 G3 NC DQ13 F11 G3 NC DQ13 F11 G3 NC DQ13 F11
M_QSC2 G10 F12 M_MDC3 G10 F12 M_MDC36 G10 F12 M_MDD3 G10 F12 M_MDD36
K11 NC DQ11 H11 K11 NC DQ11 H11 K11 NC DQ11 H11 K11 NC DQ11 H11
M_QSC4 K12 H12 M_MDC5 K12 H12 M_MDC34 K12 H12 M_MDD5 K12 H12 M_MDD34
M_QSC5 +MVDDQ NC DQ10 M_MDC6 +MVDDQ NC DQ10 M_MDC33 +MVDDQ NC DQ10 M_MDD6 +MVDDQ NC DQ10 M_MDD33
L2 NC DQ9 J11 L2 NC DQ9 J11 L2 NC DQ9 J11 L2 NC DQ9 J11
M_QSC6 M_MAC14 L3 J12 M_MDC7 M_MAC14 L3 J12 M_MDC32 M_MAD14 L3 J12 M_MDD7 M_MAD14 L3 J12 M_MDD32
(12) M_QSD[7..0] M2 NC DQ7 D1 M2 NC DQ7 D1 M2 NC DQ7 D1 M2 NC DQ7 D1
C1 M_MDC25 C1 M_MDC62 C1 M_MDD25 C1 M_MDD62
R285 DQ6 M_MDC26 R286 DQ6 M_MDC61 R288 DQ6 M_MDD26 R287 DQ6 M_MDD61
DQ5 C2 DQ5 C2 DQ5 C2 DQ5 C2
M_QSD0 4.99K L12 B1 M_MDC27 4.99K L12 B1 M_MDC60 4.99K L12 B1 M_MDD27 4.99K L12 B1 M_MDD60
M_QSD1 MCL DQ4 M_MDC28 MCL DQ4 M_MDC59 MCL DQ4 M_MDD28 MCL DQ4 M_MDD59
DQ3 A4 DQ3 A4 DQ3 A4 DQ3 A4
M_QSD2 M12 A5 M_MDC29 M12 A5 M_MDC58 M12 A5 M_MDD29 M12 A5 M_MDD58
M_QSD3 R289 C256 VREF DQ2 M_MDC30 R290 C258 VREF DQ2 M_MDC57 R291 C257 VREF DQ2 M_MDD30 R292 C259 VREF DQ2 M_MDD57
DQ1 B5 DQ1 B5 DQ1 B5 DQ1 B5
M_QSD4 DIMC0 L9 A6 M_MDC31 DIMC1 L9 A6 M_MDC56 DIMD0 L9 A6 M_MDD31 DIMD1 L9 A6 M_MDD56
M_QSD5 4.99K RFU DQ0 4.99K RFU DQ0 4.99K RFU DQ0 4.99K RFU DQ0
M_QSD6 100nF K8 B2 100nF K8 B2 100nF K8 B2 100nF K8 B2
M_QSD7 RFU VDDQ RFU VDDQ RFU VDDQ RFU VDDQ
M_CKEC M_CLKC#0 L11 B6 +MVDDQ M_CLKC#1 L11 B6 +MVDDQ M_CLKD#0 L11 B6 +MVDDQ M_CLKD#1 L11 B6 +MVDDQ
(10,12) M_CKEC CLK VDDQ CLK VDDQ CLK VDDQ CLK VDDQ
M_WEC# B7 B7 B7 B7
C (10,12) M_WEC# VDDQ VDDQ VDDQ VDDQ C
M_CASC# M_CSC# M1 B9 M_CSC# M1 B9 M_CSD# M1 B9 M_CSD# M1 B9
(10,12) M_CASC# CS VDDQ CS VDDQ CS VDDQ CS VDDQ
M_RASC# B11 B11 B11 B11
(10,12) M_RASC# VDDQ VDDQ VDDQ VDDQ
M_CSC# M_RASC# L1 D2 M_RASC# L1 D2 M_RASD# L1 D2 M_RASD# L1 D2
(10,12) M_CSC# RAS VDDQ RAS VDDQ RAS VDDQ RAS VDDQ
M_CLKC0 D11 D11 D11 D11
(10,12) M_CLKC0 VDDQ VDDQ VDDQ VDDQ
M_CLKC1 M_CASC# K1 E3 M_CASC# K1 E3 M_CASD# K1 E3 M_CASD# K1 E3
(10,12) M_CLKC1 CAS VDDQ CAS VDDQ CAS VDDQ CAS VDDQ
M_CLKC#0 E10 E10 E10 E10
(10,12) M_CLKC#0 VDDQ VDDQ VDDQ VDDQ
M_CLKC#1 M_WEC# K2 F3 M_WEC# K2 F3 M_WED# K2 F3 M_WED# K2 F3
(10,12) M_CLKC#1 WE VDDQ WE VDDQ WE VDDQ WE VDDQ
M_CKED F10 F10 F10 F10
(10,12) M_CKED VDDQ VDDQ VDDQ VDDQ
M_WED# M_DQMC#1 A11 H3 M_DQMC#5 A11 H3 M_DQMD#1 A11 H3 M_DQMD#5 A11 H3
(10,12) M_WED# DM3 VDDQ DM3 VDDQ DM3 VDDQ DM3 VDDQ
M_CASD# H10 H10 H10 H10
(10,12) M_CASD# VDDQ VDDQ VDDQ VDDQ
M_RASD# M_DQMC#2 G2 J3 M_DQMC#6 G2 J3 M_DQMD#2 G2 J3 M_DQMD#6 G2 J3
(10,12) M_RASD# DM2 VDDQ DM2 VDDQ DM2 VDDQ DM2 VDDQ
M_CSD# J10 J10 J10 J10
(10,12) M_CSD# VDDQ VDDQ VDDQ VDDQ
M_CLKD0 M_DQMC#0 G11 C6 M_DQMC#4 G11 C6 M_DQMD#0 G11 C6 M_DQMD#4 G11 C6
(10,12) M_CLKD0 DM1 VDD +MVDDC DM1 VDD +MVDDC DM1 VDD +MVDDC DM1 VDD +MVDDC
M_CLKD1 C7 C7 C7 C7
(10,12) M_CLKD1 VDD VDD VDD VDD
M_CLKD#0 M_DQMC#3 A2 D3 M_DQMC#7 A2 D3 M_DQMD#3 A2 D3 M_DQMD#7 A2 D3
(10,12) M_CLKD#0 DM0 VDD DM0 VDD DM0 VDD DM0 VDD
M_CLKD#1 D10 D10 D10 D10
(10,12) M_CLKD#1 VDD VDD VDD VDD
M_CLKC0 L10 K3 M_CLKC1 L10 K3 M_CLKD0 L10 K3 M_CLKD1 L10 K3
CLK VDD CLK VDD CLK VDD CLK VDD
VDD K6 VDD K6 VDD K6 VDD K6
DIMC0 M_CKEC M11 K7 M_CKEC M11 K7 M_CKED M11 K7 M_CKED M11 K7
(10) D IMC0 CKE VDD CKE VDD CKE VDD CKE VDD
DIMC1 K10 K10 K10 K10
(10) D IMC1 VDD VDD VDD VDD
DIMD0 A3 A3 A3 A3
(10) D IMD0 VSSQ VSSQ VSSQ VSSQ
DIMD1 A10 A10 A10 A10
(10) D IMD1 VSSQ VSSQ VSSQ VSSQ
M_QSC1 A12 C3 M_QSC5 A12 C3 M_QSD1 A12 C3 M_QSD5 A12 C3
Only for BGA Elpida memory DQS3 VSSQ DQS3 VSSQ DQS3 VSSQ DQS3 VSSQ
M_QSC2 G1 C5 +MVDDQ M_QSC6 G1 C5 M_QSD2 G1 C5 M_QSD6 G1 C5
(10,12) M_MAC[14..0] DQS2 VSSQ DQS2 VSSQ DQS2 VSSQ DQS2 VSSQ
M_MAC0 M_QSC0 G12 C9 M_QSC4 G12 C9 M_QSD0 G12 C9 M_QSD4 G12 C9
M_MAC1 DQS1 VSSQ C684 DQS1 VSSQ DQS1 VSSQ DQS1 VSSQ
M_MAC2 M_QSC3 A1 D5 10uF M_QSC7 A1 D5 +MVDDQ M_QSD3 A1 D5 M_QSD7 A1 D5
M_MAC3 DQS0 VSSQ DQS0 VSSQ DQS0 VSSQ DQS0 VSSQ
VSSQ D8 VSSQ D8 VSSQ D8 VSSQ D8
B M_MAC4 E4 E4 E4 E4 B
M_MAC5 VSSQ VSSQ C685 +MVDDQ VSSQ +MVDDC +MVDDC VSSQ +MVDDQ
VSSQ E9 VSSQ E9 VSSQ E9 VSSQ E9
M_MAC6 F4 +MVDDC F4 10uF F4 F4
M_MAC7 VSSQ VSSQ VSSQ VSSQ
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
M_MAC8 G4 G4 C260 G4 C686 C261 G4 C687
M_MAC9 VSSQ C262 VSSQ VSSQ 10uF 10uF VSSQ 10uF
E5 TH GND VSSQ G9 E5 TH GND VSSQ G9 E5 TH GND VSSQ G9 E5 TH GND VSSQ G9
M_MAC10 E6 H4 +MVDDC 10uF E6 H4 22uF 16V E6 H4 E6 H4
M_MAC11 TH GND VSSQ TH GND VSSQ TH GND VSSQ TH GND VSSQ
E7 TH GND VSSQ H9 E7 TH GND VSSQ H9 E7 TH GND VSSQ H9 E7 TH GND VSSQ H9
M_MAC12 E8 J4 E8 J4 E8 J4 E8 J4
M_MAC13 TH GND VSSQ C688 TH GND VSSQ TH GND VSSQ TH GND VSSQ
F5 TH GND VSSQ J9 F5 TH GND VSSQ J9 F5 TH GND VSSQ J9 F5 TH GND VSSQ J9
M_MAC14 F6 10uF F6 F6 F6
TH GND TH GND TH GND TH GND
(10,12) M_MAD[14..0] F7 TH GND VSS D4 F7 TH GND VSS D4 F7 TH GND VSS D4 F7 TH GND VSS D4
F8 TH GND VSS D6 F8 TH GND VSS D6 F8 TH GND VSS D6 F8 TH GND VSS D6
M_MAD0 G5 D7 G5 D7 +MVDDQ G5 D7 G5 D7
M_MAD1 TH GND VSS TH GND VSS TH GND VSS TH GND VSS
G6 TH GND VSS D9 G6 TH GND VSS D9 G6 TH GND VSS D9 G6 TH GND VSS D9
M_MAD2 G7 J5 G7 J5 G7 J5 G7 J5
G8 TH GND VSS J6 G8 TH GND VSS J6 G8 TH GND VSS J6 G8 TH GND VSS J6
M_MAD4 H5 J7 H5 J7 C263 H5 J7 H5 J7
M_MAD5 TH GND VSS TH GND VSS 10uF TH GND VSS TH GND VSS
H6 TH GND VSS J8 H6 TH GND VSS J8 H6 TH GND VSS J8 H6 TH GND VSS J8
M_MAD6 H7 K4 H7 K4 H7 K4 H7 K4
H8 TH GND VSS K9 H8 TH GND VSS K9 H8 TH GND VSS K9 H8 TH GND VSS K9
M_MAD8
M_MAD9 1Mx32x4 1Mx32x4 1Mx32x4 1Mx32x4
M_MAD10
M_MAD11
M_MAD12
(12) M_MDC[63..0]
M_MAD13
M_MAD14
(12) M_MDD[63..0]
A +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC <Core Design> A

C264 C265 C266 C267 C268 C269 C270 C271 C272 C273 C274 C275 C276 C277 C278 C279 C280 C281 C282 C283
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
+MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC +MVDDQ +MVDDC
C284 C285 C286 C287 C288 C289 C290 C291 C292 C293 C294 C295 C296 C297 C298 C299 C300 C301 C302 C303 B 105-942XX-30_11 11
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF Date: Tuesday, October 01, 2002 Sheet 14 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
STRAPS
AGPFBSKEW -- VID(1:0) X0CLK_SKEW --VID(3:2)
Ri5 R333 10K Ra2 Ra1 Ri7 Ri8 Ra4 Ra3 Ri5 Ri6
Ri6 R334 10K
Ri7 R335DNI 10K refclk slightly earlier than feedback x0clk to agpclk 0 tap delay
Ri8 DNI DNI 10K 10K (00) DNI DNI 10K 10K
R336 10K DEFAULT
DNI 10K 10K DNI refclk 1 tap earlier than feedback DNI 10K 10K DNI x0clk to agpclk 1 tap delay
D (01) D
VID[7..0] refclk 1 tap later than feedback
VID[7..0] (4,23) 10K DNI DNI 10K 10K DNI DNI 10K x0clk to agpclk 2 taps delay
+3.3V_BUS DEFAULT (10)
Ra1 R337 DNI 10K V ID0
Ra2 R338 10K V ID1 10K 10K DNI DNI refclk 2 taps earlier than feedback (11) 10K 10K DNI DNI x0clk to agpclk 3 taps delay
V ID7
Ri1 R344 10K INSTALL DEVICE ID

Ri2 R345 10K
Ri3 R346 10K BUSCFG -- VID(6:4)
Rh1 NORMAL ID (default)
Install it all the time when it is normal BUSTYPE_2 BU STYPE_1 BU STYPE_0
device ID
VID6 VID5 VID4
Rh2 Use workstation DEVICE_ID when
W SEN = 1 Ra7 Ri3 Ra6 Ri2 Ra5 Ri1 AGP8X_DET = 0 (both GC and MB 8x capable)
Rh1 +3.3V_BUS
DESCRIPTION
R347 10K
(4,23) D VALID
Rh2 DNI 10K DNI 10K DNI 10K AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD16
R348 10K
DNI 10K DNI 10K 10K DNI AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD17
+3.3V_BUS
Rh3 DNI 10K 10K DNI DNI 10K AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD16
C +3.3V_BUS C
R349 10K C733 DNI 10K 10K DNI 10K DNI AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD17
5
DNI U93 100nF INSTALL DNI ID_DISABLE
Rh10 +5VEXT
AGP8X_DET = 1 (either GC or MB not 8x capable)
R874 10K EXT_PWR 4 2 R875 1K
(4) PSYNC DNI Rh4 Rh10 Normal operation
Rh4 DNI 10K DNI 10K DNI 10K AGP 4X, PLL CLK, IDSEL = AD16
R350 10K NC7S04M5
3
R876 DNI 10K DNI 10K 10K DNI AGP 4X, PLL CLK, IDSEL = AD17
1.8K Rh3 Rh10 CHIP SHUTS DOWN
C DNI 10K 10K DNI DNI 10K AGP 1X/2X, PLL CLK, IDSEL = AD16
DNI 10K 10K DNI 10K DNI AGP 1X/2X, PLL CLK, IDSEL = AD17
C Rh10 Rh3 Rh4 Circuitry for external
power detection. (DEFAULT) 10K DNI DNI 10K DNI 10K PCI 66MHz, PLL CLK
10K DNI DNI 10K 10K DNI PCI 33MHz, 3.3V, REF CLK
INSTALL VIP DEVICE
Rh5 +3.3V_BUS 10K DNI 10K DNI DNI 10K AGP 1X, REF CLK, IDSEL = AD16
R351 10K Rh5 NOSLAVE VIP (DEFAULT)
(4,23) VHAD0 Install it when internal 10K DNI 10K DNI 10K DNI AGP 1X, REF CLK, IDSEL = AD17
pull-up doesn't work
SLAVE VIP ---
VIP device will drive low when
VIP is attached.
Rj1 Rk1 Rj2 Rk2 Rj3 Rk3 Rj4 Rk4 ROMIDCFG[3:0]

R909 10K EXT_PWR 10K 10K DNI 10K
B (4) TVO8 DNI DNI 10K DNI B
No ROM, CHG ID = 00
DNI 10K DNI 10K 10K DNI DNI 10K
No ROM, CHG ID = 01
+3.3V_BUS 10K 10K DNI DNI 10K
DNI DNI 10K
No ROM, CHG ID = 10
MEMORY TYPE STRAPS R352
Rj1 10K
DNI 10K 10K DNI 10K DNI DNI 10K
No ROM, CHG ID = 11
(4,17) ROMCS# ROMIDCFG3
Rk1 10K 10K DNI DNI 10K DNI 10K DNI 10K
Rh6 DNI +3.3V_BUS R353 DNI Parallel ROM on TVO (default)
R850 10K 10K DNI DNI 10K 10K
(4) TVO6
R354 Rj2 10K DNI 10K DNI
Serial AT25F1024, ID's from ROM
(4,17) ROMSO ROMIDCFG2
Rh7 DNI
Rk2 10K 10K DNI DNI 10K 10K DNI DNI 10K
R851 10K R355 DNI Serial AT45DB011, ID's from ROM
Rj3 10K 10K DNI DNI 10K DNI 10K DNI
R357 DNI 10K Serial ST M25P10, ID's from ROM
(4,17) ROMSI ROMIDCFG1
Rk3 10K 10K DNI 10K DNI DNI 10K DNI 10K
R358 Serial ST M25P05, ID's from ROM
Rh8 DNI +3.3V_BUS 10K DNI
Rj4 10K DNI DNI 10K 10K DNI Serial SST45LF010, ID's from ROM
R852 10K R359 10K DNI ROMIDCFG0
(4) TVO7 (4,17) ROMSCK
Rk4 10K 10K DNI 10K DNI 10K DNI DNI 10K Parallel ROM on DVO
Rh9 DNI R360
R853 10K
10K DNI 10K DNI 10K DNI 10K DNI Serial ISSI NX25F011B, ID's from ROM
MEMORY TYPE STRAPS

A <Core Design> A
MEMORY TYPE Rh6 Rh7 Rh8 Rh9 ATI Technologies Inc.

TBD TBD TBD TBD TBD
Markham, Ontario
Canada, L3T 7X6
TBD TBD TBD TBD TBD
(905) 882-2600
TBD TBD TBD TBD TBD Title AGP R300 128MB BGA DVII VGA VO
TBD TBD TBD TBD TBD Size Document Number 105-942XX-30_11 Rev
B 11
8 7 6 5 4 3 2 1
R566
8 7 6 5 4 3 2 1
D D
SPEED CONTROLED FAN
+12V_BUS +5V_BUS
Install Rl3 when +12V fan is used. R361 R362 Install Rl2 when +5V fan is used. H1
0R 0R
Rl3 Rl2
DNI
C C
R921 DNI 0R
Fan_VDD
(5) VTERM2
JU1
DNI
R363 1
100K 2
THERM
(5) VTERM1
DNI
DNI
C489 R364 C490
10nF 100K 10uF 16V
MMBT2222ALT1
R365 U76 DNI
3
DNI VT1 1 8
10K VT1 VDD R366 270R Q11 R367
2 CF OUT 7 1
3 6 0R
C491 R368 VSLP OTF DNI DNI
4 5
2
DNI DNI GND VT2 C492 Rl1
10nF 5.11K C493 MC502BM 0.1uF
10nF DNI
DNI
Fan_VDD
Place directly
R768
underneath R300
24.3K RT1
B thermal balls. B
t DNI
DNI 100K
DNI
DNI R769 0R if RT1 not used.
R891 100K 10K
Fan_VDD
DNI R892 Fan_VDD

4
100K R893 100K DNI

3 +
U95A DNI R894 100K
1
DNI R904 DNI 2 -
100K LM324M R896
DNI 100K
11
DNI
R897 100K R898 100K
THERM
DNI
DNI 5 U95B
+
10 +
U95C R899 100K 7 VT1
8 R900 6 -
9 - 100K LM324M
LM324M DNI
R901 100K
A DNI A
R902
100K
DNI <Core Design>
R903 0R ATI Technologies Inc.
Markham, Ontario
DNI
Canada, L3T 7X6
(905) 882-2600
B 11
8 7 6 5 4 3 2 1
R566
8 7 6 5 4 3 2 1
D D
SERIAL EEPROM 512K/1M
ROM_SO
Ua DNI Ub
U80 U81
SI/A16 5 2 ROM_SO 8 1
33R 1 D Q SO SI
(4,15) ROMSO 8 RP192A
2 7 SCK/WEb 6 2
(4,15) ROMSI C SCK
(4,15) ROMSCK 3 6
33R 4 5 RP192D CSb 1 3 HOLD1
(4,15) ROMCS# S HOLD# R/B#
HOLD1 7 4
(24) ROM_CSb HOLD CS#
+3.3V_BUS +3.3V_BUS
+3.3V_BUS 3 5
W WP#
C 8 4 7 6 C
VCC VSS GND VCC
C497 M25P05-VMN6T NX25F011B-3S
100nF
ALTERNATIVE PART :M25P05(512Kbit) ALTERNATIVE PART : AT45DB011
B B
A <Core Design> A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600

B 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PRIMARY DVI-I CONNECTOR (DVI-I1)
+5V_DIN
(19) +5V_DIN
DVI-I1
J4
INSTALL TERMINATION RESISTORS INSTALL TERMINATION RESISTORS M1
CLOSE TO ASIC CLOSE TO CONNECTOR CASE
M3 CASE
TX2M 1
(4) TX2M TMDS Data2-
TX2P 2
(4) TX2P TMDS Data2+
R794 330R R451 330R 3 TMDS Data2/4 Shield
4 TMDS Data4-
DNI 5 TMDS Data4+
(19) DDCCLK_DVI_R
6 DDC Clock
(19) DDCDATA_DVI_R
7 DDC Data
(19) V SYNC_DVI-I_R
8 Analog VSYNC
C TX1M 9 C
TX1P 10
R795 330R R453 330R 11 TMDS Data1/3 Shield
12 TMDS Data3-
DNI Place close to 13
B38 Bead the connector +5V_DIN TMDS Data3+
(20,22) +5VCON1 14 +5V Power
15 GND (for +5V)
16 Hot Plug Detect
TX0M 17
TX0P 18
R796 330R R455 330R 19
C558 TMDS Data0/5 Shield
20 TMDS Data5-
DNI 21
100nF TMDS Data5+
22 TMDS Clock Shield
TXCP 23
(4) TXCP TMDS Clock+
TXCM 24
(4) TXCM TMDS Clock-
R797 330R R456 330R
(19) R _DVI-I
C1 Analog Red
DNI C2
(19) G_DVI-I Analog Green
(19) B_DVI-I
C3 Analog Blue
(19) HS YNC_DVI-I_R C4 Analog HYNC
C5 Analog GND
C6 Analog GND
M4 CASE
M2 CASE
DVI A/D
c
R457 20K
(4) HPD1
1
B B
R458
100K R459 0R
D9
2.5V R460 0R
2
R461 0R
R462 0R
A A
<Core Design>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
B 105-942XX-30_11 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS +5V_BUS +5V_BUS +5V_BUS
2
R469 0R
D17 D18 D19 D20 D21 D22 D23 R_ DVI-I (18)
R471 0R G_DVI-I (18)
3 3 3 3 3 3 3 B_DVI-I (18)
R472 0R
HS YNC_ DVI-I_R (18)
1
R473 0R V S YNC_DVI-I_R (18)
DNI DNI DNI DNI DNI DNI DNI
c
+5V_DIN
+5V_DIN (18)
MJ4 DNI
R_ DVI-I 1
G_DVI-I R
2
B_DVI-I G
3
B
11 DDC2_MONID0
DDC DATA_DVI_R MS0
12 DDC2_MONID1(SDA)
MS1
4 DDC2_MONID2
DDCC LK_DVI_R MS2
15 DDC2_MONID3(SCL)
MS3
9
HS YNC_ D VI-I_R NC
13
V S YNC _DVI-I_R HS
14
VS
5
C573 C574 C575 VSS
6
5pF 5pF 5pF VSS
7
C749 C750 VSS
8
DNI DNI DNI VSS
10
22pF 22pF VSS
16
C CASE C
17
CASE
2
DNI DNI 18
DNI DNI DNI CASE
19
L16 L17 L18 CASE
DB 15F slim RA
82nH 82nH 82nH c 6050003000
Thin-DB15
1
c PLACE CLOSE TO
Co x + Loy
CONNECTOR
DDCCLK_DVI_R (18)
DDCC LK_DVI_R
DDCDATA_DVI_R (18)
R822 33R R824 33R
(20) DDCCLK_DAC1_5V DDCCLK_DAC2_5V (21)
DDC DATA_DVI_R
R823 33R R825 33R

(20) DDCDATA_DAC1_5V DDCDATA_DAC2_5V (21)
HS YNC_ D VI-I_R
R799 51R R815 0R R800 0R

(20) HS YNC_DAC1_B HS YNC_DAC2_B (21,22,23)
V S YNC _DVI-I_R
B R802 51R R816 0R R803 0R B

(20) V S YNC_DAC1_B V S YNC_DAC2_B (21,23)
ADDED DUE
TO LONG
TRACES
R_ DVI-I
L57 1 2 68nH R26 0R

(20) R_DAC1_F1 R/C_ DAC2_F (21)
G_DVI-I
L58 1 2 68nH R27 0R

(20) G_DAC1_F1 G /Y_ DAC2_F (21)
B_DVI-I
L59 1 2 68nH R28 0R

(20) B_DAC1_F1 B/COMP_DAC2_F (21)
Keep length short,

Place close to the output Place close to the
A or another set of A
of the DAC1 filters High-Density
resistor may be
Header
needed
<Core Design>

1 Com m erce V alley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Size Document Number R ev
C 105-942XX-30_11 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PRIMARY CRT INTERFACE
D D
OPTIONAL ESD/HOTPLUG PROTECTION DIODES PRIMARY VGA

+3.3V_BUS +3.3V_BUS+3.3V_BUS+5V_BUS +5V_BUS+5V_BUS +5V_BUS CONNECTOR
2
D10 D11 D12 D13 D14 D15 D16
BAT54SLT1
F1
3 3 3 3 3 3 3
R_DAC1_F1 (19) +5V_BUS
G_DAC1_F1 (19)
1
B_DAC1_F1 (19) 750mA
PLACE CLOSE TO ASIC DNI DNI DNI DNI DNI DNI DNI
C +5VCON1 (18,22) C
B39
Bead
J5
(4) R_DAC1
L43 1 2 82nH L46 1 2 82nH R_DAC1_F 1 R
(4) G_DAC1
L44 1 2 82nH L47 1 2 82nH G_DAC1_F 2 G
(4) B_DAC1
L45 1 2 82nH L48 1 2 82nH B_DAC1_F 3 B
11 MS0
DDCDATA_DAC1_5V R465 33R 12 MS1
4 MS2
DDCCLK_DAC1_5V R466 33R 15 MS3
9 NC
HSYNC_DAC1_R1 R470 0R HS YNC_DAC1_R 13
R49 R50 R51 R474 0R VSYNC_DAC1_R HS
14 VS
75.0R 75.0R 75.0R VSYNC_DAC1_R1 5
+3.3V_BUS +5V_BUS 1% 1% 1% C559 C560 C561 C562 VSS
6 VSS
+3.3V_BUS DNI DNI DNI C751 C752 7 VSS
3pF 3pF 3pF 8
R467 R463 22pF 22pF 100nF VSS
10 VSS
BSN20 GND_AVSSN C564 3pF DNI C565 1pF DNI DNI 16 CASE
1
2
Q12 C567 3pF DNI C568 1pF DNI DNI DNI 17
4.7K 6.8k C570 3pF DNI C571 1pF CASE
2 3 L7 L8 L9 Connector DB15 Female VGA Blue
(4) CRT1DDCDATA
+3.3V_BUS +5V_BUS 82nH 82nH 82nH
+3.3V_BUS c
PLACE CLOSE TO
1
R468
BSN20
R464
c CONNECTOR
1
B Q13 B
4.7K 6.8k
DDCDATA_DAC1_5V (19)
(4) CRT1DDCCLK 2 3 DDCCLK_DAC1_5V (19)
R859 R860
74ACT08MTC
10 56R 56R
(4) HSYNC_DAC1
8
+5V_BUS 9
U 2C
HSYNC_DAC1_B (19)
13
11 VSYNC_DAC1_B (19)
(4) V SYNC_DAC1
12
U 2D
74ACT08MTC
A <Core Design> A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
B 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PLACE CLOSE TO ASIC
L10 1 2 68nH L60 1 2 56nH

(22) R_DAC2 R/C_DAC2_F (19)
L12 1 2 68nH L61 1 2 56nH
(22) G_DAC2 G/Y_DAC2_F (19)
L14 1 2 68nH L62 1 2 56nH
(22) B_DAC2 B/COMP_DAC2_F (19)
+3.3V_BUS +5V_BUS
R479 6.8k
1
4.7K BSN20 R480

R791 75.0R C576 3.3pF C577 8pF
2 3 R792 75.0R C578 3.3pF C579 8pF
(4) CRT2DDCDATA DNI
R793 75.0R C580 3.3pF C581 8pF
Q14
C C
+5V_BUS
GND_A2VSSN SECONDARY CRT LOGIC
+3.3V_BUS
CRT2
R481 6.8k
1
4.7K BSN20 R482

DDCDATA_DAC2_5V (19)
(4) CRT2DDCCLK 2 3 DDCCLK_DAC2_5V (19)
Q15
R29 33R
R30 33R DDCDATA_DAC2_HDH (23)
DDCCLK_DAC2_HDH (23)
U3B
(4) HSYNC_DAC2 4
6
5
SN74ACT86PW
U3C
9 R31 47R
HSYNC_DAC2_B (19,22,23)
8 R32 47R
VSYNC_DAC2_B (19,23)
(4) V SYNC_DAC2 10
B B
SN74ACT86PW
R877
10K
DNI
A <Core Design> A

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
B 105-942XX-30_11 11
8 7 6 5 4 3 2 1
5 4 3 2 1
TV-OUT
STEREOSCOPIC DISPLAY
B50 DNI Bead
CONNECTOR DNI
Jm3
(18,20) +5VCON1
B m4
Rm21 MJ7
U3D P IN1 1
R763 0R 1
(4) STEREOSYNC 12 R m3 2
2
D 11 R517 0R COMP 7 D
L20 DNI 7
13
Y_D AC2 R925 0R TBLuma DNI 8
SN74ACT86PW CASE
9
1.8uH CASE
10
R912 CASE
Co nnector Jm3 uses the
75.0R C583 C584 same footprint as Jm1 MiniDIN 3 Pin
G
82pF 82pF
F and Jm2 c
c
GND_TVVSSN
L21
C_DAC2 R926 0R TBChroma
1.8uH
R913 C585 C586
75.0R ADDED TO REMOVE 82pF 82pF TV Out (Comp)
STUBS WHEN VO c
USED ON HDH Jm2
J8
GND_TVVSSN Jack Phono RCA
COMP 1
L22 DNI
COMP_DAC2 R927 0R TBComp
3
R914 1.8uH
75.0R C588 C587
C 82pF 82pF C
Co nnector Jm2 uses the c
c
same footprint as Jm1 B
GND_TVVSSN and Jm3
(4) R /C_DAC2
(4) G/ Y_DAC2
(4) B/COMP_DAC2
Install DNI
+5V_BUS
A C D E Uv1
TV-OUT only (main board) B G
C735 CRT2 logic (page21)
Uv1 100nF A CRT2 logic (page21) B C D E G Uv1
VGA2 only (main board)
U96
1 16 VGA2 & TV-OUT (main board) G Uv1 CRT2 logic (page21) A B C D E
(4,23) TVO0 SEL VCC
COMP_DAC2 2 4
B_DAC2 1A0 YA
(21) B_DAC2 3 1A1 YB 7 VGA2 (main board) Uv1 A B C E
Y_D AC2 5 9 D G
G_DAC2 1B0 YC & TV-OUT (daughter card)
(21) G_DAC2 6 1B1 YD 12
11 13 R_DAC2 TV-OUT (main board)
1C0 1D1 R_DAC2 (21)
10 14 C_DAC2 C G Uv1 A B D E
1C1 1D0 & VGA2 (d aughter card)
15 8
B E GND TV Out (SVHS) B
PI5V330 VGA2 (daug hter card) E A B C D G Uv1
& TV-OUT (daughter card) CRT2 logic (page21) Jm1
C DNI
R915 0R R_DAC2
(23) R /C_DAC2_HDH
Connector DIN Miniature Circular 7 Pin
R916 0R G_DAC2 J7
(23) G/ Y_DAC2_HDH
R878 0R 6 +12V
R917 0R B_DAC2 (4,23) TVO2
(23) B/COMP_DAC2_HDH
TVO0 VGA2 TV out TBLuma R606 0R Rm22 TBLuma_R 3
DNI TBChroma R608 0R Rm23 TBChroma_R Y-OUT
D 4 C-OUT
R918 0R C_DAC2 TBComp R504 0R Rm24 COMP 7
R513 330R S Y NC Comp_out
R919 0R Y_D AC2
"1" enable disable (19,21,23) HSYNC_DAC2_B 5 SYNC
DNI
R m7 P IN1 1
R920 0R COMP_DAC2 GND
"0" disable enable 2 GND
R m1
E DNI 8
R922 0R R /C_DAC2 R509 CASE
9 CASE
10 CASE
R923 0R G/ Y_DAC2 DNI Cm1
0R
R924 0R B/COMP_DAC2 Co nnector Jm1 uses the C589
470pF
same footprint as Jm2
R_DAC2 R928
A
0R
DNI
R /C_DAC2
H and Jm3
c c c
G_DAC2 R929 0R G/ Y_DAC2

A A
B_DAC2 R930 0R B/COMP_DAC2
B DNI
<Core Design> ATI Technologies Inc.
C_DAC2 R931 0R 1 Commerce Valley Drive East
Markham, Ontario
Y_D AC2 R932 0R Canada, L3T 7X6
(905) 882-2600
COMP_DAC2 R933 0R
Title
B 105-942XX-30_11 11
5 4 3 2 1
8 7 6 5 4 3 2 1
HIGH-DENSITY HEADER
D D
DVO/VID Data Bus

DVO[11..0]
DVO[11..0] (4)
CLK_VIDCLK (4)
V I D[7..0]
V ID[7..0] (4,15)
VIP Host Bus

CLK_VIPCLK (4)
VHAD0 (4,15)
VHAD1 (4)
VPHCTL (4)
3.3V I2C DATA

SOCKET STRIP 2x35 0.05x.1 R808 0R
SDA (4)
3.3V I2C CLK
C R806 0R +3.3V_BUS JU5 +5V_BUS +3.3V_BUS C
(4) SCL
VPHCTL 1 2 CLK_VIPCLK
CLK_VIDCLK 3 4
V HAD1 5 6 V ID7 Daughter Card Straps
V ID6 7 8 V HAD0 +3.3V_BUS
+3.3V_BUS Daughter Card Straps 9 10 V ID5
V ID4 11 12
R861 10K 13 14 V ID3 R867 10K
R862 10K V ID2 15 16 R868 10K
R863 10K 17 18 V ID1 R869 10K
V ID0 19 20
I2C_CLK 21 22 I2C_DATA
DC_Strap5 R809 0R 23 24 NTSC/PAL R810 0R
(4,22) TVO0 DC_Strap3 R811 0R R812 0R DC_Strap4 TVO1 (4)
25 26
(4,22) TVO2 DC_Strap1 R813 0R R814 0R DC_Strap2 TVO3 (4)
(4) TVO4
27 28 TVO5 (4)
3
29 30
4
31 32 SW1B
33 34 SW1A DIP_SWX2
R864 10K 35 36 R870 10K DIP_SWX2
2
R865 10K 37 38 AGP_RESET# R871 10K
1
R866 10K 39 40 R872 10K
41 42 DVO0
DVO1 43 44
45 46 DVO2
DVO3 47 48
49 50 DVO4 DDC CLK
Analog Display from DAC2 DVO5 51 52
53 54 DVO6
DVO7 DDCCL K _DAC2_HDH (21)
55 56
(22) G /Y_ DA C2_HDH DVO8
(19,21,22) HS YNC_DAC2_B
57 58
DVO9 59 60 Analog Display from DAC2
(19,21) V S YNC_DAC2_B DVO10
61 62 R/C_ DA C2_HDH (22)
DVO11 63 64
R818 0 R DNI B/COMP_DAC2_HDH (22)
65 66
DDC DATA 67 68
R820 0R
69 70
B B
(21) DDCDA TA_DAC2_HDH AGP_RESET# (2,3,9,10,24)
HP D2 (4)
DVO Bus control lines for

Use to reset Si168 External TMDS External DDR TMDS
CLK_DVOCLK1 (4)
R821 0R
(4,15) DVALID CLK_DVOCLK0 (4)
DVOCNTL2 (4)
DVOCNTL1 (4)
DVOCNTL0 (4)
A A
<Core Design>

1 Com m erce V alley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Size Document Number R ev
C 105-942XX-30_11 11
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(3) 8X_DET#
Hijack Circuit
MU106
TK11819M
IN- 1 6
Vin T1
2 OSC GND 5DEVSEL_TTL
I N+3 4 +5V_BUS
D DK Vout D
USED FOR THE FOOTPRINT +5V_BUS C753

100nF
14
U3A
1
3
DEVSEL_TTL R943 0R 2
+5V_BUS
7
SN74ACT86PW +5V_BUS
U106
5
C761
100nF 3 C759
+ 100nF
1 R947 0R Block_DEVSEL#
4 - 14
LMV7219M7
R1547 2 U99A
2
100K 1 R952 0R
DNI 3
(17) ROM_CSb
C1126
R1550 4.99K I N+ 100nF
(2,3) AGP_VREFGC
SN74HCT02PWR 7 DNI
+5V_BUS
R1548 1.0K IN- U99D
(2,3) AGP_DEVSEL#_R
R1551 +5V_BUS
100K C757 11
DNI 100nF 13 SWAP
C 12 C
U107
1 8 R951 0R SN74HCT02PWR
VDD VCC
2 OUT IN+ 7
C760 U103A U103B
14
10
3 GND IN- 6
4
Block_DEVSEL# 4 5 100nF
LATCH VEE
2 5 12 9
5V
PR
PR
MAX9203EKA-T D Q D Q
Place closest possible to AGP
3 6 11 8
CL
CL
connector with minimum possible C Q C Q
G
stub on AGP_DEVSEL#_R signal.
7
1
13
HighSpeed Comparator 74VHCT74MTC 74VHCT74MTC
(2,3,9,10,23) AGP_RESET#
U99B
U99C
R946 220R 5
(2,3) AGP_AGPCLK
4 8
Minimum possible stub on 6 10
9
this signal.
SN74HCT02PWR SN74HCT02PWR
B B
MK1
1 SELECT NO 6
2 5
3
V+ COM
4
Place closest possible to AGP connector with absolute
GND NC
NLAS4599DF minimum possible trace lengths and vias.
+5V_BUS
K1
MAX4625EUT-T
SWAP 1 6
2 + 5 AGP_TRDY#_R (2)
C755 3 - 4
100nF AGP_TRDY# (2,3)
K2
MAX4625EUT-T
1 6
A 2 5 A
+ AGP_STOP#_R (2)
C756 3 - 4
100nF AGP_STOP# (2,3) <Core Design>
AGP CONNECTOR R300 SIDE 1 Commerce Valley Drive East
Markham, Ontario
1
MK2
6
SIDE Canada, L3T 7X6
(905) 882-2600
SELECT NO
2 V+ COM 5
3 4 Title AGP R300 128MB BGA DVII VGA VO
GND NC
NLAS4599DF Size Document Number 105-942XX-30_11 Rev
B 11
8 7 6 5 4 3 2 1
5 4 3 2 1
CRT SCREWS DVI SCREWS

MISC. BOARD PARTS
ASSY1 ASSY2 ASSY3 REF1 REF2

BLANK
SCREW SCREW
LABEL PCB
JACKSCREW JACKSCREW SCHEMATIC
AS SY AS SY 1.50W X 0.50H
D 7020000800 7020000800 AS SY D
ASSY4 ASSY5 105-942XX-30 109-942XX-30
AS SY AS SY
SCREW SCREW ASSY7
JACKSCREW JACKSCREW
AS SY AS SY
ANTISTATIC
7020000800 7020000800
BAG
REF3
ASSY6 6 X 11
ATI LOGO
AS SY
LABEL
SCREW
PAN HEAD
ATI LOGO LABEL
ASSY8 ASSY11 ASSY10
BRACKET BRACKET BRACKET
VGA, VID OUT, DVI, 301 VGA, DVI, 308 DVI, 251
AS SY ALT ALT
C C
B B
A A
<Core Design>

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
B 105-942XX-30_11 11
5 4 3 2 1
AGP R300 128MB BGA DVII VGA VO Revised: Tuesday, October 01, 2002
105-942XX-30_11 Revision: 11

Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Bill Of Materials October 1,2002 14:09:36 Page1
Item Quantity Reference Part

__________________________________
1 4 ASSY1,ASSY2,ASSY4,ASSY5 7020000800 1 Jackscrew for DB15 Connector, 4-40, Steel w/ Zinc plate & clear chromate
2 1 ASSY3 9050005100 1 Label, blank 1.50 X 0.50
3 1 ASSY6 7020001700 1 Screw, Phillips Pan Hd., 4-40 X 3/16"
4 1 ASSY7 9040000900 1 Antistatic bag, W/O Ziplock, 6in x 11in
5 1 ASSY8 8020030100 1 BRACKET, VGA, VID OUT, DVI, 301
6 1 ASSY10 8020025100 BRACKET, DVI, 251
7 1 ASSY11 8020030800 9 BRACKET, VGA, DVI, 308
8 9 B3,B4,B5,B7,B8,B9,B38, 5050001900 1 Bead ferrite 26 ohm 600mA SM
B39,B50
9 6 B6,B10,B12,B13,B14,B15 5260001900 1 Ferrite Bead, 200mA 200R@100MHz
10 5 B11,B24,B25,B26,B27 5260001900 1 Ferrite Bead, 200mA 200R@100MHz
11 2 B18,B16 5050003200 1 Ferrite bead, 60R @100MHz, 6000mA
12 4 B19,B21,B22,B23 5050003200 1 Ferrite bead, 60R @100MHz, 6000mA
13 12 CP1,CP2,CP3,CP4,CP5,CP6, 4290000200 1 Capacitor Array, 4x10nF, 20%, 50V, X7R
CP7,CP8,CP9,CP11,CP12,
CP13
14 4 C1,C2,C3,C132 4260110700 1 100uF 20% 16V ALUMINUM SM 5.4mm High
15 1 C4 4250010000 1 10pF +/-.5pF 50V NPO CERAMIC SM
16 7 C5,C735,C753,C757,C759, 4250010400 1 100nF 10% 16V X7R CERAMIC SM
C760,C1126
17 3 C6,C89,C93 4250010300 1 10nF 10% 25V X7R CERAMIC SM
18 6 C7,C8,C10,C11,C12,C13 4265047700 4 470uF 20% 6.3V Polymer / Aluminum Low ESR 22mOhm 10mm High
19 160 C14,C48,C49,C50,C51,C149, 4170010400 1 100nF 10% 10V X7R Ceramic SM
C151,C152,C153,C154,C155,
C156,C157,C158,C159,C160,
C161,C162,C163,C164,C165,
C166,C167,C168,C169,C170,
C171,C172,C173,C174,C175,
C176,C177,C180,C181,C182,
C183,C184,C185,C186,C187,
C188,C189,C190,C191,C192,
C193,C194,C195,C196,C197,
C198,C199,C200,C201,C202,
C203,C204,C205,C208,C209,
C210,C211,C216,C217,C218,
C219,C220,C221,C222,C223,
C224,C225,C226,C227,C228,
C229,C230,C231,C232,C233,
C234,C235,C236,C237,C238,
C239,C240,C241,C242,C243,
C244,C245,C246,C247,C248,
C249,C250,C251,C252,C253,
C254,C255,C256,C257,C258,
C259,C264,C265,C266,C267,
C268,C269,C270,C271,C272,
C273,C274,C275,C276,C277,
C278,C279,C280,C281,C282,
C283,C284,C285,C286,C287,
C288,C289,C290,C291,C292,
C293,C294,C295,C296,C297,
C298,C299,C300,C301,C302,
C303,C674,C675,C676,C707,
C708,C709,C710,C727,C728,
C729,C730,C731,C733
20 20 C15,C22,C25,C29,C31,C35, 4210010500 1 1uF +80/-20% 16V Y5V CERAMIC SM (0805)
C37,C42,C43,C44,C52,C55,
C56,C57,C66,C69,C74,C75,
C673,C738
21 13 C16,C19,C23,C27,C32,C39, 4235022600 1 22uF 20% 16V TANTALUM SM
C46,C53,C67,C84,C134,
C212,C260
22 2 C17,C20 4250010100 1 100pF 10% 50V NPO CERAMIC SM
23 19 C18,C21,C24,C26,C30,C33, 4250010400 1 100nF 10% 16V X7R CERAMIC SM
C36,C38,C45,C47,C95,C131,
C133,C135,C497,C558,C562,
C762,C765
24 8 C28,C34,C98,C99,C101, 4235022600 1 22uF 20% 16V TANTALUM SM
C137,C138,C1128
25 2 C40,C41 4250010000 1 10pF +/-.5pF 50V NPO CERAMIC SM
26 12 C54,C58,C59,C60,C61,C62, 4220010600 1 10uf +80/-20% 6.3V Y5V CERAMIC SM
C63,C65,C70,C71,C72,C73
27 1 C64 4230047600 1 47uF 20% 16V Tantalum SM
28 1 C68 4262047600 1 47uF 20% 6.3V Aluminum Low ESR 760mOhm
29 1 C76 4262047700 1 470uF 20% 6.3V Aluminum Low ESR 160mOhm 10.5mm High
30 2 C747,C77 4250010200 1 1nF 10% 50V X7R CERAMIC SM
31 1 C78 4250022200 1 2.2nF 10% 50V X7R CERAMIC SM
32 1 C79 4250015100 1 150pF 10% 50V X7R CERAMIC SM
33 4 C80,C81,C82,C97 4051047700 1 470uF, 10V, 20% 10X12.5mm 0.030R@100kHz, Radial
34 1 C85 4210010200 1 1nF 10% 100V NPO CERAMIC SM
35 3 C86,C92,C1129 4210022500 1 2.2uF 10% 6.3V X5R Ceramic SM
36 5 C87,C90,C145,C146,C734 4210010500 1 1uF +80/-20% 16V Y5V CERAMIC SM (0805)
37 1 C88 4210022400 1 220nF 10% 16V X7R CERAMIC SM
38 3 C91,C732,C736 4264047700 1 470uF 20% 6.3V Polymer / Aluminum Low ESR 22mOhm 8mm High
39 2 C130,C94 4262047700 1 470uF 20% 6.3V Aluminum Low ESR 160mOhm 10.5mm High
40 6 C100,C105,C125,C129,C140, 4250010300 1 10nF 10% 25V X7R CERAMIC SM
C144
41 3 C102,C126,C141 4250022200 1 2.2nF 10% 50V X7R CERAMIC SM
42 2 C142,C103 4250015400 9 150nF 10% 16V X7R CERAMIC SM
43 3 C104,C128,C143 4250033000 1 33pF 10% 50V NPO CERAMIC SM
44 4 C119,C743,C744,C745 4250022400 1 220nF +80/-20% 16V Y5V CERAMIC SM
45 1 C120 4260018700 1 180uF 20% 16V Polymer / Aluminum Low ESR 33mOhm 8mm High
47 2 C136,C122 4051047700 1 470uF, 10V, 20% 10X12.5mm 0.030R@100kHz, Radial
50 2 C150,C148 4233010600 1 10uF 20% 16V TANTALUM SM
51 4 C178,C179,C206,C207 4271022600 1 22uF +80/-20% 10V Y5V Ceramic SM
52 17 C213,C214,C215,C261,C262, 4270010600 1 10uF 20% 10V X5R CERAMIC SM
C263,C679,C680,C681,C682,
C683,C684,C685,C686,C687,
C688,C746
53 3 C489,C491,C493 4240010300 1 10nF +80-20% 50V Y5V CERAMIC SM
54 1 C490 4260010600 1 10uF 20% 16V ALUMINUM SM 5.4mm High
56 6 C559,C560,C561,C564,C567, 4240000300 1 3pF +/-.1pF 50V NPO CERAMIC SM
C570
57 3 C565,C568,C571 4250010A00 1 1pF +/-.1pF 50V NPO CERAMIC SM
58 3 C573,C574,C575 4240005000 1 5pF +/-.5pF 50V NPO CERAMIC SM
59 3 C576,C578,C580 425003R300 1 3.3pF +/-.25% 50V NPO CERAMIC SM
60 3 C577,C579,C581 4240000800 1 8pF +/-.1pF 50V NPO CERAMIC SM
61 6 C583,C584,C585,C586,C587, 4240082000 1 82pF 5% 50V NPO CERAMIC SM
C588
63 8 C711,C712,C713,C714,C715, 4170010300 9 10nF 10% 10V X7R Ceramic SM
C716,C717,C718
64 2 C737,C739 4231068500 1 6.8uF 20% 25V Tantalum SM
65 5 C740,C741,C742,C748, 4240010500 1 1uF +80/-20% 10V Y5V CERAMIC SM
C1127
66 4 C749,C750,C751,C752 4250022000 1 22pF 10% 50V NPO CERAMIC SM
67 3 C755,C756,C761 4170010400 1 100nF 10% 10V X7R Ceramic SM
68 1 C763 4250022400 1 220nF +80/-20% 16V Y5V CERAMIC SM
70 1 D2 5160467800 1 Diode, Zener 1.8V +/-5%, 500mW, SM
71 1 D3 5160468100 1 Diode, Zener 2.4V +/-5%, 500mW, SM
72 15 D6,D10,D11,D12,D13,D14, 5170005400 1 Diode, Schottky, 30V 200mA, SM SOT-23
D15,D16,D17,D18,D19,D20,
D21,D22,D23
73 1 D9 5161038500 1 Diode, Voltage reference 2.5V +/- 75mV, SM
74 1 D24 5150000800 1 Diode, rectifier 50V 3A
75 1 D25 5170000700 1 Diode, Schottky, 40V 3A, SM
76 1 F1 5120000800 1 Fuse resettable 750mA, 13.2V
77 1 H1 7120003000 1 Heatsink, Active, 61.6mm x 81.3mm x 13mm, 12V, Hypro bearing, Black
78 1 JU1 6010007800 1 Header, 2x1, 2mm ctrs., Shrouded, Vertical
79 1 JU2 6140011300 1 Header, 1X4, 2.5mm, Right angle (Floppy Power)
80 1 JU5 6020005500 1 Socket strip 2x35 0.05x.1 .18 High TH
81 1 J4 6140005300 1 Connector, DVI, A/D, R/angle Receptacle, Low Profile, White
82 1 J5 6050001400 1 Connector DB15 Female VGA Blue PIN 9 Recessed
83 1 J7 6070001500 1 DIN Connector Y/C S video w/Full Shielding
84 1 J8 6030001400 1 Jack Phono RCA Rt. Angle Thru-Hole Yellow
85 2 K1,K2 2600001800 4 SPDT Analog Switch, 1 ohm
86 2 L1,L2 5260013200 1 Inductor, Fixed, 1.5uH 20% 9.0A
87 2 L6,L3 5260005700 1 Inductor Fixed SM 3316 3.3uH 20% 5.4A
88 1 L5 5260009800 1 Inductor Fixed 2.2uH 20% 6.1A Wound
89 12 L7,L8,L9,L16,L17,L18,L43, 5260004900 1 Inductor, Fixed 82nH 20% 300mA, Chip
L44,L45,L46,L47,L48
90 3 L10,L12,L14 5260008700 1 Inductor Fixed 68nH 20% 300mA, Chip
91 3 L20,L21,L22 5260002100 1 Inductor, Fixed 1.8uH 10% 50mA, Chip
92 3 L57,L58,L59 5260004800 1 Inductor, Fixed 68nH 20% 300mA, Chip
93 3 L60,L61,L62 5260006700 1 Inductor Fixed 56nH 5% 300mA Tape & Reel
94 1 MAGP1 614NOPN064 CONNECTOR CARD EDGE UNIVERSAL AGP BUS
95 1 MJ4 6050003000 9 DB15 Female slim right angle connector with pin 9 recess
96 1 MJ7 6070001900 1 Connector, MiniDIN, 3 Pin, Shielded, Right Angle
97 2 MK1,MK2 2600002800 9 SPDT Analog Switch, Low Voltage
98 4 MREG1,MREG4,MREG5,MREG6 2480009800 1 Precision Adj. Shunt Regulator, 1.24V, 1% 100mA (SOT-23)
99 1 MU106 2480011000 9 DC-DC Converter, 1.1 to 18Vin, 34Vout, 1.8mA
100 1 MY1 5023270000 1 Crystal 27.000 MHz, Fundamental, 18pF, 30ppm

101 2 Q1,Q2 2020002300 1 Transistor, MOSFET, N. Ch., 60V 250mA
102 2 Q3,Q4 2020007600 1 Transistor, MOSFET, Dual N Ch., 20V 9.4A, .018R, Logic level, Vgs = 12V
103 3 Q5,Q8,Q9 2020008100 1 Transistor, MOSFET, Dual N Ch., 30V 8A, .020R, Logic level, Vgs = 16V
104 1 Q11 2021222200 1 Transistor, NPN, 40V 600mA
105 4 Q12,Q13,Q14,Q15 2020000600 1 Transistor, MOSFET, N Ch., 50V 100mA
106 1 Q19 2020004300 1 Transistor, MOSFET, N Ch., 20V 1.7A, Low RDS On
107 1 REF1 105-942XX-12 SCHEMATIC AGP R300 128MB BGA DVII VGA VO VIP
108 1 REF2 109-942XX-12 PCB AGP R300 128MB BGA DVII VGA VO VIP
109 1 REF3 9110054500 1 ATI LOGO LABEL FOR THE PCB
110 4 REG1,REG4,REG5,REG6 2480010500 5 Precision Adj. Shunt Regulator, 1.24V, 1% 100mA (SOT-23-5)
111 1 REG2 2480012200 1 Voltage Regulator Adjustable LDO 800mA
112 1 REG3 2480004000 1 Voltage Regulator, 150mA, 2.5V, LDO
113 84 RP1,RP2,RP3,RP4,RP5,RP6, 3270004700 1 56R 4-Element Resistor Network Individual SM T&R
RP7,RP8,RP9,RP10,RP11,
RP100,RP101,RP102,RP103,
RP104,RP105,RP106,RP107,
RP108,RP109,RP110,RP132,
RP136,RP137,RP138,RP139,
RP140,RP141,RP142,RP143,
RP144,RP145,RP146,RP147,
RP148,RP149,RP150,RP151,
RP152,RP153,RP154,RP155,
RP156
114 64 RP25,RP26,RP27,RP28,RP29, 3270008100 1 47R 4-Element Resistor Network Individual SM T&R
RP89,RP90,RP111,RP112,
RP113,RP114,RP115,RP116,
RP117,RP118,RP119,RP120,
RP121,RP122,RP123,RP124,
RP125,RP126,RP160,RP161,
RP162,RP163,RP164,RP165,
RP166,RP167,RP168,RP169,
RP170,RP171,RP172,RP173,
RP174,RP175
115 1 RP192 3270004000 1 33R 4-Element Resistor Network Individual SM T&R 0805
116 1 RT1 5110000900 9 NTC Thermistor, 100K, 5%, .10mA
117 17 R1,R2,R3,R4,R5,R6,R8,R10, 3230000000 1 0R 1/16W 5% SM T&R
R17,R820,R895,R934,R935,
R936,R937,R938,R939
118 3 R7,R9,R16 3230082200 1 8.2K 1/16W 5% SM T&R
119 23 R13,R15,R708,R709,R710, 3150000000 1 0 Ohm Jumper
R711,R712,R713,R714,R715,
R806,R808,R809,R810,R811,
R812,R813,R814,R821,R855,
R856,R857,R858
120 1 R18 3230047300 1 47K 1/16W 5% SM T&R
121 43 R19,R333,R334,R335,R336, 3150010300 1 10K 1/16W 5% SM T&R
R337,R338,R339,R340,R341,
R342,R343,R344,R345,R346,
R352,R353,R354,R355,R357,
R358,R359,R360,R831,R833,
R839,R841,R850,R851,R852,
R853,R861,R862,R863,R864,
R865,R866,R867,R868,R869,
R870,R871,R872
122 1 R20 3240332100 1 3.32K 1/16W 1% SM T&R
123 1 R21 3240147100 1 1.47K 1/16W 1% SM T&R
124 1 R22 3230010100 1 100R 1/16W 5% SM T&R
125 2 R43,R23 3230010200 1 1K 1/16W 5% SM T&R
126 1 R24 3240102100 1 1.02K 1/16W 1% SM T&R
127 2 R25,R854 3230018100 1 180R 1/16W 5% SM T&R
128 6 R26,R27,R28,R44,R361, 3210000000 1 0R 1/10W 5% SM T&R (JUMPER)
R362
129 8 R29,R30,R465,R466,R822, 3230033000 1 33R 1/16W 5% SM T&R
R823,R824,R825
130 2 R32,R31 3230047000 1 47R 1/16W 5% SM T&R
131 1 R39 3240169000 1 169R 1/16W 1% SM T&R
132 1 R40 324071R500 1 71.5R 1/16W 1% SM T&R
133 24 R45,R46,R47,R48,R56,R58, 3230000000 1 0R 1/16W 5% SM T&R
R59,R65,R80,R81,R82,R83,
R84,R112,R470,R474,R509,
R800,R803,R921,R943,R947,
R951,R952
134 3 R49,R50,R51 3240075000 1 75.0R 1/16W 1% SM T&R
135 2 R117,R52 3240499000 1 499R 1/16W 1% SM T&R
136 2 R54,R53 3230047200 1 4.7K 1/16W 5% SM T&R
137 1 R55 3240715000 1 715R 1/16W 1% SM T&R
138 1 R57 3230010500 1 1M 1/16W 5% SM T&R
139 1 R63 3240107000 1 107R 1/16W 1% SM T&R
140 3 R66,R77,R90 3240150000 1 150R 1/16W 1% SM T&R
141 2 R142,R68 3220047000 1 47R 1/4W 5% SM T&R
142 4 R69,R140,R144,R145 3240681000 1 681R 1/16W 1% SM T&R
143 4 R70,R141,R146,R147 3240150100 1 1.50K 1/16W 1% SM T&R
144 4 R71,R79,R88,R91 323005R100 1 5.1R 1/16W 5% SM T&R
145 2 R72,R73 3210022A00 1 2.2R 1/10W 5% SM T&R
146 1 R74 3230033300 1 33K 1/16W 5% SM T&R
147 3 R75,R910,R911 3230010400 1 100K 1/16W 5% SM T&R
148 2 R76,R89 324051R100 1 51.1R 1/16W 1% SM T&R
149 1 R78 3240511000 1 511R 1/16W 1% SM T&R
150 2 R92,R85 3230010100 1 100R 1/16W 5% SM T&R
151 1 R87 3250243100 1 2.43K 1/10W 1% SM T&R
152 3 R93,R113,R123 3230010000 1 10R 1/16W 5% SM T&R
153 1 R94 3240825000 1 825R 1/16W 1% SM T&R
154 3 R95,R115,R127 3230015200 1 1.5K 1/16W 5% SM T&R
155 3 R96,R116,R128 3230027300 1 27K 1/16W 5% SM T&R
156 1 R97 3240140100 1 1.40K 1/16W 1% SM T&R
157 1 R98 3240110100 1 1.10K 1/16W 1% SM T&R
158 3 R99,R118,R132 3230010300 1 10K 1/16W 5% SM T&R
159 3 R100,R120,R133 3230051300 1 51K 1/16W 5% SM T&R
160 3 R101,R121,R134 3230030200 1 3K 1/16W 5% SM T&R

161 3 R102,R122,R135 3230015300 1 15K 1/16W 5% SM T&R
162 1 R114 3240133100 1 1.33K 1/16W 1% SM T&R
163 1 R124 3240499100 1 4.99K 1/16W 1% SM T&R
164 1 R126 3240562000 1 562R 1/16W 1% SM T&R
165 1 R130 3240133100 1 1.33K 1/16W 1% SM T&R
166 1 R131 3240200100 1 2K 1/16W 1% SM T&R
167 4 R137,R138,R773,R774 316075R000 1 75.0R 1/16W 1% SM T&R
168 2 R143,R139 3220018000 1 18R 1/4W 5% SM T&R
169 4 R164,R165,R167,R168 3150047200 1 4.7K 1/16W 5% SM T&R
170 33R166,R173,R174,R175,R176, 3150047000 1 47R 1/16W 5% SM T&R
R177,R178,R179,R180,R181,
R182,R183,R184,R185,R186,
R187,R188,R227,R228,R229,
R230,R231,R232,R233,R234,
R235,R236,R237,R238,R239,
R240,R241,R242
171 102 R169,R170,R171,R172,R189, 3150056000 1 56R 1/16W 5% SM T&R
R190,R191,R192,R193,R194,
R195,R196,R197,R198,R199,
R200,R201,R202,R203,R204,
R223,R224,R225,R226,R243,
R244,R245,R246,R247,R248,
R249,R250,R251,R252,R253,
R254,R255,R256,R257,R258,
R718,R719,R720,R721,R722,
R723,R724,R725,R726,R727,
R728,R729,R730,R731,R732,
R733,R734,R735,R736,R737,
R738,R739,R740,R741,R742,
R743,R744,R745,R746,R747,
R748,R749,R775,R776,R777,
R778,R779,R780,R781,R782,
R783,R784,R785,R786,R787,
R788,R789,R790,R826,R827,
R828,R829,R830,R832,R834,
R835,R836,R837,R838,R840,
R859,R860
172 32 R207,R208,R209,R210,R211, 3150047000 1 47R 1/16W 5% SM T&R
R212,R213,R214,R215,R216,
R217,R218,R219,R220,R221,
R222,R261,R262,R263,R264,
R265,R266,R267,R268,R269,
R270,R271,R272,R273,R274,
R275,R276
173 16 R277,R278,R279,R280,R281, 3160499100 1 4.99K 1/16W 1% SM T&R
R282,R283,R284,R285,R286,
R287,R288,R289,R290,R291,
R292
174 8 R347,R348,R349,R350,R351, 3230010300 1 10K 1/16W 5% SM T&R
R874,R877,R909
175 12 R363,R891,R892,R893,R894, 3240100300 1 100K 1/16W 1% SM T&R
R896,R897,R898,R899,R900,
R901,R902
176 2 R904,R364 3240100300 1 100K 1/16W 1% SM T&R
177 1 R365 3230010300 1 10K 1/16W 5% SM T&R
178 1 R366 3230027100 1 270R 1/16W 5% SM T&R
179 1 R367 3210000000 1 0R 1/10W 5% SM T&R (JUMPER)
180 1 R368 3240511100 1 5.11K 1/16W 1% SM T&R
181 8 R451,R453,R455,R456,R794, 3230033100 1 330R 1/16W 5% SM T&R
R795,R796,R797
182 1 R457 3230020300 1 20K 1/16W 5% SM T&R
183 1 R458 3230010400 1 100K 1/16W 5% SM T&R
184 8 R459,R460,R461,R462,R469, 3210000000 1 0R 1/10W 5% SM T&R (JUMPER)
R471,R472,R473
185 4 R463,R464,R480,R482 3230068200 1 6.8K 1/16W 5% SM T&R
186 4 R467,R468,R479,R481 3230047200 1 4.7K 1/16W 5% SM T&R
187 4 R504,R606,R608,R878 3210000000 1 0R 1/10W 5% SM T&R (JUMPER)
188 1 R513 3230033100 1 330R 1/16W 5% SM T&R
189 2 R517,R763 3230000000 1 0R 1/16W 5% SM T&R
190 1 R768 3240243200 1 24.3K 1/16W 1% SM T&R
191 1 R769 3240100200 1 10K 1/16W 1% SM T&R
192 6 R791,R792,R793,R912,R913, 3240075000 1 75.0R 1/16W 1% SM T&R
R914
193 2 R799,R802 3230051000 1 51R 1/16W 5% SM T&R
194 37 R815,R816,R873,R879,R880, 3150000000 1 0 Ohm Jumper
R881,R882,R883,R884,R885,
R886,R887,R888,R889,R890,
R905,R906,R907,R908,R915,
R916,R917,R918,R919,R920,
R922,R923,R924,R925,R926,
R927,R928,R929,R930,R931,
R932,R933
195 1 R818 3230000000 1 0R 1/16W 5% SM T&R
196 1 R875 3230010200 1 1K 1/16W 5% SM T&R
197 1 R876 3230018200 1 1.8K 1/16W 5% SM T&R
198 1 R903 3230000000 1 0R 1/16W 5% SM T&R
199 1 R946 3230022100 1 220R 1/16W 5% SM T&R
200 1 R954 3230010300 1 10K 1/16W 5% SM T&R
201 1 R1547 3160100300 1 100K 1/16W 1% SM T&R
202 1 R1548 3160100100 1 1.0K 1/16W 1% SM T&R
203 1 R1550 3160499100 1 4.99K 1/16W 1% SM T&R
204 1 R1551 3230010400 1 100K 1/16W 5% SM T&R
205 1 R1552 3230056000 1 56R 1/16W 5% SM T&R
206 1 SW1 5030003000 1 Slide Switch, SPST, 2 position
207 10 TP1,TP2,TP3,TP4,TP7,TP27, 620NOPN000 TEST POINT PCB HOLE 0.035 in.
TP28,TP33,TP34,TP35
208 1 U2 2430002100 1 Quad 2 Input And Gate
209 1 U3 2430000300 1 Quad Exclusive-OR CMOS Gate, 2 Input, TTL compatible
210 1 U3 2430000300 1 Quad Exclusive-OR CMOS Gate, 2 Input, TTL compatible
211 1 U42 215R8AAGA11 1117 ball 40x40mm, 1mm pitch BGA, 39x39 rows, 7 rows deep and with 15x15 cnter
212 1 U43 2480019600 1 Dual Synchronous PWM Controller, Programmable
213 3 U44,U48,U50 2480018900 1 Synchronous PWM Controller, 400KHz Reference Voltage 0.8V
214 3 U45,U49,U51 2480020900 1 Buck & Synchronous-Rectifier PWM Controller
215 8 U52,U53,U54,U55,U56,U57, 235C284433 1 SGRAM DDR 128Mbit 1MX32X4 Bank 300MHz w/DLL 2.5V VDD/VDDQ
U58,U59
216 1 U76 2480017000 1 Fan Controller
217 1 U80 2280001900 1 Serial Flash 512Kbit 64Kx8, SPI interface, 20MHz, 2.7V-3.6V.
218 1 U81 2280000200 6 SERIAL FLASH 1MBit 4 PIN SPI INTERFACE 3V 8-PIN SOIC
219 4 U89,U90,U91,U92 2430002900 1 Single Gate 2 Input AND
220 1 U93 2430001200 1 Single Gate Inverter, High Speed (Tiny Logic)
221 1 U95 2480000200 9 Operational Amplifier Low Power Single Power Supply Quad
222 1 U96 2710000800 1 Wideband Quad 2-Channel Video Mux/Demux

223 1 U99 2430003900 9 Quad 2 I/P NOR Gate
224 1 U103 2431007400 1 Dual Flip-flop, D-Type with Preset&Clear
225 1 U106 2480023600 9 Comparator, 7ns, Rail-to-rail Output, Low voltage
226 1 U107 200NOPN052 IC- Comparator MAXIM MAX9203EKA-T
227 1 Y1 5016270000 1 Crystal Oscillator 27.00MHz, 50ppm, 3.3V, HCMOS/TTL

Ati Agp r300 128mb Bga Dvii Vga Vo Rev 11 SCH

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Ati Agp r300 128mb Bga Dvii Vga Vo Rev 11 SCH

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<Core Design> 8 7 6 5 4 3 2 1

Title Schematic No. Date:

7 12 08/19/02 PRODUCTION RELEASE IV

8 20 08/24/02 PRODUCTION RELEASE V

9 30A 09/06/02 PROTOTYPE IV

10 30B 09/18/02 PROTOTYPE V

11 30 09/26/02 PRODUCTION RELEASE VI

Title Schematic No. Date:

1 00B PROTOTYPE I.i.i.

2 00C 06/28/2002 PROTOTYPE I.i.i.I

PRODUCTION RELEASE III

MEMORY CHANNEL A B MEMORY CHANNEL C D

MEMORY TERMINATIONS A B MEMORY TERMINATIONS C D

BIOS ROMCS# ROM

AD31..0 CBE3..0 CPUCLK STOP# PAR REQ#

AGP BUS REFERENCE RESTRICTION ATI Technologies Inc.

2X/4X/8X AGP BUS +12V_BUS +5V_BUS +3.3V_BUS

NOTE: THIS IS A DRAWING. THESE

UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X) *

ATI Technologies Inc.

Video Capture & Test

TMDS / Flat Panel

TVOut, DVOut & ROM

10pF Ra8 C42 C43 C44 100nF

CLOCK SOURCE SELECTION

<Core Design> ATI Technologies Inc.

ATI Technologies Inc.

Layout Guide Lines for switching regulators

C77 1nf R71 5.1R 2 +VDDC

1.25V 0R DNI DNI

BOOT 6 *** ** ** ISL6522CB 1.25V 576R 1% 1.02K 1% DNI

+12V_BUS MVDDC Switching Regulator for

1% Layout Guide Lines for VDD switching regulator

IRU3037A 2.55K 1.21K

IRU3037A 1.33K 499R

Part INSTALL DO NOT INSTALL

IRU3037 Alternative1 Cd1, Rd4, Alternative2

ISL6522CB Alternative2 Alternative1

Title AGP R300 128MB BGA DVII VGA VO

C DNI R132 10K

Part INSTALL DO NOT INSTALL

1.50K 1.50K <Core Design>

Title AGP R300 128MB BGA DVII VGA VO

MDA29 DQA28 QSA2 QSA3 MDB30 DQB29 QSB3 QSB4

1 Commerce Valley Drive East

MDC27 DQC26 QSC0 QSC1 MDD29 DQD28 QSD2 QSD3

MDC42 V5 MDD44 AT9

TC7SZ08FU TC7SZ08FU 10 1.8V (DDR)

ATI Technologies Inc.

1 Commerce Valley Drive East

MDA0 M_MDA[63..0] MDB0 M_MDB[63..0]

ATI Technologies Inc.

ATI Technologies Inc.

Ri1 R344 10K INSTALL DEVICE ID

Rj1 Rk1 Rj2 Rk2 Rj3 Rk3 Rj4 Rk4 ROMIDCFG[3:0]

MEMORY TYPE STRAPS

MEMORY TYPE Rh6 Rh7 Rh8 Rh9 ATI Technologies Inc.

SPEED CONTROLED FAN

DNI R892 Fan_VDD

100K R893 100K DNI

ALTERNATIVE PART :M25P05(512Kbit) ALTERNATIVE PART : AT45DB011

ATI Technologies Inc.

Title AGP R300 128MB BGA DVII VGA VO

BOOT 6 * ** ISL6522CB 1.25V 576R 1% 1.02K 1% DNI