ISSCC 2017 / SESSION 2 / POWER AMPLIFIERS / 2.
2.2 A Fully Integrated Reconfigurable Wideband
Envelope-Tracking SoC for High-Bandwidth WLAN
Applications in a 28nm CMOS Technology
Debopriyo Chowdhury, Sraavan R. Mundlapudi, Ali Afsahi
Broadcom, San Diego, CA
Envelope tracking (ET) has become popular for enhancing battery life in mobile
communication devices that employ high peak-to-average power ratio (PAPR)
signals. Most of the published ET systems have focused either on narrow-
bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for
higher bandwidths and data-rates increases, so does the need for wideband ET
solutions. Furthermore, to support modulations with different PAPR and transmit
powers, the PA will likely require seamless switching between a continuous ET
mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO).
Hence, fast reconfigurability is needed, which most published ET systems lack.
This paper describes a fully integrated, reconfigurable WLAN ET system with
digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The
ET modulator directly interfaces with a battery (Vbat) and is fully integrated within
a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.
Figure 2.2.1 shows the hybrid ET modulator [1], where a fast linear regulator (LR)
operates in parallel with an efficient switching regulator (SWR), with the current
hand-off controlled by a hysteresis comparator (HC). Simulations show that for
high bandwidth applications, a fast, low-delay HC is required. However, traditional
HCs use voltage sensing across a series resistor [1], which increases the ET loop
delay and output impedance. We employ a fully current-mode HC that employs
low-impedance nodes and low delay (Fig. 2.2.1). A scaled replica of the linear
regulator sourcing or sinking current (created by devices Mr1–Mr8) is compared
with programmable threshold currents (Ithrsh_src/Ithrsh_sink) and an up or down signal
is generated using an SR latch to create hysteresis. This fast comparator enables
the switching regulator to source current in sync with the PA transient
requirements while decreasing current ripple.
The modulator can interface directly to Vbat (up to 5.5V) without the aid of an
additional voltage regulator. Meanwhile, since I/O devices can handle a maximum
voltage of only 1.8V in a standard 28nm technology, the SWR employs custom
laterally diffused MOS (LDMOS) transistors with extended drain to handle high
Vds. The maximum Vgs is still limited to 1.8V, which required the implementation
of high-side drive circuits (Fig. 2.2.1). The output of the hysteresis comparator
(0-to-1.8V) is level-shifted to swing from (Vbat – 1.8V) to Vbat for the gate drive
of the PMOS (MP1 in Fig. 2.2.1). A low-output-impedance Class-AB op-amp
generates the (Vbat – 1.8V) sliding voltage reference. Since this voltage serves
as an artificial ground for the inverters connected to the PMOS gate, very low
impedance is required to avoid disturbing the PWM signal and any consequent
distortion in the envelope waveform.
The high frequency content of the envelope signal is handled primarily by the LR.
The LR must have a 3dB bandwidth covering at least 3× to 4× of the signal
bandwidth as well as a high slew rate and low total harmonic distortion. These
requirements are in direct conflict with the Vbat interface requirement, which
necessitates the use of LDMOS devices that have longer channel lengths. In order
to circumvent this issue, we use a thin-oxide 28nm core device with a minimum
channel length as the output transistor (MPL1/MNL1, Fig. 2.2.2) in cascode with
an LDMOS transistor (MPL2/MNL2, Fig. 2.2.2). This extends the dominant pole
of the LR and helps achieve a wide large-signal bandwidth. The gate of the p-side
LDMOS (MPL2) is biased using a sliding voltage (Vbat – 1.8V) to ensure that the
Vds across the core device never exceeds its reliability limits. A current mirror-
based architecture is employed in the first stage to avoid unwanted
high-impedance nodes. A floating voltage source generates the Class-AB bias
needed for the output stage of the linear regulator [3], which needs to source and
sink dynamic currents.
In addition to high PAPR and higher-order modulation schemes, WLAN systems
may transmit low-PAPR BPSK or QPSK modulated signals at high power levels.
Unfortunately, low PAPR at higher power levels reduces ET current savings and
may also lower the maximum transmit power due to spectral regrowth arising
from drain modulation. Although switching to a fixed-supply mode is preferred
for such low-PAPR signals, adding a separate PA LDO adds area and current
34 • 2017 IEEE International Solid-State Circuits Conference
overhead. We describe an ET system in this paper that can be reconfigured as a
PA LDO dynamically with a low settling time. Based on a control bit setting, the
SWR is turned off when the LDO mode is enabled, and the LR is configured to
output a fixed 3.4V. A large off-chip capacitor (CL, Fig. 2.2.2) is switched in at
the ET output only when the LDO mode is enabled. However, because CL is
typically large in value (e.g., 1μF), simply switching in a capacitor at the ET output
increases the transition time significantly. To avoid this, we introduce a pre-
charging technique where the capacitor CL is kept pre-charged to Vbat through a
small transistor PC1 (PC2 is off). In the LDO mode transmit cycle, PC1 is turned
off and PC2 connects the pre-charged CL to the ET output, resulting in fast
transition between the modes.
The wideband ET is integrated with the digital baseband circuitry that performs
envelope generation and conditioning (Fig. 2.2.3). A Coordinate Rotation Digital
Computer (CORDIC) processor generates the envelope signals while a
programmable farrow-based fractional-delay filter aligns the envelope and RF
paths. A look-up table (LUT1) performs envelope shaping (detroughing, scaling,
etc.). A second LUT adjusts the envelope magnitude based on power control and
digital pre-distortion (DPD). The digital envelope is fed to a 12b D/A converter,
and, finally, to the analog modulator. The ET system is integrated on the same
die with a complete 802.11n WLAN transceiver.
The chip is fabricated in 28nm CMOS. The ET section measures 0.6mm2 (Fig.
2.2.7). While the digital baseband is designed for a 20MHz operation, an analog-
only version of the above SoC has been fabricated to allow measurements up to
40MHz. With a resistor load, the modulator measures peak efficiency of 94% and
an average efficiency of 75% (with the WLAN envelope) from a 3.6V supply. Note
that this design used only one external inductor, unlike other ET designs [2–4].
The ET SoC is measured with a 2GHz WiFi PA using a 20MHz 802.11n 64-QAM
72Mb/s OFDM WLAN signal and provides an efficiency enhancement of 28% (PA
average drain efficiency improves from 29% to 38%) at 19dBm (Psat=26dBm),
while meeting –33dB EVM and –45dBr spectral mask requirements with on-chip
DPD (Fig. 2.2.4). When transmitting a BPSK-modulated low-PAPR MCS0 signal,
the modulator is switched dynamically into the LDO mode and improves spectral-
compliant transmission power to 21dBm, proving the effectiveness of the fast
reconfigurable design. The analog ET section is also measured with an external
5GHz WiFi PA using a 40MHz 802.11n 64-QAM 150Mb/s WLAN signal, providing
an efficiency enhancement of 34% (PA average drain efficiency improves from
22 to 30%) at 19dBm with an EVM of –34dB (with DPD) (Fig. 2.2.5). This shows
the effectiveness of the wideband design techniques used in what is a state-of-
the-art reconfigurable WLAN ET SoC solution for 20MHz and 40MHz modes (Fig.
2.2.6).
Acknowledgements:
The authors would like to thank Rethnakaran Pulikkoonattu, Chuan Wang, Stephen
Au, Mike DeGennaro, Michael Irvin, Akira Ito, Navid Lashkarian, Oliver Hsu,
Andrew Adams, Keith Carter and Arya Behzad for their help.
References:
[1] F. Wang, et al., “A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS
Envelope-Tracking OFDM Power Amplifier”, IEEE JSSC, vol. 42, no 6., pp. 1271-
1281, June 2007.
[2] P. Riehl, et al., “An AC-Coupled Hybrid Envelope Modulator for HSUPA
Transmitters with 80% Modulator Efficiency”, ISSCC, pp. 364-365, Feb. 2013.
[3] M. Hassan, et al., “A CMOS Dual-Switching Power-Supply Modulator with 8%
efficiency improvement for 20MHz LTE Envelope Tracking RF Power Amplifiers”,
ISSCC, pp. 366-367, Feb. 2013.
[4] J.-S. Paek, et al., “An RF-PA Supply Modulator Achieving 83% Efficiency and
-136dBm/Hz Noise for LTE-40MHz and GSM 35dBm Applications.”, ISSCC, pp.
354-355, Feb. 2016.
[5] K. Moon, et al., “Highly Linear Envelope Tracking Power Amplifier with Simple
Correction Circuit”, IEEE RFIC, pp. 127-130, June 2015.
978-1-5090-3758-2/17/$31.00 ©2017 IEEE
 ISSCC 2017 / February 6, 2017 / 2:00 PM

Figure 2.2.1: Block diagram of a hybrid ET modulator with current mode Figure 2.2.2: Wideband linear regulator that can be reconfigured to operate as
hysteretic comparator. an LDO.

Figure 2.2.3: Block diagram of the WLAN transmitter with integrated envelope Figure 2.2.4: Measured EVM and spectrum (at 19dBm) with WLAN SoC at
tracking. 2442MHz for 20MHz 802.11n in fixed 3.4V (LDO) and ET Modes.

Figure 2.2.5: Measured EVM and PA current consumption (including ET) at

5500MHz in fixed 3.4V (LDO) and ET modes for 40MHz 802.11n WLAN and
measured spectrum at 19dBm Pout for 40MHz WLAN in ET mode. Figure 2.2.6: Performance comparison to published work.

DIGEST OF TECHNICAL PAPERS • 35

 ISSCC 2017 PAPER CONTINUATIONS

Figure 2.2.7: Die micrograph (the ET section is marked).

• 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE