Controlled Slew Rate Enhancement Circuit for
Error Amplifier in High Frequency DC-DC
Converters
Chunming Zhang, and Zhibiao Shao, Senior Member, IEEE
School of Electronic and Information Engineering, Xi’an Jiaotong University
Xi’an Shanxi, P. R. CHINA
e-mail: zhangcm@ mail.xjtu.edu.cn
Abstract—Modern power applications are driving the demand
for power supply systems with fast transient response. A novel
controlled slew-rate enhancement (CSRE) circuit for error
amplifier in high frequency DC-DC converters is proposed to
improve transient responds of DC-DC converters under large
load current changes. The CSRE circuit with embedded
current-detection is connected in parallel with the error amplifier.
By detecting the maximum difference current corresponding to
the maximum derivation of the output voltage and optimizing
sizes of the CSRE circuit, the CSRE circuit can be controlled
properly so that the system stability can be guaranteed in various
operating conditions. When the proposed circuits was employed
in 100MHz buck DC-DC converters implemented in SMIC 0.18
µm CMOS process, the simulation results of transient responses
show that the CSRE circuit improves the average 1% settling time
by 20 times and overshoot by 16 times, while the total quiescent
power is only increased by less than 7.1
I. INTRODUCTION
T HE pulse-width-modulated (PWM) DC-DC converter is
one of the popular power converters widely used in power
management with the rapid development of
microprocessors and digital signal processors (DSPs). Power
converters are now subjected to large load and supply-voltage
variations, which require converters can supply with low output
voltage, high output current, and the main challenge of fast
transient response [1]. The transient response time under large
load change consists of two phases, the initial settling phase and
the slew phase [2]. The settling phase is determined by the
gain-bandwidth product of the system. Achieving high
frequency operation provides the opportunity to design high
bandwidth loop compensation. High slew rate can increases the
transient response. However, the efficiency is sacrificed. How
to design error amplifier (EA) for accurate, fast response, and
robust stable operation of the system under a wide range
operating conditions is a big challenge [3].
Different techniques have been used to improve the transient
responses of DC-DC converters in slew phase. More
significantly, the EAs have two values of transconductance [4].
But the slewing time is not controlled properly, which may
cause oscillation. For this problem, the slew-rate enhancement
The National Natural Science Foundation of China under the grant number of
60206003
978-1-4244-2342-2/08/$25.00 ©2008 IEEE.
(SRE) circuit has been developed, which is connected in
parallel to the core amplifier and serves as a plug-in module [5].
But this circuit is not controlled by the output voltage variation.
Fast transient controller based on one-shot circuit is proposed in
[6], but, there exist larger loading capacitances. This paper
proposes a novel controlled slew-rate enhancement (CSRE)
circuit. In the proposed circuit, the sensing circuit detects the
changes of the current signal at the active load of EA in order to
avoid increasing the loading capacitance of EA. The driving
circuit only supplies the dynamic transient current to the output
of the EA in transient phase to improve transient response of
DC-DC converter. The controller circuit controls the driver by
detecting the maximum difference current corresponding to
maximum derivation of the output voltage when large load
current change. The SCRE circuit guarantees the fast transient
of DC-DC converter with no excessive power consumption
during normal operation, and robust stability achieved under a
wide range of operating conditions.
II. TRANSIENT RESPONSE UNDER LARGE LOAD CHANGE
Basically, the slew rate is proportional to the biased current
of EA. Thus, the biased current should be increased for fast
transient response. However, it will directly violate the
requirement of low quiescent current. To solve this
contradiction, the novel CSRE circuit is embedded in parallel
with the error amplifier. The CSRE circuit only provides the
dynamic current during transient, and is completely turned off
in the static state. Consequently the transient response is
enhanced, while the quiescent current of EA can be minimized.
The waveforms of the transient response with and without
CSRE circuit when load current I load has a positive and sudden
load current change ΔI load are shown in Fig. 1(a). It is noted that
the quiescent current is same for the EA with and without
CSRE circuit and state-space averaging model is used to
simplify the analysis of transient response. Assuming the
equivalent series resistance and the equivalent series
inductance of the output capacitor C are ignored for simple
analysis [7]. For the DC-DC converter without CSRE circuit,
the insufficient charge between the inductor L current I L and
I load from time t0 to t3 is supplied by the output capacitor C.
The output voltage Vo steps downward from its steady-state
value Vo1 and I L increases from its initial value I load 1 . The
transient response consists of two phases, the initial settling
phase in a quasi-linear fashion from time t0 to t2 and the slew
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phase in a grossly nonlinear fashion from time t2 to t3 . In the
settling phase, current I L increases with the slope dI AF dt which
is proportional to the transconductance of the EA. In the slew
phase, current I L increases with the slope dI FC dt which is
proportional to the biased current of the EA. It will take a long
time to achieve time t3 when I L is equal to I load due to the small
biased EA. At time t3 , output capacitor C stops supplying
current to the load and Vo stops dropping. The area of
multirange S AFCE in Fig. 1(a) represents the charge supplied by
capacitor C, and the value of maximum voltage drop can be
calculated as [6]:
1 t3 S AFCE
C ∫t0
Vdrop = ( I load − I L )dt =
C
Because of long time t3 , the maximum voltage drop of Vo is a
bigger value. After time t3 , Vo steps upwards. It operates in
slew phase before time t4 , and then operates in settling phase
until Vo achieves a new steady-state value Vo 2 . The error in the
final value Vo 2 is inversely proportional to the dc gain of the
loop gain. Thus high performances DC-DC converter require
the EA should have high bandwidth, high slew rate, and high dc
gain. For the DC-DC converter with CSRE circuit proposed in
this paper, the transient response consists of three phase. The
initial phase is settling phase with a slew slope dI AB dt from
time t0 to t1 . At time t1 , the CSRE circuit is triggered, and then
the second phase is settling phase with a fast slope dI BG dt from
t1 to t′2 . The last phase is slew phase with high slew rate from
time t′2 to t′3 . The CSRE circuit is controlled to turn off from the
EA when the value of I L is slightly larger than that of the load
current for robust stability and smaller voltage ripple. It is
obvious that the time t′3 is smaller than the time t3 due to the
Fig. 1 Transient response with and without CSRE circuit (a) under positive load
current change and (b) under negative load current change.
larger transconductance and slew rate of error amplifier from
time t1 to t′3 . Moreover, the value of maximum voltage drop can
be calculated as:
1 t3' S ABGDE
C ∫t0
Vdrop
'
= ( I load − I L )dt = (2)
C
Because the area of S ABGDE is smaller than that of S AFCE , the value
of Vdrop
'
is smaller than that of Vdrop . Even though the CSRE
circuit is turned off after time t′3 , it will take a smaller time to
achieve the steady-state value Vo 2 due to smaller voltage drop.
Similar to the Fig. 2(a), transient signal waveforms are depicted
in Fig. 2 (b) in case of negative and sudden load current change.
(1) III. DESIGN FOR CSRE CIRCUIT
Fig. 2 shows the conceptual block diagram of the EA with
CSRE circuit. The CSRE circuit consists of sensing, controlling,
and driving circuits. The sensing circuit detects the changes of
the current signal at the active load of the EA so that the sensing
circuit does not increase the loading of EA. The controlling
circuit controls the driver by detecting the maximal difference
current corresponding to the maximum drop of the output
voltage under large load current change. The driving circuit
only supplies the dynamic transient current to the output of the
EA, and is completely turned off in the static state.
The circuit diagram of the CSRE circuit is depicted in Fig. 3.
In this novel topology CSRE circuit, transistors M a1 and M a 2
represent the active load of the EA, transistors M d 1 – M d 4
construct the sensing circuit, transistors M d 5 – M d 6 , M P1 , and
M N 1 form the driving circuit, and transistors M c1 – M c17
contribute to controlling circuit. In the static state, transistors
M P1 , M N 1 , M c12 , and M c13 are off. When load current I load has a
sudden and positive (or negative) load current change
ΔI load ( ΔI load
′ ) as shown in Fig. 1, the output voltage Vo steps
downward (upward) from its steady-state value Vo1 . For
VL ≤ V fb ≤ Vo1 ( Vo1 ≤ V fb ≤ VH ), the current I d + through active load
M a 2 is less than IVL which is the current when V fb is equal to
VL ( the current I d − through active load M a1 is less than IVH
which is the current when V fb is equal to VH ). Consequently,
current I P ( I N ) can be derived as:
I P = b1 I d + ≤ b1 IVL ; I N = b2 I d − ≤ b2 IVH (3)
Transistors M d 5 ( M d 6 ) and biased current I bias1 ( I bias1 ) are
designed such that transistors operate in the boundary
saturation region, and the biased current is designed as:
b3 I bias1 = b1 IVL ; b4 I bias 2 = b2 IVH (4)
As a result, M d 5 ( M d 6 ) operates in triode region such that the
voltage at node N1 (N2) is pulled up (down) to Vdd (gnd). Thus
driver transistors M P1 and M N 1 are off. For Vdrop ≤ V fb ≤ VL
( VH ≤ V fb ≤ Vrise ), current I P ( I N ) is given by:
Fig. 2 The conceptual block diagram of the error amplifier with CSRE circuit
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 ⎧ I P = b1I d + > b1IVL = b3 I bias1 = I1 with the transconductance g mfc can be calculated as:
⎨ (5)
⎩ I N = b2 I d − > b2 IVH = b4 I bias 2 = I 2 ⎧ 2Cload (Vdrop1 − VL ) Fv ( jw) ( R f 1 + R f 2 )
The voltage at node N1 (N2) decreases (increases) and causes ⎪tc1 =
⎪ g mfc ((Vdrop1 + VL ) R f 2
⎨ (11)
driver transistor M P1 ( M N 1 ) to be turned on. Consequently, a ⎪t ′ = 2Cload (Vrise1 − VH ) Fv ( jw) ( R f 1 + R f 2 )

larger dynamic current is supplied to charge (discharge) the ⎪ c1 g ((Vrise1 + VH ) R f 2

⎩ mfc

compensation capacitor CZ and load capacitance of EA. For Where Fv ( jw) is the magnitude of voltage feedback
V fb ≤ Vdrop ( V fb ≥ Vrise ), the current I c+ ( I c− ) through active diode
compensation transfer function of the feedback controller in
transistor M c 4 ( M c 3 ) is more than I drop ( I rise ) which is the current slew rate enhancement model. In the latter phase, the capacitor
when V fb is equal to Vdrop ( Vrise ). Thus, current I c1 ( I c 2 ) is given Cload is charged (discharged) with the slew rate SR for the time
I c1 = b6 I c+ ≥ b6 I drop ; I c 2 = b5 I c− ≥ b5 I rise (6) period of tc 2 ( t′c 2 ) which is calculated as:
Transistor M c16 ( M c14 ) and biased current I L ( I H ) are designed ⎧ (Vdrop − Vdrop1 ) Fv ( jw)
such that transistors operate in the saturation region when V fb is ⎪⎪tc 2 =
SR
⎨ (12)
equal to Vdrop ( Vrise ). Therefore, the bias current I L ( I H ) is ⎪ t′ = (Vrise − Vrise1 ) Fv ( jw)
⎪⎩ c 2 SR
b10 I L = b6 I drop ; b9 I H = b5 I rise (7)
As a result, a net current starts to flow through transistor M c10 The maximum value of the size of driver transistors M P1 and
( M c11 ). The current I c 3 ( I c 4 ) through transistor M c13 ( M c12 ) is M N 1 can be found when the response time tresp ,P ( tresp , N ) is set to

⎧ I c 3 = b8 ( I c1 − b10 I L ) = b8 (b6 I c+ − b10 I L ) = 0 V fb > Vdrop 10% of the time tc1 + tc 2 ( tc′1 + tc′2 ) of the SRE circuit embedded as
⎪ Ic3 > 0 V fb ≤ Vdrop shown in [5] with the assumption that C p1 ( C p 2 ) is
⎪
⎨ (8) 2 2
I
⎪ c4 = b7 ( I c2 − b 9 H ) = b7 (b5 I c − − b9 I H ) = 0
I V fb < Vrise approximately expressed as C p1 = (WL) MP1 Cox ( C p 2 = (WL) MN 1 Cox ).
⎪⎩ Ic 4 > 0 V fb ≥ Vrise 3 3

And the voltage at node N1 (N2) increase (decrease) which
cause transistor M P1 ( M N 1 ) be turned off.
It is necessary to optimize the size of driver transistors M P1
and M N 1 according to the slew rate, slew time, and response
time of SRE circuit. For a given slew rate SR and an equivalent
loading capacitor Cload which consists of CL and CZ with the
assumption that both M P1 and M N 1 are in saturation regions
with constant dynamic current during the positive and negative
sudden load current change. It can be calculated that the lower
bounds of the size of M P1 and M N 1 are given by:
⎧W 2SR ⋅ Cload
⎪( L ) LOW ,M P1 = μ p Cox (Vdd − VOV ,M − Vth ,M ) 2
⎪
⎨
d4 P1
(9)
W
⎪ ( ) LOW ,M N 1 = 2 SR ⋅ C load
⎪⎩ L μ N Cox (Vdd − VOV ,M d 2 − Vth ,M N 1 ) 2
The response time of SRE circuit is the time required to turn
on the driver transistors M P1 and M N 1 when V fb steps
downward (upward) from voltage VL ( VH ). In this period time,
current I P ( I N ) is more than b1 IVL ( b2 IVH ) which can be used to
discharge (charge) the parasitic capacitance C p1 ( C p 2 ) at node
N1 (N2) from the voltage of Vdd − VOV ,M ( VOV ,M 6 ) to Vdd − Vth ,M d5
Thus, the upper bounds of the size of M P1 and M N 1 are given
⎧W 3g mb1ΔVdrop
⎪( L )UP ,M P1 = 40Cox ( Vth,M − VOV ,M ) ⋅ (tc1 + tc 2 )
⎪
⎨
P1 d5
(13)
W
⎪ ( )UP ,M N 1 = 3 g m b2 Δ Vrise
⋅ (tc′1 + tc′2 )
⎪⎩ L 40Cox (Vth,M N 1 − VOV ,M d 6 )
IV. IMPLEMENTATION AND SIMULATION RESULTS
To verify the functionality of the proposed EA with the
CSRE circuit and compare its performance with that of without
the CSRE circuit, the buck DC-DC converters with EA with
and without the CSRE circuit were designed with L = 80nH and
C = 20nF at its switching frequency of 100MHz in SMIC
0.18µm CMOS process with Vdd = 3.3V , Vo = 1.8V . The circuit
implementation of EA with the CSRE circuit was shown in Fig.
4. EA was constructed by ac boosting compensation (ACBC) [8]
and enhancement current-mode capacitor multiplier (ECMCM)
[9] for wideband of DC-DC converters. In this circuit, ECMCM
realized by transistors M 309 – M 311 increases the capacitance of
compensation capacitor, and an ac amplifier implemented by
transistors M a 00 – M a 08 is added to the main path, which yields a
P1

( Vth,M ) in order to turn on M P1 ( M N 1 ). Therefore, the response

N1

time tresp ,P and tresp ,N are given by referenced to Fig. 1 for the
first-order approximation.
2C p1 ( Vth ,M P1 − VOV ,M d 5 )
tresp ,P =
g mb1ΔVresp ,drop
(10)
2C p 2 (Vth ,M N 1 − VOV ,M d 6 )
tresp , N =
g mb2 ΔVresp ,rise
Where g m is the transconductance of the input differential pair
of EA, VOV is the overdrive voltage of MOS transistor, ΔVresp ,drop
( ΔVresp ,rise ) is the voltage drop (rise) during the time tresp ,P ( tresp ,N )
depicted in Fig. 1, which can be derived as shown in [7].
The transient response consists of two phases when the
CSRE circuit is triggered, the initial phase is settling phase and
the latter phase is slewing phase. In the initial phase, the output
voltage drop (rise) is Vdrop1 ( Vrise1 ).the time period of tc1 ( t′c1 ) Fig. 3 The circuit diagram of CSRE circuit.

1854
pole-zero pair in the first nondominant pole to extend the
bandwidth. The implementation of the CSRE circuit has been
described in section III. It is critical to optimizing the size of
driver transistors M P1 and M N 1 for high performances of the
fast transient response and robust stability, which should be set
according to (9) and (13).
Fig. 5 shows the simulation performances of the system with
and without the CSRE circuit under large load current changes
to evaluate the performance improved. The load current is
pulsed from 100mA to 300mA and back down to 100mA with rise
and fall times of less than 1nS . Curve (a) illustrates the EA
without the CSRE circuit. It needs about 2μ S and 2.5μ S with
230mV overshot and 270mV overshot to achieve stability under
positive load current change and negative load current change.
Curve (b) shows the result of the EA with the CSRE circuit. It is
evident that the transient response is improved significantly.
From the enlarged waveforms shown in Fig. 5, it demonstrates
that the proposed circuit only need 100nS and 113nS with
14mV and 17mV overshot to recover the output voltage to a
stable voltage under large load current from 100mA to 300mA
and from 300mA to 100mA . Compared to the performance of the
EA without the CSRE circuit, the CSRE circuit improve the
Fig. 4 The circuit implementation of EA with CSRE circuit.
Fig. 5 The transient response of the system with and without the CSRE circuit
under large load current changes
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average 1% settling time by 20 times and the overshot by 16
times with only consuming 7.1% additional static current.
Furthermore, there will be oscillation in the output voltage and
it will take long time to recover to the new stable voltage if the
controlling circuit is disconnected with the SRE circuit under
large load current change bigger than 100mA in 1nS , which
verifies the function of the controlling circuit in the CSRE
circuit. Therefore, with the use of CSRE circuit in the EA,
significant improvement in transient response can be achieved
in low-power condition.
V. CONCLUSION
This paper addresses the design CSRE circuit for EA in high
frequency DC-DC converters. The CSRE circuit is embedded
with the EA to improve transient response of DC-DC converter
under large load current changes. Operating principle,
systematic design, and optimizing size are discussed to confirm
the CSRE circuit controlled properly so that the system stability
can be guaranteed in various operating conditions. When the
proposed circuits were utilized in 100MHz DC-DC converter
designed in SMIC 0.18 µm CMOS process with Vdd = 3.3V ,
Vo = 1.8V , the simulation results verify the significant
improvement of the transient respond under larger load current
changes due to the embedded CSRE circuit.
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