258 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 18, NO.

1, JANUARY 2003

Operation of a DSTATCOM in Voltage Control Mode

Mahesh K. Mishra, Student Member, IEEE, Arindam Ghosh, Senior Member, IEEE, and Avinash Joshi

Abstract—The paper presents the operating principles of a

distribution static compensator (DSTATCOM) that is used to
maintain the voltage of a distribution bus. A three-phase, four-wire
distribution system is assumed in this study. A three-phase bridge
inverter circuit that is supplied by two neutral-clamped dc storage
capacitors realizes the DSTATCOM. Three filter capacitors, one
for each phase, are connected in parallel with the DSTATCOM (a)
to eliminate high-frequency switching components. The voltage
across the filter capacitor is controlled by a dead-beat controller
to maintain the ac bus voltage. The magnitude of the bus voltage
is chosen as nominal value, i.e., 1.0 p.u., while its phase angle
is obtained through a feedback loop that maintains the voltage
across the dc storage capacitors. Through detailed simulation and
experimental results, it has been shown that the DSTATCOM
can maintain the voltage against any unbalance and distortion in
either the load or supply side.
Index Terms—Deadbeat control and neutral clamped inverter,
distribution static compensator (DSTATCOM), voltage regulation. (b)
Fig. 1. (a) Simple radial system and (b) its Thevenin equivalent at bus 3.

I. INTRODUCTION
DSTATCOM can be used at this bus to reduce harmonics and
I N THE last two decades, various schemes of load compensa-
tion have been proposed [1]–[3]. These schemes can cancel
the effect of unbalance and distortion in currents and can also
balance the bus voltages.
Consider the three-phase, four-wire radial system shown in
Fig. 1(a). Let us assume that we would like to correct the voltage
correct the power factor at the load bus. All of these schemes as-
of bus 3. The single-phase Thevenin equivalent of the system is
sume the source voltages to be balanced and sinusoidal. In prac-
shown in Fig. 1(b). Here, , , and constitute the Thevenin
tice, however, the upstream source voltages may be unbalanced
equivalent looking toward the left into the network, while the
and distorted. In such cases, sensitive loads must be protected
equivalent load is the impedance looking toward the right into
by a compensator that can regulate the bus voltage to provide
the network, at bus 3. Since the DSTATCOM is connected at
balanced sinusoidal voltage of prespecified magnitude.
this bus, it is called the point of common coupling (PCC). We
This paper proposes a method to operate a distribution static
now have to use the DSTATCOM in the voltage control mode at
compensator (DSTATCOM) as a voltage regulator to maintain
bus 3. However, since the Thevenin equivalents can change any
the voltage of a specified bus. The magnitude of the bus voltage
time depending on the load, it is desirable that these parameters
is prespecified while its phase angle is generated from the dc ca-
are not used in the voltage controller design. Below, we present
pacitor control loop. A deadbeat controller [4]–[8] for inverter is
a voltage control technique that only requires the timing infor-
used for voltage tracking using the DSTATCOM. The algorithm
mation from the source for synchronization.
has been discussed in detail. The proposed structure is verified
The single-phase equivalent circuit of the DSTATCOM that
through detailed simulation and experimental results.
is connected to the PCC is shown in Fig. 2(a). The DSTATCOM
is realized by a two-level neutral-clamped voltage source con-
II. DSTATCOM IN VOLTAGE CONTROL MODE verter (VSC) [9], as shown in Fig. 2(b). A filter capacitor
In a distribution system, there may be several different com- is used in parallel with the VSC circuit to provide a path for the
pensating devices. However, in a radial distribution system, the high-frequency components. Note that the PCC is referred to as
voltage of a particular bus can be distorted or unbalanced if the the terminal in this paper and its voltage is denoted by .
loads in any part of the system are nonlinear or unbalanced. In Fig. 2(a), is the switching variable that can take on values
The customers connected to that bus would be supplied by a 1 corresponding to the states of one inverter phase, as shown
set of unbalanced and distorted voltages, even when their loads in Fig. 2(b). The capacitor voltages and are assumed
are not contributing to the bus voltage pollution. Therefore, a to be equal to in the equivalent circuit. To derive a control
law, we assume for the time being that is equal to a continous
signal . Then, the state space equation for the system shown
Manuscript received September 26, 2001. in Fig. 2(a) is given as
The authors are with the Department of Electrical Engineering, Indian Insti-
tute of Technology, Kanpur 208016, India.
Digital Object Identifier 10.1109/TPWRD.2002.807746 (1)
0885-8977/03$17.00 © 2003 IEEE
MISHRA et al.: OPERATION OF DSTATCOM IN VOLTAGE CONTROL MODE 259

Let be the reference (nominal) voltage to be maintained at

the terminal bus. We now choose the cost function

(5)

and minimize it as

(6)
From (4) and (6), the control input is given by

(a)

(7)
This control action is termed as a deadbeat action. The deriva-
tion of from is discussed next.

III. SWITCHING CONTROL

As mentioned earlier, the switching variable is constrained
to be 1. One leg of the neutral clamped inverter chosen to re-
alize DSTATCOM is shown in Fig. 2(b). Here, there are two
dc storage capacitors, namely, and . The voltage across
each capacitor is maintained at . In Fig. 2(b), is the status
of the top switch, bottom switch being complementary. This
means for , the top switch is closed (open), while
(b) the bottom switch is open (closed) connecting the output of the
Fig. 2. DSTATCOM. (a) Equivalent circuit. (b) Corresponding inverter circuit. inverter leg to . Therefore, through switching the
inverter supplies a voltage . This is represented as
in Fig. 2(a). The variable controls the status of the inverter
where
switches through gate drive circuits.
The switching variable is obtained from the continuous
signal by a hysteresis action around zero, i.e.
and
if then
else if then (8)

The state vector and the output vector are given as where is a prespecified hysteresis band. The value of the pa-
rameter determines the switching frequency.

IV. REFERENCE VOLTAGE GENERATION

Writing the continuous state (1) into discrete form
When two dc storage capacitors are supplying the
(2) DSTATCOM, the average of real power entering the PCC
(terminal) from source must equal the sum of average load
where is the th sampling instant. The state transition matrix power and the losses in the DSTATCOM. Otherwise, the
and the input matrix , given by capacitors will continuously either charge or discharge. The
magnitude of the terminal voltage can be arbitrarily chosen
and up to a certain limit. The lower limit of is decided by the
maximum permissible value of its angle with respect
where is the sampling period. For the system of (1), let us to the source voltage, while its upper limit set by the voltage
define the elements of these matrices as rating of the inverter and the dc capacitors. The phase angle
must be adjusted in a closed loop for power balance. In this
and (3) paper the nominal value of the terminal voltage is chosen to
be 1.0 p.u. and the phase angle is controlled by a two-loop
We can then write from (2) feedback control shown in Fig. 3.
Assuming that the voltage across each capacitor is , the
(4) total voltage across the dc link is . The deviation of this
260
Fig. 3. Block diagram of closed loop voltage control.
total voltage from its reference value is a good indica-
tion of losses in the inverter. Therefore, we add the two capac-
itor voltages and compare the total with the reference value. It
is to be noted that the dc capacitor voltage usually contains the
switching frequency components. Therefore, comparing its in-
stantaneous value with that of the reference will result in a large
error in control. Instead, the average value of the dc capacitors
can be regulated around the reference value. Alternatively, the
value of the total voltage across the capacitors at the end of a
cycle can be regulated around a reference value. This is done
through a proportional controller with a gain of . The output
of this controller is , which is the amount of power that
must be drawn from the compensator in order to maintain the
dc capacitor voltage. Thus
(9)
where is the summation of voltage across the two capacitors
(see Fig. 3). Since the loop maintains the capacitor voltage, we
call it the outer voltage loop.
The power angle (which is the phase angle between the
terminal and the source voltages in their respective phases) is
computed in such a way that it ensures that the shunt link draws
an amount of power that is equal to . To achieve
this, a PI controller is used, the output of which is power angle
. This is given as
(10)
where and are the PI controller gains. These gains must
be carefully chosen, as high gain may cause unnecessary oscil-
lations and may even cause instability.
The instantaneous power in shunt link is computed as
follows:
(11)
It is to be noted that a positive value of corresponds to
a direction of power flow from the compensator into the bus,
which reduces the dc capacitor voltage. In the steady state, the
average value of is negative due to the inverter losses. The
instantaneous value of obtained from (11) is averaged over
a cycle. This average value is denoted by and is used to im-
plement the inner power loop to compute , as shown in Fig. 3.
The angle is defined with the source voltage as reference.
Thus, we require the zero crossing of the phase voltage of
the source. This information can be obtained through telemetry
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 18, NO. 1, JANUARY 2003
TABLE I
SYSTEM PARAMETERS
when bus to be controlled is remotely located. The reference
voltages for the PCC bus are given as
(12)
where is the desired magnitude of the terminal voltage and
is the fundamental frequency of the system.
V. SIMULATION RESULTS
In this section, detailed simulation results will be presented.
It is demonstrated that the DSTATCOM in the voltage regulator
mode is able to maintain the terminal bus voltage at the nominal
value irrespective of the load changes and the upstream voltage
fluctuations. For this, we assume a simplified distribution
system in which a three-phase load is supplied by a source
through a radial feeder. The objective is to supply a balanced
voltage to the load. The simulation parameters are given in
Table I.
The three-phase load consists of
1) , , ;
2) three-phase diode bridges rectifier drawing a current of
5 A.
For the source voltage of 360 V peak, the uncompensated
terminal voltages are shown in Fig. 4(a). It can be seen that the
terminal voltages contain the spikes due to diode rectifier load
and feeder inductance. In Fig. 4(b), the compensated terminal
voltages are shown. These are sinusoidal and balanced with a
peak of 360 V.
A. Performance in Case of Voltage Swell and Sag
Voltage swell and sag are special (transient) cases of over
voltage and under voltage, respectively. The short duration (a
few cycles) transient over voltage is called a swell while an un-
dervoltage is called a sag. The voltage swell and sag in source
voltage is shown in Fig. 5(a). The different segments of the
source voltage are as follows. For the first ten cycles, the source
voltage has the nominal value of 360 V (peak). This is fol-
lowed by a balanced 20% swell in the source voltage for eight
cycles. After attaining the nominal value for the next ten cy-
cles, the source voltage undergoes an eight-cycle, 20% balanced
sag. Following this, the source voltage again attains the nominal
MISHRA et al.: OPERATION OF DSTATCOM IN VOLTAGE CONTROL MODE
(a)
(b)
Fig. 4. Terminal voltages. (a) Before compensation. (b) After compensation.
Fig. 5. (a) Swell and sag in source voltage. (b) Terminal voltage. (c) Terminal
voltage on magnified scale. (d) Variation of  (e). (e) Total dc capacitor voltage.
(f) Reference shunt power and instantaneous shunt actual power.
value. When the DSTATCOM is operated in the voltage control
mode, the terminal voltage of phase a is shown in Fig. 5(b). It
261
is seen that terminal is regulated to nominal value, i.e., 360 V
(peak), against the transient changes in the source voltage. The
three-phase terminal voltage on a magnified scale is shown in
Fig. 5(c). This figure indicates that the terminal voltages are bal-
anced and sinusoidal. Fig. 5(d) shows the power angle. The total
dc capacitor voltage is shown in Fig. 5(e).
It can be seen from Fig. 5(d) that initially, when the compen-
sator is switched on with the nominal value of source voltage,
the power angle settles at 0.092 rad (5.3 ). During the voltage
swell, the dc capacitor voltage rises as the increased power
coming from the source starts charging the capacitors. To offset
this, the power angle decreases. Exactly the opposite phenom-
enon can be seen during the voltage sag. During this period, the
capacitors momentarily supply real power to the load and as a
consequence, the load angle rises to draw more power from the
source. It is to be noted that the duration of either swell or sag is
rather small. Therefore, the controller does not have sufficient
time to settle. However, when the source supplies the nominal
voltage, the load angle settles to the steady state value of 0.092
rad.
The increase in the shunt power during the voltage swell and
the decrease during the voltage sag can be seen from Fig. 5(f),
which depicts the instantaneous shunt power and its ref-
erence value .
B. Performance in Case of Unbalanced and Distorted Source
Voltage
The DSTATCOM in voltage control mode must be able to
clean up any supply side disturbances. To investigate this, a
source voltage is chosen that is both unbalanced and distorted,
while the load remains the same as given before. To verify this,
the source voltages are assumed to be unbalanced and contam-
inated by third harmonics. The voltages are given by:
1) phase a: 360 V (peak) and 15% third harmonic;
2) phase b: 432 V (peak) and 16% third harmonic;
3) phase c: 288 V (peak) and 8% third harmonic.
The source voltages are shown in Fig. 6(a), while the terminal
voltages are shown in Fig. 6(b). The compensator is connected
at the end of the first cycle (0.02 s). It can be seen from Fig. 6(b)
that the terminal voltages become balanced sinusoidal as soon
as the compensator is connected. The power angle settles around
0.1 rad, i.e., 5.7 . The harmonic spectrums of phase a the source
voltage and the terminal voltage are shown in Fig. 7(a) and (b),
respectively. The total harmonic distortion (THD) in phase a of
the source voltage is 15%, while in phase a of the compensated
terminal voltage it is 0.95%. The THD in terminal voltage of the
other two phases is also around 1%.
C. Performance Under Change in Feeder Impedance
It was mentioned previously that the source side impedance
is, at best, the Thevenin impedance looking toward the source
from the bus controlled by the DSTATCOM. Therefore, the
DSTATCOM should be able to regulate the bus voltage even
when the feeder impedance is changed. To test this, the feeder
impedance is halved at the end of ten cycles (0.2 s) when the
DSTATCOM is operating in the steady state. The system re-
sponse is shown in Fig. 8, in which the bus voltage, total voltage
262 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 18, NO. 1, JANUARY 2003

(a)

Fig. 8. System response to change in feeder impedance.

(b)
Fig. 6. (a) Unbalanced source voltages with harmonics and (b) terminal
voltages before and after regulation.

Fig. 9. System response to change in load.

(a) siently, the power drawn from the source is larger than the power
required by the load. As a result, the sum of the capacitor volt-
ages increases. Then, the control loop (see Fig. 3) takes over and
adjusts the power angle to bring back the sum of the capacitor
voltages to the desired reference value in about ten cycles.

D. Performance Under Load Change

(b)
Fig. 7. Harmonic spectrum in (a) source voltage and (b) compensated terminal
voltage.
across the dc capacitors, and the load angle are shown. It can be
seen that the ripples in the bus voltage die out within two cy-
cles. Due to the sudden reduction in the feeder impedance, tran-
To investigate the effect of abrupt changes in load on the per-
formance of DSTATCOM, the load pattern is divided into three
regions. The phase a of the load current is shown in Fig. 9 where
the regions are demarcated. For region 1, the load is normal
and the power angle settles to around 0.09 rad (5.1 ). The
total dc capacitor voltage is maintained at the reference
value of 1200 V. In region 2, the unbalanced R-L load is re-
moved from all three phases and only the diode rectifier load
is present. Since this is smaller than the normal load current,
reduces to a smaller value. Since the power requirement at the
load is suddenly reduced, the sum of the capacitor voltages
rises transiently but is then gradually brought back toward the
steady state value of 1200 V by the control action. The load is in-
MISHRA et al.: OPERATION OF DSTATCOM IN VOLTAGE CONTROL MODE 263

TABLE II
EXPERIMENTAL PARAMETERS

Fig. 11. Variations in (a)  and (b) P for unbalanced load.

Fig. 10. Source and uncompensated terminal voltage in phase a.

creased in region 3. The effect of this load increase on the load

angle and the capacitor voltage is just the reverse of region 2.
However, power angle gradually settles around 0.16 rad, while Fig. 12. Source and compensated terminal voltage in phase a.
settles around 1200 V. It is to be noted that the sum of the
capacitor voltages in region 2 tries to recover to the reference
value, but the load is changed before it can reach the steady state.
Throughout the change in load, the terminal voltage is regulated
and its waveform is similar to those shown in Fig. 8. It is also
mentioned that for the parameters considered in simulation, the
switching frequency of the inverter is approximately 3 kHz.

VI. EXPERIMENTAL RESULTS

The experimental system parameters are given in Table II.
The load and the feeder impedance are the same as those given
in the simulation studies. Three-phase terminal voltages [ in
Fig. 2(a)] are measured using three Hall-effect voltage trans-
ducers across the filter capacitors. In addition, six Hall-effect
current transducers are employed for the measurement of filter
capacitor currents and shunt link currents . These
quantities are given to an IBM compatible PC (P-II, 350 MHz)
through a data acquisition card (NuDAQ 9118DG).
A. When Load is Both Unbalanced and Nonlinear
The phase a of the source voltage and uncompensated
terminal voltage are shown in Fig. 10. It can be seen that
the terminal voltage is distorted due to the rectifier load and the
feeder impedance.
To start the compensator, the load angle is initially set
to zero and the dc capacitors are supplied by independent dc
sources. Then, at an instant , the DSTATCOM is
connected to the ac bus and (see Fig. 3) is set to zero.
Since the inner control loop is active during this time, rises to
a small value to supply the load power. Then, at a later instant
, the outer control loop is activated and, at the same
time, the independent sources are turned off. The steady state
then settles to 0.17 rad (10 ). The entire transient is shown in
Fig. 13. Load current and terminal bus voltage during load change.
Fig. 11, which also shows the variation of average shunt power
. The phase a of the compensated voltage in steady state is
shown in Fig. 12 along with the phase a source voltage. The
steady state can also be seen in this figure.
B. Transient Performance
The phase a of the load is changed suddenly by switching
off the passive load and retaining only rectifier load. After ap-
proximately one and one-half cycle, the load is switched back
to normal. The load current and terminal voltage in phase a are
shown in Fig. 13. It is seen from the voltage waveform that the
terminal voltage is not affected by change in the load. Thus,
the voltage regulator is able to regulate the voltage at the bus
under load transient. This experiment verifies the findings of
Section V-D.
C. Unbalanced Source Voltages
For this test, the source voltage in phases a and c are set to
32 V (peak), while the source voltage in phase b is set to 40 V
(peak). These are shown in Fig. 14. Once the compensator is
connected, the terminal voltages become balanced with the de-
sired magnitude of V (peak) in each phase. In the steady state,
264
Fig. 14. Unbalanced sources voltages.
Fig. 15. Compensated balanced terminal voltages.
settles at 0.14 rad. The compensated terminal voltages are
shown in Fig. 15. These are similar to those shown in Fig. 6.
VII. CONCLUSIONS
In this paper, a deadbeat control algorithm is applied to op-
erate a DSTATCOM to regulate the voltage of the terminal bus
at a nominal value. A closed loop control scheme, consisting of
an outer dc capacitor voltage loop and an inner load angle con-
trol loop, is proposed. The control scheme maintains the power
balance at the PCC to regulate the dc capacitor voltages. It has
been shown that the DSTATCOM is able to regulate the PCC
voltage against disturbances either in the load or in the source
side.
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Mahesh K. Mishra (S’00) received the B.Tech. degree from College of Tech-
nology, Pantnagar, India, and the M.E. degree from University of Roorkee, India.
Currently, he is a research scholar at the Indian Institute of Technology, Kanpur.
His interests are in the areas of power electronics and controls.
Arindam Ghosh (S’80–M’83–SM’93) received the Ph.D. degree in electrical
engineering from the University of Calgary, Calgary, AB, Canada.
Currently, he is a Professor of electrical engineering at the Indian Institute of
Technology, Kanpur. He has held visiting positions at Nanyang Technological
University, Singapore, the University of Queensland, and Queensland Univer-
sity of Technology, Australia. His areas of interest are power systems, and power
electronics and controls.
Avinash Joshi received the Ph.D. degree in electrical engineering from the Uni-
versity of Toronto, Toronto, ON, Canada.
Currently, he is a Professor of electrical engineering at the Indian Institute of
Technology, Kanpur. He has also been with the G.E.C. of India, Ltd. His inter-
ests involve power electronics circuits, digital electronics, and microprocessor
systems.