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VLSI Lab Viva Questions and Answers PDF PDF
VLSI Lab Viva Questions and Answers PDF PDF
cadence .
59. What are the other alternative software apart from cadence used for VLSI design?
RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL)
used for defining digital circuits. The most popular RTL languages are VHDL and Verilog.
Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of
ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study
including estimated delays, verify setup, hold and other timing requirements of devices like flip
flops are met
Synthesis: One of the foremost in back end steps where by synthesizing is nothing but
converting VHDL or VERILOG description to a set of primitives or components(as in
FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design
description into equations or components.
63. Which is the tool used for analog design of vlsi circuits?
Virtuoso
Encounter
65. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of
them together for that purpose.
66. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass
transistor, both voltage levels need to be passed and hence both nmos and pmos need to be used.
67. What are set up time & hold time constraints? What do they signify?
Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the
signal changes state during this interval, the output of that flip-flop cannot be predictable (called
metastable).
Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the
signal changes during this interval, the output of that flip-flop cannot be predictable (called
metastable).
clock skew is the time difference between the arrival of active clock edge to different flip-flops’
of the same chip.
69. Why is not NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a faster
gate. Additionally, the gate-leakage in NAND structures is much lower.
In general multiple MOS devices are made on a common substrate. As a result, the substrate
voltage of all devices is normally equal. However while connecting the devices serially this may
result in an increase in source-to-substrate voltage as we proceed vertically along the series chain
(Vsb1=0, Vsb2 0).Which results Vth2>Vth1.
71. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
we try to reverse bias not the channel and the substrate but we try to maintain the drain, source
junctions reverse biased with respect to the substrate so that we don’t loose our current into the
substrate.
In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes(p-channel
MOS) - In BJT, we see current due to both the carriers..Electrons and holes. BJT is a current
controlled device and MOSFET is a voltage controlled device
73. In CMOS technology, in digital design, why do we design the size of pmos to be higher
than the nmos. What determines the size of pmos wrt nmos. Though this is a simple
question try to list all the reasons possible?
In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the
carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos
helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If the
sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output
node. If we have a larger PMOS than there will be more carriers to charge the node quickly and
overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for
the output node.
74. Why PMOS and NMOS are sized equally in a Transmission Gates?
In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's
the reason why we need not size them like in CMOS. In CMOS design we have NMOS and
PMOS competing which is the reason we try to size them proportional to their mobility.
75. What happens when the PMOS and NMOS are interchanged with one another in an
inverter?
If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1
O/P will be degraded 1 Similarly degraded 0
76. Why are pMOS transistor networks generally used to produce high signals, while
nMOS networks are used to product low signals?
This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS
can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in
pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing.
Testing: A manufacturing step that ensures that the physical device , manufactured from the
synthesized design, has no manufacturing defect.
Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will
perform the given I/O function
78. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?
A latch up is the inadvertent creation of a low-impedance path between the power supply rails of
an electronic component, triggering a parasitic structure(The parasitic structure is usually
equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning
of the part. Depending on the circuits involved, the amount of current flow produced by this
mechanism can be large enough to result in permanent destruction of the device due to electrical
over stress - EOS
The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a
particular path. Slack may be +ve or -ve.
81. Mention what are the different gates where Boolean logic are applicable?
NOT Gate: It has one out input and one output. For example, if the value of A= 0 then
the Value of B=1 and vice versa
AND Gate: It has one output due to the combination of two output. For example, if the
value of A and B= 1 then value of Q should be 1
OR Gate: Either of the value will show the same output. For example, if the value of A
is 1 or B is 0 then value of Q is 1
These are the basic three types of gates where Boolean logic work, apart from these, other gates
that are functional works with the combination of these three basic gates, they are XNOR gate,
NAND gate, Nor gate and XOR gate.
82. Explain how binary number can give a signal or convert into a digital signal?
Binary number consists of either 0 or 1, in simple words number 1 represents the ON state and
number 0 represents OFF state. These binary numbers can combine billion of machines into one
machines or circuit and operate those machines by performing arithmetic calculations and sorting
operations.
83. Mention what is the difference between the TTL chips and CMOS chips?
88. Mention what are the two types of procedural blocks in Verilog?
The two types of procedural blocks in Verilog are
Initial: Initial blocks runs only once at time zero
Always: This block loop to execute over and again and executes always, as the name
suggests
89. Explain why present VLSI circuits use MOSFETs instead of BJTs?
In comparison to BJT, MOSFETS can be made very compact as they occupy very small silicon
area on IC chip and also in term of manufacturing they are relatively simple. Moreover, digital
and memory ICs can be employed with circuits that use only MOSFETs, i.e., diodes, resistors,
etc.
90. Mention what are three regions of operation of MOSFET and how are they used?
MOSFET has three regions of operations
Cut-off region
Triode region
Saturation region
The triode and cut-off region are used to function as a switch, while, saturation region is used to
operate as an amplifier.
92. Explain why is the number of gate inputs to CMOS gates usually limited to four?
Higher the number of stacks, slower the gate will be. In NOR and NAND gates the number of
gates present in the stack is usually alike as the number of inputs plus one. So input are restricted
to four.