Spartan 6 FPGA Configurable Logic Block PDF

Spartan-6 FPGA
Configurable Logic Block
User Guide
UG384 (v1.1) February 23, 2010

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Revision History
The following table shows the revision history for this document.
Date Version Revision

06/24/09 1.0 Initial Xilinx release.
02/23/10 1.1 Clarified the Slice Description section. Added Figure 6. Clarifying edits to Storage
Elements, Initialization, Distributed RAM and Memory (SLICEM only), and Fast
Lookahead Carry Logic sections. Added Using the Latch Function as Logic and
Interconnect Resources. Updated parameter names in Table 9 and Table 10 and
Figure 35. Updated description TCINA function and description Table 12.
Spartan-6 FPGA CLB User Guide www.xilinx.com UG384 (v1.1) February 23, 2010
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Spartan-6 FPGA CLB

CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CLB/Slice Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Storage Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Distributed RAM and Memory (SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Shift Registers (SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Designing Large Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Fast Lookahead Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Using the Latch Function as Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interconnect Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Spartan-6 FPGA Interconnect Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Global Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STARTUP_SPARTAN6 Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interconnect Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Slice (LUT and Storage Element) Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Slice Distributed RAM Timing Model (SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Slice SRL Timing Model (SLICEM only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Slice Carry-Chain Timing Model (SLICEM and SLICEL only) . . . . . . . . . . . . . . . . . . . 50
CLB Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Distributed RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Shift Registers (SRLs) Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Other Shift Register Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Multiplexer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Carry Chain Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Spartan-6 FPGA CLB User Guide www.xilinx.com 3

UG384 (v1.1) February 23, 2010
4 www.xilinx.com Spartan-6 FPGA CLB User Guide
UG384 (v1.1) February 23, 2010
Preface
About This Guide

This guide serves as a technical reference describing the Spartan®-6 FPGA configurable
logic blocks (CLBs). Usually, the logic synthesis software assigns the CLB resources
without system designer intervention. It can be advantageous for the designer to
understand certain CLB details, including the varying capabilities of the look-up tables
(LUTs), the physical direction of the carry propagation, the number and distribution of the
available flip-flops, and the availability of the very efficient shift registers. This guide
describes these and other features of the CLB in detail.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/support/documentation/spartan-6.htm.
• Spartan-6 Family Overview
This overview outlines the features and product selection of the Spartan-6 family.
• Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and switching characteristic specifications for the
Spartan-6 family.
• Spartan-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Spartan-6 FPGA Configuration User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and parallel), multi-bitstream management, bitstream encryption,
boundary-scan and JTAG configuration, and reconfiguration techniques.
• Spartan-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO™ resources available in all Spartan-6 devices.
• Spartan-6 FPGA Clocking Resources User Guide
This guide describes the clocking resources available in all Spartan-6 devices,
including the DCMs and PLLs.
• Spartan-6 FPGA Block RAM Resources User Guide
This guide describes the Spartan-6 device block RAM capabilities.
• Spartan-6 FPGA GTP Transceivers User Guide
This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs.

UG384 (v1.1) February 23, 2010
Preface: About This Guide
• Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and
provides configuration examples.
• Spartan-6 FPGA Memory Controller User Guide
This guide describes the Spartan-6 FPGA memory controller block, a dedicated
embedded multi-port memory controller that greatly simplifies interfacing
Spartan-6 FPGAs to the most popular memory standards.
• Spartan-6 FPGA PCB Design Guide
This guide provides information on PCB design for Spartan-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Additional Support Resources

To search the database of silicon and software questions and answers or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.

UG384 (v1.1) February 23, 2010
Spartan-6 FPGA CLB
CLB Overview
The Configurable Logic Blocks (CLBs) are the main logic resources for implementing
sequential as well as combinatorial circuits. Each CLB element is connected to a switch
matrix for access to the general routing matrix (shown in Figure 1). A CLB element
contains a pair of slices. These two slices do not have direct connections to each other, and
each slice is organized as a column. For each CLB, the slice in the bottom of the CLB is
labeled as SLICE(0), and the slice in the top of the CLB is labeled as SLICE(1).
X-Ref Target - Figure 1
COUT
CLB
Slice(1)
Switch
Matrix
Slice(0)
CIN
ug384_01_042309
Figure 1: Arrangement of Slices within the CLB
The Xilinx tools designate slices with the following definitions. An “X” followed by a
number identifies the position of each slice in a pair as well as the column position of the
slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB
column); 2, 3 (the second CLB column); etc. A “Y” followed by a number identifies a row of
slices. The number remains the same within a CLB, but counts up in sequence from one
CLB row to the next CLB row, starting from the bottom. Figure 2 shows four CLBs located
in the bottom-left corner of the die.

UG384 (v1.1) February 23, 2010
COUT COUT
CLB CLB
SLICEX SLICEX
X1Y1 X3Y1
Slice Slice
X0Y1 X2Y1
CIN CIN
COUT COUT
CLB CLB
SLICEX SLICEX
X1Y0 X3Y0
Slice Slice
X0Y0 X2Y0
ug384_02_042309
Figure 2: Row and Column Relationship between CLBs and Slices
Slice Description
Every slice contains four logic-function generators (or look-up tables, LUTs) and eight
storage elements. These elements are used by all slices to provide logic and ROM functions
(Table 1). SLICEX is the basic slice. Some slices, called SLICELs, also contain an arithmetic
carry structure that can be concatenated vertically up through the slice column, and wide-
function multiplexers. The SLICEMs contain the carry structure and multiplexers, and add
the ability to use the LUTs as 64-bit distributed RAM and as variable-length shift registers
(maximum 32-bit).
Table 1: Slice Features

Feature SLICEX SLICEL SLICEM
6-Input LUTs √ √ √
8 Flip-flops √ √ √
Wide Multiplexers √ √
Carry Logic √ √
Distributed RAM √
Shift Registers √
Each column of CLBs contain two slice columns. One column is a SLICEX column, the
other column alternates between SLICEL and SLICEMs. Thus, approximately 50% of the
available slices are of type SLICEX, while 25% each are SLICEL and SLICEMs. The
XC6SLX4 does not have SLICELs (Table 3).
SLICEM (shown in Figure 3) represents a superset of elements and connections found in
all slices. SLICEL is shown in Figure 4. SLICEX is shown in Figure 5. All eight SR, CE, and
CLK inputs are driven by common control inputs.

UG384 (v1.1) February 23, 2010
COUT
DI
DI2 CLK WE D
D6:D1 A6:A1 O6
WA6:WA1 O5 D Q
LUT CE D5Q
RAM CK MC31
ROM DI1 CARRY4 SRINIT0 CY DMUX
SRINIT1 XOR
DPRAM64 O5
DPRAM32 SR O6
SPRAM64
SPRAM32 D Q DQ
SRL16 FF
MC31 CE
SRL32 WA8 LATCH
CY CK
WA7 AND2L
XOR
MC31 OR2L
DX SRINIT0
O5 SRINIT1
DX O6
SR
CI
DI2 CLK WE
A6:A1 O6 C
C6:C1
WA6:WA1 O5 D Q
LUT CE
RAM CK C5Q
ROM DI1 SRINIT0 F7
SRINIT1 CY
DPRAM64 XOR CMUX
DPRAM32 SR O5
SPRAM64 O6
SPRAM32
SRL16
SRL32 WA8 F7
WA7 CY D Q CQ
FF
MC31 XOR CE LATCH
CX CK AND2L
CX O5 OR2L
CLK O6 SRINIT0
SRINIT1
SR
WE
CE
SR
BI
DI2 CLK WE B
B6:B1 A6:A1 O6
WA6:WA1 O5 D Q
LUT CE B5Q
RAM CK F8
ROM DI1 SRINIT0 CY
BMUX
SRINIT1 XOR
DPRAM64 O5
DPRAM32 SR O6
SPRAM64
SPRAM32 D FF Q BQ
SRL16 WA8 F8
CY
CE LATCH
SRL32 CK AND2L
WA7 XOR
MC31 BX OR2L
O5 SRINIT0
BX O6 SRINIT1
SR
AI
DI2 CLK WE A
A6:A1 A6:A1 O6
WA6:WA1 O5 D Q
LUT CE A5Q
RAM CK F7
ROM DI1 SRINIT0 CY
XOR AMUX
SRINIT1
DPRAM64 O5
DPRAM32 SR O6
SPRAM64
SPRAM32 D Q AQ
SRL16 WA8 F7 FF
CY
CE LATCH
SRL32
WA7 XOR CK AND2L
MC31 AX OR2L
O5 SRINIT0
O6 SRINIT1
SR
1
AX
CIN
ug384_03_042309
Figure 3: Diagram of SLICEM

UG384 (v1.1) February 23, 2010
COUT
D
D6:D1 A6:A1 O6
O5 D Q
CE D5Q
CK
CARRY4 SRINIT0 CY DMUX
SRINIT1 XOR
O5
SR O6
D FF Q DQ
CE LATCH
CY CK AND2L
XOR
OR2L
DX SRINIT0
O5 SRINIT1
DX O6
SR
A6:A1 O6 C
C6:C1
O5 D Q
CE
CK C5Q
SRINIT0 F7
SRINIT1 CY
XOR CMUX
SR O5
O6
F7
CY D FF Q CQ
XOR CE LATCH
CX CK AND2L
CX O5 OR2L
CLK O6 SRINIT0
SRINIT1
SR
CE
SR
B
B6:B1 A6:A1 O6
O5 D Q
CE B5Q
CK F8
SRINIT0 CY
BMUX
SRINIT1 XOR
O5
SR O6
D FF Q BQ
F8
CY
CE LATCH
XOR CK AND2L
BX OR2L
O5 SRINIT0
BX O6 SRINIT1
SR
A
A6:A1 A6:A1 O6
O5 D Q
CE A5Q
CK F7
SRINIT0 CY
XOR AMUX
SRINIT1
O5
SR O6
D FF Q AQ
F7
CY
CE LATCH
XOR CK AND2L
AX OR2L
O5 SRINIT0
O6 SRINIT1
SR
1
AX
CIN
ug384_04_042309
Figure 4: Diagram of SLICEL

UG384 (v1.1) February 23, 2010
D
D6:D1 A6:A1 O6
O5 D Q
CE
CK D5Q
SRINIT0 DMUX
SRINIT1
O5
SR O6
D FF Q DQ
CE LATCH
CK AND2L
OR2L
DX DX SRINIT0
SRINIT1
O6
SR
A6:A1 O6 C
C6:C1
O5 D Q
CE
CK
SRINIT0 C5Q
SRINIT1 CMUX
SR O5
O6
D FF Q CQ
CE LATCH
CX CX CK AND2L
OR2L
CLK O6 SRINIT0
SRINIT1
SR
CE
SR
B
B6:B1 A6:A1 O6
O5 D Q
CE
CK B5Q
SRINIT0 BMUX
SRINIT1
O5
SR O6
D FF Q BQ
CE LATCH
CK AND2L
BX BX OR2L
SRINIT0
O6 SRINIT1
SR
A
A6:A1 A6:A1 O6
O5 D Q
CE
CK A5Q
SRINIT0 AMUX
SRINIT1
O5
SR O6
D FF Q AQ
CE LATCH
CK AND2L
AX OR2L
SRINIT0
O6 SRINIT1
SR
AX
ug384_05_121108
Figure 5: Diagram of SLICEX

UG384 (v1.1) February 23, 2010
CLB/Slice Configurations
Table 2 summarizes the logic resources in one CLB. Each CLB or slice can be implemented
in one of the configurations listed.
Table 2: Logic Resources in One CLB

Arithmetic and
Slices LUTs Flip-Flops Distributed RAM(1) Shift Registers(1)
Carry Chains(2)
2 8 16 1 256 bits 128 bits
Notes:
1. SLICEM only, SLICEL and SLICEX do not have distributed RAM or shift registers.
2. SLICEM and SLICEL only.
Table 3 shows the available CLB resources for the Spartan-6 FPGAs. The ratio between the
number of 6-input LUTs and logic cells is 1.6. This reflects the increased capability of the
new 6-input LUT architecture compared to traditional 4-input LUTs.
Table 3: Spartan-6 FPGA Logic Resources

Maximum Shift
Logic Total Number of Number of
Device SLICEMs SLICELs SLICEXs Distributed Registers
Cells Slices 6-Input LUTs Flip-Flops
RAM (Kb) (Kb)
XC6SLX4 3,840 600 300 0 300 2,400 75 38 4,800
XC6SLX9 9,152 1,430 360 355 715 5,720 90 45 11,440
XC6SLX16 14,579 2,278 544 595 1,139 9,112 136 68 18,224
XC6SLX25 24,051 3,758 916 963 1,879 15,032 229 115 30,064
XC6SLX45 43,661 6,822 1,602 1,809 3,411 27,288 401 200 54,576
XC6SLX75 74,637 11,662 2,768 3,063 5,831 46,648 692 346 93,296
XC6SLX100 101,261 15,822 3,904 4,007 7,911 63,288 976 488 126,576
XC6SLX150 147,443 23,038 5,420 6,099 11,519 92,152 1,355 678 184,304
XC6SLX25T 24,051 3,758 916 963 1,879 15,032 229 115 30,064
XC6SLX45T 43,661 6,822 1,602 1,809 3,411 27,288 401 200 54,576
XC6SLX75T 74,637 11,662 2,768 3,063 5,831 46,648 692 346 93,296
XC6SLX100T 101,261 15,822 3,904 4,007 7,911 63,288 976 488 126,576
XC6SLX150T 147,443 23,038 5,420 6,099 11,519 92,152 1,355 678 184,304
Look-Up Table (LUT)

The function generators in Spartan-6 FPGAs are implemented as six-input look-up tables
(LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent
outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The
function generators can implement any arbitrarily defined six-input Boolean function.
Each function generator can also implement two arbitrarily defined five-input Boolean
functions, as long as these two functions share common inputs. Only the O6 output of the
function generator is used when a six-input function is implemented. Both O5 and O6 are
used for each of the five-input function generators implemented. In this case, A6 is driven

UG384 (v1.1) February 23, 2010
High by the software. The propagation delay through a LUT is independent of the function
implemented, or whether one six-input or two five-input generators are implemented.
Signals from the function generators can exit the slice (through A, B, C, D output for O6 or
AMUX, BMUX, CMUX, DMUX output for O5), enter the XOR dedicated gate from an O6
output (see Fast Lookahead Carry Logic), enter the carry-logic chain from an O5 output
(see Fast Lookahead Carry Logic), enter the select line of the carry-logic multiplexer from
an O6 output (see Fast Lookahead Carry Logic), feed the D input of the storage element, or
go to F7AMUX/F7BMUX from an O6 output.
Figure 6 shows a simplified view of the connectivity for a single LUT6.
DI
QD or Q6
A6 D Q
LUT6
LUT5 O6 O6
A[5:1]
O5 or Q5
LUT5 O5
D Q
UG384_06new_021210
Figure 6: LUT6
In addition to the basic LUTs, SLICEL and SLICEM contain three multiplexers (F7AMUX,
F7BMUX, and F8MUX). These multiplexers are used to combine up to four function
generators to provide any function of seven or eight inputs in a slice. F7AMUX and
F7BMUX are used to generate seven input functions from slice A and B, or C and D, while
F8MUX is used to combine all slices to generate eight input functions. Functions with more
than eight inputs can be implemented using multiple slices. There are no direct
connections between slices to form function generators greater than eight inputs within a
CLB or between slices, but CLB outputs can be routed through the switch matrix and
directly back into the CLB inputs.
Storage Elements
Each slice has eight storage elements. There are four storage elements in a slice that can be
configured as either edge-triggered D-type flip-flops or level-sensitive latches. The D input
can be driven directly by a LUT output via AFFMUX, BFFMUX, CFFMUX or DFFMUX, or
by the BYPASS slice inputs bypassing the function generators via AX, BX, CX, or DX input.
When configured as a latch, the latch is transparent when the CLK is Low.
In Spartan-6 devices, there are four additional storage elements that can only be configured
as edge-triggered D-type flip-flops. The D input can be driven by the O5 output of the LUT.
When the original 4 storage elements are configured as latches, these 4 additional storage
elements can not be used.
Figure 7 shows both the register only and the register/latch configuration in a slice, both
are available.

UG384 (v1.1) February 23, 2010
Registers Only Registers or Latches

DFF DFF/LATCH
LUT D O6 Output
SRINIT1 FF
LUT D O5 SRINIT0 Q DQ LATCH Q DQ
D D SRINIT1
Output CE CE SRINIT0
DX
CK CK
SR SR
CFF CFF/LATCH
LUT C O6 Output
SRINIT1 FF
LUT C O5 SRINIT0 Q CQ LATCH Q CQ
D D SRINIT1
Output
CE CX CE SRINIT0
CK CK
SR SR
Reset Type Reset Type

Sync Sync
Async Async
BFF BFF/LATCH
LUT B O6 Output
SRINIT1 FF
LUT B O5 SRINIT0 Q BQ LATCH Q BQ
D D SRINIT1
BX
CK CK
SR SR
AFF AFF/LATCH
LUT A O6 Output
SRINIT1 Q FF
AQ LATCH Q AQ
LUT A O5 D
SRINIT0
D SRINIT1
AX
CK CK
SR SR
ug384_06_042309
Figure 7: Configuration in a Slice: 4 Registers Only and 4 Register/Latch
The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all
storage elements in one slice. When one flip-flop in a slice has SR or CE enabled, the other
flip-flops used in the slice will also have SR or CE enabled by the common signal. Only the
CLK signal has independent polarity but applies it to all eight storage elements. Any
inverter placed on the clock signal is automatically absorbed. The CE and SR signals are
active High. All flip-flop and latch primitives have CE and non-CE versions. The SR signal
always has priority over CE.
Initialization
The SR signal forces the storage element into the initial state specified by SRINIT1 or
SRINIT0. SRINIT1 forces a logic High at the storage element output when SR is asserted,
while SRINIT0 forces a logic Low at the storage element output (see Table 4).

UG384 (v1.1) February 23, 2010
Table 4: Truth Table When Using SRINIT
SR SRINIT Function
0 SRINIT0 (default) No Logic Change
1 SRINIT0 (default) 0
0 SRINIT1 No Logic Change
1 SRINIT1 1
SRINIT0 and SRINIT1 can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) is common to all
eight storage elements and cannot be set individually for each storage element in a slice.
The initial state after configuration or global initial state is also defined by the same SRINIT
option. The initial state is set whenever the Global Set/Reset (GSR) signal is asserted. The
GSR signal is always asserted during configuration, and can be controlled after
configuration by using the STARTUP_SPARTAN6 primitive. To maximize design
flexibility and utilization, use the GSR and avoid local initialization signals.
The initial state of any storage element (SRINIT) is defined in the design either by the INIT
attribute or by the use of a set or reset. If both methods are used, they must both be 0 or
both be 1. INIT = 0 or a reset selects SRINIT0, and INIT = 1 or a set selects SRINIT1.
The storage element must be initialized to the same value both by the global power-up or
GSR signal, and by the local SR input to the slice. A storage element cannot have both set
and reset, unless one is defined as a synchronous function so that it can be placed in the
LUT. Avoid instantiating primitives with the control input while specifying the INIT
attribute in an opposite state, for example, an FDRE with a reset input and the INIT
attribute set to 1. Care should be taken when re-targeting designs from another technology
to the Spartan-6 architecture. If converting an existing FPGA design, avoid primitives that
use both set and reset, such as the FDCPE primitive.
Each of the eight flip-flops in a slice must use the same SR input, although they can be
initialized to different values. A second initialization control will require implementation
in a separate slice, so minimize the number of initialization signals. The SR could be turned
off for all flip-flops in a slice and implemented independently for each flip-flop by
implementing it synchronously in the LUT.
The SR signal is available to the flip-flop, independent of whether the LUT is used as a
distributed RAM or shift register, which supports a registered read from distributed RAM
or an additional pipeline stage in a shift register while still allowing initialization.
The configuration options for the set and reset functionality of a register or the four storage
elements capable of functioning as a latch are as follows:
• No set or reset
• Synchronous set
• Synchronous reset
• Asynchronous set (preset)
• Asynchronous reset (clear)
Distributed RAM and Memory (SLICEM only)

The function generators in SLICEMs add a data input and write enable that allows the
function generator to be implemented as distributed RAM. RAM resources are

UG384 (v1.1) February 23, 2010
configurable within a SLICEM to implement the distributed RAM shown in Table 5.
Multiple LUTs in a SLICEM can be combined in various ways to store more data.
Distributed RAM is fast, localized, and ideal for small data buffers, FIFOs, or register files.
For larger memory requirements, consider using the 18K block RAM resources.
Distributed RAM are synchronous (write) and asynchronous (read) resources. However, a
synchronous read resource can be implemented with a storage element or a flip-flop in the
same slice. By placing this flip-flop, the distributed RAM performance is improved by
decreasing the delay into the clock-to-out value of the flip-flop. However, an additional
clock latency is added. The distributed resources share the same clock input. For a write
operation, the Write Enable (WE) input, driven by either the CE or WE pin of a SLICEM,
must be set High.
Table 5 shows the number of LUTs (four per slice) occupied by each distributed RAM
configuration.
Table 5: Distributed RAM Configuration

Number of
RAM Description
LUTs
32 x 2Q(2) 4 Quad-Port 32 x 2-bit RAM
32 x 6SDP(2) 4 Simple Dual-Port 32 x 6-bit RAM
64 x 1S 1 Single-Port 64 x 1-bit RAM
64 x 1D 2 Dual-Port 64 x 1-bit RAM
64 x 1Q(3) 4 Quad-Port 64 x 1-bit RAM
64 x 3SDP(3) 4 Simple Dual-Port 64 x 3-bit RAM
128 x 1D 4 Dual-Port 128 x 1-bit RAM
Notes:
1. S = single-port configuration; D = dual-port configuration; Q = quad-port configuration; SDP = simple
dual-port configuration.
2. RAM32M is the associated primitive for this configuration.
3. RAM64M is the associated primitive for this configuration.
For single-port configurations, distributed RAM has a common address port for
synchronous writes and asynchronous reads. For dual-port configurations, distributed
RAM has one port for synchronous writes and asynchronous reads, and another port for
asynchronous reads. In simple dual-port configuration, there is no data out (read port)
from the write port. For quad-port configurations, distributed RAM has one port for
synchronous writes and asynchronous reads, and three additional ports for asynchronous
reads.
In single-port mode, read and write addresses share the same address bus. In dual-port
mode, one function generator is connected with the shared read and write port address.
The second function generator has the A inputs connected to a second read-only port
address and the WA inputs shared with the first read/write port address.
Figure 8 through Figure 16 illustrate various example distributed RAM configurations
occupying one SLICEM. When using x2 configuration (RAM32X2Q), A6 and WA6 are
driven High by the software to keep O5 and O6 independent.

UG384 (v1.1) February 23, 2010
RAM 32X2Q
DPRAM32
(DX)
DID[1] DI1 O6 DOD[0]
(AI/BI/CI/DI)
DID[0] DI2
D[5:1] 5
ADDRD[4:0] A[6:1]
5
WA[6:1]
(CLK)
WCLK CLK O5 DOD[1]
(WE)
WED WE
DPRAM32
DI1 O6 DOC[0]
DI2
C[5:1] 5
ADDRC[4:0] A[6:1]
5
WA[6:1]
CLK O5 DOC[1]
WE
DPRAM32
DI1 O6 DOB[0]
DI2
B[5:1] 5
ADDRB[4:0] A[6:1]
5
WA[6:1]
CLK O5 DOB[1]
WE
DPRAM32
DI1 O6 DOA[0]
DI2
A[5:1] 5
ADDRA[4:0] A[6:1]
5
WA[6:1]
CLK O5 DOA[1]
WE
ug384_07_042309
Figure 8: Distributed RAM (RAM32X2Q)

UG384 (v1.1) February 23, 2010
RAM 32X6SDP
DPRAM32
unused DI1
unused DI2
WADDR[5:1] D[5:1] 5
A[6:1]
WADDR[6] = 1 5
WA[6:1]
(CLK)
WCLK CLK
(WE)
WED WE
DPRAM32
DATA[1] DI1 O6 O[1]
DATA[2] DI2
C[5:1] 5
RADDR[5:1] A[6:1]
RADDR[6] = 1 5
WA[6:1]
CLK O5 O[2]
WE
DPRAM32
DATA[3] DI1 O6 O[3]
DATA[4] DI2
B[5:1] 5
A[6:1]
5
WA[6:1]
CLK O5 O[4]
WE
DPRAM32
DATA[5] DI1 O6 O[5]
DATA[6] DI2
A[5:1] 5
A[6:1]
5
WA[6:1]
CLK O5 O[6]
WE
ug384_08_042309
Figure 9: Distributed RAM (RAM32X6SDP)

UG384 (v1.1) February 23, 2010
RAM64X1S
SPRAM64
(DX) O
D DI1 O6 Output
6 (D[6:1]) Registered
A[5:0] A[6:1] D Q
Output
6
WA[6:1]
(CLK) (Optional)
WCLK CLK
(WE/CE)
WE WE
ug384_09_042309
Figure 10: Distributed RAM (RAM64X1S)
If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 64 x 4-bit single-port distributed RAM.
RAM64X1D
DPRAM64
(DX) SPO
D DI1 O6
(D[6:1]) 6 Registered
A[5:0] A[6:1] D Q
Output
6
WA[6:1]
(CLK) (Optional)
WCLK CLK
(WE/CE)
WE WE
DPRAM64
DPO
DI1 O6
(C[6:1]) 6 Registered
DPRA[5:0] A[6:1] D Q
Output
6
WA[6:1]
(Optional)
CLK
WE
ug384_10_042309
Figure 11: Distributed RAM (RAM64X1D)
If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a
SLICEM, as long as they share the same clock, write enable, and shared read and write port
address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM.

UG384 (v1.1) February 23, 2010
RAM64X1Q
DPRAM64
(DX) DOD
DID DI1 O6
(D[6:1]) Registered
ADDRD A[6:1] D Q Output
WA[6:1]
(CLK)
WCLK CLK
(WE) (Optional)
WE WE
DPRAM64
DI1 DOC
O6
(C[6:1])
ADDRC A[6:1] Registered
D Q Output
WA[6:1]
CLK
WE (Optional)
DPRAM64
DOB
DI1 O6
(B[6:1]) Registered
ADDRB A[6:1] D Q Output
WA[6:1]
CLK
WE (Optional)
DPRAM64
DOA
DI1 O6
(A[6:1]) Registered
ADDRA A[6:1] D Q Output
WA[6:1]
CLK
WE (Optional)
ug384_11_042309
Figure 12: Distributed RAM (RAM64X1Q)

UG384 (v1.1) February 23, 2010
RAM 64X3SDP
DPRAM32
unused DI1
unused DI2
D[6:1] 6
WADDR[6:1] A[6:1]
6
WA[6:1]
(CLK)
WCLK CLK
(WE)
WED WE
DPRAM32
DATA[1] DI1 O6 O[1]
DI2
C[6:1] 6
RADDR[6:1] A[6:1]
6
WA[6:1]
CLK O5
WE
DPRAM32
DATA[2] DI1 O6 O[2]
DI2
B[6:1] 6
A[6:1]
6
WA[6:1]
CLK O5
WE
DPRAM32
DATA[3] DI1 O6 O[3]
DI2
A[6:1] 6
A[6:1]
6
WA[6:1]
CLK O5
WE
ug384_12_042309
Figure 13: Distributed RAM (RAM64X3SDP)
Implementation of distributed RAM configurations with depth greater than 64 requires the
usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX).

UG384 (v1.1) February 23, 2010
RAM128X1S
A6 (CX)
SPRAM64
(DX)
D DI1 O6
[5:0]
A[6:0] A[6:1]
7
WA[7:1]
(CLK)
WCLK CLK
(WE/CE)
WE WE
0
Output
SPRAM64 Registered
F7BMUX D Q
Output
DI1 O6
[5:0]
(Optional)
A[6:1]
7
WA[7:1]
CLK
WE
ug384_13_042309
If two single-port 128 x 1-bit modules are built, the two RAM128X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM.

UG384 (v1.1) February 23, 2010
RAM128X1D
A6 (CX)
DPRAM64
DX
D DI1 O6
6
A[6:0] A[6:1]
7
WA[7:1]
(CLK)
WCLK CLK
(WE)
WE WE
SPO
DPRAM64 Registered
F7BMUX D Q
Output
DI1 O6
(Optional)
6
A[6:1]
7
WA[7:1]
CLK
WE
DPRAM64
DI1 O6
6
DPRA[6:0] A[6:1]
7
WA[7:1]
CLK
WE
DPO
DPRAM64 Registered
F7AMUX D Q
Output
DI1 O6
(Optional)
6
A[6:1]
7
WA[7:1]
CLK
WE
AX
ug384_14_042309
Figure 15: Distributed RAM (RAM128X1D)

UG384 (v1.1) February 23, 2010
RAM256X1S
SPRAM64
D DI1 O6
6
A[7:0] A[6:1]
8
WA[8:1]
(CLK)
WCLK CLK
(WE/CE) A6 (CX)
WE WE
SPRAM64 F7BMUX
DI1 O6
6
A[6:1]
8
WA[8:1]
A7 (BX)
CLK
WE O
Output
Registered
F8MUX D Q
SPRAM64 Output
DI1 O6 (Optional)
6
A[6:1]
8
WA[8:1] A6 (AX)
CLK
WE
SPRAM64 F7AMUX
DI1 O6
6
A[6:1]
8
WA[8:1]
CLK
WE
ug384_15_042309
Distributed RAM configurations larger than the examples provided in Figure 8 through
Figure 16 require more than one SLICEM. There are no direct connections to form larger
distributed RAM configurations within a CLB or between slices.
Using distributed RAM for memory depths of 64 bits or less is generally more efficient
than block RAM in terms of resources, performance, and power. For depths greater than 64
bits but less than or equal to 128 bits, use the following guidelines:
• To conserve LUT resources, use any extra block RAM
• For asynchronous read capability, use distributed RAM
• For widths greater than 16 bits, use block RAM

UG384 (v1.1) February 23, 2010
• For shorter clock-to-out timing and fewer placement restrictions, use registered
distributed RAM
Distributed RAM Data Flow

Synchronous Write Operation
The synchronous write operation is a single clock-edge operation with an active-High
write-enable (WE) feature. When WE is High, the input (D) is loaded into the memory
location at address A.
Asynchronous Read Operation

The output is determined by the address A (for single-port mode output/SPO output of
dual-port mode), or address DPRA (DPO output of dual-port mode). Each time a new
address is applied to the address pins, the data value in the memory location of that
address is available on the output after the time delay to access the LUT. This operation is
asynchronous and independent of the clock signal.
Distributed RAM Summary

• Single-port and dual-port modes are available in SLICEMs.
• A write operation requires one clock edge.
• Read operations are asynchronous (Q output).
• The data input has a setup-to-clock timing specification.
Read Only Memory (ROM)

Each function generator can implement a 64 x 1-bit ROM. Three configurations are
available: ROM64x1, ROM128x1, and ROM256x1. ROM contents are loaded at each device
configuration. Table 6 shows the number of LUTs occupied by each ROM configuration.
Table 6: ROM Configuration

ROM Number of LUTs
64 x 1 1
128 x 1 2
256 x 1 4
Shift Registers (SLICEM only)

A SLICEM function generator can also be configured as a 32-bit shift register without using
the flip-flops available in a slice. Used in this way, each LUT can delay serial data
anywhere from one to 32 clock cycles. The shiftin D (DI1 LUT pin) and shiftout Q31 (MC31
LUT pin) lines cascade LUTs to form larger shift registers. The four LUTs in a SLICEM are
thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift
registers across more than one SLICEM. Note that there are no direct connections between
slices to form longer shift registers, nor is the MC31 output at LUT B/C/D available. The
resulting programmable delays can be used to balance the timing of data pipelines.
Applications requiring delay or latency compensation use these shift registers to develop
efficient designs. Shift registers are also useful in synchronous FIFO and content
addressable memory (CAM) designs.

UG384 (v1.1) February 23, 2010
The write operation is synchronous with a clock input (CLK) and an optional clock enable
(CE). A dynamic read access is performed through the 5-bit address bus, A[4:0]. The LSB of
the LUT is unused and the software automatically ties it to a logic High. The configurable
shift registers cannot be set or reset. The read is asynchronous; however, a storage element
or flip-flop is available to implement a synchronous read. In this case, the clock-to-out of
the flip-flop determines the overall delay and improves performance. However, one
additional cycle of clock latency is added. Any of the 32 bits can be read out
asynchronously (at the O6 LUT outputs) by varying the 5-bit address. This capability is
useful in creating smaller shift registers (less than 32 bits). For example, when building a
13-bit shift register, simply set the address to the 13th bit. Figure 17 is a logic block diagram
of a 32-bit shift register.
SRLC32E
SHIFTIN (MC31 of Previous LUT)
SRL32
(AX)
SHIFTIN (D) DI1
MC31
SHIFTOUT (Q31)
5 (A[6:2])
A[4:0] A[6:2]
(CLK) O6 Output (Q)

CLK CLK
(WE/CE) (AQ) Registered
CE CE D Q
Output
(Optional)
ug384_16_042309
Figure 17: 32-bit Shift Register Configuration
Figure 18 illustrates an example shift register configuration occupying one function

generator.
32-bit Shift Register

SHIFTIN (D)
WE SHIFTOUT(Q31)
CLK
5
Address (A[4:0]) MUX
Q ug384_17_042309
Figure 18: Representation of a Shift Register
Figure 19 shows two 16-bit shift registers. The example shown can be implemented in a
single LUT.

UG384 (v1.1) February 23, 2010
SRL16
SHIFTIN1 (AX) DI1 O5
4
A[3:0] A[5:2]
CLK CLK
CE WE
SRL16
SHIFTIN2 (AI) DI2 O6
4
A[5:2] MC31
CLK
WE
ug384_18_042309
Figure 19: Dual 16-bit Shift Register Configuration
As mentioned earlier, an additional output (MC31) and a dedicated connection between

shift registers allows connecting the last bit of one shift register to the first bit of the next,
without using the LUT O6 output. Longer shift registers can be built with dynamic access
to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX
multiplexers allow up to a 128-bit shift register with addressable access to be implemented
in one SLICEM. Figure 20 through Figure 22 illustrate various example shift register
configurations that can occupy one SLICEM.
SRL32
SHIFTIN (D) DI1 O6
5
A[5:0] A[6:2]
MC31 A5 (AX)
(CLK)
CLK CLK
(WE/CE)
WE WE
Output (Q)
(AQ) Registered
SRL32 F7AMUX D Q
Output
DI1 O6
(Optional)
5 (MC31)
A[6:2] MC31
CLK
WE SHIFTOUT (Q63)
ug384_19_042309

UG384 (v1.1) February 23, 2010
CX (A5)
SRL32
SHIFTIN (D) DI1 O6
5
A[6:0] A[6:2]
MC31 F7BMUX
BX (A6)
(CLK)
CLK CLK
(WE/CE)
WE WE (BMUX)
Output (Q)
(BQ) Registered
F8MUX D Q
Output
SRL32 (Optional)
DI1 O6
5
A[6:2]
MC31
CLK
WE
AX (A5)
SRL32
Not Used
DI1 O6
F7AMUX
5
A[6:2]
CLK
WE UG384_20_042309

UG384 (v1.1) February 23, 2010
SRL32
SHIFTIN (D) DI1 O6
5
A[6:0] A[6:2]
MC31 CX (A5)
(CLK)
CLK CLK
(WE/CE)
WE WE
SRL32 F7BMUX
DI1 O6
A[6:2] BX (A6)
MC31
CLK
WE (BMUX)
Output (Q)
(BQ) Registered
D Q
F8MUX Output
SRL32 (Optional)
DI1 O6
A[6:2]
MC31 AX (A5)
CLK
WE
SRL32
F7AMUX
DI1 O6
A[6:2]
(MC31)
MC31
CLK SHIFTOUT (Q127)
WE
ug384_21_042309
It is possible to create shift registers longer than 128 bits across more than one SLICEM.
However, there are no direct connections between slices to form these shift registers.

UG384 (v1.1) February 23, 2010
Shift Register Data Flow
Shift Operation
The shift operation is a single clock-edge operation, with an active-High clock enable
feature. When enable is High, the input (D) is loaded into the first bit of the shift register.
Each bit is also shifted to the next highest bit position. In a cascadable shift register
configuration, the last bit is shifted out on the M31 output.
The bit selected by the 5-bit address port (A[4:0]) appears on the Q output.
Dynamic Read Operation

The Q output is determined by the 5-bit address. Each time a new address is applied to the
5-input address pins, the new bit position value is available on the Q output after the time
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock-enable signals.
Static Read Operation

If the 5-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from 1 to 16 bits in one LUT. The shift register length
is (N+1), where N is the input address (0 – 31).
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Shift Register Summary

• A shift operation requires one clock edge.
• Dynamic-length read operations are asynchronous (Q output).
• Static-length read operations are synchronous (Q output).
• The data input has a setup-to-clock timing specification.
• In a cascadable configuration, the Q31 output always contains the last bit value.
• The Q31 output changes synchronously after each shift operation.
Multiplexers
Function generators and associated multiplexers in SLICEL or SLICEM can implement the
following:
• 4:1 multiplexers using one LUT
• 8:1 multiplexers using two LUTs
• 16:1 multiplexers using four LUTs
These wide input multiplexers are implemented in one level or logic (or LUT) using the
dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT
combinations of up to four LUTs in a slice. Dedicated multiplexers can be automatically
inferred from the design, or the specific primitives can be instantiated. See WP309:
Targeting and Retargeting Guide for Spartan-6 FPGAs White Paper.

UG384 (v1.1) February 23, 2010
Designing Large Multiplexers
4:1 Multiplexer
Each LUT can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flip-
flop in the same slice. Up to four 4:1 MUXes can be implemented in a slice, as shown in
Figure 23.
SLICE
LUT
(D)
O6 4:1 MUX Output
(D[6:1]) 6 (DQ) Registered
SEL D [1:0], DATA D [3:0] D Q
A[6:1] Output
Input
(Optional)
LUT
(C)
O6 4:1 MUX Output
SEL C [1:0], DATA C [3:0] (C[6:1]) 6 (CQ) Registered

A[6:1] D Q
Input Output
(Optional)
LUT
(B)
O6 4:1 MUX Output
(B[6:1]) 6 (BQ) Registered
SEL B [1:0], DATA B [3:0] A[6:1] D Q
Output
Input
(Optional)
LUT
(A)
O6 4:1 MUX Output
(A[6:1]) (AQ) Registered
SEL A [1:0], DATA A [3:0] 6 D Q
A[6:1] Output
Input
(CLK) (Optional)
CLK
ug384_22_042309
Figure 23: Four 4:1 Multiplexers in a Slice

UG384 (v1.1) February 23, 2010
8:1 Multiplexer
Each SLICEL or SLICEM has an F7AMUX and an F7BMUX. These two multiplexers
combine the output of two LUTs to form a combinatorial function up to 13 inputs (or an 8:1
MUX). Up to two 8:1 MUXes can be implemented in a slice, as shown in Figure 24.
SLICE
LUT
O6
SEL D [1:0], DATA D [3:0] (D[6:1]) 6

A[6:1] F7BMUX
Input (1)
(CMUX)
8:1 MUX
LUT Output (1)
(CQ) Registered
O6 D Q
Output
SEL C [1:0], DATA C [3:0] (C[6:1]) 6
A[6:1]
Input (1)
(Optional)
(CX)
SELF7(1)
(CLK)
CLK
LUT
O6
(B[6:1]) 6
SEL B [1:0], DATA B [3:0] A[6:1]
Input (2) F7AMUX
(AMUX)
8:1 MUX
LUT Output (2)
(AQ) Registered
O6 D Q
Output
(A[6:1])
SEL A [1:0], DATA A [3:0] 6
A[6:1]
Input (2)
(Optional)
(AX)
SELF7(2)
ug384_23_042309
Figure 24: Two 8:1 Multiplexers in a Slice

UG384 (v1.1) February 23, 2010
16:1 Multiplexer
Each SLICEL or SLICEM has an F8MUX. F8MUX combines the outputs of F7AMUX and
F7BMUX to form a combinatorial function up to 27 inputs (or a 16:1 MUX). Only one 16:1
MUX can be implemented in a slice, as shown in Figure 25.
SLICE
LUT
O6
(D[6:1]) 6
SEL D [1:0], DATA D [3:0] A[6:1] F7BMUX
Input
LUT
O6
SEL C [1:0], DATA C [3:0] (C[6:1]) 6

A[6:1]
Input
F8MUX
(CX) (BMUX) 16:1 MUX

SELF7
Output
LUT
(B) Registered
D Q
O6 Output
SEL B [1:0], DATA B [3:0] (B[6:1]) 6

A[6:1] F7AMUX (Optional)
Input
LUT
O6
SEL A [1:0], DATA A [3:0] (A[6:1])
6
Input A[6:1]
(AX)
SELF7
(BX)
SELF8
(CLK)
CLK
ug384_24_042309
Figure 25: 16:1 Multiplexer in a Slice
It is possible to create multiplexers wider than 16:1 across more than one SLICEM.
However, there are no direct connections between slices to form these wide multiplexers.
Fast Lookahead Carry Logic

In addition to function generators, SLICEM and SLICEL (but not SLICEX) contain
dedicated carry logic to perform fast arithmetic addition and subtraction in a slice. A CLB
has one carry chain, as shown in Figure 1. The carry chains are cascadable to form wider
add/subtract logic, as shown in Figure 2.
The carry chain in the Spartan-6 device is running upward and has a height of four bits per
slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for
adding/subtracting the operands with a selected carry bits. Typically, the carry logic

UG384 (v1.1) February 23, 2010
allows four bits of a counter or other arithmetic function to fit in each slice, independent of
the function's total size. The dedicated carry path and carry multiplexer (MUXCY) can also
be used to cascade function generators for implementing wide logic functions.
Figure 26 illustrates the carry chain with associated logic elements in a slice.
COUT (To Next Slice)

Carry Chain Block
(CARRY4)
CO3
DMUX/DQ*
S3
O6 From LUTD MUXCY
O3
DMUX
O5 From LUTD DI3
DX D Q DQ
(Optional)
CO2
CMUX/CQ*
S2
O6 From LUTC MUXCY
O2
CMUX
O5 From LUTC DI2
CX D Q CQ
(Optional)
CO1
BMUX/BQ*
S1
O6 From LUTB MUXCY
O1
BMUX
O5 From LUTB DI1
BX D Q BQ
(Optional)
CO0
AMUX/AQ*
S0
O6 From LUTA MUXCY
O0
AMUX
O5 From LUTA DI0
AX D Q AQ
CYINIT CIN (Optional)
* Can be used if
01 unregistered/registered
outputs are free.
CIN (From Previous Slice)
ug384_25_042309
Figure 26: Fast Carry Logic Path and Associated Elements
The carry chains carry lookahead logic along with the function generators. There are ten
independent inputs (S inputs – S0 to S3, DI inputs – DI1 to DI4, CYINIT and CIN) and eight
independent outputs (O outputs – O0 to O3, and CO outputs – CO0 to CO3).
The S inputs are used for the “propagate” signals of the carry lookahead logic. The
“propagate” signals are sourced from the O6 output of a function generator. The DI inputs
are used for the “generate” signals of the carry lookahead logic. The “generate” signals are
sourced from either the O5 output of a function generator or the BYPASS input (AX, BX,

UG384 (v1.1) February 23, 2010
CX, or DX) of a slice. The former input is used to create a multiplier, while the latter is used
to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The
CYINIT value can be 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry
bit). The CIN input is used to cascade slices to form a longer carry chain. The O outputs
contain the sum of the addition/subtraction. The CO outputs compute the carry out for
each bit. CO3 is connected to COUT output of a slice to form a longer carry chain by
cascading multiple slices. The propagation delay for an adder increases linearly with the
number of bits in the operand, as more carry chains are cascaded. The carry chain can be
implemented with a storage element or a flip-flop in the same slice.
Consider using the DSP48A1 slice adders (see the Spartan-6 FPGA DSP48A1 Slice User
Guide) for designs consuming too many carry logic resources.
To conserve carry logic resources when designing with adder trees, the 6-input LUT
architecture can efficiently create ternary addition (A + B + C = D) using the same amount
of resources as simple 2-input addition.
Using the Latch Function as Logic

Since the latch function is level-sensitive, it can be used as the equivalent of a logic gate.
The primitives to specify this function are AND2B1L (a 2-input AND gate with one input
inverted) and OR2L (a 2-input OR gate), as shown in Figure 27.
AND2B1L OR2L
ug384_27_012710
Figure 27: AND2B1L and OR2L Components
As shown in Figure 28, the data and SR inputs and Q output of the latch are used when the
AND2B1L and OR2L primitives are instantiated, and the CK gate and CE gate enables are
held active High. The AND2B1L combines the latch data input (the inverted input on the
gate, DI) with the asynchronous clear input (SRI). The OR2L combines the latch data input
with an asynchronous preset. Generally, the latch data input comes from the output of a
LUT within the same slice, extending the logic capability to another external input. Since
there is only one SR input per slice, using more than one AND2B1L or OR2L per slice
requires a shared common external input.
IN[6:1] O6 Q
LUT6 D Q
VCC
OR2L
CE SRINIT1
CK RESET TYPE = ASYNC
SR
SRI
ug384_28_021610
Figure 28: Implementation of OR2L (Q = D or SRI)

UG384 (v1.1) February 23, 2010
The device model shows these functions as AND2L and OR2L configurations of the
storage element (Figure 3 through Figure 5). The ISE™ software reports these as AND/OR
Logics within the slice utilization report. As shown in Table 7, the two inputs of the OR2L
gate are not architecturally equivalent; DI is the D input to the latch, and SRI is the SR
input.
Table 7: OR2L Logic Table

Inputs Outputs
DI SRI O
0 0 0
0 1 1
1 0 1
1 1 1
The AND2B1L and OR2L two-input gates save LUT resources and are initialized to a
known state on power-up and on GSR assertion. Using these primitives can reduce logic
levels and increase logic density of the device by trading register/latch resources for logic.
However, due to the static inputs required on the clock and clock enable inputs, specifying
one or more AND2B1L or OR2L primitives can cause register packing and density issues in
a slice disallowing the use of the remaining registers and latches.
Interconnect Resources
Interconnect is the programmable network of signal pathways between the inputs and
outputs of functional elements within the FPGA, such as IOBs, CLBs, DSP slices, and block
RAM. Interconnect, also called routing, is segmented for optimal connectivity. The Xilinx
Place and Route (PAR) tool within the ISE Design Suite software exploits the rich
interconnect array to deliver optimal system performance and the fastest compile times.
Most of the interconnect features are transparent to FPGA designers. Knowledge of the
interconnect details can be used to guide design techniques but is not necessary for
efficient FPGA design. Only selected types of interconnect are under user control. These
include the clock routing resources, which are selected by using clock buffers, and
discussed in more detail in the Spartan-6 FPGA Clocking Resources User Guide. Two global
control signals, GTS and GSR, are selected by using the STARTUP_SPARTAN6 primitive,
which is described in Global Controls. Knowledge of the general-purpose routing
resources is helpful when considering floorplanning the layout of a design.
Spartan-6 FPGA Interconnect Types

The Spartan-6 FPGA CLBs are arranged in a regular array inside the FPGA. Each connects
to a switch matrix for access to the general-routing resources, which run vertically and
horizontally between the CLB rows and columns (Figure 29). A similar switch matrix
connects other resources, such as the DSP slices and block RAM resources.

UG384 (v1.1) February 23, 2010
Switch Switch Switch

CLB CLB CLB
Matrix Matrix Matrix

CLB CLB CLB

CLB CLB CLB
ug384_29_012710
Figure 29: CLB Array and Interconnect Channels
The various types of routing in the Spartan-6 architecture are primarily defined by their
length (Figure 30). Longer routing elements are faster for longer distances.
Fast Interconnects
Fast connects route block outputs back to block inputs. Along with the larger size of the
CLB, fast connects provide higher performance for simpler functions.
Single Interconnects
Singles route signals to neighboring tiles, both vertically and horizontally.
Double Interconnects
Doubles connect to every other tile, both horizontally and vertically, in all four directions,
and to the diagonally adjacent tiles.
Quad Interconnects
Quads connect to one out of every four tiles, horizontally and vertically, and diagonally to
tiles two rows and two columns distant. Quad lines provide more flexibility than the
single-channel long lines of earlier generations.

UG384 (v1.1) February 23, 2010
Fast
Single Double Quad
CLB CLB CLB CLB CLB
Double
CLB CLB CLB CLB CLB
Quad
CLB CLB CLB CLB CLB
UG384_30_012710
Figure 30: Examples of Interconnect Types
Interconnect Delay and Optimization

Interconnect delays vary according to the specific implementation and loading in a design.
The type of interconnect, distance required to travel in the device, and number of switch
matrices to traverse factor into the total delay. A good estimate of interconnect delay is to
use the same value as the block delays in a path.
Most timing issues are addressed by examining the block delays and determining the
impact of using fewer levels or faster paths. If interconnect delays seem too long, increase
PAR effort levels or iterations to improve performance along with making sure that the
required timing is in the constraints file.
Nets with critical timing or that are heavily loaded can often be improved by replicating
the source of the net. The dual 5-input LUT configuration of the slice simplifies the
replication of logic in the same slice, which minimizes any additional loads on the inputs to
the source function. Replicating logic in multiple slices gives the software more flexibility
to place the sources independently.
Interconnect delays are typically improved not by changing the interconnect but by
changing the placement. This is the Floorplanning process.
Viewing Interconnect Details with FPGA Editor

The FPGA Editor is used to view the interconnect of a blank device or to view the
interconnect used in an implemented design. FPGA Editor is a graphical application for
displaying and configuring FPGAs.
To access the FPGA Editor, first run place-and-route on your design. Then double-click on
the View/Edit Routed Design (FPGA Editor) process to open FPGA Editor.
For details on using FPGA Editor, see the on-line help within the FPGA Editor application.

UG384 (v1.1) February 23, 2010
Global Controls
In addition to the general-purpose interconnect, Spartan-6 FPGAs have two global logic
control signals, as described in Table 8.
Table 8: Global Logic Control Signals

Global Control Input Description
Global Set/Reset: When High, asynchronously places all registers
and flip-flops in their initial state (see Storage Elements). Asserted
GSR automatically during the FPGA configuration process (see the
Configuration Sequence section in the Spartan-6 FPGA
Configuration User Guide.
Global 3-State: When High, asynchronously forces all I/O pins to a
GTS
high-impedance state (High-Z, 3-state).
Use the GSR control in a design instead of a separate global reset signal to make CLB
inputs available, which results in a smaller more efficient design. The GSR signal must
always re-initialize every flip-flop. The GSR signal is asserted automatically during the
FPGA configuration process, guaranteeing that the FPGA starts up in a known state.
Using GSR and GTS does not use any general-purpose routing resources.
STARTUP_SPARTAN6 Primitive
The GSR and GTS signal sources are defined and connected using the
STARTUP_SPARTAN6 primitive. This primitive allows the user to define the source of
these dedicated nets. GSR and GTS are always active during configuration, and connecting
signals to them on the STARTUP primitive defines how they are controlled after
configuration. By default, they are disabled after configuration on a selected clock cycle of
the start-up phase, enabling the flip-flops and I/Os in the device. The STARTUP primitive
also includes other signals used specifically during configuration. For more information,
read the Spartan-6 FPGA Configuration User Guide.
Interconnect Summary
The flexible interconnect resources of the Spartan-6 family allows efficient implementation
of almost any configuration of logic and I/O resources. The ISE software automatically
places and routes designs to take best advantage of these general-purpose resources.
Dedicated resources for clocks are used when clock buffers are used in a design. Dedicated
resources for global set/reset and global 3-state are controlled by using the
STARTUP_SPARTAN6 primitive.
Floorplanning
Floorplanning is the process of specifying user-placement constraints. Floorplanning can
be done either before or after automatic place and route, but automatic place and route is
always recommended first before specifying user floorplanning. The PlanAhead Design
Analysis tool provides a graphical view of placement, and helps the designer make choices
between RTL coding and synthesis and implementation, with extensive design exploration
and analysis features. More information on the PlanAhead tool is available at:
http://www.xilinx.com/tools/planahead.htm.
For floorplanning and design analysis it is important to understand the general layout and
naming designations for the CLB resources. As shown in Figure 2, CLBs each contain two

UG384 (v1.1) February 23, 2010
slices, with columns of SLICEM/SLICEX CLBs alternating with columns of
SLICEL/SLICEX CLBs. The numbering begins from the bottom left corner. Although all
the I/O blocks are outside the CLB array, the IOI cells sometimes take the place of CLBs on
the perimeter. In addition, columns of block RAM, DSP slices, and clock management tiles
are embedded in the columns of CLBs. Lastly, the GTP transceivers and integrated blocks
for PCI Express are embedded in the top of the array, as well as in the bottom of the array
in the larger devices.
An example floorplan for the XC6SLX45T is shown in Figure 31.
GTP Transceivers
Integrated Block
for PCI Express
IOB Bank
IOB Cells
IOI Cells
Memory Controller
Block
Block RAM
Column
DSP Column
Clock Management
Tile Column
UG384_31_012710
Figure 31: XC6SLX45T Floorplan View in PlanAhead

UG384 (v1.1) February 23, 2010
CLB / Slice Timing Models
Due to the large size and complexity of Spartan-6 FPGAs, understanding the timing
associated with the various paths and functional elements is a difficult and important task.
Although it is not necessary to understand the various timing parameters to implement
most designs using Xilinx software, a thorough timing model can assist advanced users in
analyzing critical paths or planning speed-sensitive designs.
Three timing model sections are described:
• Functional element diagram – basic architectural schematic illustrating pins and
connections
• Timing parameters – definitions of Spartan-6 FPGA Data Sheet timing parameters
• Timing Diagram - illustrates functional element timing parameters relative to each
other
Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer
software (TRCE) and the section on switching characteristics in the Spartan-6 FPGA Data
Sheet. All pin names, parameter names, and paths are consistent with the post-route timing
and pre-route static timing reports. Most of the timing parameters found in the section on
switching characteristics are described in this chapter.
All timing parameters reported in the Spartan-6 FPGA Data Sheet are associated with slices
and CLBs. The following sections correspond to specific switching characteristics sections
in the Spartan-6 FPGA Data Sheet:
• Slice (LUT and Storage Element) Timing Models
• Slice Distributed RAM Timing Model (SLICEM only)
• Slice SRL Timing Model (SLICEM only)
• Slice Carry-Chain Timing Model (SLICEM and SLICEL only)
Slice (LUT and Storage Element) Timing Models

A simplified Spartan-6 FPGA slice is shown in Figure 32. Some elements of the slice are
omitted for clarity. Only the elements relevant to the timing paths described in this section
are shown.

UG384 (v1.1) February 23, 2010
LUT
D 6
O6 D
Inputs
O5
DMUX
FF/LAT
D Q DQ
DX CE
CLK
D Q
SR
CE
CK
LUT SR
F7BMUX
C 6
O6 C
Inputs
O5 CMUX
FF/LAT
D Q CQ
CX
CE
CLK
D Q
SR
F8MUX CE
CK
SR
LUT
B 6
O6 B
Inputs
O5 BMUX
FF/LAT
D Q BQ
BX
CE
CLK
D Q
SR
CE
CK
LUT F7AMUX SR
A 6
O6 A
Inputs
O5 AMUX
AX
D Q
FF/LAT
CE
CK D Q AQ
SR
CE
CE CLK
CLK SR
SR ug384_26_042309
Figure 32: Simplified Spartan-6 FPGA Slice

UG384 (v1.1) February 23, 2010
Timing Parameters
Table 9 shows the general slice timing parameters for a majority of the paths in Figure 32.
Table 9: Slice (LUT and Storage Element) Timing Parameters

Parameter Function Description
Combinatorial Delays
TILO(1) A/B/C/D inputs to A/B/C/D Propagation delay from the A/B/C/D inputs of
outputs the slice, through the look-up tables (LUTs), to the
A/B/C/D outputs of the slice (six-input
function).
TILOF A/B/C/D inputs to Propagation delay from the A/B/C/D inputs of
AMUX/CMUX outputs the slice, through the LUTs and
F7AMUX/F7BMUX to the AMUX/CMUX
outputs (seven-input function).
TOPAB A/B/C/D inputs to BMUX Propagation delay from the A/B/C/D inputs of
output the slice, through the LUTs, F7AMUX/F7BMUX,
and F8MUX to the BMUX output (eight-input
function).
Sequential Delays
TCKO Flip-Flop/ Latch element FF Clock (CLK) to Time after the clock that data is stable at the
AQ/BQ/CQ/DQ outputs AQ/BQ/CQ/DQ outputs of the slice sequential
elements (configured as a flip-flop).
TCKO Flip-Flop only element FF Clock (CLK) to Time after the clock that data is stable at the
elements.
TCKLO Latch Clock (CLK) to Time after the clock that data is stable at the
elements (configured as a latch).
Setup and Hold Times for Slice Sequential Elements(2)
TDICK/TCKDI Flip-Flop/ Latch AX/BX/CX/DX inputs Time before/after the CLK that data from the
element AX/BX/CX/DX inputs of the slice must be stable
at the D input of the slice sequential elements
(configured as a flip-flop).
TDICK/TCKDI Flip-Flop only AX/BX/CX/DX inputs Time before/after the CLK that data from the
element AX/BX/CX/DX inputs of the slice must be stable
at the D input of the slice sequential elements.
TCECK/TCKCE Flip-Flop/ Latch CE input Time before/after the CLK that the CE input of
element the slice must be stable at the CE input of the slice
sequential elements (configured as a flip-flop).
TCECK/TCKCE Flip-Flop only CE input Time before/after the CLK that the CE input of
element the slice must be stable at the CE input of the slice
sequential elements.
TSRCK/TCKSR Flip-Flop/ Latch SR input Time before/after the CLK that the SR inputs of
element the slice must be stable at the SR inputs of the slice
sequential elements (configured as a flip-flop).

UG384 (v1.1) February 23, 2010
Table 9: Slice (LUT and Storage Element) Timing Parameters (Cont’d)
TSRCK/TCKSR Flip-Flop only SR input Time before/after the CLK that the SR inputs of
element the slice must be stable at the SR inputs of the slice
sequential elements
Set/Reset
TSRMIN Minimum Pulse Width for the SR.
TRQ Propagation delay for an asynchronous set/reset
of the slice sequential elements from the SR
inputs to the AQ/BQ/CQ/DQ outputs.
FTOG Toggle Frequency – Maximum frequency that a
CLB flip-flop can be clocked: 1 / (TCH + TCL).
Notes:
1. This parameter includes a LUT configured as two five-input functions.
2. TXXCK = Setup Time (before clock edge), and TCKXX = Hold Time (after clock edge).
Timing Characteristics
Figure 33 illustrates the general timing characteristics of a Spartan-6 FPGA slice.
1 2 3
CLK
TCEO
CE
TDICK
AX/BX/CX/DX
(DATA)
TSRCK
SR (RESET)
TCKO TCKO
AQ/BQ/CQ/DQ
(OUT)
ug384_27_042309
Figure 33: General Slice Timing Characteristics
• At time TCEO before clock event (1), the clock-enable signal becomes valid-high at the
CE input of the slice register.
• At time TDICK before clock event (1), data from either AX, BX, CX, or DX inputs
become valid-high at the D input of the slice register and is reflected on either the AQ,
BQ, CQ, or DQ pin at time TCKO after clock event (1).
• At time TSRCK before clock event (3), the SR signal (configured as synchronous reset)
becomes valid-high, resetting the slice register. This is reflected on the AQ, BQ, CQ, or
DQ pin at time TCKO after clock event (3).

UG384 (v1.1) February 23, 2010
Slice Distributed RAM Timing Model (SLICEM only)
Figure 34 illustrates the details of distributed RAM implemented in a Spartan-6 FPGA
slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the
timing paths described in this section are shown.
RAM
DX DI1
DI DI2 O6 D
6
D input A[6:0]
WA[6:0]
CLK CLK O5 DMUX
WE WE
RAM
CX DI1
CI DI2 O6 C
6
C input A[6:0]
WA[6:0]
CLK O5 CMUX
WE
RAM
BX DI1
BI DI2 O6 B
6
B input A[6:0]
WA[6:0]
CLK O5 BMUX
WE
RAM
AX DI1
AI DI2 O6 A
6
A input A[6:0]
WA[6:0]
CLK O5 AMUX
WE
ug384_29_042309
Figure 34: Simplified Spartan-6 FPGA SLICEM Distributed RAM

UG384 (v1.1) February 23, 2010
Distributed RAM Timing Parameters
Table 10 shows the timing parameters for the distributed RAM in SLICEM for a majority of
the paths in Figure 34.
Table 10: Distributed RAM Timing Parameters

Sequential Delays for a Slice LUT Configured as RAM (Distributed RAM)
TSHCKO(1) CLK to A/B/C/D outputs Time after the CLK of a write operation that the
data written to the distributed RAM is stable on
the A/B/C/D output of the slice.
Setup and Hold Times for a Slice LUT Configured as RAM (Distributed RAM)(2)
TDS/TDH(3) AX/BX/CX/DX configured as Time before/after the clock that data must be
data input (DI1) stable at the AX/BX/CX/DX input of the slice.
TAS/TAH A/B/C/D address inputs Time before/after the clock that address signals
must be stable at the A/B/C/D inputs of the slice
LUT (configured as RAM).
TWS/TWH WE input Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as RAM).
Clock CLK
TMPW Minimum pulse width.
TMCP Minimum clock period to meet address write
cycle time.
Notes:
1. This parameters includes a LUT configured as a two-bit distributed RAM.
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2).

UG384 (v1.1) February 23, 2010
Distributed RAM Timing Characteristics
The timing characteristics of a 16-bit distributed RAM implemented in a Spartan-6 FPGA
slice (LUT configured as RAM) are shown in Figure 35.
1 2 3 4 5 6 7
TMCP
TMPW
TMPW
CLK
TAS
A/B/C/D
2 F 3 4 5 E
(ADDR)
TDS
AX/BX/CX/DX
1 X 0 1 0 X
(DI)
TWS TILO TILO
WE
TSHCKO
DATA_OUT
A/B/C/D 1 MEM(F) 0 1 0 MEM(E)
Output
WRITE READ WRITE WRITE WRITE READ
ug384_29_021610
Figure 35: Slice Distributed RAM Timing Characteristics
Clock Event 1: Write Operation

During a Write operation, the contents of the memory at the address on the ADDR inputs
are changed. The data written to this memory location is reflected on the A/B/C/D
outputs synchronously.
• At time TWS before clock event 1, the write-enable signal (WE) becomes valid-high,
enabling the RAM for a Write operation.
• At time TAS before clock event 1, the address (2) becomes valid at the A/B/C/D
inputs of the RAM.
• At time TDS before clock event 1, the DATA becomes valid (1) at the DI input of the
RAM and is reflected on the A/B/C/D output at time TSHCKO after clock event 1.
This is also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time
TSHCKO and TWOSCO after clock event 1.
Clock Event 2: Read Operation

All Read operations are asynchronous in distributed RAM. As long as WE is Low, the
address bus can be asserted at any time. The contents of the RAM on the address bus are
reflected on the A/B/C/D outputs after a delay of length TILO (propagation delay through
a LUT). The address (F) is asserted after clock event 2, and the contents of the RAM at
address (F) are reflected at the output after a delay of length TILO.

UG384 (v1.1) February 23, 2010
Slice SRL Timing Model (SLICEM only)
Figure 36 illustrates shift register implementation in a Spartan-6 FPGA slice. Some
elements of the slice have been omitted for clarity. Only the elements relevant to the timing
paths described in this section are shown.
SRL
DX DI1
O6 D
D address A MC31
6
CLK WE
CLK
W
SRL
DI1
CX O6 C
C address A MC31
6
CLK WE
SRL
DI1
BX O6 B
B address A MC31
6
CLK WE
SRL
DI1
AX O6 A
A address A MC31 DMUX
6
CLK WE
ug384_30_042309
Figure 36: Simplified Spartan-6 FPGA Slice SRL

UG384 (v1.1) February 23, 2010
Slice SRL Timing Parameters
Table 11 shows the SLICEM SRL timing parameters for a majority of the paths in Figure 36.
Table 11: Slice SRL Timing Parameters

Sequential Delays for a Slice LUT Configured as an SRL
TREG(1) CLK to A/B/C/D outputs Time after the CLK of a write operation that the
data written to the SRL is stable on the A/B/C/D
outputs of the slice.
TREG_MUX(1) CLK to AMUX - DMUX output Time after the CLK of a write operation that the
data written to the SRL is stable on the DMUX
output of the slice.
TREG_M31 CLK to DMUX output via Time after the CLK of a write operation that the
MC31 output data written to the SRL is stable on the DMUX
output via MC31 output.
Setup and Hold Times for a Slice LUT Configured SRL(2)
TWS/TWH CE input (WE) Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as an SRL).
TDS/TDH(3) AX/BX/CX/DX configured as Time before the clock that the data must be stable
data input (DI) at the AX/BX/CX/DX input of the slice
(configured as an SRL).
Notes:
1. This parameter includes a LUT configured as a two-bit shift register.
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2) or two bits with a common shift.
Slice SRL Timing Characteristics

Figure 37 illustrates the timing characteristics of a 16-bit shift register implemented in a
Spartan-6 FPGA slice (a LUT configured as an SRL).
1 2 3 4 5 6 32
CLK
TWS
Write Enable
(WE)
TDS
Shift_In (DI) 0 1 1 0 1 0
Address
0 2 1
(A/B/C/D)
TREG TILO TILO
Data Out
X 0 1 1 0 1 1 0 1
(A/B/C/D)
TREG
MSB
X X X X X X X 0
(MC31/DMUX)
ug384_31_042309
Figure 37: Slice SRL Timing Characteristics

UG384 (v1.1) February 23, 2010
Clock Event 1: Shift In
During a write (Shift In) operation, the single-bit content of the register at the address on
the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to
this register is reflected on the A/B/C/D outputs synchronously, if the address is
unchanged during the clock event. If the A/B/C/D inputs are changed during a clock
event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.
• At time TWS before clock event 1, the write-enable signal (WE) becomes valid-High,
enabling the SRL for the Write operation that follows.
• At time TDS before clock event 1 the data becomes valid (0) at the DI input of the SRL
and is reflected on the A/B/C/D output after a delay of length TREG after clock event
1. Since the address 0 is specified at clock event 1, the data on the DI input is reflected
at A/B/C/D output, because it is written to register 0.
Clock Event 2: Shift In

• At time TDS before clock event 2, the data becomes valid (1) at the DI input of the SRL
and is reflected on the A/B/C/D output after a delay of length TREG after clock event
2. Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
Clock Event 3: Shift In/Addressable (Asynchronous) READ

All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (A/B/C/D outputs) after a delay of length TILO (propagation delay
through a LUT).
• At time TDS before clock event 3, the data becomes valid (1) at the DI input of the SRL
and is reflected on the A/B/C/D output TREG time after clock event 3.
• The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0
(in this example, this was the first data shifted in), and it is reflected on the A/B/C/D
output after a delay of length TILO.
Clock Event 32: MSB (Most Significant Bit) Changes

At time TREG after clock event 32, the first bit shifted into the SRL becomes valid (logical 0
in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is
also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time TREG and
TWOSCO after clock event 1.
Slice Carry-Chain Timing Model (SLICEM and SLICEL only)

Figure 26, page 34 illustrates a carry chain in a Spartan-6 FPGA slice. Some elements of the
slice have been omitted for clarity. Only the elements relevant to the timing paths
described in this section are shown.
Slice Carry-Chain Timing Parameters

Table 12 shows the slice carry-chain timing parameters for a majority of the paths in
Figure 26, page 34.

UG384 (v1.1) February 23, 2010
Table 12: Slice Carry-Chain Timing Parameters
Sequential Delays for Slice LUT Configured as Carry Chain
TAXCY/TBXCY/TCXCY/TDXCY AX/BX/CX/DX input to Propagation delay from the AX/BX/CX/DX
COUT output inputs of the slice to the COUT output of the
slice.
TBYP CIN input to COUT output Propagation delay from the CIN input of the
slice to the COUT output of the slice.
TOPCYA/TOPCYB/TOPCYC/TOPCYD A/B/C/D input to COUT Propagation delay from the A/B/C/D inputs of
output the slice to the COUT output of the slice.
TCINA/TCINB/TCINC/TCIND CIN input to AMUX/BMUX/ Propagation delay from the CIN input of the
CMUX/DMUX output slice to AMUX/BMUX/CMUX/DMUX output
of the slice using XOR (sum).
Setup and Hold Times for a Slice LUT Configured as a Carry Chain(1)
TCINCK/TCKCIN CIN Data inputs Time before the CLK that data from the CIN
input of the slice must be stable at the D input of
the slice sequential elements (configured as a
flip-flop).
Notes:
Slice Carry-Chain Timing Characteristics

Figure 38 illustrates the timing characteristics of a slice carry chain implemented in a
Spartan-6 FPGA slice.
1 2 3
CLK
TCINCK
CIN
(DATA)
TSRCK
SR (RESET)
TCKO TCKO
AQ/BQ/CQ/DQ
(OUT)
ug384_32_042309
Figure 38: Slice Carry-Chain Timing Characteristics
• At time TCINCK before clock event 1, data from CIN input becomes valid-high at the D
input of the slice register. This is reflected on any of the AQ/BQ/CQ/DQ pins at time
TCKO after clock event 1.
• At time TSRCK before clock event 3, the SR signal (configured as synchronous reset)
becomes valid-high, resetting the slice register. This is reflected on any of the
AQ/BQ/CQ/DQ pins at time TCKO after clock event 3.

UG384 (v1.1) February 23, 2010
CLB Primitives
More information on the CLB primitives are available in the software libraries guide.
Distributed RAM Primitives

Seven primitives are available; from 32 x 2 bits to 256 x 1 bit. Three primitives are single-
port RAM, two primitives are dual-port RAM, and two primitives are quad-port RAM, as
shown in Table 13.
Table 13: Single-Port, Dual-Port, and Quad-Port Distributed RAM

Primitive RAM Size Type Address Inputs
RAM32X1S 32-bit Single-port A[4:0] (read/write)
RAM32X1D 32-bit Dual-port A[4:0] (read/write)
DPRA[4:0] (read)
RAM32M 32-bit Quad-port ADDRA[4:0] (read)
ADDRB[4:0] (read)
ADDRC[4:0] (read)
ADDRD[4:0] (read/write)
RAM64X1D 64-bit Dual-port A[5:0] (read/write)
DPRA[5:0] (read)
RAM64M 64-bit Quad-port ADDRA[5:0] (read)
ADDRB[5:0] (read)
ADDRC[5:0] (read)
ADDRD[5:0] (read/write)
RAM128X1D 128-bit Dual-port A[6:0], (read/write)
DPRA[6:0] (read)
The input and output data are 1-bit wide (with the exception of the 32-bit RAM).
Figure 39 shows generic single-port, dual-port, and quad-port distributed RAM
primitives. The A, ADDR, and DPRA signals are address buses.

UG384 (v1.1) February 23, 2010
RAM#X1S RAM#X1D RAM#M

D D DI[A:D][#:0]
O
WE WE SPO WE DOD[#:0]
WCLK WCLK WCLK
A[#:0] A[#:0] R/W Port ADDRD[#:0] R/W Port
DPO
DPRA[#:0] Read Port ADDRC[#:0] Read Port DOC[#:0]
ADDRB[#:0] Read Port DOB[#:0]
ADDRA[#:0] Read Port DOA[#:0]
ug384_33_042309
Figure 39: Single-Port, Dual-Port, and Quad-Port Distributed RAM Primitives
Instantiating several distributed RAM primitives can be used to implement wide memory
blocks.
Port Signals
Each distributed RAM port operates independently of the other while reading the same set
of memory cells.
Clock – WCLK
The clock is used for the synchronous write. The data and the address input pins have
setup times referenced to the WCLK pin.
Enable – WE/WED
The enable pin affects the write functionality of the port. An active write enable prevents
any writing to memory cells. An active write enable causes the clock edge to write the data
input signal to the memory location pointed to by the address inputs.
Address – A[#:0], DPRA[#:0], and ADDRA[#:0] – ADDRD[#:0]

The address inputs A[#:0] (for single-port and dual-port), DPRA[#:0] (for dual-port), and
ADDRA[#:0] – ADDRD[#:0] (for quad-port) select the memory cells for read or write. The
width of the port determines the required address inputs. Some of the address inputs are
not buses in VHDL or Verilog instantiations. Table 13 summarizes the function of each
address pins.
Data In – D, DID[#:0]
The data input D (for single-port and dual-port) and DID[#:0] (for quad-port) provide the
new data value to be written into the RAM.
Data Out – O, SPO, DPO and DOA[#:0] – DOD[#:0]

The data out O (single-port or SPO), DPO (dual-port), and DOA[#:0] – DOD[#:0] (quad-
port) reflects the contents of the memory cells referenced by the address inputs. Following
an active write clock edge, the data out (O, SPO, or DOD[#:0]) reflects the newly written
data.

UG384 (v1.1) February 23, 2010
Inverting Clock Pins
The clock pin (CLK) has an individual inversion option. The clock signal can be active at
the negative edge of the clock or the positive edge for the clock without requiring other
logic resources. The default is at the positive clock edge
Global Set/Reset – GSR

The global set/reset (GSR) signal does not affect distributed RAM modules.
Shift Registers (SRLs) Primitive

One primitive is available for the 32-bit shift register (SRLC32E). Figure 40 shows the
32-bit shift register primitive.
SRLC32E
D
6 Q
A[4:0]
CE
Q31
CLK
ug384_34_042309
Figure 40: 32-bit Shift Register
Instantiating several 32-bit shift register with dedicated multiplexers (F7AMUX, F7BMUX,
and F8MUX) allows a cascadable shift register chain of up to 128-bit in a slice. Figure 20
through Figure 22 in the Shift Registers (SLICEM only) section of this document illustrate
the various implementation of cascadable shift registers greater than 32 bits.
Port Signals
Clock – CLK
Either the rising edge or the falling edge of the clock is used for the synchronous shift
operation. The data and clock enable input pins have setup times referenced to the chosen
edge of CLK.
Data In – D
The data input provides new data (one bit) to be shifted into the shift register.
Clock Enable - CE
The clock enable pin affects shift functionality. An inactive clock enable pin does not shift
data into the shift register and does not write new data. Activating the clock enable allows
the data in (D) to be written to the first location and all data to be shifted by one location.
When available, new data appears on output pins (Q) and the cascadable output pin (Q31).
Address – A[4:0]
The address input selects the bit (range 0 to 31) to be read. The nth bit is available on the
output pin (Q). Address inputs have no effect on the cascadable output pin (Q31). It is
always the last bit of the shift register (bit 31).

UG384 (v1.1) February 23, 2010
Data Out – Q
The data output Q provides the data value (1 bit) selected by the address inputs.
Data Out – Q31 (optional)

The data output Q31 provides the last bit value of the 32-bit shift register. New data
becomes available after each shift-in operation.
Inverting Clock Pins

The clock pin (CLK) has an individual inversion option. The clock signal can be active at
the negative or positive edge of the clock without requiring other logic resources. The
default is positive clock edge.
Global Set/Reset – GSR

The global set/reset (GSR) signal does not affect the shift registers.
Other Shift Register Applications

Synchronous Shift Registers
The shift-register primitive does not use the register available in the same slice. To
implement a fully synchronous read and write shift register, output pin Q must be
connected to a flip-flop. Both the shift register and the flip-flop share the same clock, as
shown in Figure 41.
SRLC32E FF
Synchronous
D Q D Q Output
Address
CE (Write Enable)
CLK Q31
ug384_35_042309
Figure 41: Synchronous Shift Register
This configuration provides a better timing solution and simplifies the design. Because the
flip-flop must be considered to be the last register in the shift-register chain, the static or
dynamic address should point to the desired length minus one. If needed, the cascadable
output can also be registered in a flip-flop.
Static-Length Shift Registers

The cascadable 32-bit shift register implements any static length mode shift register
without the dedicated multiplexers (F7AMUX, F7BMUX, and F8MUX). Figure 42
illustrates a 72-bit shift register. Only the last SRLC32E primitive needs to have its address
inputs tied to 0b00111. Alternatively, shift register length can be limited to 71 bits
(address tied to 0b00110) and a flip-flop can be used as the last register. (In an SRLC32E
primitive, the shift register length is the address input + 1).

UG384 (v1.1) February 23, 2010
LUT LUT
D D D D
Q31 Q31
SRLC32E SRLC32E
LUT LUT
D D
Q31 Q31
SRLC32E SRLC32E
FF
LUT LUT
D Q OUT D Q D Q OUT
(72-bit SRL) (72-bit SRL)
00111 A[4:0] 00110 A[4:0]
5 5
Q31 Q31
SRLC32E SRLC32E
ug384_36_042309
Figure 42: Example Static-Length Shift Register
Multiplexer Primitives
Two primitives (MUXF7 and MUXF8) are available for access to the dedicated F7AMUX,
F7BMUX and F8MUX in each SLICEM or SLICEL. Combined with LUTs, these multiplexer
primitives are also used to build larger width multiplexers (from 8:1 to 16:1). The
Designing Large Multiplexers section provides more information on building larger
multiplexers.
Port Signals
Data In – I0, I1
The data input provides the data to be selected by the select signal (S).
Control In – S
The select input signal determines the data input signal to be connected to the output O.
Logic 0 selects the I0 input, while logic 1 selects the I1 input.
Data Out – O
The data output O provides the data value (one bit) selected by the control inputs.

UG384 (v1.1) February 23, 2010
Carry Chain Primitive
The CARRY4 primitive represents the fast carry logic for a SLICEM or SLICEL in the
Spartan-6 architecture. This primitive works in conjunction with LUTs in order to build
adders and multipliers. This primitive is generally inferred by synthesis tools from
standard RTL code. The synthesis tool can identify the arithmetic and/or logic
functionality that best maps to this logic in terms of performance and area. It also
automatically uses and connects this function properly. Figure 26, page 34 illustrates the
CARRY4 block diagram.
Port Signals
Sum Outputs – O[3:0]
The sum outputs provide the final result of the addition/subtraction.
Carry Outputs – CO[3:0]

The carry outputs provide the carry out for each bit. A longer carry chain can be created if
CO[3] is connected to CI input of another CARRY4 primitive.
Data Inputs – DI[3:0]

The data inputs are used as “generate” signals to the carry lookahead logic. The “generate”
signals are sourced from LUT outputs.
Select Inputs – S[3:0]

The select inputs are used as “propagate” signals to the carry lookahead logic. The
“propagate” signals are sourced from LUT outputs.
Carry Initialize – CYINIT

The carry initialize input is used to select the first bit in a carry chain. The value for this pin
is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit).
Carry In – CI
The carry in input is used to cascade slices to form longer carry chain. To create a longer
carry chain, the CO[3] output of another CARRY4 is simply connected to this pin.

UG384 (v1.1) February 23, 2010
UG384 (v1.1) February 23, 2010

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Configurable Logic Block

UG384 (v1.1) February 23, 2010

Date Version Revision

Preface: About This Guide

Spartan-6 FPGA CLB

Spartan-6 FPGA CLB User Guide www.xilinx.com 3

About This Guide

Spartan-6 FPGA CLB User Guide www.xilinx.com 5

• Spartan-6 FPGA DSP48A1 Slice User Guide

Additional Support Resources

6 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 1: Arrangement of Slices within the CLB

Spartan-6 FPGA CLB User Guide www.xilinx.com 7

Figure 2: Row and Column Relationship between CLBs and Slices

Table 1: Slice Features

8 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 3: Diagram of SLICEM

Spartan-6 FPGA CLB User Guide www.xilinx.com 9

Figure 4: Diagram of SLICEL

10 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 5: Diagram of SLICEX

Spartan-6 FPGA CLB User Guide www.xilinx.com 11

Table 2: Logic Resources in One CLB

Table 3: Spartan-6 FPGA Logic Resources

Look-Up Table (LUT)

12 www.xilinx.com Spartan-6 FPGA CLB User Guide

Spartan-6 FPGA CLB User Guide www.xilinx.com 13

Registers Only Registers or Latches

Reset Type Reset Type

Figure 7: Configuration in a Slice: 4 Registers Only and 4 Register/Latch

14 www.xilinx.com Spartan-6 FPGA CLB User Guide

Distributed RAM and Memory (SLICEM only)

Spartan-6 FPGA CLB User Guide www.xilinx.com 15

Table 5: Distributed RAM Configuration

16 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 8: Distributed RAM (RAM32X2Q)

Spartan-6 FPGA CLB User Guide www.xilinx.com 17

Figure 9: Distributed RAM (RAM32X6SDP)

18 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 10: Distributed RAM (RAM64X1S)

Figure 11: Distributed RAM (RAM64X1D)

Spartan-6 FPGA CLB User Guide www.xilinx.com 19

Figure 12: Distributed RAM (RAM64X1Q)

20 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 13: Distributed RAM (RAM64X3SDP)

Spartan-6 FPGA CLB User Guide www.xilinx.com 21

Figure 14: Distributed RAM (RAM128X1S)

22 www.xilinx.com Spartan-6 FPGA CLB User Guide

Figure 15: Distributed RAM (RAM128X1D)

Spartan-6 FPGA CLB User Guide www.xilinx.com 23

Figure 16: Distributed RAM (RAM256X1S)

24 www.xilinx.com Spartan-6 FPGA CLB User Guide

Distributed RAM Data Flow

Asynchronous Read Operation

Distributed RAM Summary

Read Only Memory (ROM)

Table 6: ROM Configuration

Shift Registers (SLICEM only)

Spartan-6 FPGA CLB User Guide www.xilinx.com 25

SHIFTIN (MC31 of Previous LUT)

(CLK) O6 Output (Q)

Figure 17: 32-bit Shift Register Configuration