VLSI

VLSI Testing
Testing
Introduction
Introduction

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 1
 Reading
Reading Material
Material
™ Text Book:
¾ M.L. Bushnell and V.D. Agrawal, Essentials of
Electronic Testing for Digital, Memory and Mixed-Signal
VLSI Circuits, Springer, 2005
™ Reference Books:
1. H. Fujiwara, Logic Testing and Design for Testability,
MIT Press, 1985
2. M. Abramovici, M. Breuer, and A.D. Friedman, Digital
System Testing and Testable Design, Jayco Pub., 2002
3. S. Mourad and Y. Zorian, Principles of Testing
Electronic Systems, John Wiley, 2000
™ Journals:
¾ IEEE TC, TCAD, and TVLSI
¾ ACM TODAES
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 Acknowledgement
Acknowledgement
¾ Prof. Hideo Fujiwara, NAIST, Japan
¾ Prof. Kewal K. Saluja, Univ. of Wisconsin, USA
¾ Prof. Michiko Inoue, NAIST, Japan
¾ Prof. Vishwani D. Agrawal, Auburn Univ., USA
¾ Prof. Samiha Mourad, Santa Clara Univ., USA
¾ Prof. Erik Larsson, Linkoping Univ., Sweden
¾ Dr. Rubin Parekhji, TI, Bangalore
¾ Dr. Subir Roy, TI, Bangalore

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 VLSI
VLSI Realization
Realization Process
Process
Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabrication
Manufacturing test

Chips to customer
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 Definitions
Definitions
™ Design synthesis: Given an I/O function, develop a
procedure to manufacture a device using known
materials and processes.

™ Verification: Predictive analysis to ensure that the

synthesized design, when manufactured, will perform
the given I/O function.

™ Test: A manufacturing step that ensures that the

physical device, manufactured from the synthesized
design, has no manufacturing defect.

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 Verification
Verification vs.
vs. Test
Test
Verification Test
¾ Verifies correctness of ¾ Verifies correctness of
design. manufactured hardware.
¾ Performed by simulation, ¾ Two-part process:
hardware emulation, or 1. Test generation: software
formal methods. process executed once
during design
2. Test application: electrical
tests applied to hardware
¾ Performed once prior to ¾ Test application performed on
manufacturing. every manufactured device.
¾ Responsible for quality of ¾ Responsible for quality of
design. devices.

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 Problems
Problems of
of Ideal
Ideal Tests
Tests

¾ Ideal tests detect all defects produced in the

manufacturing process.
¾ Ideal tests pass all functionally good devices.
¾ Very large numbers and varieties of possible
defects need to be tested.
¾ Difficult to generate tests for some real defects.
Defect-oriented testing is an open problem.

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 Real
Real Tests
Tests

„ Based on analyzable fault models, which may not

map on real defects.
„ Incomplete coverage of modeled faults due to
high complexity.
„ Some good chips are rejected. The fraction (or
percentage) of such chips is called the yield loss.
„ Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing chips
is called the defect level.

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 Testing
Testing as
as Filter
Filter Process
Process

Good chips Prob(pass test) = high Mostly

good
Prob(good) = y Pr w
ob lo chips
( fa ) =
il st
te
Fabricated Tested
s te
chips s st chips
pa ) =l
( ow
ob
Pr
Defective chips Mostly
bad
Prob(bad) = 1- y Prob(fail test) = high chips

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 Roles
Roles of
of Testing
Testing

™ Detection: Determination whether or not the device

under test (DUT) has some fault.
™ Diagnosis: Identification of a specific fault that is
present on DUT.
™ Device characterization: Determination and
correction of errors in design and/or test
procedure.
™ Failure mode analysis (FMA): Determination of
manufacturing process errors that may have
caused defects on the DUT.

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 Costs
Costs of
of Testing
Testing
„ Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
„ Software processes of test
Test generation and fault simulation
Test programming and debugging
„ Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost

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 Design
Design for
for Testability
Testability (DFT)
(DFT)
DFT refers to hardware design styles or added hardware
that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Primary Logic bus Primary
Logic
inputs block A outputs
block B
(PI) (PO)
Test Test
input output
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 Testing
Testing Principle
Principle

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 ADVANTEST
ADVANTEST Model
Model
T6682
T6682 ATE
ATE

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 Cost
Cost of
of Manufacturing
Manufacturing
Testing
Testing
„ 0.5-1.0GHz; analog instruments; 1,024 digital pins:
ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
„ Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
„ Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
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 Cost
Cost Analysis
Analysis Graph
Graph
40,000 100
al
Fixed, Total and Variable

t
To st

Average Cost (cents)

co
Fixed cost
25,000
Costs ($)

20,000 50

t Average cost
s
co
l e
b
ria
Va
0 0
0 50k 100k 150k 200k
Miles Driven

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 AA Modern
Modern VLSI
VLSI Device
Device
System-on-a-chip
System-on-a-chip (SOC)
(SOC)

DSP RAM
core ROM
Data Transmission
terminal medium
Inter- Mixed-
face signal
logic Codec

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