VLSI Testing

Random
Random Access
Access Scan
Scan Design
Design

Virendra Singh
Indian Institute of Science (IISc)
Bangalore
virendra@computer.org

E0-286: Testing and Verification of SoC Design

Lecture – 18
Mar 7, 2008 E0-286@SERC 1
 No
No Serial
Serial Scan
Scan (???)
(???)
A
A solution
solution to
to test
test power,
power, test
test time
time and
and test
test
data
data volume
volume
„ Three Problems with serial-scan
Test power
Test application time
Test data volume

„ Efforts and limitations

ATPG for low test power consumption
Æ Test power ↓ Test length ↑
Reducing scan clock frequency
Æ Test power ↓ Test application time ↑
Scan-chain re-ordering (with additional logic insertion)
Æ Test power/time ↓ Design time ↑
Test Compression
Æ Test time/data size ↓ Has limited capability for Compacted test

„ Orthogonal attack
Random access scan instead of Serial-scan
Hardware overhead? Silicon cost << Testing cost
Mar 7, 2008 E0-286@SERC 2
 Random
Random Access
Access Scan
Scan
Saluja et al [ITC’04]

™ Architecture
CUT

A d d re s s d e c o d e r(y )
F ilp - flo p s
™ Each FF has unique
address

™ Address shift register

™ X-Y Decoder

™ Select FF to
write/read A d d re s s d e c o d e r(x )

A d d re s s R e g is te r
S c a n - in
Mar 7, 2008 E0-286@SERC 3
 Scan
Scan Operation
Operation Example
Example
„ Scan operation for t2
„ Test vector

t1 t2
Test PPI(ii) PPO(oi) 1 1 1 1
0 0
t1 00101 00110 1 1

0 0 0 0
t2 00100 00101 i1 CUT
0 o1 i2 CUT
0 o2
0 0
1 1
t3 11010 11010 1 1
0 1 0 0
t4 00111 01011 1 0 0 1

Scan-in
operation
„ Complete test application
Total number of scan operation = 15

i1 o1 i2 o 2 i3 o 3 i4 o 4
5 1 5 4
No. of s can
Mar 7, 2008 E0-286@SERC 4
 Test
Test Vector
Vector Ordering
Ordering
„ Test data volume and Test application
time is proportional to the random
access scan operation
„ Goal: Reduce # scan operation
3
V1
5
Test PPI(ii) PPO(oi) 0
3 1 5
t1 00101 00110 1
5
t2 00100 00101 Dummy
t3 11010 11010 V4 2
1
t4 00111 01011 5 4
4
V2 5 V3
5
# Scan operation = 8
4
Mar 7, 2008 E0-286@SERC 5
 Hamming
Hamming Distance
Distance Reduction
Reduction
„ Don’t care values in PPI do not need scan operation
Use Don’t care identification method
Fully specified test vector Æ Vectors w/ X values on targeted bit positions
without loss of fault coverage
1. Before vector ordering: Identify don’t cares in PPI
2. Vector ordering
3. Simulate test vector in order / Fill X’s with previous vectors PPO
4. Identify more X’s on targeted bit in PPI
- odd vector Change allowed
- even vector
5. Repeat 3,4 until no more X’s are identified Targeted

TF1 TF2 TF3 TF4

1 1 0
1 1 X
1 1 1 1
X C X X C X
1 1 C 1 X
1 C 0
U U U U
1 1 1 0
1 1 0 0 0
T T T T
0
X 1 X
1 1 01 1
X
0 0 X
X 0 0 1 X
1 1 1 0

Mar 7, 2008 E0-286@SERC 6

 Optimizing
Optimizing Address
Address Scan
Scan
„ The cost of address shifting
# of scan operation x ASR width
Example address set = { 1, 5, 6, 11 } for 4-bit ASR
4 X 4 = 16
„ Proper ordering of address can minimize shifting cost
Apply 11(1011) after 5(0101) Æ needs only 1 left-shift
„ Minimizing address shifting cost
Construct Address Shifting Distance Graph (ASD-graph)
Find min-cost Hamiltonian path using ATSP algorithm ( Result
: 5 shifts )

0001 G = < V, E >

1

V = Aij = {1,5,6,11}
4 4 3 2
2 3
E = {eij | eij is an edge
between vi and vj}
4 1011
0000 1
w(eij ) =
1
The number of
3
4 2 minimum left-shift
0101 2 0110 operation for the
3
transition
Las t ASR contents of 3 from vi to vj .
prev ious tes t v ector

Mar 7, 2008 E0-286@SERC 7

 Result
Result (Test
(Test Time/Data)
Time/Data)

Test data volume Test Application time

1000K 1000K
900K 900K
800K Serial 800K Serial
700K 700K
RAS RAS
600K 600K

C lo c k s
B its

500K 500K
400K 400K
300K 300K
200K 200K
100K 100K
K K
7s

0s

2s

7s

0s

2s
07

50

32

17

84

07

50

32

17

84
b1

b2

b2

b1

b2

b2
32

58

59

84

85

32

58

59

84

85
s1

s1

s3

s3

s3

s1

s1

s3

s3

s3
Benchmarks Benchmarks

Mar 7, 2008 E0-286@SERC 8

 Result
Result on
on Power
Power Consumption
Consumption
• Switching activity is measured by simulation ( # of switching gate / total # of gate ) X 100 %
Peak Power consumption Avg. Power Consumption

Circuit Serial RAS Rate(%) Serial RAS Rate(%)

s5378 39.76 5 12.58 22.79 0.218 0.957

s9234 42.27 10.81 25.57 25.72 0.22 0.857

s13207 38.8 4.15 10.7 24.93 0.052 0.207

s15850 40.75 8.51 20.89 24.55 0.092 0.374

s35932 21.5 0.21 0.96 6.3 0.032 0.506

s38417 34.58 1.46 4.22 23.62 0.001 0.002

s38584 31.31 18.86 60.23 24.23 0.04 0.165

b17s 30.65 5.01 16.34 13.5 0.004 0.033

b20s 37.87 12.37 32.67 24.39 0.006 0.027

b22s 36.52 8.16 22.34 22.67 0.003 0.015

¾ Peak power consumption is reduced 40% to 99%

¾ Average power consumption is negligible!
Mar 7, 2008 E0-286@SERC 9
 Thank You

Mar 7, 2008 E0-286@SERC 10