Microprocessors

Module 11
Fetch decode execute
cycle
1. Orient the students on the fetch-decode-execute cycle
of a microprocessor.
2. Orient the students on how addresses are decoded.
Exercise:

Connecting a total of 64K x 8 memory to an 8088-based

system using 62255 32K x 8 SRAM chips starting at
address 80000H.

Since the total memory required is 64K x 8 and the

available memory chip is only 32K x 8, then two memory
chips are needed.
Take note that SRAM chip has 15 address lines (since it
has 32K or 32,768 memory locations). If the first chip is
mapped starting at memory address 80000H, then its
ending memory address would be 87FFFH. The second
memory chip should therefore start at memory address
88000H and end at 8FFFFH.
Memory chip capacity 32KB

32K X 1024 = 32768

LOG 32768 / LOG 2 = 15 address lines

80000H 88000H
80001H 88001H
. 1st 32,768 . 2nd 32,768
. Memory memory . Memory memory
Chip locations Chip locations
. .
87FFEH 8FFFEH
87FFFH 8FFFFH
The first connections that should be done is to connect
the 15 address lines of the SRAM chips to A0 to A14 of the
8088 and the 8 data lines of the SRAM chips to D0 to D7
of the 8088. The OE’ line of the memory chip should also
be connected to MEMR’ of the CPU and the WE’ line to
MEMW’.
 D0 D0 D0
D1 D1 D1
. . .
. . .
. . .
1st 2nd
D7 D7 D7
32K x 8 32K x 8
A0 A0 Memory A0 Memory
Chip Chip
A1 A1 A1
. . .
8088 . . .
CPU . . .
A14 A14 CS' OE' WE' A14 CS' OE' WE'
A15
.
.
.
A19

MEMR'
MEMW'
The first memory chip is mapped to addresses 80000H to
87FFFH. In other words, the memory chip should be
activated if the CPU issues out any address between the
given range. By examining the said addresses, it is
easily observed that the bits that are common to these
addresses are:

1000 0000 0000 0000 0000 = 80000H

1000 0111 1111 1111 1111 = 87FFFH
The second memory chip is mapped to addresses
88000H to 8FFFFH. The bits that are common to these
addresses are:

1000 1000 0000 0000 0000 = 88000H

1000 1111 1111 1111 1111 = 8FFFFH
The first SRAM chip should therefore be activated if the
values of A19 to A15 are 10000. The second SRAM chip
should be activated if the values of are A19 to A15 are
10001. The address decoders of the memory interface
circuit should activate the proper memory chip (CS’ = 0)
if these conditions.
 D0 D0 D0
D1 D1 D1
. . .
. . .
. . .
1st 2nd
D7 D7 D7
32K x 8 32K x 8
A0 A0 Memory A0 Memory
Chip Chip
A1 A1 A1
. . .
8088 . . .
CPU . . .
A14 A14 CS' OE' WE' A14 CS' OE' WE'
A15
.
.
.
A19

MEMR'
MEMW'

A19
A18
A17
A16
A15

A19
A18
A17
A16
A15
S. Mathur(2016), Microprocessor and Microcontrollers,
PHI Learning and Private Limited
Taylor and Francis Group. Essentials of Computer
Architecture. CRC Press, Comer, D. (2017).
Jones and Bartlett Learning, Computer Organization And
Architecture (10th Ed.), Stallings, (2016)