Microprocessor and

Interfacing
Ch2_lec4_ Memory Interface

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 Memory Devices
Common types of memory

 ROM: Read Only Memory

 EEPROM: Electrically Erasable Programmable ROM

 SRAM: Static Random Access Memory

 DRAM: Dynamic Random Access Memory

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 Memory Devices
Consist of:

 Address lines (Address Bus)

 Input, Output lines (Data Bus)

 Selection Input (CS)

 Control Input(R/W)

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 Memory Addressing
 The semiconductor memories are organized as two
dimensional arrays of memory locations.
 For example, 4K x 8 or 4K byte memory contains 4096
locations, where each location contains 8-bit data and
only one of the 4096 locations can be selected at a
time.
 To address a memory location out of N memory
locations, it is required at least n bits address, i. e. n
address lines where n = Log2N.

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 Memory Addressing
 The 8086 is a 16-bit microprocessor; it can transfer 16-
bit data. So in addition to byte, word (16-bit) has to be
stored in the memory.
 This is stored by using two consecutive memory
locations, one for least significant byte and the other for
most significant byte.
 The address of word is the address of least significant
byte.
 To access two memory location, the entire memory is
divided into two memory banks:
 bank0 and bank1. Kassahun Tamir 5
Memory Addressing

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 Address Pin Connection
 Select a memory location within the memory device
 Common memory devices have between 1K (1024) to
1G (1,073,741,824)
 A 1K (2^10) memory needs 10 address pins
 Hex representation of 1K is 400
 For a starting address of 1000 the end address will be
13FF

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 Data Pin Connection
 Points at which data are entered for storage or
extracted for Reading

 For 8086 System

 Labelled 𝐷0 to 𝐷 7 for an 8-bit Bank 0 memory

 Labelled 𝐷 8 to 𝐷 15 for an 8-bit Bank 1 memory

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 Selection Pin Connection

 Selects or enables the memory device

 Chip select (CS) is used, and it is generated using:

✗ NAND gate or,
✗ 3-to-8 decoder

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 Control Pin Connection
 ROM usually have one control input
 Output enable RD(OE) or gate (G) (it is a read only memory, so
it has only one pin to enable)

 RAM may have one or two

 If one: (R/W)
 If two: WE(or W ) and OE(or G)

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 Address Decoding
 NAND gate decoder (74LS133)

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 Address Decoding
 One of the most common, although not only, integrated
circuit decoders found in many microprocessor based
system is the 74LS138 3-to-8 line decoder.

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RAM or EPROM Block

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8086 and 74LS138 Block

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 Example
 Design an 8086 based system with the following
specifications.
 64 Kbytes EPROM
 64 Kbytes RAM

 Draw the complete schematic of the design

indicating address map

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 Example
 The 8086 is a 16 bit microprocessor. It can access 16
bit data simultaneously.
 For interfacing memory module to 8086 CPU, it is
necessary to have odd and even memory banks.
 This can be achieved by using two 32 Kbyte EPROMs
and two 32 Kbyte RAMs, one for odd bank another
for even bank.
 As 32 Kbyte RAM and EPROM need 15 address lines,
A1 to A15 lines are used. A0 and BHE are used to
even and odd memory banks respectively.
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Example (Address Line Mapping)

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Example (Put Together)

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Example (74LS138 as a Control
8086 Processor Pins
Signal
74LS138 O/P
Decoder)
Explanation
Signals
M/IO RD WR

0 0 0 Cannot happen Cannot read and write at the same time

0 0 1 I/0 Read

0 1 0 I/O Write

0 1 1 No Operation Both read and write signals aren’t set

1 0 0 Cannot happen Cannot read and write at the same time

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 No OperationKassahun Tamir
Both read and write signals aren’t set 19
 Example (74LS138 as a Chip
Selection Decoder)
Inputs Output
A19 A18 A17 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Notice: Based on the Address Mapping Table (A19 … A0);

1.Y1 is set to 1 when ONLY address line 17 (A17) is 1: we select the RAMs
2.and Y7 is set to 1 when they Kassahun
all areTamir
1: we select the EPROMs 20
Questions?

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