Chapter Five

Memory Interfacing
 Memory Connections
A memory device or memory chip must have three types of lines or
connections:
Address lines
Data lines, and
Control lines
 Address Lines
Address Lines: The input lines that select a memory location
within the memory device.
 Decoders are used, inside the memory chip, to select a Y 00 Location 000
Y 01 Location 001
specific location Y 02 Location 002
 The number of address pins on a memory chip specifies A 00 Y 03 Location 003
A 01
the number of memory locations.
 If a memory chip has 13 address pins (A0..A12), then it A n-2
has: A n-1 Y FC Location 0FC
Y FD Location 0FD
213 = 23 X 210 = 8K locations Y FE Location 0FE
 If a memory chip has 4K locations, then it should have Y FF Location 0FF

N pins:
2N = 4K = 22 X 210 = 212 => N=12 address pins
(A0..A11)
 Data Lines
Data Connections: All memory devices have a set of data output
pins (for ROM devices), or input/output pins (for RAM devices)
Most RAM chips have common bi-directional I/O connections
Most memory devices have 1, 8 or 16 data lines
Data Input Lines
(DI 0..DI n-1)
k- address lines k- address lines
2 m w ords (A 0..A m-1 ) 2 m w ords
(A 0 ..A m-1 )
k- address lines
(A 0..A m-1 ) 2 m w ords Read/Write (R/W) n-bits per Output Enable (OE) n-bits per
Read (RD) Chip Select (CS) w ord Chip Select (CS) w ord
n-bits per
Write (WR) w ord
Chip Select (CS) Data Output Lines
Data Input/Output (D 0..D n-1 )
Lines (D 0 ..D n-1 )
Data Output Lines
(2 m X n) RAM with common I/P (2 m X n) ROM with only O/P Data
(DO 0..DO n-1 )
and O/P Data lines lines
(2 m X n) RAM with separate I/P
and O/P Data lines
 Control Lines
Enable Connections:
 All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device
 If a device is not selected or enabled, then no data can be read from, or written
into it
 The CS or CE input is usually controlled by the microprocessor through the
higher address lines via an address decoding circuit
Control Connections:
 RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals
 Some RAM chips have a common Read/ Write (R/W) signal
 ROM chips can perform only memory read operations, thus there is no need for a
Write (WR) signal
 In most real ROM devices, the Read signal is called the Output Enable (OE)
signal
 Address Decoding
The physical address space, or memory map, of a microprocessor refers to the range
of addresses of memory location that can be accessed by the microprocessor
The size of the address space depends on the number of address lines of the
microprocessor
At least two memory devices are required in a microprocessor system: one for the
ROM and one for the RAM
In an 8086 the high addresses in the memory map should always be occupied by a
ROM, while the low addresses in the memory map should always be occupied by a
RAM
Address decoding is required in order to enable the connection of more than one
memory devices on the microprocessor
Each device will occupy a unique area in the memory map
 Address Decoding Circuits
A number of types of address decoding circuits can be used in a microprocessor
system: NAND Gates, Line Decoders, PLD, Comparators
The main issues related to the selection of an address decoding circuit are:
The time delays introduced by the address decoding circuit
This delays are added to the access time of the memory devices, and might
yield to the insertion of wait states
The number of chips required by the address decoding circuit, as well as the
complexity of the circuit (number of tracks required on the board)
 An address decoding circuit must ensure that an address section is occupied by
only one memory device
If two or more devices occupy the same addresses then bus contention will occur
Bus contention occurs if two of more devices drive the bus at the same time
 Address Decoding Circuits Using Line Decoders
One or more line decoders such as the 74LS139 (2 x 4 decoder) or the
74LS138 (3 x 8 decoder) are used to decode(enable) one out of a number of
memory device
The CS inputs of the decoders are enabled by a NAND decoding circuit,
according to the required memory map
This decoding circuit has the disadvantage that it adds at least three gate
delays in the memory path
The advantage of this circuit is that less gates (NAND, NOT and decoders)
are needed for memory systems that have a number memory of chips
A M
em1M
em2 M
em8 A A A A A A M
emo
ryMa
p
0
19 1
8 1
7 1
6 1
5 1
4 A0
A
14 C
S C
S C
S
0 1 0 0 0 0 0 4
000
0H
ME
M1
3
X 8De
c. 0 1 0 0 0 1 1 4
7FF
FH

A A Y 0 1 0 0 1 0 0 4
800
0H
15 0 ME
M2
A
16
B Y
1
0 1 0 0 1 1 1 4
FFF
FH
A
17
C
A
18 0 1 1 1 1 0 0 7
800
0H
C
S ME
M8
A
19
Y
7 0 1 1 1 1 1 1 7
FFF
FH
 Address Decoding Examples
 Show how a 128Kbyte RAM module can be connected on an 8088
system using 62256 SRAM chips, occupying the address range
starting from the address C0000H. Use Line decoders for address
decoding

Solution:
62256 SRAM chips: A19 A18 A17 A16 A15 A14 A13 A0 Memory Map

 256/8 =32  32KX8 1 1 0 0 0 0 0 0 C0000

RAM1
Number of chips needed: 1 1 0 0 0 1 1 1 C7FFF
 128K/32K = 4 1 1 0 0 1 0 0 0 C8000
RAM2
Number of address lines: 1 1 0 0 1 1 1 1 CFFFF
 32K = 25K = 25 * 210 = 215 1 1 0 1 0 0 0 0 D0000
RAM3
 15 address lines (A0 .. A14) 1 1 0 1 0 1 1 1 D7FFF
1 1 0 1 1 0 0 0 D8000
RAM4
1 1 0 1 1 1 1 1 DFFFF
 Answer: Using a Line Decoder and a NAND Gate

62
256 62
256 62
256 62
256
A
0 D0 A
0 D0 A
0 D0 A
0 D0

D
0 D
7 D
7 D
7 D
7
A
14
A
14
A
14
A
14
R
DWRC
S R
DWRC
S R
DWRC
S R
DWRC
S
D
7

R
D
W
R
A A L
S13
9
0 15 AY
808System

0
A
16 Y
B 1
A
17 Y
A
18
E 2
Y3
A1
9 A
19
IO
/M'
 Homework
Show how a 32Kbyte ROM module can be connected on an 8088
system using 2764 EPROM chips, occupying the address range
starting from the address E0000H
Use A line decoder and a NAND gate address decoding circuits:

Solution: A19 A18 A17 A16 A15 A14 A13 A12 A11 A0 Memory Map
Size of 2764 EPROM chips:

Number of chips needed:

Number of address lines:

Answer: Using a Line Decoder and a NAND Gate

2764 2764 2764 2764

A0 D0 A0 D0 A0 D0 A0 D0

D0 D7 D7 D7 D7
A12 A12 A12 A12
OE CS OE CS OE CS OE CS
D7

RD
WR
8088System

A0

A19
IO/M'
 16-bit Memory Interfacing (8086)
 The 8086 differs from the 8088 in three ways:
 The data bus is 16 bits wide instead of 8 bits as on the 8088
 The IO/M’ signal on the8088 is replaced by the M/IO’ on the 8086
 There is a BHE’ (Bus High Enable) signal to enable the upper data bus lines (D8..D15)
 The address line A0 behaves as the BLE’ (Bus Low Enable) signal
 The memory is separated into the High Bank (odd addresses) and the Low Bank (even addresses)
 The 8086 microprocessor can access either the low bank (D0..D7), or only the high bank (D8..D15), or both banks
(D0..D15)
 There is a need only for separate Bank Write Strobes
 When the processor reads from the memory, it always reads both banks, and selects the necessary bank internally
(BHE') (BLE'/A0)
FFFFF FFFFE
FFFFD FFFFC
FFFFB FFFFA BHE' BLE'(A0) Function Example
0 0 Both banks enabled (16 bit) MOV [1000H],AX
0 1 High bank enabled (8 bit) MOV [1001H],AL
00005 00004 1 0 Low bank enabled (8 bit) MOV [1000H],AL
00003 00002
1 1 No banks enabled ---------------
00001 00000
High Bank (D15..D8) Low Bank (D7..D0)
(Odd Addresses) (Even Addresses)
 16-bit Memory Interfacing Using Separate Bank Decoders
The first decoder (left side) is enabled when A0 is zero, thus it is enable with even addresses. Thus
the data lines of the memory devices decoded by this decoder must be connected on the processor’s
data lines D0..D7.
The second decoder (right side) is enabled when BHE is zero, thus it is enable with odd addresses.
Thus the data lines of the memory devices decoded by this decoder must be connected on the
processor’s data lines D8..D15

D15 A1
62256 A1
62256 A1
62256 A1
62256
A0 D0 A0 D0 A0 D0 A0 D0
D8
D7
A15 A14 D7
A15
A14 D7 A15 A14 D7
A15
A14 D7
RD W R CS RD W R CS RD W R CS RD W R CS
D0
8086 System

RD
WR

A0

Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3
LS139 LS139
A19 A B 1E A B 1E

BHE' IO'/M

A16 A17 A16 A17

A18 A19 A0 A18 A19
 16-bit Memory Interfacing Using Separate Bank Write
Signals
With this method the decoder always enables both banks
On a memory read operation, the data from both banks is loaded on the data bus
The microprocessor selects internally the appropriate bank, according to the instruction being
executed
On a memory write operation, only the WR signal of the appropriate bank is enabled, thus data is
copied only in the appropriate memory chip

D1 5 62256 62256 62256 62256

A1 A1 A1 A1
A0 D0 A0 D0 A0 D0 A0 D0
D8
D7 A 1 4D7 A 1 4D7 A 1 4D7 A 1 4D7
A 15 A 15 A 15 A 15
RD
WRCS RD
WRCS RD
WRCS RD
WRCS
D0
RD
B HE '
8086System

WR
A0
A1 Y Y Y Y
0 1 2 3

LS139
A B 1E

A 19
A 1A
6 17
IO'/M

A 1 8A 1 9