CHAPTER TWO

Programming 8085 Microprocessor

1
 Outline
Introduction
Organization of 8085
-Data and address bus
-Addressing memory and I/O devices
-functional organization of 8085
-registers in 8085 MP
Machine codes
Instruction formats
Addressing modes
Instruction set of 8085 2
 Introduction
• The MP has a set of instructions designed to manipulate data and
communicate with peripherals
• The MP is programmed using these instructions
• The instructions are given to the MP by writing them into a
memory
• The MP:
-Reads or transfer one instruction at a time
-Performs the data manipulation indicated by the instruction
-The result can be stored in memory or sent to o/p devices such
as LEDs or other terminals
• In addition the MP can respond to external signals
-It can be interrupted, reset, or asked to wait to synchronize with
slower peripherals
3
Organization of 8085

4
The Data and Address Busses
• The data bus is 8-bits wide. i.e.8-bits(1 byte) of data can be
transferred to/from 8085 in parallel
• The address bus has 8 signal lines A8 –A15 which are
unidirectional.
•The other 8 address bits are multiplexed(time shared) with the 8
data bits.
-So, the bits AD0 –AD7are bi-directional and serve for both A0 –
A7 and D0 –D7.
-During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of
the execution, they carry the 8 data bits.
• 8085 has a 16-bit address transmission capability. This implies a
total of 216(65536) memory locations can be addressed directly.
• Therefore we say that 8085 can directly address 64K(1k=1024)
bytes of memory. 5
Memory map and addresses
-The memory map is a picture representation of the address range and
shows where the different memory chips are located within the address
range.

6
 • A memory is a circuit that can store bits- high or low, generally
voltage levels or capacity charges representing 1 or 0.
• A flip-flop or a latch is a typical basic element of memory.
• This latch, which can store one binary bit, is called a memory cell.

DIN D Q Dout I7 I0
.......
WR
EN EN WR I/p Buffer
RD
A0 R0 0000
(a) R1 0001
A1 . R2
. 0002
. .

2 16 =65,536
.

Decoder
. .
. . .
A14 . .
A15 R65,535 FFFE
Fig. R65,536 FFFF
A memory cell latch with two tri-state
Buffers (a). Each register Ri in (b) contains RD O/P Buffer
.......
8 D latches or flip-flops. The i/p and o/p
(b) O7 O0
buffers are each of 8-tri-state buffers 7
To communicate with memory, the MP should be able to:
- select a chip
- identify the register
- read from or write in to the register
The memory that is addressed by the MP (RAM or ROM) consists of
one or more LSI chips arranged to provide the designed memory
capacity.

CS WR CS

A0 RD RD
A0
A1 A1
RAM ROM
.....

Memory

.....
Memory
chip chip
2nx8 2nx8
An An

8-bit I/O data bus 8-bit I/O data bus

8
Addressing the I/O devices:
There are two different methods by which I/O devices can be
interfaced to 8085:
1. I/O mapped I/O mode
- treat I/O devices as distinct from the memory and assign them
addresses that do not conflict with the memory addresses.
- The signal is used to distinguish between I/O read/write
operation and memory read/write operation
- The I/O devices can be accessed during IN and OUT instructions

2.Memory mapped I/O mode

- An I/O device is interfaced in the same manner as memory devices
e.g. address 0005 may correspond to a LED display and 0006 to
keyboard. This would mean that no byte in the memory have an
address 0005 or 0006
9
 I/O mapped I/O mode Memory mapped I/O mode
• Only two instructions are • Larger instruction set of
used to access I/O 8085 used to access I/O
devices(IN and OUT) devices
• 8085 treats such an I/O
• All data to/from ports device as a memory
have to be routed through location
the Acc. • Data to/from port can be
• I/o devices are accessed moved to any reg.
with a lesser number of • Fewer memory locations
clocks are available
e.g LDA 16-bit addr
STA 16-bit addr 10
Functional organization of 8085

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 Registers in the 8085 MP
-There are several registers used during the execution
of a program
-we shall describe the size & use of each of these registers
1.Special purpose registers
A. Accumulator(Acc)
-an 8-bit register
-used in various arithmetic & logical operations
E.g during addition of two 8-bit registers, one of the
operand must be in acc. And the other may be in
memory or in one of the other registers
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B. Flag register
-The ALU includes five flip-flops that are set or
reset according to the result of an operation.
-The microprocessor uses the flags for testing the
data conditions.
-They are Zero (Z), Carry (CY), Sign (S), Parity
(P), & Auxiliary Carry (AC) flags. The most
commonly used flags are Sign, Zero, & Carry.
-The bit position for the flags in flag register is,

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-The state of a flag flip flop is changed only, after the execution of an
arithmetic or logic instruction.
1. Sign flag(s):-After executing an arithmetic or logic instruction, if
the most significant bit of the result is 1 then the sign flag is set to
1 else 0.
Example: 35H: 0 0 1 1 0 1 0 1
+82H: 1 0 0 0 0 0 1 0
--------------------------------------------------------
1 0 1 1 0 1 1 1 => s=1

2. Zero flag(z):-After executing an arithmetic or logic instruction, if

the result in accumulator is zero then the zero flag is set else reset.
Example: FFH: 1 1 1 1 1 1 1 1
+01H: 0 0 0 0 0 0 0 1
--------------------------------------------------------
0 0 0 0 0 0 0 0 =>Z=1 14
3. Auxiliary carry flag(Ac):-After executing an arithmetic or logic instruction, if
a carry is generated from low nibble to high nibble then Ac flag is set.
( A carry generated from D3 bit)
Example: 28H : 0 0 1 0 1 0 0 0
+39H: 0 0 1 1 1 0 0 1
--------------------------------------------------------
0 1 1 0 0 0 0 1 => Ac=1
Exercise: 23H
+27H
---------------- Ac?

4. Parity flag(P):-After executing an arithmetic or logic instruction, if the

content of A register contains even number of binary “1”, then parity flag is
set else reset.
Example: 2AH: 0 0 1 0 1 0 1 0
+39H: 0 0 1 1 1 0 0 1
--------------------------------------------------------
0 1 1 0 0 0 1 1 => P=1 15
5. Carry flag(cy):-After executing an arithmetic or logic instruction , if the
operation generates a carry from most significant bit(MSB) position Cy
flag is set.
( A carry generated from D7 bit)
Example: 87H : 1 0 0 0 0 1 1 1
+A2H: 1 0 1 0 1 0 0 1
--------------------------------------------------------
0 0 1 1 0 0 0 0 => cy=1

Exercises
1. Indicate the status flag after performing following operation.
(a) 78H
+99H
----------------------

(b) FCH
+FDH
--------------------- 16
2. General purpose registers
• they are 6 in number & are 8-bit wide
• can be used by a programmer for a variety of
purposes
• they are labeled as B,C,D,E,H & L
• these registers can be used individually, when
operation on 8-bit data is desired, or in pair when
a 16-bit address is to be stored.
• when used in pairs, only the combinations shown
below are permitted.

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3. 16-bit registers
• they are two in number, Program counter and stack
pointer
A. Program counter(PC)
• The program counter (PC) keeps track of program execution
• To execute a program the starting address of the program is loaded
in program counter
• The PC is updated by the processor and points to the next
instruction after it has fetched an instruction(i.e. when a byte
of instruction is fetched, the PC holds the address of the next byte
of the instruction )
• the exact number by w/c the processor updates depends on
the nature of the instruction
e.g 1-byte instruction-updates by 1
3-byte instruction-updates by 3 18
B. Stack pointer(SP)
• The stack is a sequence of RAM memory locations
defined by the programmer
• The stack is used to save the content of registers
during the execution of a program.
• The contents are stored and retrieved in LIFO (Last
In First Out) form.
• Stack pointer- is a 16-bit memory pointing register,
having the last address of the stack in RAM.
• Stack writing instructions fill memory positions in
progressively decreasing addresses
• Increasing/decreasing is always by two bytes since
all stack operations involve register pairs 19
 Machine codes
In the design of the 8085 P chip, all operations, registers, and
status flags are identified with a specific codes.
 Codes for registers  codes for some operations
Code Registers Function code
000 B 1. RLC 00000111 =07H (8-bit code)
001 C
010 D 2. ADD RS 10000 SSS
011 E (5-bits opcode, 3-bits are for a register)
100 H e.g. ADD : 10000
101 L B : 000  ADD B
110 … to A : implicit
111 A binary instruction 10000000 = 80H
110 is reserved for memory-related
3. MOV Rd, Rs 01 DDD SSS
operations
op Rd Rs
Code Register pair e.g. MOV : 01
00 BC to C : 001 (DDD)  MOV C, A
01 DE from A : 111 (SSS)
10 HL Binary instruction 01001111 =4FH
11 SP (2-bit opcode, 6-bits are for registers) 20
 Instruction formats

• An instruction is a binary pattern designed inside

a microprocessor to perform a specific function.
• The instruction set of a P is the collection of the
instructions that the P is designed to execute.
• There are 3 types of instruction based on their
size
1. One byte instructions
2. Two byte instructions
3. Three byte instructions
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One byte instructions
-A 1-byte instruction includes the opcode and operand in the same
byte.
-Operand(s) are internal register and are coded into the instruction

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Two byte instructions
• In a two-byte instruction, the first byte specifies the
operation code and the second byte specifies the
operand.

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Three byte instructions
• In a three-byte instruction, the first byte specifies the opcode,
and the following two bytes specify the 16-bit address
• Note that the second byte is the low-order address and the
third byte is the high-order address.

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• Can be defined as a mechanism used for
specifying the address of operands in an
instruction.
• Every instruction of a program has to operate on
a data
• The method of specifying the data to be operated
by the instruction is called Addressing.

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 Addressing modes
There are five types of addressing modes.
I. Direct addressing
II. Register Addressing Mode
III. Register Indirect Addressing Mode
IV. Immediate Addressing Mode
V. Implicit Addressing Mode

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I. Direct Addressing
 In this mode of addressing the address of the operand(data) is explicitly
given in the instruction itself.
 The data will be in memory
 In this addressing mode, the program instructions and data can be stored in
different memory blocks
 This type of addressing can be identified by 16-bit address present in the
instruction
 All such instructions are 3-byte long, except IN and OUT instructions
 Instructions of these types are: LDA, STA, IN, OUT, SHLD, LHLD
E.g.
1. STA 2400H ; Store the contents of ACC in the memory
location 2400H
32, 00, 24 ; in binary code form
2. LDA 2300H ; Get the content in memory location 2300H in to ACC .
3A, 00, 23 ; in machine code form
3. IN 02 ; Read data from an I/O port (the Port C).
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DB, 02 ; in binary code form
II. Register Addressing Mode
- In this mode, the operands are in general-purpose registers.
- The opcode specifies the address of the register in addition
to the operation to be performed.
- Instructions of these type include: MOV, ADD, SPHL,
SUB, INR, PCHL, …
E.g.
1. MOV A, B ; Move the contents of register B to
register A
78 ; in code form
2. ADD B ; add the content of Register B to the content
of Register A
80 ; in code form
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III. Register Indirect Addressing Mode
- In this mode, the address of the operand is specified by a
register.
- Instructions of these type include: MOV, LDAX, STAX,
PUSH, ADD, SUB, INR, …
E.g.
1. LXI H, 2500H ; Load H-L pair with 2500H
MOV C, M ; move the contents of the memory location,
whose address is in register pair H-L (i.e., 2500h) to register
C.
ADD M ; add the content of memory location, whose
address is in H-L pair with ACC
2. LXI D, 2600H ; Load D-E pair with 2600H
STAX D ; Store ACC into memory location indicated by29
IV. Immediate Addressing Mode
 In this addressing mode, the operand (data) is specified
within the instruction itself.
 The data will be apart of the program instruction
 All instructions that have ‘I’ in their mnemonics are of
Immediate addressing type
 Instructions of these type include: MVI, LXI, ADI, SUI,
ANI, ACI, CPI, …
e.g.
MVI A, 05 ; Move 05 in register A . (3E, 05 in code)
ADI 06 ; Add 06 to the content of ACC . (C6, 06 in code)
LXI H, 2500H ,Load rp H-L with 2500H. (21, 00, 25 in
code)
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V. Implicit Addressing Mode
 Instructions in this category, operate on the content
of the ACC.
 This type of instruction does not have any address,
register name, immediate data specified along with it
 Instructions of these type include: RLC, RRC,
CMA, RAL, RAR, …
e.g.
1. CMA ; complement ACC (i.e. 1’s complement).
2F ; in code form
2. RAR ; Rotate ACC right through carry by one bit.
1F ; in code form 31
 The Intel 8085 Instruction set
• The 8085 instruction set is functionally grouped as
follows:
1. Data transfer group
2. Arithmetic group
3. Logical group
4. Branch control group
5. Stack, and Machine control group

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I. Data Transfer group instructions
 moves(copy)data - between registers,
- between registers & memory,
- specific data byte to register or memory,
- between I/O device and ACC.
 Data transfer instructions do not affect the flags.
 Data transfer instructions do not affect the contents of
source register or memory or I/O.
• These instructions include: MOV, MVI, LXI, LDA, STA,
LHLD, SHLD, LDAX, STAX, XCHG, (IN, OUT).

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Each instruction in assembly is given as bellow.
1. MOV r1, r2 ; Move the content of one register to another
[r1]  [r2]
e.g. MOV B, A

2. MOV r, M ; move the content of the memory location,

whose address is in H-L pair into register r.
[r]  [ [H-L] ]
e.g.
LXI H, 2000H ; load H-L pair by 2000H
MOV B, M ; Move the content of the memory location 2000H to B
HLT ; Halt
3. MOV M, r ; move the content of a register in to memory
4. MVI r, data8 ; move immediate 8-bit data to register.
[r]  data8
e.g. MVI D, 45H
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5. MVI M, data8 ; Move immediate data to memory
[ [H-L] ]  data8
e.g. LXI H, 2500H ; load H-L pair with 2500H
MVI M, 08 ; move 08 to memory location 2500H
HLT ; halt

6. LXI rp, Data16 ; Load register pair immediate.

[ rp ]  data16
[ rh]  8MSbs, [ rl]  8LSbs of data
only the high-order register is mentioned in the rp place, i.e. rp can
be B, D, H, or SP. i.e. LXI H means H-L pair, similarly LXI B
means B-C, LXI D means D-E
e.g. LXI B, 2500H ; B=25h, C=00H

7. LDA addr ; Load ACC direct.

[ A ]  [addr]
e.g. LDA 2400H ; load the content of the M.L 2400H into ACC.
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8. STA addr ;store ACC direct
9. LHLD addr ; Load H-L pair direct
[ L]  [addr] , [ H]  [addr +1]
e.g. LHLD 2500H ; [L]= [2500H], [H]=[2501H]
10. SHLD addr ; Store H-L pair direct
11. LDAX rp ; Load ACC indirect. rp can be B-C or D-E pairs
[ A ]  [ [rp] ]
 the content of the M.L, whose address is in the register pair rp, is loaded into
ACC.
e.g. LXI B, 2300H
LDAX B ; load the content of the M.L, whose address is in B-C pair.
HLT
12. STAX rp ; Store ACC indirect. rp can be B-C or D-E pairs
13. XCHG ; Exchange the contents of H-L with the D-E pair.
[H-L] [D-E]
i.e., [H] [D] , [L] [E]
14. IN portAddr ; Input to ACC from I/O port.
[A]  [portAddr]
15. OUT PortAddr ; Output from ACC to I/O port.
[portAddr] [A]
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II. Arithmetic group instructions
These instructions are: ADD, ADC, ADI, ACI, DAD, SUB, SBB, SUI, INR, DCR,
INX, DCX, DAA
1. ADD r ;add the content of register r to ACC. The sum (result) is placed in
ACC.
[A]  [A] + [r]
e.g. MVI C, 45H ; load reg C with 45H
MVI A, 50H ; load reg A with 50H
ADD C ; add C=45H with A=50H, result is in A=95H
HLT ; stop

2. ADD M ; add memory content to ACC. The result is stored in ACC.

[A]  [A] + [ [H-L] ]
- the content of the M.L addressed by H-L pair is added to the content of the ACC.
The sum is stored in ACC.
e.g. LXI H, 2400H
MVI A, 20H
ADD M ; add memory content to ACC.
HLT ; stop
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3. ADC r ; add register with carry to ACC. Result is in ACC.
[A]  [A] + [ r] + [CS]

4. ADC M , add content of memory with carry to ACC.

[A]  [A] + [ [H-L]] + [CS]

5. ADI data8 ; Add 8-bit immediate data to ACC. Result in ACC.

[A]  [A] + data8
e.g. MVI A, 0FH
ADI E1H ; result is in A=F0H

6. ACI data8 ; Add with carry immediate data to ACC. Result in ACC.
[A]  [A] + data8 + [CS]

e.g. MVI C, F7H

MVI A , 10H
ADD C ; A= 07H, cy=1
ACI 45H ; add 45 with carry to ACC. Result is in A=4DH

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7. DAD rp ; Add the content of register pair to H-L pair. rp can be
H-L, B-C, D-E, SP.
[H-L]  [H-L] + [rp]
- the contents of register pair rp is added to the contents of H-L pair
and the result is placed in H-L pair.
e.g. LXI H, 2000H
LXI D, 0550H
DAD D ; result is in H-L pair, H=25H, L=50H

8. SUB r ; subtract register from ACC. Result (remainder) in ACC.

[A]  [A] - [r]

e.g. MVI C, 30H ; load reg C with 30H

MVI A, 45H ; load reg A with 45H
SUB C ; subtract C=30H from A=45H, result is in A=15H
HLT ; stop
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9 . SUB M ; Subtract memory content from ACC. The result is
stored in ACC.
[A]  [A] - [ [H-L] ]
- the content of the M.L addressed by H-L pair is subtracted from
the content of the ACC. The difference is stored in ACC.

e.g. LXI H, 2400H

MVI A, 20H
SUB M ; subtract memory content to ACC.
HLT ; stop

10. SBB r ; subtract register with borrow from ACC. Result is in

ACC.
[A]  [A] - [ r] - [CS]

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11. SBB M ; subtract content of memory with borrow from ACC.
[A]  [A] - [ [H-L]] - [CS]
12. SUI data8 ; Subtract 8-bit immediate data from ACC. Result in
ACC.
[A]  [A] - data8
e.g. MVI A, E1H
SUI 0FH ; result is in A=D2H

13. SBI data8 ; Subtract with borrow immediate data from ACC.
Result in ACC.
[A]  [A] - data8 - [CS]

e.g. MVI C, 10H

MVI A , F7H
SUB C ; A=E7H , CY=0
SBI 45H ; subtract 45 with borrow from ACC. Result is in
A=A2H
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14. INR r ; increment register content
[r]  [r] +1
15. INR M ; increment memory content.
[[H-L]]  [[H-L]] +1
16. DCR r ; decrement register content
[r]  [A] -1
17. DCR M ; decrement memory content.
[[H-L]]  [[H-L]] -1
18. INX rp ; Increment register pair. rp can be H-L, B-C, D-E,SP.
[rp]  [rp] +1
19. DCX rp ; decrement register pair. rp can be H-L, B-C, D-E, SP.
[rp]  [rp] -1

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20. DAA ; decimal adjust ACC. Decimal result is placed in
ACC.

- the DAA instruction is used in the program after ADD, ADI,

ACI, or ADC instructions.
- it uses carry and auxiliary carry for decimal adjustment:
6 is added to 4 LSbs of the content of ACC if their value lies
between A & F or the AC flag is set to 1.
6 is added to 4MSBs of the content of ACC if their value lies
between A & F or the CY flag is set to 1.

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Example: What would be the out put of the following Code.

mvi A,95h
mvi D,98h
add D
DAA
hlt
Exercises:
98h
+99h

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III. Logical Group Instructions
• The 8085 microprocessor supports the following
logic operations.
• Like arithmetic operations these instructions
change the state of the flags according to the result.
• These includes:
ANA ANI
ORA ORI
XRA XRI
CMA CMC STC
CMP CPI
RLC RAL RRC RAR

45
 AND logical instructions. Used to mask or extract and reset bit(s)
1. ANA r ; AND register r with ACC
[A]  [A] ^ [r]
2. ANA M ; AND memory with ACC
[A]  [A] ^ [[H-L]]
3. ANI data8 ; AND immediate data with ACC
[A]  [A] ^ data8
Example:
4.Let A contains 82h, and D contains 54H, now logically AND D with ACC.
Ans.
ANA D ; AND reg. D with ACC
(A)=82H = 1000 0010
AND
(D)=54H = 0101 0100
0000 0000 = 00h=(A) result in ACC 46
OR logical instructions. Used to selectively set bit(s)
4. ORA r ; OR register r with ACC
[A]  [A]  [r]

5. ORA M ; OR memory with ACC

[A]  [A]  [[H-L]]

6. ORI data8 ; OR immediate data with ACC

[A]  [A]  data8

EXCLUSIVE-OR logical instructions

7. XRA r ; Exclusive-OR register r with ACC
[A]  [A]  [r]

8. XRA M ; XOR memory with ACC

[A]  [A]  [[H-L]]

9. XRI data8 ; XOR immediate data with ACC

[A]  [A]  data8
47
10. CMA ; Complement the ACC
[A]  [/A]

11. CMC ; Complement carry

[Cs]  [/Cs]

12. STC ; set carry status

[Cs]  1

48
13. CMP r ; Compare register with ACC
[A] - [r]
14. CMP M ; Compare memory with ACC
[A] - [[H-L]]
15. CPI data8 ; Compare immediate data with ACC
[A] - data8
Note:
Status flags are affected according to the result of the subtraction. But the result is
discarded. Neither of the operands’ contents are modified.
. If (A)< operand, CY flag is set (CS=1), and Z flag is reset (Z=0)
. If (A)==operand, CY flag is reset (CS=0), and Z flag is set (Z=1)
. If (A)>operand, both CY and Z flags reset (CS=0,Z=0)
Example:
1. Register B contains data byte 62h and ACC contains 57H. Compare B with ACC.
MVI A, 57H Before execution After execution
MVI B, 62H CY
CMP B A 57 XX F A 57 1 F
B 62 XX C B 62 XX C
HLT
49
Flags: S=1, Z=0, AC=0, P=1, CY=1
16. RLC ; Rotate accumulator left
[An+1] [An], [A0] [A7], [CS] [A7]

Cy A7 A6 A5 A4 A3 A2 A1 A0

18. RAL ; Rotate ACC left through carry

[An+1] [An], [CS] [A7], [A0] [CS]

Cy A7 A6 A5 A4 A3 A2 A1 A0

50
19. RRC ; Rotate ACC right
[A7] [A0], [CS] [A0], [An] [An+1],

CS A7 A6 A5 A4 A3 A2 A1 A0

20. RAR ; Rotate ACC right through carry

[CS] [A0], [A7] [CS], [An] [An+1],

CS A7 A6 A5 A4 A3 A2 A1 A0

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IV. Branch Group Instructions
• These includes:
JMP
J(condition)
CALL
C(condition)
RET
R(condition)
RST n
PCHL

52
Branch instructions are used to change the normal sequence of the program.
Two types of branch instructions:
. Unconditional jump-transfer the program to specified label unconditionally.
. Conditional branch (jump)- transfer the program to specified label
when certain condition is satisfied.
1. JMP addr16 (Label) ; unconditionally jump to the instruction addressed by
Label.
[PC] Label
2. J(Condition) addr16(Label) ; Jump if condition is satisfied.
[PC] Label

The jump on condition instructions are:

JZ Label ; Jump if flag Z=1; Go to address specified if the Zero flag is set.
JNZ Label ; jump if flag Z=0;Go to address specified if the Zero flag is not set.
JC Label ; jump if flag Cy is set; Go to the address specified if the Carry flag is set.
JNC Label ; jump if CY=0; Go to the address specified if the Carry flag is not set.
JP Label ; (Jump on Plus); ; Go to the address specified if the Sign flag is not set
JM Label ; (Jump on Minus); Go to the address specified if the Sign flag is set.
JPE Label ; jump if parity flag is set
JPO Label ; jump if P=0
53
3. CALL addr16(Label) ; Unconditional call: Call the subroutine located at Label
[[SP]-1] [PCH] -save address of next instruction of main program in stack
[[SP]-2] [PCL]
[SP] [SP]-2 - update SP to the current stack top
[PC] addr16 - jump to subroutine.
Note:
. Before the control is transferred to the subroutine , the address of the next
instruction of the main program is saved in the stack.
. SP is decremented by two to indicate the new stack point.
. Then the program control jumps to subroutine starting at address specified by the
Label.
4. C(Condition) addr16(Label) ; Conditional call.
[[SP]-1] [PCH], [[SP]-2] [PCL]
[PC] addr16, [SP] [SP]-2
The call on condition instructions are:
CZ Label ; call if flag Z=1
CNZ Label ; call if flag Z=0
CC Label ; call if flag Cy is set
CNC Label ; call if CY=0
CP Label ; call if sign flag reset
CM Label ; call if S=1
CPE Label ; call if parity flag is set
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CPO Label ; call if P=0
5.RET ; Return to calling program unconditionally.
[PCL] [[SP]], [PCH] [[SP]+1]
[SP] [SP]+2
Note: RET instruction is used at the end of a subroutine
. RET causes the saved address in stack to read back to PC.
. The SP is incremented by two to indicate the new stack top
. Then the control jumps to the instruction of the main program next to CALL
instruction.

6. R(cond) ; Conditional return. Return on condition.

[PCL] [[SP]], [PCH] [[SP]+1]
[SP] [SP]+2
The return on condition instructions are:
RZ ; return if flag Z=1
RNZ ; return if flag Z=0
RC ; return if flag Cy is set
RNC ; return if CY=0
RP ; return if sign flag reset
RM ; return if S=1
RPE ; return if parity flag is set
RPO ; return if P=0 55
7.RST n ; Restart
[[SP]-1] [PCH], [[SP]-2] [PCL]
[SP] [SP]-2, [PC] 8*n,

Note: Restart is a one-word CALL instruction

. The content of PC is saved in the stack
. The control jumps to the instruction starting at restart location.
. The address of restart location is 8 times n, where n=0,1,…, 7
The restart instructions and restart locations are as follows:
Instruction Hex Code Restart Location
8085 additional interrupts
RST 0 C7 0000
Interrupts Restart Address User Location
RST 1 CF 0008
TRAP 0024H ----
RST 2 D7 0010
RST 5.5 002CH 0509
RST 3 DF 0018
RST 6.5 0034H FFB7
RST 4 E7 0020
RST 7.5 003CH FFBD
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038

8. PCHL ; unconditional jump to address specified by H-L pair

[PC] [H-L], i.e. [PCH] [H], [PCL] [L]
56
V. Stack, I/O and machine control Group instructions

These includes:
IN OUT
PUSH POP
EI DI
RIM SIM
XTHL
SPHL
HLT
NOP

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1. IN portAddr8 ; Input from input port to ACC
[A]  [portaddr8]
e.g. IN 01 ; move the data on port address to ACC
2. OUT portAddr8 ; Output from ACC to output port
[portaddr8]  [A]
e.g. OUT 00H ; move from ACC to output port 00h
3. PUSH rp ; Push the content of register pair to stack
[[SP]-1] [rh], [[SP]-2] [rl]
[SP] [SP]-2
4. PUSH PSW ; Push processor status word i.e. A and Flags
[[SP]-1] [A], [[SP]-2] [PSW]
[SP] [SP]-2
5.POP rp ; pop the content which was saved in stack to register pair.
[rl] [[SP]], [rh] [[SP]+1]
[SP] [SP]+2
6. POP PSW ; Pop Processor status word, i.e. A and Flags
[PSW] [[SP]], [A] [[SP]+1]
[SP] [SP]+2
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7. HLT ; Halt. Stop the program (but not off). Halt and enter
WAIT state

8. XTHL ;Exchange stack –top with H-L pair

[L]↔[[SP]], [H]↔[[SP]+1]

9. SPHL ; Move the contents of H-L pair to stack pointer

[SP] [H-L]

10. EI ; Enable interrupts.

11. DI ; Disable interrupts.
12. SIM ; Set interrupt masks.
13. RIM ; Read interrupt mask.
14. NOP ; No operation.
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 The Stack
• The stack is an area of memory
identified by the programmer for
temporary storage of information.
•The stack is a LIFO structure.
–Last In First Out.
•The stack normally grows backwards
into memory
–In other words, the programmer
defines the bottom of the stack and
the stack grows up into reducing
address range.

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-Given that the stack grows backwards into memory, it is customary
to place the bottom of the stack at the end of memory to keep it as far
away from user programs as possible.
-In the 8085, the stack is defined by setting the SP (Stack Pointer)
register.
-This sets the Stack Pointer to location FFFFH (end of memory for
the 8085).
LXI SP, FFFFH

Saving Information on the Stack

-Information is saved on the stack by PUSHing it on.
–It is retrieved from the stack by POPing it off.
-The 8085 provides two instructions: PUSH and POP for storing
information on the stack and retrieving it back.
–Both PUSH and POP work with register pairs ONLY.

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 The PUSH Instruction
•PUSH B
–Decrement SP
–Copy the contents of register B to the memory location pointed to
by SP
–Decrement SP
–Copy the contents of register C to the memory location pointed to
by SP

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 The POP Instruction
•POP B
–Copy the contents of the memory location pointed to by the SP to
register C
–Increment SP
–Copy the contents of the memory location pointed to by the SP to
register B
–Increment SP

63
 Operation of the Stack

• During pushing, the stack operates in a“decrement then store” style.

–The SP is decremented first, then the information is placed on the stack.
• During poping, the stack operates in a “use then increment” style.
–The information is retrieved from the top of the stack and then the
pointer is incremented.
•The SP pointer always points to “the top of the stack”.
The PSW Register Pair
• The 8085 recognizes one additional register pair called the PSW
(Program Status Word).
–This register pair is made up of the Acc and the Flags registers.
•It is possible to push the PSW onto the stack, do whatever operations
are needed, then POP it off of the stack.
–The result is that the contents of the Acc and the status of the Flags
are returned to what they were before the operations were executed.
64
 Subroutines

•A subroutine is a group of instructions that will be used repeatedly

in different locations of the program.
-Rather than repeat the same instructions several times, they can be
grouped into a subroutine that is called from the different locations.
•In Assembly language, a subroutine can exist any where in the code.
However, it is customary to place subroutines separately from the
main program.
•The 8085 has two instructions for dealing with subroutines.
–The CALL instruction is used to redirect program execution to
the subroutine.
–The RET instruction is used to return the execution to the calling
routine.

65
 The CALL Instruction
CALL 4000H
–Push the address of the instruction immediately following the
CALL onto the stack
–Load the program counter with the 16-bit address supplied with the CALL
instruction.

The RET Instruction

•RET
–Retrieve the return address from the top of the stack
–Load the program counter with the return address.

66
Cautions
•The CALL instruction places the return address at the two memory
locations immediately before where the Stack Pointer is pointing.
–You must set the SP correctly BEFORE using the CALL instruction.
•The RET instruction takes the contents of the two memory locations
at the top of the stack and uses these as the return address.
–Do not modify the stack pointer in a subroutine. You will loose the
return address.

Passing Data to a Subroutine

•In Assembly Language data is passed to a subroutine through
registers.
–The data is stored in one of the registers by the calling program
and the subroutine uses the value from the register.
•The other possibility is to use agreed upon memory locations.
–The calling program stores the data in the memory location and
the subroutine retrieves the data from the location and uses it. 67