VLSI Testing

Delay Test (Non-Scan) &

Built-In Self-Test (BIST)
Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0286: Testing and Verification of SoC Designs

Lecture 24
Mar 28, 2008 E0286@SERC 1
 Non Scan Design
Iwagaki et al. [ETS’04]

Mar 28, 2008 E0286@SERC 2

 Non Scan Design

Mar 28, 2008 E0286@SERC 3

 Non Scan Design

Mar 28, 2008 E0286@SERC 4

 Timing Design & Delay Test
™Timing simulation:
¾Critical paths are identified by static (vector-less)
timing analysis tools like Primetime (Synopsys).
¾Timing or circuit-level simulation using designer-
generated functional vectors verifies the design.
™Layout optimization: Critical path data are used in
placement and routing. Delay parameter
extraction, timing simulation and layout are
repeated for iterative improvement.
™Testing: Some form of at-speed test is necessary.
PDFs for critical paths and all transition faults are
tested.
Mar 28, 2008 E0286@SERC 5
 Built-In Self-Test
(BIST)

Mar 28, 2008 E0286@SERC 6

 BIST Motivation
™ Useful for field test and diagnosis (less
expensive than a local automatic test
equipment)
™ Software tests for field test and diagnosis:
¾ Low hardware fault coverage
¾ Low diagnostic resolution
¾ Slow to operate
™ Hardware BIST benefits:
¾ Lower system test effort
¾ Improved system maintenance and repair
¾ Improved component repair
¾ Better diagnosis
Mar 28, 2008 E0286@SERC 7
 Costly Test Problems
Alleviated by BIST
™ Increasing chip logic-to-pin ratio – harder
observability
™ Increasingly dense devices and faster clocks
™ Increasing test generation and application times
™ Increasing size of test vectors stored in ATE
™ Expensive ATE needed for 1 GHz clocking chips
™ Hard testability insertion – designers unfamiliar with
gate-level logic, since they design at behavioral level
™ Shortage of test engineers
™ Circuit testing cannot be easily partitioned

Mar 28, 2008 E0286@SERC 8

 Economics – BIST Costs
™Chip area overhead for:
¾Test controller
¾Hardware pattern generator
¾Hardware response compacter
¾Testing of BIST hardware
™Pin overhead -- At least 1 pin needed to activate
BIST operation
™Performance overhead – extra path delays due to
BIST
™ Yield loss – due to increased chip area or more
chips In system because of BIST
™Reliability reduction – due to increased area
™Increased BIST hardware complexity – happens
when BIST hardware is made testable
Mar 28, 2008 E0286@SERC 9
 BIST Benefits
™ Faults tested:
¾ Single combinational / sequential stuck-at faults
¾ Delay faults
¾ Single stuck-at faults in BIST hardware
™ BIST benefits
¾ Reduced testing and maintenance cost
¾ Lower test generation cost
¾ Reduced storage / maintenance of test patterns
¾ Simpler and less expensive ATE
¾ Can test many units in parallel
¾ Shorter test application times
¾ Can test at functional system speed
Mar 28, 2008 E0286@SERC 10
 BIST Architecture

Note: BIST cannot test wires and transistors:

¾ From PI pins to Input MUX
¾ From POs to output pins
Mar 28, 2008 E0286@SERC 11
 BILBO – Works as PG and RC

™ Built-in Logic Block Observer (BILBO) -- 4 modes:

1. Flip-flop
2. LFSR pattern generator
3. LFSR response compacter
4. Scan chain for flip-flops

Mar 28, 2008 E0286@SERC 12

 Complex BIST Architecture

• Testing epoch I:
¾ LFSR1 generates tests for CUT1 and CUT2
¾ BILBO2 (LFSR3) compacts CUT1 (CUT2)
• Testing epoch II:
¾ BILBO2 generates test patterns for CUT3
¾ LFSR3 compacts CUT3 response

Mar 28, 2008 E0286@SERC 13

 Bus-Based BIST Architecture

¾ Self-test control broadcasts patterns to each CUT over

bus – parallel pattern generation
¾ Awaits bus transactions showing CUT’s responses to
the patterns: serialized compaction
Mar 28, 2008 E0286@SERC 14
 Pattern Generation
¾ Store in ROM – too expensive
¾ Exhaustive
¾ Pseudo-exhaustive
¾ Pseudo-random (LFSR) – Preferred method
¾ Binary counters – use more hardware than LFSR
¾ Modified counters
¾ Test pattern augmentation
™ LFSR combined with a few patterns in ROM
™ Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
ROM

Mar 28, 2008 E0286@SERC 15

 Pattern Generation
¾ Store in ROM – too expensive
¾ Exhaustive
¾ Pseudo-exhaustive
¾ Pseudo-random (LFSR) – Preferred method
¾ Binary counters – use more hardware than LFSR
¾ Modified counters
¾ Test pattern augmentation
™ LFSR combined with a few patterns in ROM
™ Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
ROM

Mar 28, 2008 E0286@SERC 16

 Exhaustive Pattern Generation

¾ Shows that every state and transition works

¾ For n-input circuits, requires all 2n vectors
¾ Impractical for n > 20
Mar 28, 2008 E0286@SERC 17
 Pseudo-Exhaustive Method

™ Partition large circuit into fanin cones

¾ Backtrace from each PO to PIs influencing it
¾ Test fanin cones in parallel
™ Reduced # of tests from 28 = 256 to 25 x 2 = 64
¾ Incomplete fault coverage

Mar 28, 2008 E0286@SERC 18

 Pseudo-Exhaustive Pattern
Generation

Mar 28, 2008 E0286@SERC 19

 Random Pattern Testing

Bottom:
Random-
Pattern
Resistant
circuit

Mar 28, 2008 E0286@SERC 20

 Thank You

Mar 28, 2008 E0286@SERC 21