VLSI Testing

Built-In Self-Test (BIST)

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0286: Testing and Verification of SoC Designs

Lecture 25
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 BIST Architecture

Note: BIST cannot test wires and transistors:

¾ From PI pins to Input MUX
¾ From POs to output pins
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 Pattern Generation
¾ Store in ROM – too expensive
¾ Exhaustive
¾ Pseudo-exhaustive
¾ Pseudo-random (LFSR) – Preferred method
¾ Binary counters – use more hardware than LFSR
¾ Modified counters
¾ Test pattern augmentation
™ LFSR combined with a few patterns in ROM
™ Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
ROM

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 Pattern Generation
¾ Store in ROM – too expensive
¾ Exhaustive
¾ Pseudo-exhaustive
¾ Pseudo-random (LFSR) – Preferred method
¾ Binary counters – use more hardware than LFSR
¾ Modified counters
¾ Test pattern augmentation
™ LFSR combined with a few patterns in ROM
™ Hardware diffracter – generates pattern
cluster in neighborhood of pattern stored in
ROM

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 Pseudo-Random Pattern
Generation

™ Standard Linear Feedback Shift Register (LFSR)

¾ Produces patterns algorithmically – repeatable
¾ Has most of desirable random # properties
™ Need not cover all 2n input combinations
™ Long sequences needed for good fault coverage
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 Matrix Equation for Standard
LFSR

X0 (t + 1) 0 1 0 … 0 0 X0 (t)
X1 (t + 1) 0 0 1 … 0 0 X1 (t)
. . . . . . .
. . . . . . .
. = . . . . . .
Xn-3 (t + 1) 0 0 0 … 1 0 Xn-3 (t)
Xn-2 (t + 1) 0 0 0 … 0 1 Xn-2 (t)
Xn-1 (t + 1) 1 h1 h2 … hn-2 hn-1 Xn-1 (t)

X (t + 1) = Ts X (t) (Ts is companion matrix)

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 LFSR Implements a Galois Field

ƒ Galois field (mathematical system):

¾ Multiplication by x same as right shift of LFSR
¾ Addition operator is XOR ( ⊕ )
ƒ Ts companion matrix:
¾ 1st column 0, except nth element which is always
1 (X0 always feeds Xn-1)
¾ Rest of row n – feedback coefficients hi
¾ Rest is identity matrix I – means a right shift
• Near-exhaustive (maximal length) LFSR
¾ Cycles through 2n – 1 states (excluding all-0)
¾ 1 pattern of n 1’s, one of n-1 consecutive 0’s

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 Standard n-Stage LFSR
Implementation

™ Autocorrelation – any shifted sequence same as

original in 2n-1 – 1 bits, differs in 2n-1 bits
™ If hi = 0, that XOR gate is deleted
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 LFSR Theory

• Cannot initialize to all 0’s – hangs

• If X is initial state, progresses through states
X, Ts X, Ts2 X, Ts3 X, …
• Matrix period:
Smallest k such that Tsk = I
ƒ k ≡ LFSR cycle length
• Described by characteristic polynomial:
f (x) = |Ts – I X |
= 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn

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 External XOR LFSR

• Characteristic polynomial f (x) = 1 + x + x3

(read taps from right to left)

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 External XOR LFSR

• Pattern sequence for example LFSR (earlier):

X0 1 0 0 1 0 1 1 1 0
X1 0 0 1 0 1 1 1 0 0 …
X2 0 1 0 1 1 1 0 0 1

• Always have 1 and xn terms in polynomial

• Never repeat an LFSR pattern more than 1 time –
Repeats same error vector, cancels fault effect
X0 (t + 1) 0 1 0 X0 (t)
X1 (t + 1) = 0 0 1 X1 (t)
X2 (t + 1) 1 1 0 X2 (t)
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 Generic Modular LFSR

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 Modular Internal XOR LFSR
• Described by companion matrix Tm = Ts T
• Internal XOR LFSR – XOR gates in between D
flip-flops
• Equivalent to standard External XOR LFSR
ƒ With a different state assignment
ƒ Faster – usually does not matter
ƒ Same amount of hardware
• X (t + 1) = Tm x X (t)
• f (x) = | Tm – I X |
= 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn
• Right shift – equivalent to multiplying by x, and
then dividing by characteristic polynomial and
storing the remainder
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 Modular LFSR Matrix

X0 (t + 1) 0 0 0 … 0 0 1 X0 (t)
X1 (t + 1) 1 0 0 … 0 0 h1 X1 (t)
X2 (t + 1) 0 1 0 … 0 0 h2 X2 (t)
. . . . . . . .
. = . . . . . . .
. . . . . . . .
Xn-3 (t + 1) 0 0 0 … 0 0 h
n-3
Xn-3 (t)
Xn-2 (t + 1) 0 0 0 … 1 0 h Xn-2 (t)
n-2
Xn-1 (t + 1) 0 0 0 … 0 1 hn-1 Xn-1 (t)

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 Example Modular LFSR

f (x) = 1 + x2 + x7 + x8
• Read LFSR tap coefficients from left to right

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 Primitive Polynomials
• Want LFSR to generate all possible 2n – 1 patterns
(except the all-0 pattern)
• Conditions for this – must have a primitive
polynomial:
ƒ Monic – coefficient of xn term must be 1
• Modular LFSR – all D FF’s must right shift
through XOR’s from X0 through X1, …, through
Xn-1, which must feed back directly to X0
• Standard LFSR – all D FF’s must right shift
directly from Xn-1 through Xn-2, …, through X0,
which must feed back into Xn-1 through XORing
feedback network
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 Primitive Polynomials

¾Characteristic polynomial must divide the

polynomial 1 – xk for k = 2n – 1, but not for
any smaller k value

¾ If p (error) = 0.5, no difference between

behavior of primitive & non-primitive
polynomial
¾ But p (error) is rarely = 0.5 In that case, non-
primitive polynomial LFSR takes much longer
to stabilize with random properties than
primitive polynomial LFSR

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 Weighted Pseudo-Random
Pattern Generation
s-a-0
F

1
• If p (1) atf all PIs is 0.5, pF (1) = 0.58 =
256
1
pF (0) = 1 – = 255
256 256
• Will need enormous # of random patterns to test a
stuck-at 0 fault on F -- LFSR p (1) = 0.5
ƒ We must not use an ordinary LFSR to test this
• IBM – holds patents on weighted pseudo-random
pattern generator in ATE
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 Weighted Pseudo-Random
Pattern Generator
¾ LFSR p (1) = 0.5
¾ Solution: Add programmable weight selection
and complement LFSR bits to get p (1)’s other
than 0.5
¾ Need 2-3 weight sets for a typical circuit
¾ Weighted pattern generator drastically shortens
pattern length for pseudo-random patterns

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 Weighted Pattern Gen.

w1 w2 Inv. p (output) w1 w2 Inv. p (output)

0 0 0 ½ 1 0 0 1/8
0 0 1 ½ 1 0 1 7/8
0 1 0 ¼ 1 1 0 1/16
0 1 1 3/4 1 1 1 15/16
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 Response Compaction
™ Severe amounts of data in CUT response to
LFSR patterns – example:
¾ Generate 5 million random patterns
¾ CUT has 200 outputs
¾ Leads to: 5 million x 200 = 1 billion bits
response
™Uneconomical to store and check all of
these responses on chip
™Responses must be compacted

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 Definitions
¾ Aliasing – Due to information loss, signatures of
good and some bad machines match
¾ Compaction – Drastically reduce # bits in original
circuit response – lose information
¾ Compression – Reduce # bits in original circuit
response – no information loss – fully invertible
(can get back original response)
¾ Signature analysis – Compact good machine
response into good machine signature. Actual
signature generated during testing, and
compared with good machine signature
¾ Transition Count Response Compaction – Count #
transitions from 0 1 and 1 0 as a signature
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 Transition Counting

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 Transition Counting

™ Transition count:
m
C (R) = Σ (ri ⊕ ri-1) for all m primary outputs
i=1
™ To maximize fault coverage:
¾ Make C (R0) – good machine transition count –
as large or as small as possible

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 LFSR for Response Compaction
• Use cyclic redundancy check code (CRCC) generator
(LFSR) for response compacter
• Treat data bits from circuit POs to be compacted as a
decreasing order coefficient polynomial
• CRCC divides the PO polynomial by its characteristic
polynomial
¾ Leaves remainder of division in LFSR
¾ Must initialize LFSR to seed value (usually 0)
before testing
• After testing – compare signature in LFSR to known
good machine signature
• Critical: Must compute good machine signature

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 Example Modular LFSR
Response Compacter

• LFSR seed value is “00000”

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 Polynomial Division
Inputs X0 X1 X2 X3 X4
Initial State 0 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
Logic 0 0 0 1 0 0
Simulation: 0 0 0 0 1 0
1 1 0 0 0 1
0 1 0 0 1 0
1 1 1 0 0 1
0 1 0 1 1 0
Logic simulation: Remainder = 1 + x2 + x3
0 1 0 1 0 0 0 1
0 . x0 + 1. x1 + 0 . x2 + 1. x3 + 0. x4 + 0 . x5 + 0 . x6 + 1. x7
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 Symbolic Polynomial Division

x2 + 1
x5 + x3 + x + x7 + x3 +x
1 x7 + x5 + x3 + x2
x5 + x2 + x
x5 + x3 +x +1
remainder x3 + x2 +1

Remainder matches that from logic simulation

of the response compacter!

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 Multiple-Input Signature
Register (MISR)
• Problem with ordinary LFSR response compacter:
ƒ Too much hardware if one of these is put on each
primary output (PO)
• Solution: MISR – compacts all outputs into one
LFSR
ƒ Works because LFSR is linear – obeys
superposition principle
ƒ Superimpose all responses in one LFSR – final
remainder is XOR sum of remainders of
polynomial divisions of each PO by the
characteristic polynomial
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 MISR Matrix Equation

• di (t) – output response on POi at time t

X0 (t + 1) 0 1 … 0 0 X0 (t) d0 (t)
X1 (t + 1) 0 0 … 0 0 X1 (t) d1 (t)
. . . . . . .
. . . . . . .
. . . . . . .
Xn-3 (t + 1) = 0 0 … 1 0 Xn-3 (t) + dn-3 (t)
Xn-2 (t + 1) 0 0 … 0 1 Xn-2 (t) dn-2 (t)
Xn-1 (t + 1) 1 h1 … hn-2 hn-1 Xn-1 (t) dn-1 (t)

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 Modular MISR Example

X0 (t + 1) 0 0 1 X0 (t) d0 (t)
X1 (t + 1) = 1 0 1 X1 (t) + d1 (t)
X2 (t + 1) 0 1 0 X2 (t) d2 (t)
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 Multiple Signature Checking

• Use 2 different testing epochs:

¾ 1st with MISR with 1 polynomial
¾ 2nd with MISR with different polynomial
• Reduces probability of aliasing –
¾ Very unlikely that both polynomials will alias
for the same fault
• Low hardware cost:
¾ A few XOR gates for the 2nd MISR polynomial
¾ A 2-1 MUX to select between two feedback
polynomials

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 Aliasing Probability

• Aliasing – when bad machine signature equals

good machine signature
• Consider error vector e (n) at POs
ƒ Set to a 1 when good and faulty machines
differ at the PO at time t
• Pal ≡aliasing probability
• p ≡ probability of 1 in e (n)
• Aliasing limits:
ƒ 0 < p ≤ ½, pk ≤ Pal ≤ (1 – p)k

ƒ ½ ≤p ≤1, (1 – p) k
≤ Pal ≤ pk

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 Aliasing Theorems
• Theorem 1: Assuming that each circuit PO dij has
probability p of being in error, and that all outputs dij
are independent, in a k-bit MISR, Pal = 1/(2k),
regardless of initial condition of MISR. Not exactly
true – true in practice.
• Theorem 2: Assuming that each PO dij has probability
pj of being in error, where the pj probabilities are
independent, and that all outputs dij are
independent, in a k-bit MISR, Pal = 1/(2k),
regardless of the initial condition.

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 Transition Counting vs. LFSR
• LFSR aliases for f sa1, transition counter for a sa1
Pattern Responses
abc Good a sa1 f sa1 b sa1
000 0 0 1 0
001 1 1 1 0
010 0 1 1 0
011 0 1 1 0
100 0 0 1 1
101 1 1 1 1
110 1 1 1 1
111 1 1 1 1
Signatures
Transition Count 3 3 0 1
LFSR 001 101 001 010
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 Thank You

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