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DOST-ASTI Electric Manual PDF
DOST-ASTI Electric Manual PDF
System
Training Manual
(Version 6.03)
Loading Electric
Load Electric by either clicking the Electric icon on the desktop or by clicking on
Start → Programs → Electric.
Editing Window
Messages Window
Status Area
The editing window or design window is the largest window that initially says “No
facet in this window” (this indicates that no circuit is being displayed in that window).
The messages window is a text window that is typically found at the bottom of the
screen. This is used for all textual communication.
The components menu shows a list of nodes or components (in black outline) and
arcs or wires (in red outline) that can be used in the design. The selected arc is highlighted
with a bolder red outline.
The status area provides useful information about the design state.
SCHEMATIC
Adding Components
1. Select the desired device in the components menu by using the left mouse button. A
white outline will appear around the chosen component.
2. Click on the design window to drop the component.
Adding Wires
1. In the components menu, check if the wire arc (blue line) is highlighted (with a bold
red outline). If it is not highlighted, click on the wire arc to select it.
2. Select the wire starting point by left clicking the component near the desired port.
Make sure that the desired port is highlighted, as discussed in Selecting Components
and Ports, before proceeding to the next step.
3. To create the wire, right click on another device port (to connect two device ports) or
anywhere on the design window (to create a wire segment). Once a wire has been
created, the other end is highlighted.
4. Type the appropriate SPICE card parameters in the SPICE Card window. Table 3 is
a list of SPICE card formats for the different analyses.
5. Click OK.
Table 2
Table 3
LAYOUT
Adding Nodes
1. Select a node from the components menu by using the left mouse button.
2. Click on the design window.
Note: Nodes in the mocmossub components menu are the ones in blue outlines.
Adding Arcs
1. Select an arc in the components menu.
2. Choose the arc starting point by left clicking the node near the desired port. Make
sure that the desired port is highlighted before proceeding to the next step.
3. To create the arc, right click on another node port (to connect two node ports) or
anywhere on the design window (to create an arc segment). Once an arc has been
created, the other end is highlighted.
Note: Arcs in the mocmossub components menu are the ones in red outlines.
SIMULATION
Example:
Plotting several parameters in one window,
The above picture shows the transient response of Va, Vb and Vout superimposed in
one plot. To plot each parameter in separate windows, delete the above code and
rewrite it as:
If the simulation has been run already, simply type the following on the WinSpice command
prompt:
plot <parameter><node name in parenthesis>
Listed here are some of the most common errors encountered and their corresponding
solutions.
This means that the ground and power in the circuit is not connected to the DC source.
Refer to Checking forCconnectivity in the Tips section of this manual.
Example:
Corrected Example:
Notice that all occurrences of ‘ ’ are now substituted with ‘v’.
Unconnected Nodes
Note: * in the beginning of a line denotes it is a comment in the program and is therefore not an error, while an *
within a command denotes a missing node in the program
3. Check the schematic for unconnected nodes in the transistors. For this example, the
bulk nodes are unconnected. Connect the bulk correspondingly (to ground for NMOS
and to Vdd for PMOS).
4. Save the schematic and recreate the SPICE netlist. Check if the line is correctly
modified by opening the *.cir file again.
.model N NMOS
+…
+…
TIPS
Example:
Notice that all the nodes connected to ground are highlighted. An example of an
unconnected wire is shown below:
The ground in black circle is not connected to the rest of the nodes connected to ground. If
this is the case, do the following:
1. Save the library (Ctrl-S).
2. Open the same library without closing the current facet.
3. Check for connectivity. The nodes concerned should now all be highlighted.
Transistor Layout
1. Overlapping two nodes does not automatically connect them. This will only generate
spacing errors. Make sure to connect them first using an arc and then move them closer
as in the example below:
2. Try to move the node closer one step at a time while checking the message window
to see if a DRC error is generated. Or you can perform the DRC independently as
specified in the Layout section of this manual.
3. Checking their connectivity is the same as with the schematic. Clicking a node should
highlight all that is connected to it as in the figures below.
Connected Unconnected
4. If nodes are well connected, and there are still spacing errors, double click on the arc
connecting the nodes with the spacing error.
5. Uncheck “ends extend” (This option sizes the node / arc in proportion to the node
width).
6. Another cause of spacing errors is multiple components that are overlapping. One can
easily identify this by moving the component concerned and checking if there is an
extra component under it as in the example below.
In this case, the extra component is not connected to the other nodes and so it
generates the other spacing errors. Simply delete the extra component and run a
DRC again.
7. If there is still a spacing error, then the two nodes must be really too close. One of
the nodes should therefore be moved until the error disappears.
Special nodes:
p/n active-to-metal1 contact:
cuts 2x2, separated 3
metal1 extends around cut by 1 (4x4)
active extends around cut by 1.5 (5x5)
select extends around active by 2 (8x8)
well extends around active by 6 (17x17)
poly1-to-metal1 contact:
cuts 2x2, separated 3
metal1 extends around cut by 1 (4x4)
poly1 extends around cut by 1.5 (5x5)
poly2-to-metal1 contact:
cuts 2x2 , separated 3
metal1 extends around cut by 1 (4x4)
poly2 size: 3 (3x3)
poly1-to-poly2 (capacitor) contact:
cuts 2x2 [5.1], separated 3
poly2 size: 3 (3x3)
poly1 extends around poly2 by 2 (7x7)
Transistors:
active is 3 wide and sticks out by 3 (3x8)
poly1 is 2 wide and sticks out by 2 (7x2)
transistor area is 3x2
select surrounds active by 2 (7x12)
well surrounds active by 6 (15x20)
Via1:
cuts 2x2, separated 3
DRC:
metal1-to-metal1: 3
metal2-to-metal2: 4
metal3-to-metal3: 3
metal4-to-metal4: 6
poly1-to-poly1: 3
poly1-to-active: 1
poly2-to-poly2: 3
poly2-to-active: 1
poly2-to-polyCut: 3
active-to-active: 3
select-to-trans: 3
polyCut/actCut-to-polyCut/actCut: 3
polyCut/actCut-to-via1: 2
polyCut-to-active: 2
actCut-to-poly: 2
via1-to-via1: 3
via1-to-via2: 2
via2-to-via2: 2
via3-to-via3: 4