St.

Thomas’ College of Engineering & Technology

B.Tech. 3rd Semester, September 2018

Computer Organization (CS – 303)

Full Marks: 18 Given Date: 21/08/2018 Submission Date: 03/09/2018

Assignment Number: 02 Faculty Name: Sanchita Saha Ray

CO 1: Understand the basics of computer hardware and able to examine the operation of the major building
blocks of a computer system.
CO 2: Interpret hardware design including data format, instruction format, instruction set, addressing modes,
bus structure, input/output, memory, arithmetic/logic unit, control unit, and data, instruction and address flow.
CO 3: Understand basics of systems topics: Von Neumann, Harvard architecture, parallel, pipelined,
superscalar, and RISC/CISC architectures.
CO 4: Establish how I/O devices are being accessed and their working principles.
CO 5: Impart working knowledge on Instruction Level Parallelism.

Question 1
a) Suppose a bus has 16 data lines and it requires 4 cycles of 250ns each to transfer data. What is the
bandwidth (Mbytes/sec) of this bus?
b) If cycle time is reduced to 125ns while number of cycles remained same, then calculate the
bandwidth of the bus? 3+2=5

Question 2
A Computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored
in one word of memory. The instruction has four parts:
 An indirect bit
 An operation code,
 A register code part to specify one of 64 registers
 An address part.
a) How many bits are there in the operation code, the register code part, and the address part? Draw
the instruction word format and indicate the number of bits in each part.
b) How many bits are there in the data and address bus of the memory? 3+2=5

Question 3

a) Analyse the operation of a CSA circuit for computing A+B+C+D, where each of these operands are
4 bits wide. Establish a generalized time delay expression for computing N operands.
b) What is a Wallace tree? (5+2)+1=8

Q. No CO mapping

1. a) & b) C206.2

2. a) & b) C206.2

3. a) & b) C206.2