/****************************************************************************

Module
SR_HillAndMotor.c

Description
This module acts as the low level interface to a write to the Shift Register
2 that controls output to the Flag motor, Mario motor, and Hill lights/
The flag motor and the mario motor are interfaced with the ControlSM. The Hill
lights are controlled by the ScoringSM

Notes

History
When Who What/Why
-------------- --- --------
10/18/18 19:55 pma First version

****************************************************************************/
//Defining all bits
#define ALL_BITS (0xff << 2)

// the common headers for C99 types

#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>

// the headers to access the GPIO subsystem

#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
#include "inc/hw_sysctl.h"

// the headers to access the TivaWare Library

#include "driverlib/sysctl.h"
#include "driverlib/pin_map.h"
#include "driverlib/gpio.h"
#include "driverlib/timer.h"
#include "driverlib/interrupt.h"

#include "BITDEFS.H"

#include "SR_HillAndMotor.h"
// readability defines

//
********************************************************************************
*****************

//********************For Serial DATA output from TIVA to shift

register******************
//defines for configuring the data pin
#define HillAndMotor_SR_DATA_PORT_HI BIT0HI //Port A BIT2
#define HillAndMotor_SR_DATA_PORT_LOW BIT0LO

//setting data pins

#define HillAndMotor_SR_DATA_PIN_HI BIT2HI
#define HillAndMotor_SR_DATA_PIN_LOW BIT2LO

#define HillAndMotor_SR_DATA_SYSCTL_PRGPIO SYSCTL_PRGPIO_R0

#define HillAndMotor_SR_DATA_GPIO_BASE GPIO_PORTA_BASE

//********************For SCLK output from TIVA to shift

register******************

//defines for the SCLK

#define HillAndMotor_SR_SCLK_PORT_HI BIT0HI //Port A BIT3
#define HillAndMotor_SR_SCLK_PORT_LOW BIT0LO
//setting data pins
#define HillAndMotor_SR_SCLK_PIN_HI BIT3HI
#define HillAndMotor_SR_SCLK_PIN_LOW BIT3LO

#define HillAndMotor_SR_SCLK_SYSCTL_PRGPIO SYSCTL_PRGPIO_R0

#define HillAndMotor_SR_SCLK_GPIO_BASE GPIO_PORTA_BASE

//********************For RCLK output from TIVA to shift

register******************

//defines for the RCLK

#define HillAndMotor_SR_RCLK_PORT_HI BIT0HI //Port A BIT4
#define HillAndMotor_SR_RCLK_PORT_LOW BIT0LO

//setting data pins

#define HillAndMotor_SR_RCLK_PIN_HI BIT4HI
#define HillAndMotor_SR_RCLK_PIN_LOW BIT4LO

#define HillAndMotor_SR_RCLK_SYSCTL_PRGPIO SYSCTL_PRGPIO_R0

#define HillAndMotor_SR_RCLK_GPIO_BASE GPIO_PORTA_BASE

//
********************************************************************************
******************************

/* Defines from SR_Pipe

// readability defines
#define DATA GPIO_PIN_0

#define SCLK GPIO_PIN_1

#define SCLK_HI BIT1HI
#define SCLK_LO BIT1LO

#define RCLK GPIO_PIN_2

#define RCLK_LO BIT2LO
#define RCLK_HI BIT2HI
*/

//**************Other defines ***********************************

#define GET_MSB_IN_LSB(x) ((x & 0x80) >> 7)
#define ALL_BITS (0xff << 2)
#define ALL_HI (BIT0LO | BIT0HI)
#define ALL_LOW (BIT0LO & BIT0HI)

//*********************************MODULE
DEFINES***********************************************
// an image of the last 8 bits written to the shift register
static uint8_t LocalRegisterImage = 0;

//**********************Module
Functions***********************************************
//SR_Write will not be a module function here, but a public function

/****************************************************************************
Function
SR_HillAndMotor_Init

Parameters
Nothing

Returns
Nothing

Description
A function to initialize the shift register. One of the state machine calls this
function to initialize SR2
The data and sclk lines start from low and the RCLK starts from high

Notes

Author
****************************************************************************/

// Create your own function header comment

void SRHillAndMotor_Init(void)
{
puts("\r \n Initializing SR_HillAndMotor Shift Register");

// set up the ports by enabling the peripheral clock, waiting for the
// peripheral to be ready and setting the direction
HWREG(SYSCTL_RCGCGPIO) |= HillAndMotor_SR_DATA_PORT_HI; //Port enable for
DATA
HWREG(SYSCTL_RCGCGPIO) |= HillAndMotor_SR_SCLK_PORT_HI; //Port enable for
SCLK
HWREG(SYSCTL_RCGCGPIO) |= HillAndMotor_SR_RCLK_PORT_HI; //Port enable for
RCLK

while ((HWREG(SYSCTL_PRGPIO) & HillAndMotor_SR_DATA_SYSCTL_PRGPIO) !=

HillAndMotor_SR_DATA_SYSCTL_PRGPIO)
{}

while ((HWREG(SYSCTL_PRGPIO) & HillAndMotor_SR_SCLK_SYSCTL_PRGPIO) !=

HillAndMotor_SR_SCLK_SYSCTL_PRGPIO)
{}

while ((HWREG(SYSCTL_PRGPIO) & HillAndMotor_SR_RCLK_SYSCTL_PRGPIO) !=

HillAndMotor_SR_RCLK_SYSCTL_PRGPIO)
{}

//enable DATA bit of ports for digital output

HWREG(HillAndMotor_SR_DATA_GPIO_BASE + GPIO_O_DEN) |=
HillAndMotor_SR_DATA_PIN_HI; //Setting it as Digital IO
HWREG(HillAndMotor_SR_DATA_GPIO_BASE + GPIO_O_DIR) |=
HillAndMotor_SR_DATA_PIN_HI; //Setting it as Digital Ouptut

//enable SCLK bit of ports for digital output

HWREG(HillAndMotor_SR_SCLK_GPIO_BASE + GPIO_O_DEN) |=
HillAndMotor_SR_SCLK_PIN_HI; //Setting it as Digital IO
HWREG(HillAndMotor_SR_SCLK_GPIO_BASE + GPIO_O_DIR) |=
HillAndMotor_SR_SCLK_PIN_HI; //Setting it as Digital Ouptut

//enable RCLK bit of ports for digital output

HWREG(HillAndMotor_SR_RCLK_GPIO_BASE + GPIO_O_DEN) |=
HillAndMotor_SR_RCLK_PIN_HI; //Setting it as Digital IO
HWREG(HillAndMotor_SR_RCLK_GPIO_BASE + GPIO_O_DIR) |=
HillAndMotor_SR_RCLK_PIN_HI; //Setting it as Digital Ouptut

//Not required -- Sample the button port pin and use it to initialize
LastButtonState
//LastPinState = HWREG(LEAF_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &
LEAF_SENSOR_PIN_HI;

// start with the data & sclk lines low and the RCLK line high
HWREG(HillAndMotor_SR_DATA_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &=
HillAndMotor_SR_DATA_PIN_LOW;
HWREG(HillAndMotor_SR_SCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &=
HillAndMotor_SR_SCLK_PIN_LOW;
HWREG(HillAndMotor_SR_RCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) |=
HillAndMotor_SR_RCLK_PIN_HI;

//Getting all bits of the SR2 LOW for the start

SR_HillAndMotor_Write(ALL_LOW);
}
/****************************************************************************
Function
SR_HillAndMotor_GetCurrentRegister

Parameters

Returns
uint8_t

Description
This function gives the last provided value to the shift register

Notes

Author

****************************************************************************/
// Create your own function header comment
uint8_t SR_HillAndMotor_GetCurrentRegister(void)
{
return LocalRegisterImage;
}

/****************************************************************************
Function
SR_HillAndMotor_Write()

Parameters
uint8_t NewValue

Returns
Nothing

Description
Writes to the shift register

Notes

Author

****************************************************************************/

// Create your own function header comment

void SR_HillAndMotor_Write(uint8_t NewValue)
{
uint8_t BitCounter = 0;
LocalRegisterImage = NewValue; // save a local copy
//printf("\r \n NewValue %d", NewValue);

// lower the register clock

HWREG(HillAndMotor_SR_RCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &=
HillAndMotor_SR_RCLK_PIN_LOW;

// shift out the data while pulsing the serial clock

// Isolate the MSB of NewValue, put it into the LSB position and output to
port
// raise SCLK
// lower SCLK
// finish looping through bits in NewValue
while (BitCounter < 8)
{
uint8_t LeftMostBit = GET_MSB_IN_LSB(NewValue);
//printf("\r \n Bit %d at Count %d", LeftMostBit, BitCounter);

//pushing data to port B bit 0

if (LeftMostBit == 0)
 {
HWREG(HillAndMotor_SR_DATA_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &=
HillAndMotor_SR_DATA_PIN_LOW;
}
else
{
HWREG(HillAndMotor_SR_DATA_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) |=
HillAndMotor_SR_DATA_PIN_HI;
}

//pulsing SCLK
HWREG(HillAndMotor_SR_SCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) |=
HillAndMotor_SR_SCLK_PIN_HI;
HWREG(HillAndMotor_SR_SCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) &=
HillAndMotor_SR_SCLK_PIN_LOW;

NewValue = NewValue << 1;

BitCounter += 1;
}
// raise the register clock to latch the new data
HWREG(HillAndMotor_SR_RCLK_GPIO_BASE + (GPIO_O_DATA + ALL_BITS)) |=
HillAndMotor_SR_RCLK_PIN_HI;
}