LCD26P08to42p08 PDF

维修手册
型号：LCD26P08/LCD26P08A
LCD32P08/LCD32P08A
LCD37P08/LCD40P08
LCD42P08/LCD42P08A
P08系列中文维修手册仅用于维修参考
第 1 页，共 122 页
目录
封面------------------------------------------------------------------------------------1
目录------------------------------------------------------------------------------------2
1 安全与注意事项--------------------------------------------------------------------------4
1.1 安全注意事项----------------------------------------------------------------------4
1.2 操作使用注意点--------------------------------------------------------------------4
1.3 高压警告--------------------------------------------------------------------------4
1.4 静电敏感器件（ESD）注意事项-------------------------------------------------------4
1.5 安装注意事项----------------------------------------------------------------------4
2 液晶电视规格----------------------------------------------------------------------------6
2.1 基本规格---------------------------------------------------------------------------6
2.2 LCD TV 描述------------------------------------------------------------------------7
2.3 电源连接---------------------------------------------------------------------------7
3 操作说明及调整--------------------------------------------------------------------------8
3.1 遥控器说明------------------------------------------------------------------------8
3.2 正面示意图及控制面板--------------------------------------------------------------9
3.3 菜单功能-------------------------------------------------------------------------10
4 连接介绍-------------------------------------------------------------------------------13
4.1 底面及背面连接示意图--------------------------------------------------------------13
4.2 后AV连接示意图--------------------------------------------------------------------13
4.3 机内连接示意图--------------------------------------------------------------------13
1. LCD26P08A---------------------------------------------------------------------14
2. LCD32P08A---------------------------------------------------------------------15
3. LCD37P08----------------------------------------------------------------------16
4. LCD42P08A---------------------------------------------------------------------17
5 TV电气方框图---------------------------------------------------------------------------18
6 故障处理流程---------------------------------------------------------------------------19
7 PCB LAYOUT ----------------------------------------------------------------------------24
7.1 主板-----------------------------------------------------------------------------24
7.2 电源板---------------------------------------------------------------------------26
1. MIP260B-19(LCD26P08A)---------------------------------------------------------26
2. MIP320G-A(LCD32P08A)----------------------------------------------------------27
3. MIP328B-K-1(LCD37P08)---------------------------------------------------------29
4. MIP988-J(LCD42P08A)-----------------------------------------------------------31
7.3 IR 板----------------------------------------------------------------------------34
7.4 SIED AV板------------------------------------------------------------------------34
7.5 按键转接板与薄膜按键-------------------------------------------------------------35
8 电路图---------------------------------------------------------------------------------36
8.1 主板-----------------------------------------------------------------------------36
8.2 电源板---------------------------------------------------------------------------43
1. MIP260B-19(LCD26P08A)---------------------------------------------------------43
2. MIP320G-A(LCD32P08A)----------------------------------------------------------48
3. MIP328B-K-1(LCD37P08)---------------------------------------------------------52
4. MIP988-J(LCD42P08A)-----------------------------------------------------------56
9.3 IR 板----------------------------------------------------------------------------60
8.4 按键板---------------------------------------------------------------------------61
9 主要芯片规格-------------------------------------------------------------------------62
9.1 TSUMV36K--------------------------------------------------------------------------63
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9.2 AT24CXX---------------------------------------------------------------------------70
9.3 AT26DF081A------------------------------------------------------------------------73
9.4 TDA7266SA-------------------------------------------------------------------------77
9.5 LD1117----------------------------------------------------------------------------79
10 屏&电源接口说明-----------------------------------------------------------------------86
10.1 屏接口说明-----------------------------------------------------------------------86
1.IVO M260TWR1 R1-----------------------------------------------------------------86
2.LG LC320WXE SB V1---------------------------------------------------------------91
3.LG LC370WXE SV V2---------------------------------------------------------------95
4.AUO T420HW06 V.3----------------------------------------------------------------99
10.2 电源接口规格--------------------------------------------------------------------103
1.MIP260B-19---------------------------------------------------------------------103
2. MIP320G-A---------------------------------------------------------------------105
3. MIP328B-K-1-------------------------------------------------------------------107
4. MIP988-J----------------------------------------------------------------------110
11 爆炸图-------------------------------------------------------------------------------111
12 软件升级-----------------------------------------------------------------------------115
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1. 安全与注意事项
1.1 安全注意事项
(1) 为了持续保持安全，不要企图修改电路板。
(2) 在维修之前，断开交流电源。
(3) 维修技术人员配有任何时候都可以使用的准确电压表，这一点至关重要。定期检查电压表的校准。
(4) 请不要使显示器受强烈的外力震动。
1.2 操作使用注意点
(1) 移动显示器之前请拔掉电源接线。
(2) 为安全起见，一些部件被抬高，高过印刷电路板。有时，使用绝缘管或胶带。有时，内部接线被
加起来，目的是为了防止与致热部件接触。把所有此类元件重新安装到其原来的位置
(3) 在维修后，要检查螺钉和接线是否正确地重新安装。要保证维修过的部件周围区域没有损坏。
(4) 请注意在长时间显示同一个画面后关机原来的图象信息可能还保持在上面。
(5) 检查交流插头的插片和易碰到的导电部件（如金属盘、输入端子和耳机塞孔）之间的绝缘情况。
1.3 高压警告
显示器高压是由电源升压板产生的，如果不注意接触到高压，可能被严重电击。
1.4 静电敏感器件（ESD）注意事项
一些半导体（固态）设备很容易被静电损坏，此类部件一般称为静电敏感器件器件（ESD）。典型的
ESD器件有集成电路和一些场效应晶体管。下列方法会减少静电造成部件损坏时间的发生率。
1. 在处理任何半导体部件或组件之前，要立即通过接触已知的接地点，将静电从身体上放到。另一
种发放是，带上放电的腕带装置。为了避免点击的危险，在给液晶电视加电之前，务必取下腕带。
2．在拆除有ESD的组件后，将其放到导电平面（如铝箔）以防积聚静电。
3. 不要使用带氟利昂的化学品，这会产生足以破坏ESD的电荷。
4．仅使用接地的铝铁焊接或焊开ESD.
5. 仅使用防静电除焊装置。一些不属于“防静电”类的除焊装置可能产生以破坏ESD的电荷。
6．在准备安装之前，不要将设备用ESD由保护包装中取出。绝大多数用ESD包装有导线，这些导线通
过导电泡沫与、铝箔或其它导电材料短接。
7. 即将由设备ESD导线上出去保护材料之前，应使保护材料与安装器件的地板和电路组件接触。
注意：不要给底板或电路加电并遵守其它安全注意事项。
8. 在处理没有包装的备用ESD时，要尽量减少身体的运动。一些运动如摩擦衣服或由铺地毯的地板上
抬起脚都会产生足以破坏ESD的静电。
1.5 安装注意事项
1. 为了保障安全，搬运产品需要两人以上。
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2．让电源线远离散热设备，否则外壳融化可能导致起火或触电。
3. 不要将产品置于通风不良的区域，如书架和壁橱。内部温度升高可能造成起火。
4. 把外部天线接到产片上时，要弯曲内部天线。该措施旨在防止天线受潮。否则，可能造成
起火或触电。
5. 必须保证在重新放置产品之前关闭电源并从插座拔下电源线。如果天线或外部链接器未完
全插入，还应检查天线或外部连接器。天线损坏可能造成起火或触电。
6. 让天线远离高压线，并将天线安装牢靠。与高压线接触或天线掉下来可能造成起火或触电。
7. 当安装产品时，在产品和墙壁之间留下足够的空间（10cm），以便通风。
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2. 液晶电视规格
2.1 基本规格
项目液晶电视
电视标准 PAL B/G、D/K、I
电视功能
声音系统 FM-MONO
视频1 RCA x 2(音频L/R x 2)
视频2 RCA x 2(音频L/R x 2)
视频输入 S端子 x 1
高清信号 Y、Pb、Pr x 1
影音端子 HDMI x 1
信号输入模拟:D-Sub 15 针
即插即用兼容 DDC
模拟:FH:31.5kHz 到 50kHz
PC 输入输入频率
FV:60Hz 到75Hz
推荐模拟:1360x768 (60Hz)
音频输入用于立体声的耳机迷你型插孔(3.5 ø)
视频输出功能输出TV/AV1/AV2/ 视频输出（RCA）
扬声器(内置)：6Wx2(L/R)
音频输出音频输出音频输出:L/R 用于立体声的耳机迷你型插孔(3.5 ø)
声音输出(RCA L/R)
OSD 语言中文/英文(出厂设定为中文)
底座可选
墙壁装配件可选
电源 AC 100V~240V, 50/60HZ
电源
功率消耗 26”:120W/32”:140W/37”:200W/42”:240W
温度 + 0 °C ~ + 40 °C
使用环境储存温度 - 25 °C ~ + 60 °C
湿度 10% ~ 85%
附件遥控器、电池(AAAX2)、电源线、保修单、使用说明书
640 x 480 (60/75Hz)
800 x 600 (60/75Hz)
电脑支持的格式
1024 x 768 (60Hz)
1360x768(60Hz)
480i/p
576i/p
高清支持的模式
720p
1080i/p
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2.2 LCD TV 描述
该 LCD TV 包含主板（内置音频板）、开关电源板（含逆变器）、遥控接收板、按键板。主板和电源
板含 I2C 逻辑控制总线, DDC, LCD panel 的亮度逻辑控制和通过DC-DC 转换器来提供整个主板和TTL信号
给液晶模块去驱动LCD显示电路。
2.3 电源连接
将电源线一端插入本机后下方的“交流输入”插孔内，另一端接入市电220V的电源插座上。
在您未切断电源而处于待机的情况下，电视机始终会消耗部份功率。
在长时间不使用电视情况下 , 最好将下面的电源开关关闭并将电源线从电源插座中拔下。
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3 操作说明及调整
3.1 遥控器说明回看
用来显示前一次选择的电视频道。
音量+、-键
在进入菜单状态时可以用作确认和参数调整；在未
进入菜单时为音量的加减。
频道+、-键、
在进入菜单时进行上下选择在未进入菜单时
静音
中断声音或恢复声音。
菜单
菜单下是返回主菜单，在信源下是确认功能
图像大小
包含2 种模式,重复按可切换为满屏/标准。
方向键、、、
在菜单中选择各个子菜单
声音模式
可选择关、立体声、新闻、电影、音乐、环绕
音与自设定。
彩色模式
调整成标准色温，暖色温与冷色温
睡眠
使用这个按键，您可以设置电视在多长时间之
电源
后进入待机状态。重复按这个键可以在关闭、
按这个键可以打开或待机，但电视不会完全断
15、30、45、60、90 和120 分钟之间选择。(定
电，处于节能状态。
时器从菜单消失之后所选择的分钟开始倒数计
时。
信源
按此键可显示当前可选信源，按、选择
图像制式
可以快捷更改TV制式。
0-9 -
用来选择电视频道。
图像静止
打开与关闭画面静止
显示
(1)当使用电视信号时显示频道号码及声音模丽音
式。选择丽音通道
(2)当使用电视信号之外的其它输入时，显示当前
输入源等信息
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3.2 正面示意及控制面板
待机键: 按此键可以打开或使电视进入待机状态，如果电视处在待机状态，则前面的指示灯会亮起红色。
信源键: 按此键可以变换不同的输入信源。
菜单: 按此键可以进入或退出菜单。
节目增减键：在屏幕出现菜单时，按此两键可以选择所要执行选项，在屏幕无OSD 菜单时，为TV模式时可以
换台。
音量增减键：在屏幕出现菜单时，按此两键可以确认所选择之选项，在屏幕无OSD 菜单时，为音量之调整。
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3.3 菜单功能
使用菜单
1.按菜单按钮可以显示或关闭菜单菜单。
2.使用左或右键可以选择所要调整之菜单选项。
3.使用上或下键可以进入子菜单表，或启用或调整所选择之功能，光标所在位置为调整状态。
4.按菜单按钮可以退出菜单。
电视/视频信源下的菜单画面
（注意：在不同的信源下，所能调节的功能有所不同）
按菜单按钮进入主菜单，调节项目包括：图像、声音、系统、高级、电视、电脑。请见以下详述:
图像
1. 图像模式-选择合适的图像效果（注：四种状态可选，分别是标准、艳丽、柔和、用户）。
2. 对比度-调节画面黑白层次，适当的对比度可使画面清晰明亮。
3. 亮度-调节画面的背景亮度，一般与对比度配合使用。
4. 色调-调节色彩的色调（注：只在NTSC制式图像状态下才可以选择和调整功能）。
5. 饱和度-调节色彩的鲜艳度、饱和度（注：电脑状态下无此选项）。
6. 清晰度-调节画面清晰度（注：电脑状态下无此选项）。
7. 色温-调节画面的冷暖感觉（注：三种状态可选，分别是标准、暖色、冷色）。
8. 图像大小-选择合适的图像模式（注：两种状态可选，分别是满屏和标准）。
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声音
1. 声音模式-调节声音模式（注：四种状态可选，分别是用户、标准、新闻、音乐）。
2. 低音-调节电视机的声音低频效果。
3. 高音-调节电视机的声音高音效果。
4. 平衡-调节左右音箱大小比例、
系统
1．菜单语言-选择语言的种类（注：两种语言可选，分别是中文、英文）。
2．菜单透明度-选择调节OSD的透明亮度。
3．复位-初始化设置。
高级
1. 图像降噪-图像噪点抑制（注：有四种状态可选，分别是关、低、中、高）
2. 睡眠时间-设定睡眠关机时间（注：有七种状态可选，分别是关、15、30、45、60、90、120）
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电视
1. 频道-选择频道。
2. 彩色制式-选择视频信号制式（有三种状态可选，分别是自动、PAL、SECAM）。
3. 声音制式-选择伴音信号制式（有四种状态可选，分别是D/K、M、B/G、I）。
4. 跳跃-台号跳跃功能。
5. 微调-微调功能
6. 手动搜台-手动搜台功能。
7. 自动搜台-自动搜台功能。
8. 丽音-选择丽音或者单声道（注:当地电视台如有发送丽音伴音信号，才能选择。）
电脑(只在电脑信源下有作用)
1．水平位置-调节画面的水平位置。
2．垂直位置-调节画面的垂直位置。
3．时钟-调节画面的时钟频率。
4．相位-调整A/D的采样相位。
5．自动-自动调节屏幕显示到最佳状态
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4.连接介绍
4.1 底面及背面连接示意图
4.2 后AV端子示意图
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4.3 机内连接示意图
1、LCD26P08A
二合一电源板 T-CON 板 LCD 显示屏
主板
薄膜按键
侧 AVAV
SIDE 板板
接收板
按键转接板喇叭
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2．LCD32P08A
二合一电源板 T-CON 板 LCD 显示屏
主板
薄膜按键
SIDE AV 板
接收板
按键转接板喇叭
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3．LCD37P08
电源板 T-CON 板 LCD 显示屏
逆变器（右）
逆变器（左）
主板
薄膜按键
SIDE AV 板
接收板
按键转接板
喇叭
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3．LCD42P08A
电源板 T-CON 板 LCD 显示屏
平衡板
逆变器
主板
薄膜按键
SIDE AV 板
接收板
按键转接板
喇叭
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5. TV电气方框图
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6.故障处理流程
6.1板故障处理
1、无显示（LED不亮）
不加电
NG
检查电源接口重插接口
OK
NG
检查F1、BD1、D101 更换F1或BD1或D101
OK 检查负载
NG
检查U2、Q104、D109(VCC) 更换U2或Q104或D109
OK
NG
检查 U1、Q101 更换 U1 或 Q101
OK
NG
检查 T103 更换 T103
OK
NG
检查 D103、D13、Z101 更换 D103 或 D13 或 Z101
OK
NG
检查 L404 检查 L404
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2、无显示（LED亮红色灯）
无显示
LED红色
NG
检查 +3.3V_STB 更换 U4
OK
NG
检查 +3.3V 更换 U3
OK
NG
检查 VCC1.26V 更换 U1
OK
NG
检查 Q15、D43 更换 Q15、D43
OK
NG
检查 X1 更换 X1
OK
NG
检查 U14 更换 U14
OK
NG
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3、无显示（LED不亮）
无显示
NG NG
检查主板 12V 供电检查 Z102 更换 Z102
OK OK
NG NG NG
更换Q8 检查Q8 检查主板 5V 供电检查 L105 更换 L105
OK OK
NG NG
更换 Q20 或 Q19 检查 CN503 3、4 检查 L105 更换 L105
OK OK
NG NG
更换 U17 检查 LVDS VCC 检查 D104、D105、D106、D107 更换 D104 或 D105 或 D106 或 D107
OK OK
NG NG
更换 U15 程序检查 LVDS sigal 检查 T101 更换 T101
OK
NG
检查 T102、Q102、Q103 更胡 T102 或 Q102 或 Q103
OK
NG
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4、画面异常
画面异常
NG
检查信号源更换信号源
OK
NG
检查 LVDS 线连接重插 LVDS 接口或更换 LVDS 线
OK
NG
检查各输入端滤波电容和磁珠更换入端滤波电容和磁珠
TV 信号
NG
TV 信号制式重设信号制式 AV、S-VIDEO、YPbPr、VGA、HDMI 信号
OK
NG
检查高频头、声表面更换高频头、声表面
OK
NG
检查 U8 更换 U8
OK
NG
检查 PANEL 更换 PANEL
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5、无声
无声
NG
检查信号源重插信号源
OK
NG
检查各输入端滤波电容和磁珠更换入端滤波电容和磁珠
OK
TV 信号
TV 信号制式 NG
重设信号制式 AV、S-VIDEO、YPbPr、VGA、HDMI 信号
OK
NG
检查高频头、声表面更换高频头、声表面
OK
NG
检查 U8 更换 U8
检查 Q40、Q26、Q39、Q23 NG
更换 Q40 或 Q26 或 Q39 或 Q23
OK
NG
检查 Q12 更换 Q12
OK
NG
OK
NG
检查喇叭更换喇叭
第 23 页，共 122 页
5 PCB LAYOUT
5.1 主板
正面视图
第 24 页，共 122 页
第 25 页，共 122 页
5.2 电源板
1.MIP260B-19(LCD26P08A)
第 26 页，共 122 页
2、MIP320G-A(LCD32P08A)
1) TOP
第 27 页，共 122 页
2)BOTTOM
第 28 页，共 122 页
3、MIP328B-K-1(LCD37P08)
1)TOP
第 29 页，共 122 页
2)BOTTOM
第 30 页，共 122 页
4、MIP988A-J（LCD42P08A）
1)TOP
第 31 页，共 122 页
2)BOTTOM
第 32 页，共 122 页
2)BOTTOM
第 33 页，共 122 页
5.3 IR板
5.4 SIDE AV板
第 34 页，共 122 页
5.5 按键转接板与薄膜按键
第 35 页，共 122 页
5 4 3 2 1
7 电路图
7.1 主板
+3.3STB VDDP_PM
+12V 5VCC +5VSTB +5VSTB +3.3STB 1.4mA
CN504
+3.3STB
1 +3.3STB 5
D
1)Power 2
3
4
5
R128
4.7K
R6
4.7K
C3
0.1uF
+5VSTB
+5VSTB 3,5
D
6
7 SW L2 AVDD_MPLL 5VCC
8 5VCC 4,6,7,8
R2 4.7K FB
3
9 6.8mA +12V
3
10 R7 1K Q2 +12V 4,7,8
Q1 1 R9 4.7K WAKEUP
11 1 3904
C2 3904
C6 C7 VDDP
VDDP 5
2
C138
2
P11/2.54MM 0.1uF 2.2uF C8 C9
CON2.5_11 0.1uF 0.1uF 0.1uF 100pF
For PM Mode==> WAKEUP
WAKEUP 5
AVDD_MPLL
VDDP_PM & AVDD_MPLL must be alive AVDD_MPLL 5
+3.3V L4 AVDDA VDDP

295mA 78mA +3.3V
FB AVDD_AU 5,6,7
4
+3.3V
+3.3V 5,6,7
如果直接输入5V
LDO就需选择大封装
VCC1.26V C14
2.2uF
C15 C16 C17 C18 C19 C20 C21 C22 C23
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
U1
GPIO Define AMS1117-ADJ

TV 380mA
ADJ
OUT
IN
C 5VCC C
VCC1.26V
20090626_ECN R114 R113
3
2.2R/2W 2.2R/2W 1.25V
PIN115: Standby Power WAKEUP
PIN77 GPIOD0: LED CONTROL G CA7
CA12
PIN76 GPIOD1: SCART ENABLE SC_EN + C37 C38
+
+3.3V AVDD_AU
PIN70 AD1: 24C32 EEPROT WITE PROTEL 100uF/16V 0.1uF 0.1uF
100uF/16V
14mA
PIN71 AD0: Audio AMP Mute
C27
0.1uF
PIN59 PWM3: 12V BOOT TO 40VDC
PIN60 PWM2: FLASH WP +3.3V L5 AVDD_VIF
PIN62 PWM0: Backlight Diming Control FB 142mA
PIN66 RDZ: LVDS Power Switching TO-252封装,贴片SOT-223

PIN67 WRZ: Backlight ON/OFF Control YPbPr 1080P 500mA
+3.3V_STB +
CA5 C28 C29 C30 C35

PIN68 AD2: I2C_SCL U4 10uF/16V 100pF 0.1uF 0.1uF 1uF
AMS1117-3.3
4
PIN69 AD3: I2C_SDA R8 Schematics pages list:
4
B U3 B
PIN65 ALE: NO USE R5
ADJ
OUT
AMS1117-3.3
PIN106 IRIN: IR_SYNC 301 01.BLOCK
IN
ADJ
OUT
IN
PIN107 SAR2: 4052_CTL 301

02. LDO & Power Decoupling
3
+3.3STB VCC1.26V VDDC
PIN108 SAR1: KEYPADS control2
1
+3.3V 380mA
PIN109 SAR0: KEYPADS control1
+5VSTB R131 0ohm/NC
Index & Power Connector
L3 FB/NC
5VCC
PIN114: HDCEC 20090626_ECN R10 C13
R11
03.HDMI & VGA Interface
C31
PIN126: HDMI HOT PLUG HPLUG C25 CA4 8mA 2.2uF C32 C33 C34
C24 C26
0.1uF
0.1uF
511
C137 C11 0.1uF 0.1uF 0.1uF 04.IF Interface
2.2uF 0.1uF 2.2uF 0.1uF
511 100uF/16V
05. 36KU
06.Audio AMPLIFIER Interface
07. LVDS OUT& Panel interface
HOLE/GND HOLE/GND HOLE/GND
E1
HOLE/GND HOLE/GND
08.Video & Audio Interface
H6 H1 H2 H3 HOLE/GND H5
1 6 H4
A A
9 2 9 2 9 2 2 7 9 9 2 2 9 2 9 2
9 2 9 2 9 2 9 2 9 2
8 3 8 3 8 3 3 8 8 8 3 3 8 3 8 3
8 3 8 3 8 3 8 3 8 3
7 4 7 4 7 4 4 9 7 7 4 4 7 4 7 4
7 4 7 4 7 4 7 4 7 4 M1 M2 M3 M4
6 5 6 5 6 5 5 10 6 6 5 5 6 5 6 5
6 5 6 5 6 5 6 5 6 5 JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z
1
1
1
1
Title
1
1
1
1
EMC DGND POWER

EMISD
Size Document Number Rev
Custom JPE_36KURW_V01 01
第 36 页，共 122 页 Draw: Zhangwd Date: Wednesday, July 28, 2010 Sheet 2 of 8
5 4 3 2 1
5 4 3 2 1
2)HDMI&VGA INPUT INTERFACE

24C02=>EDID code must Layout Placement Layout Placement
be upto 256byte space, PC audio Input close to connect. close to Mstar IC
for HDMI interface.
D
J402 HDMI HD_+5V1
D2
BAT54C
+5VSTB
R
D
4 R54 10K C45 2.2uF

PC_AUR0 5
2
GND 20
3
GND 21 R55 C47
HD5V R15 R16 HD_+5V1 5
GND 22 HD5V C46
2
GND 23 L
22pF 12K 560pF
10K 10K HD5V 1
J408 D23
U6
NC
C39
1
+5V 18 8 VCC NC 1 PHONEJACK_STEREO
17 7 2 0.1uF
CEC/DDC GND WP NC PHONEJACK/5P/DIP R56 10K C48 2.2uF
15 DDC_CLK_IN R17 100R 6 3 PC_AUL0 5
DDC SCL DDC_DAT_IN SCL NC
2
DDC SDA 16 5 SDA GND 4 C50
13 CEC R18 100R
CEC R57
19 HPD 24C02
HPD C49 560pF
22pF 12K
Dat2 shield 2 D24
5 CEC R32 200R HDCEC
Dat1 shield HDCEC 5 NC
1
Dat0 shield 8
11 R19 100R SDA_HD
clk shield SDA_HD 5
R20 100R SCL_HD
SCL_HD 5
16
C 7 RX_0+ R21 10R B_TX0+ VGA_TX 11 1 R R33 33R C40 47nF C
DAT0+ B_TX0+ 5 RIN+ 5
9 RX_0- R22 10R B_TX0- 6
DAT0- B_TX0- 5
4 RX_1+ R23 10R G_TX1+ 12 2 G R34 33R C41 47nF
DAT1+ G_TX1+ 5 GIN+ 5
6 RX_1- R24 10R G_TX1- 7
DAT1- G_TX1- 5
1 RX_2+ R25 10R R_TX2+ 13 3 B R35 33R C42 47nF
DAT2+ R_TX2+ 5 BIN+ 5
3 RX_2- R26 10R R_TX2- 8
DAT2- R_TX2- 5
10 RX_C+ R27 10R TXCLK+ 14 4 VGA_RX R38 0R C43 1nF
clk+ TXCLK+ 5 R37 R39 SOG 5
12 RX_C- R28 10R TXCLK- 9 VGA5V R36
clk- TXCLK- 5
15 5 D16 D17 D18 75R 75R 75R
10
J406 R- close to MST IC
17
HDMI VGA
NC NC NC G-
B-
R40 100R HS-RGB

HS-RGB 6 +5VSTB
+5VSTB 2,5
R41 100R VS-RGB
VS-RGB 6
B B
DDC_SCL R42 NC/100R RXD
RXD 5
DDC_SDA R45 NC/100R TXD
TXD 5
+5VSTB R46 4.7K R43 R44 VGA_TX R47 100R/NC

D22
R48 4.7K VGA_RX R49 100R/NC
2.2K 2.2K
VGA5V C44 R51 R52

0.1uF U7 100R 100R
BAT54C 1 8
NC VCC
2 NC VCLK 7
HD5V 3 6
NC SCL
4 GND SDA 5
HD5V
NC/24C02
R29
1K R30
NC/10K
A HPD A
3
JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z

Q4 1 R31 4.7K HPLUG
HPLUG 5
MMBT3904
Title
HDMI & VGA INPUT INTERFACE
2
HOTPLUG Size Document Number Rev

第 37 页，共 122 页 Custom JPE_36KURW_V01 01
Draw: Zhangwd Date: Friday, January 22, 2010 Sheet 3 of 8

5 4 3 2 1
5 4 3 2 1
3)IF INTERFACE
TU1 +12V +12V
+12V 2,7,8
TUNER
VIF_12V 5VCC
14
15
16
17
18
19
20
21
13
12
5VCC 2,6,7,8
R65
D 150R VIF_12V D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5VCC
C55 C56
2.2uF 10nF R66 R67

6.8K L8 680R
IFout
L15
AGC
SDA
NC1
NC2
NC3
SCL
5V-IF
33V
0.82uH
AS
5V
5V
NC/2.2uH
1
2
3
4
5
6
7
8
9
10
11
L9 IF_TV R68
R69 C57 1.2K
100uH/NC
SDA
SCL
C58 56R 10nF
IF-AGC
2
+ + Tuner_+30V 40V 10nF
CA10 CA8 C59 1
47uF/16V C92 47uF/16V 0.1uF
0.1uF R75 1K Q5
3
2SC2216/2SC2217
L13 R73 R70
C60 C61 D28 R76 R71 R72
1K 20R
0.1uF 100pF 1K NC/0R
NC/2.2uH
C 33V 100K C
SDA R78 10R I2C_SDA

I2C_SDA 5,7
SCL R81 10R I2C_SCL
I2C_SCL 5,7
SAW1 SIF
5V-IF C62
C63 C64 K9653M30/K9650M
22pF 22pF 1 5 SIFP
R83 IN SAWOUT2 SIFP 5
D30
1N4148 4K7
10nF SIF
GND
2 4 SIFM
ING OUT1 SIFM 5
IF-AGC TAGC
TAGC 5
3
R82 R85
12K
B B
C65 C66
100K 0.1uF 0.1uF SAW2
K3959M30/K3953D
+12V 1 5 VIFM
IN SAWOUT2 VIFM 5
C68
R89 10 L11 220uH 40V

10nF VIF
GND
C98 2 4 VIFP
D31 1N4148 ING OUT1 VIFP 5
0.1uF
3
3
CA9
PWM3 R90 4.7K 1 Q7 +
5 PWM3 MMBT3904
PWM3 DUTY MUST BE 0x23(CANN'T >0x40), C175 2.2uF/50V
2
or will destroy Q44!

680PF
WARNING !!!
A A
Title
IF Interface
第 38 页，共 122 页
Draw: Zhangwd Date: Wednesday, July 28, 2010 Sheet 4 of 8
5 4 3 2 1
5 4 3 2 1
4)SCALE
AVDD_MPLL
CL=20pf of XTAL
AVDD_VIF
VDDP_PM
AVDD_AU
+3.3STB C109
27pF VDDP_PM
+3.3STB 2
HWRESET
VDDP VDDC VDDP VDDP
VDDP 2
3
D43 X1 R159 +5VSTB
R158 2 BAV99 R161 200R +5VSTB 2,3
C110 14.318MHZ 1M AVDD_MPLL

+ CA20 AVDD_MPLL 2
10uF/16V 27pF
AVDD_AU
113
110
123
118
116
102
2
AVDD_AU 2,6,7
25
24
23
15
78
54
90
64
57
56
38
36
28
27
100K
7
1
D R160 4.7K1 Q15 D
+3.3V
3906 AVDD_AU 2,6,7
VDDP_2
AVDD_MPLL
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
XIN
XOUT
HWRESET
VDDC
VDDC
VDDC
AVDD_DVI
AVDD_ADC
AVDD_ADC
AVDD_AU
AVDD_VIF
AVDD_VIF
AVDD_VIF
R162
SYS_RST HWRESET
3
C111 R163 100R
2.2uF C112 5VCC

SCL_HD 111 5VCC 2,4,6,7,8
1nF SDA_HD DDCDB_CK
112 DDCDB_DA
2 4 6 8 2 4 6 8
TXCLK- RXO0-
1 3 5 7 1 3 5 7
22K 119 RXACKN LVA0P 100 RXO0- 7
TXCLK+ 120 99 RXO0+
RXACKP LVA0M RXO0+ 7
B_TX0- 121 RXA0N LVA1P 98 RP1 RP22X4RXO1-
RXO1- 7
B_TX0+ 122 97 RXO1+
RXA0P LVA1M RXO1+ 7
G_TX1- 124 96 RXO2-
RXA1N LVA2P RXO2- 7
G_TX1+ 125 95 RXO2+
RXA1P LVA2M RXO2+ 7
TXCLK- HPLUG 126 HPLUGA LVACKP 94 RP2 RP22X4RXOC-
RXOC- 7
3 TXCLK- R_TX2- RXOC+
TXCLK+ 127 RXA2N LVACKM 93 RXOC+ 7
3 TXCLK+ R_TX2+ RXO3-
B_TX0- 128 92 RXO3- 7
PANEL
3 B_TX0- RXA2P LVA3P
B_TX0+ 91RP22X4 RP3 RXO3+
1 3 5 7
2 4 6 8
3 B_TX0+ LVA3M RXO3+ 7
DVI/HDMI
G_TX1- RXE0-
RXE0- 7
INTERFACE
3 G_TX1- RXE0+
G_TX1+ LVB0P 89 RXE0+ 7
3 G_TX1+ PB+
R_TX2- 2 BIN1 LVB0M 88
3 R_TX2-
INPUT
R_TX2+ SOY 3 87 RXE1- +5VSTB

3 R_TX2+ SOGIN1 LVB1P RXE1- 7
SDA_HD Y+ 4 86 RXE1+
1 3 5 7
2 4 6 8
3
3
SDA_HD
SCL_HD
SCL_HD R164 68R C113 47nF 5
GIN1
GIN1M
LVB1M
LVB2P 85RP22X4 RP4 RXE2-
RXE1+
RXE2-
7
7
Debug port
HDCEC PR+ 6 84 RXE2+
3 HDCEC RIN1 LVB2M RXE2+ 7 UART0
2 4 6 8
RXEC-
1 3 5 7
HPLUG LVBCKP 83 RXEC- 7 R204 R203
3 HPLUG HS_RGB RXEC+ CON3
8 HSYNC0 LVBCKM 82 RXEC+ 7 Debug Port
BIN+ 9 BIN0 LVB3P 81 RP5 RP22X4RXE3-
RXE3- 7
R167 68R C114 47nF 10 80 RXE3+ 1
GIN0M LVB3M RXE3+ 7
HS_RGB GIN+ 11 10K 10K RXD 2
INPUT
6 HS_RGB SOG GIN0 3

VS_RGB 12 SOGIN0 TXD
6 VS_RGB RIN+ 4
BIN+ 13
VGA
3 BIN+ VS_RGB RIN0

3 SOG
SOG
GIN+
14 VSYNC0 U8 CON4-2.0MM
C 3 GIN+ SV_C0 C
RIN+ 16 CVBS3P
3 RIN+ SV_Y0 WAKEUP
17 CVBS2P WAKEUP 115
CVBS1 18 114 HDCEC
CVBS1P CEC
Y,Pb,Pr
PR+ CVBS0 19 109 do not use GPIO function in PAD_INT

TSUMV26KU
INPUT
6 PR+ R171 68R C115 47nF CVBS0P SAR0 R172 0R SAR1

SOY 20 108 if the system need HDMI_CEC function
6 SOY VCOM0 SAR1 SAR2
Y+ SAR2 107
6 Y+ CVBSOut1 21 R174 100R IR_SYNC
PB+ CVBSOUT IRIN 106
6 PB+
INT 105
CVBS0 104 TXD +5VSTB +5VSTB
6 CVBS0 DDCA_DA TXD 3
VIFP 30 103 RXD
VIFP DDCA_CK RXD 3
VIFM 31 I2C address
SIFM VIFM C127
32 SIFM at A0.
SV_C0 SIFP 33 77 R168 100R LED_G
6 SV_C0 SIFP GPIOD[0] 0.1uF
SV_Y0 CA21 10uF/16V SC_EN
+
76
VIDEO
INPUT
6 SV_Y0 GPIOD[1] SC_EN 6 R185

CVBS1 35 R186
6 CVBS1 VR27
C116 0.1uF U14
CVBSOut1 TAGC 4.7K 4.7K
6 CVBSOUT1 37 TAGC 1 8
SPI_CK A0 VCC
SCK 75 2 7
SPI_CZ A1 WP I2C_SCL
SCZ 74 3 6
SPI_DI A2 SCL I2C_SDA
SDI 73 AD[1]不能上拉到5V 4 5
C118 C119 PC_AUL0 SPI_DO1 GND SDA
39 LINE_IN_2L SDO 72
0.1uF 100pF PC_AUR0 R183 100R AMP-MUTE 24C32
40 LINE_IN_2R AD[0] 71
PC_AUL0 AV_AUL1 41 70
3 PC_AUL0 LINE_IN_3L AD[1]
PC_AUR0 AV_AUR1 42
3 PC_AUR0 LINE_IN_3R
AV_AUL1 AV_AUL2 43 69 R180 100R I2C_SCL
6 AV_AUL1
AUDIO
I2C_SCL 4,7
INPUT
AV_AUR1 AV_AUR2 LINE_IN_4L AD[2] R181 100R I2C_SDA

6 AV_AUR1 44 LINE_IN_4R AD[3] 68 I2C_SDA 4,7
COMP_AUL2 67 ON-PBACK
6 AV_AUL2 WRZ
COMP_AUR2 R182 0R C123 0.1uF 45 66 ON-PANEL
6 AV_AUR2 AUCOM RDZ
65 SIF-CTL
AUVRADN ALE
46 AUVRM
AUVRADP 47
AUOutL2 AUVRP
6 AUOutL2 AUVREF 48 62 PWM0
AUOutR2 AUVREF PWM0 ADJ-PWM 7
OUTPUT
6 AUOutR2 61
AUOutL1_amp PWM1
AUDIO
8 AUOutL1_amp 60
B AUOutR1_amp PWM2 B
8 AUOutR1_amp CA22 + C124 C125 C126 AUOutL1_amp 50 59 PWM3
DAC_OUT_0L PWM3 PWM3 4
AUOutR1_amp 51
10uF/16V 0.1uF 4.7uF 1uF AUOutL2 DAC_OUT_0R
52 LINE_OUT_0L
VIFP AUOutR2 53 PWM freq :
4 VIFP LINE_OUT_0R
VIFM from 6MHz ~ 12M/2^34(=0.0007)Hz
INPUT
4 VIFM +5VSTB +3.3STB

SIFP
4 SIFP
SIFM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VIF
4 SIFM
4 TAGC
TAGC R178
4.7K
Key&IR Pad CN502
1
22
26
29
34
49
55
58
63
79
101
117
P5/2.0MM
R179 FB
IR_SYNC L30
NC/4.7K 1
R184 2
L29 FB
L18 0 3
120R/FB0603 L28 FB 4
+3.3STB
GPIO Control Pins C158 C159 L27 FB 5
3
+3.3STB C154 C155 C156 C157
+3.3STB +3.3STB LED_G 1 0.01uF
C128 22pF
Q17 0.01uF 0.01uF0.01uF
CON_5_2.0
0.01uF
+3.3STB NC
2
0.1uF
U15
R175
R188
R189
R190
R192
R193
R208
R195
R177
R209 EN25F80_100GCP
4.7K
CZ 1 8
CE# VDD
10K
10K
10K
10K
10K
10k
NC/10K
R220
10K/NC
10k
SO 2 7
SO HOLD# LED_G 8.2K
3 6 SCK ON-PANEL RDZ
WP# SCK ON-PANEL 7
PWM3 SAR1
AD[0] PWM3 4 L25 FB 2
4 5 SI AMP-MUTE AMP-MUTE 8 L24 FB
VSS SI WAKEUP 1
GPIOD[0] WAKEUP 2
ADJ-PWM D46 C152 C153
ADJ-PWM 7
A C121 A
ON-PBACK WRZ CN506
ON-PBACK 7 0.1uF 0.01uF
NC 0.01uF H2P
SPI_CK SCK SIF-CTL ALE
SIF-CTL 8
SPI_CZ RP6 CZ C129
1 3 5 7
2 4 6 8
SAR2
SPI_DI RP22X4 SI SAR2 6
SPI_DO1 SO NC/22pF
Title
第 39 页，共 122 页
SCALE
Draw: Zhangwd Date: Friday, January 15, 2010 Sheet 5 of 8

5 4 3 2 1
5 4 3 2 1
5)VIDEO&AUDIO
CVBS1
CVBS1 5
R91 33R
C70
47nF
R94
J403 AUDIO&VIDEO Input 75R Close to MST IC J401
12
11
10
D D
12
11
10
Y1_IN R59 33R C52 47nF Y+

Y+ 5
AV2 AV_OUT
C71 R61 0R C54 1nF SOY
AUL1_AV R92 AV_AUL1 AV_AUL1 5 SOY 5
2
8
3
4
9
5
6
7
2
8
3
4
9
5
AUR1_AVAUR1_AV 10K 2.2uF Pb_IN R60 33R C53 47nF PB+

R95 C74 PB+ 5
AV2_RIN AUR1_AV AV_AUR1 AV_AUR1 5 AV_ROUT
10K 2.2uF R58 33R C51 47nF PR+
PR+ 5
R96
AUL1_AV AUL1_AV C72 C75 R93 C76 Pr_IN
12K C73 AV_LOUT
AV2_LIN
22pF 22pF 12K D25 D26 D27 R62 75 ohm colse to Mstars IC
560pF 560pF R63 R64
2
2
RCA2X3 RCA2X3
RCA/6P/DIP/JPE D32 D33 D34 RCA/6P/DIP/JPE
75R 75R 75R
NC
NC
NC
Close to connector Close to MST IC NC NC NC

1
Layout Placement close to Mstar IC 5VCC

5VCC 2,4,7,8
S-Y
+5VSTB
+5VSTB 2,3,5
SV_Y0 +3.3V
SV_Y0 5 +3.3V 2,5,7
J301
2
C C
R97 C77
3
S_VIDEO COAXIAL
33R 47nF
6 D35
NC R98 VCC-OP1 VCC-OP1 VCC-OP1
G
VCC-OP1
Y
75R VCC-OP1 8
5
1
C
R308 R200
G
7
5VCC 1k 1k
audio_OUT
4
S-C SV_C0 C103

SV_C0 5
2
2.2uF AV_LOUT
3
R99 C78
R100 33R 47nF R305 1K 1 Q14
D36 R223 R224 5 AUOutL2
NC 75R MMBT3904
1k 1k C104
2
2.2uF AV_ROUT
3
1
R123 0 R311 1K 1 Q13

5 AUOutR2
R121 0 MMBT3904 D41 D42
J10
220K
220K
1nF
1nF
R313 NC NC
2
S-C C190
10 470R
10 12 13 2.2uF
9 3 HS-RGB X0 X HS_RGB 5 Gain=R314/R313
9
C260
R304
C259
R302
8 S-Y 14 X1 R312
8 15 C191 470R
7 7 SC_FS X2 2.2uF
6 AV2_LIN 11 X3 Y 3 VS_RGB 5
6
5 5 3 VS-RGB
4 AV2_RIN 5VCC
4 AV2 1 16 5VCC
3 3 Y0 VCC Gain=R308/R312
5 8
2 2
2
Y1 GND
6 C88 Near MST.IC
1 1 SC_FB Y2 INH 0.1uF
B 4 7 B
R126
4.7k
Y3 VEE Ground in the middle of the L/R
CON6
10 A
5VCC
VIDEO_OUT
3
Q10 9 B
SAR2 R124 4.7k 1 3904
5 SAR2 U22 L12 FB
74HC4052/NC
2
J407 C79 C80

SCART/NC 2.2uF 0.1uF R101 R102
R103 22k 220R
21 SHIELD
2
33R
20 V_IN AV2 CVBS0
CVBS0 5
19 V_OUT AV_OUT 1 Q8
C81 47nF C89
3
18 BLANKGND Q9 3906
17 VGND R109 5 CVBSOut1 1 3904
3
AV2_LIN AV_AUL2
16 BLANK SC_FB AV_AUL2 5
15 R Pr_IN 10K R105 220R R106 75R AV_OUT
2
R104 R110 C84 C82 2.2uF R107
14DATAGND R120
C83
2
RGND 75R 2.2uF 10k R108
13 22pF 12K 560pF
12 DATA 75R +3.3V 75R D40
11 G Y1_IN
NC
10 CLKOUT
9 GGND R111 AV_AUR2
8 SWTCH R116 10k SC_FS AV2_RIN AV_AUR2 5
1
7 B Pb_IN 10K
R112 C85
6 A_IN_L AV2_LIN
R119 C86 2.2uF
C87
5 BGND 2.7k 12K 560pF
22pF R136
4 AGND
4.7k
3 A_OUT_L AV_LOUT
A
2 A_IN_R AV2_RIN YPrPb R137 100 SC_EN
SC_EN 5
A
1 A_OUT_R AV_ROUT Close to connector Close to MST IC

3
Q16
SC_FS R135 10k 1
3904
2
20090902_ECN
Title
第 40 页，共 122 页 Video Audio SCART Interface
Draw: Zhangwd Date: Thursday, January 14, 2010 Sheet 6 of 8

5 4 3 2 1
5 4 3 2 1
6)PANEL
DIP40/P2.0
P20x2/2.0MM
LVDSVDD 40 39 LVDSVDD
LVDSVDD 38 37 GND
D GND 36 35 GND D
+12V 5VCC L220 AM2309GN RXO0- RXO0+
R234 34 33
NC/0R/1206 U17 AP2309/NC RXO1- RXO1+
NC/0R/1206 32 31
LVDSVDD RXO2- 30 29 RXO2+
GND 28 27 GND RXO0-
2 3 RXOC- RXOC+ 5 RXO0-
26 25 RXO0+
C130 RXO3- RXO3+ 5 RXO0+
L230 24 23 RXO1-
1k
5 RXO1-
R231 1k
0R/1206 RXE0- 22 21 RXE0+ RXO1+
1uF/16v + CE5 +3.3V RXE1- RXE1+ 5 RXO1+
100uF/16v 20 19 RXO2-
5 RXO2-
R232
RXE2- RXE2+
1
18 17 RXO2+
R210 C95 GND GND 5 RXO2+
16 15 RXOC-
100K 0.1uF RXEC- RXEC+ 5 RXOC-
14 13 RXOC+
2 R211 R221 RXE3- 12 11 RXE3+ 5 RXOC+
RXO3-
D38 +3.3V 5 RXO3-
NC/0R 10 9 RXO3+
100k 5 RXO3+
+3.3V 8 7
1N4148 DCR_OUT 6 5 DCR_ON
4 3 GND
1
R233 R222 R228

330 2 1
10K NC/0R R226 +3.3V
3
5 RXE0- RXE0-
R225 4K7 Q18 R230 R229 NC/0R RXE0+
C 1 NC/0R NC/0R 5 RXE0+ C
3904 RXE1-
LOW = > LVDS POWER OFF CN508 5 RXE1-
C132 RXE1+
5 RXE1+
0.1uF/16v
2
HIGH = > LVDS POWER ON RXE2-

3
5 RXE2-
R212 10K Q22 RXE2+
ON-PANEL 1 5 RXE2+
3904 RXEC-
5 RXEC-
R227 5 RXEC+ RXEC+
I2C_SCL
2
10K I2C_SDA 5 RXE3- RXE3-

+3.3V 5 RXE3+ RXE3+
R214
1k +24V
R235 +24V 8
120
BL_ON/OFF +12V
+12V 2,4,8
C136 5VCC
3
R217 C99 5VCC 2,4,6,8

Q20
ON-PBACK 1 0.1uF +3.3STB
3904 0.1uF +3.3STB 2,5
B CN503 B
4.7k P4/2.0MM +3.3V
2
+3.3V 2,5,6
+3.3V ONOFF
4 I2C_SCL
I2C_SCL 4,5
3 ADJ
R213 2 GND I2C_SDA
I2C_SDA 4,5
1k 1
NC
R173 ON-PANEL
D39 1N4148 R218 NC/4.7K R215 con4 ON-PANEL 5
120 +24V
1 2 DCR_ON DCR_OUT
ON-PBACK
L22 ON-PBACK 5
3
0 FB
Q19 L21 ADJ-PWM
ADJ-PWM R216 NC/4.7K 1 C135 C101 C145 ADJ-PWM 5
3904 FB C143
1uF 1uF 1uF
R219 1uF
C139
10k
2
2.2uF
A JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z A
Title
PANEL I/F

5 4 3 2 1
5 4 3 2 1
7)AMPLE +12V
R274
10R
HS2
1 GND GND 2
D VCC-OP1 D
HEATSINK
+ CA11
47uF/16V HS1 U12 U11
R276
470R
1 GND GND 2 TDA7297
TDA7297
TDA7266SA
TDA7266SA Audio AMP +3.3V +3.3V
+3.3V 2,5,6,7
PW-GND
2
+12V HEATSINK +12V
+12V 2,4,7
OUT1+
OUT2+
S-GND
OUT1-
OUT2-
ST-BY
MUTE
1 Q26
VCC
VCC
3906 5VCC
IN1
IN2
NC
NC
NC
5VCC 2,4,6,7
Gain=R285/R291+1
3
3
10
11
12
13
14
15
R278 1K 1 Q40 VCC-OP1 VCC-OP1
5 AUOutL1_amp MMBT3904 C174 VCC-OP1 6
2.2uF
220K
1nF
2 VD +24V +24V
R285 220R C173 AMP-LIN +24V 7
2.2uF MUTE CE1 + C163 SIF-CTL
SIF-CTL 5
C236
R288
R291 R122 C168 C164 C165

100R 1R/3W/P5.0 ST-BY 470uF/25V 0.1uF/50V
0.1uF/50V 1.5nF 1.5nF AMP-MUTE AMP-MUTE 5
R125
1R/3W/P5.0
Ground in the middle of the L/R
VCC-OP1 CN601
C R129 C
AMPRIN 1K C169 2.2uF 5 LOUT+
R130 4 LOUT-
R281 AMPLIN 1K C170 2.2uF
Near MST.IC 470R
2 Gain=R295/R298+1 3
2
ROUT+
ROUT-
C96
1 Q23 1 ROUT+
AUDIO Pre AMP 3906 R133
10K
1.5nF C90
C91 C166 con5
3
3
C171 AMP-RIN C97 1.5nF C167 P5/2.54mm

R134
R294 1K 1 Q39 2.2uF 1.5nF 1.5nF 1.5nF
5 AUOutR1_amp MMBT3904 10K 1.5nF
220K
1nF
R295 220R C172

2.2uF
C237
R299
R298
100R R139
VCC-OP1 CTL
J20
4.7K +24V 1
R165 MUTE 2
10K 3
4
3
+12V AMPLIN 5
5VCC +24V Q21
B 1 AMPRIN 6 B
5 SIF-CTL 3904
R140
H : WP DISABLE
2
L : WP ENABLE10K P6/2.0MM
R142 CON6_2.0
R146 R141
NC/47K R145 47K
NC 0 R143 4.7K R144 ST-BY
VD
NC/0 J410
1 + CE3
D29 R147 R148
220uF/16V 5VCC AMP-Rin 4
R
3 BAV99 22K C93
R151 R150 47nF AMPRIN 3
0 AMPLIN
2 5
AMP-LIN 2
R149 R152 mute=L 2.3-4.1V L
2
1
1nF
47K 330
BAT54C
1 Q11
3906
mute=H D39
4.7K
R153 10K MUTE UnMute>=3.6V PHONEJACK/5P/DIP
1nF
NC/47K AMP-MUTE PHONEJACK_STEREO

C144
R156
R154 4.7K Q12 R157
C146
NC/100K mute=H 1 3904 10K C94

+ CA13
47uF/16V
MUTE_ MUTE_ R155 1.5nF
2
100K
A BAT54C A

Title
AMP

5 4 3 2 1
7.2 电源板
1. MIP26B-19(LCD26P08A)
1) PFC
1 2 3 4
D D
CN2
RT1 VPFC
1
2
3
4
5
6
7
1
+HV1
RM1 L102A C106 D101

4 - + 2 C101
RM2 CY2
RV5 RV8 + C102
CX1 BD1 LB1
8
CY1
CY3 RP1 L103

L101A
CY2 RV6
C C
RV9
4
CY5 RP2 RV7 Q101
RF5 CF1 RF1 RF3 RF12

DF1
ZR1
CF4 RF7 RF11 RV10
F1
RF6
U1
B RF9 B
5 4
1
RF2 CF3
6 3 CF2
7 2
2
3
2
1
8 1
RFS1 RFS2 RFS3 RS101 RF10
QF1
CN1 CF6
3
RF4 CF5
CF11
RF8
+Vc
Title
A A
Size Number Revision

A4
Date: 8-Oct-2007 Sheet of
File: F:\高压二合一\MIP260B\MIP260B－原理图.ddbDrawn By:
1 2 3 4
第 43 页，共 122 页
2)5VSTB
1 2 3 4 5 6 7 8
D D
T103B L104
VPFC RK1 CK1
+HV1
+12V1
D103
RV1 T103A
R101
RV2 D13
D102 C110 + Z101
C108
QV1 C109 +
1
2 RV3 D109 C113

+VCC
C R7 Z4 C
R22
+
23
QV2 CV1 RV4 T103D

+
2
2
1 3 C25 C2 Q8
2
D1
1 3 Q104 1
R1 D3
QV3 1
3
1
R2 T103C
3
R3 2 Q1 C111 + R18 CK7 C3
CK4
R5 R4
3
+5V
A
2
RS1 RS2 RS3
U2 Q3
6
5
4
3
+VC1 R14
1
2
3
R6
B B
Z2
Z9 + C107
P103
+VB
R25 R9
R35
SB
C1 R13
+5VSB
R10 CK8 R34
R33
+5VSB
A
U101
3
R12 R11
Z1 Z5 Q6 Q5 R30
+VCC 2
Q10
Q2 C6 R31
R8
1
P102 Q11
+VC
R24 C5
R29 R36
R23 R21
SB
R16
Q4
A A
Title

A3
1 2 3 4 5 6 7 8
第 44 页，共 122 页
3) INVERTER
1 2 3 4 5 6 7 8
R38
Q12
R29
RE
D D
CB37
R40
R37 Q9
+VB
DB3
R28 3 1
PT
RB7 RB6 CB2 QB1
R27
C118 + RB1
2
RB8
RB56 RB55 CB24 RB5 CB5 U102
Q7 CB4
3 1 RB4
RB14
1 16
R26
2 15
RB13
3 14
C117
2
4 13
+ RB15 RB10
R? 5 12
Z3
6 11
C4 QB3
7 10
3
+5VMCU RB38 RB11
C DB4B DB5A DB5B 8 9 C
RB12 RB3
2 DB9 CB36
3
DB4A
RB39 CB7 RB9 CB6 CB9 CB3
2
1
CB8 C?
QB4
1
DB18 DB19
RB36 CB10 RB18
RB2 RB17
Is1
1
RB35
2
Vs2
QB2 T102C RB41 RB16
RB34
3
Vs1
RB33 RB28
U103
DM
CB25
RE
RB29 RB27
1 20
2 19
RB30 RB37
3 18 RB44
B RB22 B
4 17 +5VMCU
5 16
RB31
6 15 RB21 RB47
7 14 +5VMCU QB5
8 13 RB42
RB32
9 12 EPWM
10 11 QB6
RB20
A/EPWM LED1 RB45
BK
1
RB24 RB43
+5VMCU 2
CB18 CB17 CB16 CB19 CB20 CB21 CB22 CB23
3
RB46
RB25
RB26
RB40 A/EPWM
CB14 CB13 CB15 CB12 RB19 RB23 RB52
CN8
3
2
1
CN9
1
2
RB67
A A
Title

A3
1 2 3 4 5 6 7 8
第 45 页，共 122 页
4) 12VCC
1 2 3 4 5 6 7 8
RN9
RJ52 RJ50 RJ54 RJ53
+12V
C119 DN2
VS1
DB10
DN5
RB53 CB30
CB26 RN1
CB60
D T? DN1 CN4 D
CB61 RB48
CB35 1
RN2 2
CB27
VS2
DB11
DB8
RB68
PT
C120
C121 DN3
DB12
VPFC
RM3 L106 C116
CB28 RN3
2
DD3 Q103 1 5 CB63
RK2 CK5 CN5
RD8 C104 T104 DN4
1 CB62
1
T102A RM4 D104 4 8
RN4 2
RD10
3
RD7 CB29
C T101 D105 DB13 C
1 5
DD2 C122
QD3 3 1 D106
4 8
RD12
D107
2
RM5
2
DD4 Q102 C123 DN8

DB14
RD9
1 RK3 CK2
C105 CB31 RN5
T102B RD11 RM6 DN9
3
T? CB66 CN4
RD5 RK4 CK6
CB67 1
2
RDS1 RDS2 RDS3 RK5 L105 CB32 RN6
C115 DB15
+
C124
RD6
B DD1 CD1 RD1 B
+12V1
R102
1
DN6
QD2 2 F2 C125
DB16
3
Z102
P101 QD1
3
2 CB33 RB75
1 5 CB64
CN4
RD4 CD2 RD2 T105 DN7
1
+12V
CB65
1
4 8
RN8 2
RD3 CB34
DB17
+VC1
C126
CD3 DB7
RB58
PT
T107
DB7B
Is1
A DB8B A
C34
R59 Title
DB9B
A3
1 2 3 4 5 6 7 8
DB7B
第 46 页，共 122 页
5) OUT
1 2 3 4
D D
CN10
13
12
11
10
HS1 J101 J111
9
8
7
6
5
4
3
2
1
RES2 RES2 RES2
HS2 J102 J112
RES2 RES2 RES2
HS3 J103
+5V J123
RES2 RES2
HS4 J104 J114 RES2
J124
RES2 RES2 RES2
+12V SB J105 J115 RES2
CN11
C J125 C
5
4
3
2
1
RES2 RES2
J106 J116 RES2
+5VSB J126
RES2 RES2
J107 J117 RES2
EPWM
RES2 RES2
J108 J118
DM
RES2 RES2
GND_SIGNAL
J109 J119
BK
RES2 RES2
J110 J120
RES2 RES2
10
11
12
1
2
3
4
5
6
7
8
9
CN3
B B
RJ1 00 RJ6 00 RJ11 00 RJ16 00
RJ2 00 RJ7 00 RJ12 00 RJ17 00
RJ3 00 RJ8 00 RJ13 00 RJ18 00
RJ4 00 RJ9 00 RJ14 00 RJ19 00

Title
A A
RJ5 00 RJ10 00 RJ15 00
A4
1 2 3 4
第 47 页，共 122 页
2.MIP320G-A(LCD32P08A)
1) PFC
D1
VPFC
L3 L5E RT1
3
1 2 4 L5D 5
1
BD1
D D
ZR1 C1
- + L5A
L5B
1
4 1 1 2 L16
3 L1 2 C4 R6
2
C1A EC1
2
4 1 C4A
2
R13 Q1
A2 1 R16
3
CX1 R1 1 Q1A
+VC R14
R12
C R7 R9 R13A C
CY1
2
CY3 R8 R10 R11 R15
CY4
1
U1
L2 8 1
1 4 C9
EC2
7 2
R18
C10
6 3
2 3
2
R22
5 4 R23
F1 T3.15AH/250VAC
B B
R20A
R20C
R20B
R19
R21
R20
C7 C8
L N
1
2
CN1
Title
A A
B
Date: 14-May-2010 Sheet of
File: C:\Documents and Settings\Administrator\桌面
Drawn
\MIP320G-1.1.ddb
By:
第 48 页，共 122 页
2) 5VSTB
1 2 3 4
D D
D4 EC6 EC8 L10 Q2

+5VSB/1A
T5 1 2 3 2
VPFC +5V
R24 C12
7
D3 C12A R25
4
1 2 T5B C14 R27 C16

+ + +
1
T5A EC3 C15
1
R44A
T5E EC4 D5 R35 R38 R39 T5I
R26
T5G
+VCC
T5D
1
D6 R44
5
2
2 1
8
R34
R31 R32 R33
R41 C20
2
+5VSB/1A T5F
C A2 CY2 C
R29 R36
2
R42
Q4 D8
C18 Q5
P103 1 T5H
3
2 3 D7
6
R28 K E 1 6
1 2 STB
3
C17 R30 Q3 +VB
1 4 1
A C 2 5
R37 R43
R40 VPFC EC7 +
3 4
2
R46 U3 R49
+VCC P102 R54

EC5
U2 R48 R53 R57
C21 R51A
R50 R51 R55
R45 R47 4 1
+VC
Q6 3 2
B B
Q7
Z1 R52
R56 C22
Title
A A

A4
Drawn
\MIP320G-1.1.ddb
By:
1 2 3 4
第 49 页，共 122 页
3)12VCC
1 2 3 4
L9
F2
VPFC D10
D D
R60 1 2
+24V
R58
2
Q8
4
D11
3
C23 1 2 VS2
T7B 1 R63 R64
4
R58A 1 Q24 R61

+ +5V
7
D12 Q10
3
3
R62 C24 C25

T8 T8G EC9
2
3
R59
3
R72
EC11
T8B 2 1 L11 R70
6
L15 AA2
D13
T8C T8F R71
2 1
AA3
T8H
2
R67 D14 EC10
C C
2
R65 Q9
C26A + R73
8
3
R69 C27
1
1 C28
R65A 1 Q25 R68 C26
R66 D9
3
1
+12V
T7A CN4 CON4A
2
1 1
2
AA2 2 2
2
C29
6
T1G D19
R76
1
T1C 3
VS2
CN2 2
D16
+12V 1 C34
T1F 1 1 C35 R78
+12V 2
T1A
B 3 B
2
7
4 Is1
3
+5V 5
3
+5V 6 T9 D20
3 2
7 32 C31 C32
R74 R75 1 R79
8
+5VSB/1A 9 C36
CN7 2
STB 10
4 1
BK 1 AA3 41
3
DM 2 C33 VS1
3 R77
4
CN5
C38 CON5A
1
2 1
CN3
2
+24V 1
2
3
Title
A 4 A

A4
Drawn
\MIP320G-1.1.ddb
By:
1 2 3 4
第 50 页，共 122 页
4)INVERTER
1 2 3 4
VS1 VS2 +5VMCU

CON1
1 20
Is1 P23/AN3 P130
2
2 19
D DM P22/AN2 P45 D
1
3 18
P21/AN1 P44
4 17 D17A
AK P20/AN0 P43/INTP1 PWM_32K EC12
5 16
VREF P42/TOH1 OVP
6 15
PWM_OUT VSS P41/INTP3 LED
7 14
BK_1 P121 P40 P_CON
8 13
1
P122 P30/INTP0
9 12
P123 P31/INTP2 K2
10 11
2.9V VDD P34 PIN20(K1)
+VB
LED R97A
2
+A Q20
R89A
1
R82
C41 1
R80
4
CN6 U4A EC13
R81 3 D22
+5VMCU
1 R86
1
33
2 1
C C
1
2
3
4
5
OVP1 2
2
D21 3 1 Q21 C57
2.9V K2 VS1 R84
8
U5 T7E
8
D17 2 +5VMCU
C42 1 16 Q22
2
PIN20(K1) IN- REF
1
2
VS2
2
+5VMCU C40 2 15
R85 IN+ VCC R87
+5VMCU T7H
3 14 1
C43 SYNC B
PWM_32K
5
R90 Is1 D23
R83 +5VMCU 4 13
OSCOUT VC
33
BK_1 R94 R90A
2
2 1 5 12
CT GND Q23
R91 6 1
1 Q11 R92 7 6 11
BK R93 R95 RT A
R99A 5
R97
2
U4B 7 10
2
C46 DIS SD
C47 C48 R96
3
C44 R89 8 9
B ST COM B
C45 OVP1 C49
C52
3
3
3
+A +5VMCU +24V C56 C51 D25 D24
2
D18 1 Q12
Z2A Z2
2
PWM_OUT
R114
2
R127 R98 R99
1
R128
R126
AK OVP
2
Q24A P_CON
1 Q2A 1
Title
A R125 A
R113
3
C62 Size Number Revision

A4
Drawn
\MIP320G-1.1.ddb
By:
1 2 3 4
第 51 页，共 122 页
3.MIP328B-K-1(LCD37P08)
1) PFC
1 2 3 4
D D
CX1 ZR2
HL2
RA1 ZR1 a3
HL1 a19 HL3 BG1
RA3
1
CN1 L3 D3
CA6 CA7 400V
RA2 4 2
1 2 1
RA4 PL1
2 F1 a18
3 CY2 RA16
3
C RA15 CY1 L4 C
T5AH/250V PGND
CA15
CY4
Q1 EC2
RA10 RA17
2
RA5 RA6 RA7 FG1 FG4
RA8
SD
+VC 1 RA11 RA13
QA1 G
D1
a11
3
EC1
RA14
IC5 RA9 RA18
CA10 CA11 RA23 CA13
a6
a9 RA21 RA25 RA24
1 8
B RA20 RA12 B
2 7 RA26
a5 RA27 RA28
QA2 3 6 CA14
RA19 RA22
CA12 4 5
CA9
Title
A A

A4
第 52 页，共 122 页 Date: 19-Jun-2010 Sheet of
File: E:\产品\MIP328B-K\SCH\MIP328B-1.1(2010.01.20).ddb
Drawn By:
1 2 3 4
2)5VSTB
1 2 3 4
RB40
QB7
L104
T1B RB6 CB2 +5VSB +5V
T1A 3 2
RB2 RB3
a3 400V
4
CB9
RB1 RB21 D103
D + CB8 D
RB5
1
2
4
+ + A
3
C108 Z101 + CB5
QB1 D102 CB3 CB4 R14
RB8 RB22
3
+VCC
CB1
D1A RB17
+12V1 CB7
QB3
RB4
6
CB10
0
+ D109 T1C
6
RB16 CY3
0
QB2 CB20 CB11
5
FG3 FG2 HS2-1 HS2-2
2
Q2
5
C C
CB19
+VC1 RB42 QB5 RB41
RB18
a10
1
D3A
RB7
8
RB9 RB39 RB10 QB4
3
VB
RB11 RB19
T1D
8
RB38 + CB6
RB12
7
CB15 +
7
RB29 RB30
U2 CB18
6
5
4
RB33
1
2
3
B B
+ CB12 +VCC RB20
P102
+VC
R15 STB CB21 SB_1 +12V1
Z9 P103 RB13 +5VSB QB11
4 1 RB34 RB35 Z4
C A
RB28 RB31
CB13 3 2 QB6
RB27 E K
CB16
R13 SB_1
Z1 D5 RB23 QB13
1 QB12
a15
R10
RB14 3 2 RB24 RB36
Q5 CB14 RB15
U101 13 CB17
RB37 RB32 Title

2
A A
+5VSB
A4
Drawn By:
1 2 3 4
3)INVERTER
1 2 3 4
CK5
D 400V A1 D
CK6 CN7
RK5
12
11
2
RK1 Q4
A1 10
RK9 CK3
9
CK8 CK1
A2 8
QK1 1
7
T3A DK1 RK6
6
RK11
3
5
RK3 VS1 4
T2 DK9A
3
1 5
C5 2
HVGND1 1
DK9B
a12
4 8
a16
C A2 C
RK7
2
RK12 a14 Q3
CK7 CN8
QK4 1 RK10 CK4
RK2 RK8 CK2
12
T3B a13
3
A2 11
DK2
RK4 10
9
L105
A1 8
7
RK17 RK18 RK19 RK27 RK28
6
5
CK11
VS2 4
C6 3
+
2
CK9
HVGND2 1
DK4 CK10 RK20
+
B +12V1 B
RK24 DK6A
ISEN T107
QK3 F2
Z102 DK6B
HVGND1
CK12
QK5
RK25 RK26
HVGND2
CK14 RK23
CK13
R2 +12V
RK22
+VC1
C4 Title
A A

A4
Drawn By:
1 2 3 4
4) OUTPU
1 2 3 4
D D
CN3
1 EPWM_IN
2 BK
3 APWM
4 STB
5 SGND
VB R6
12V ISEN 1
CN2
+ APWM 2
CN10
1 SGND SGND 3
C1 CN4
2 A/E RES 4
1 5VSB +5VMCU 5
2 +12V KEY2 6
R1 3 +12V KEY1 7
Q7
C 4 +12V DRA 8 C
CN6
R9 +5VMCU 5 +12V DRB 9
6 SGND SGND 10
a17 1 SGND 7 SGND 12V 11
R4 2 RES 8 SGND 12
C2
R3 3 +5VMCU 9 SGND 13
4 KEY2 10 STB 14
C117
+ 5 KEY1 11 BK 15
6 SET+ 12 APWM SET+ 16
U104
R5 A/E 17
R7 18
BK 19
CN5
EPWM_IN 20
1 SGND VS2 21
R8
2 SGND VS1 22
3 +5V 23
DRA 4 +5V 24
5 STB
T3C
6 5VSB
C3
B 7 +5V B
8 +5V
9 SGND
DRB 10 SGND
11 SGND
D2A D2B 12 +12V
13 +12V
Title
A A

A4
Drawn By:
1 2 3 4
4.MIP988-J(LCD42P08A)
1)PFC
1 2 3 4 5 6
3
BD1 D101
+VH1
BD2
2
L103 LB1
ZR2 4 - + 1
VPFC
D RF16 D
LB2
1
2 L3 1 RF14
C107
2
2
3 4 RF1
A1 RF7 C101
1
RF13
RF6 Q101
3
+VC RF8
C103
3
RF2
1 L2 2 C102 RF12
8
CF2 1 QF1
RF5 IC1
C C
RF3 RF9
4 3
2
C105
2
ZR1 RF11
1 2
RT2 RT1 RF15 RF10 RF7A 1

A2
CX1 Q101A
3
RF4 RF8A
CY3 CY2
3
A4
RFS5
RFS6
RFS1
RFS2
RM3 RM4 CF4

CF3 1 QF1A
CF1 CF6 EC6 C104
CF5
RM1 RM2
RFS3 RFS4 RF9A
2
B L1 B
4 3
1 2
CY1
F1
A A
1
2
3
N L
1
2
3
CN1
1 2 3 4 5 6
第 56 页，共 122 页
2) 5VSTB
1 2 3 4
RB40
QB7
L104
T1B RB6 CB2 +5VSB +5V
T1A 2 3
RB2 RB3
1
A1 VPFC
4
CB9
RB1 RB21 D103
1
D D
RB5
1
2
4
2
+ + + + CB8
3
C108 Z101 CB5
2
QB1 D102 CB3 CB21
CB4 RB8 CB7 RB25RB26 +
3
+VCC CB1
CB20
D1A RB17
RB4 +12V1
QB3 CB10
6
+ D109 T1C
6
RB16 CY4
QB2 CB11
2
Q2
5
C C
+VC1 QB5 RB41
RB18
1
D3A
RB42 RB7
8
RB9 RB39 RB10 QB4
3
VB
RB11 RB19
T1D
8
RB38 + CB6
A7 RB12
7
CB15 +
7
RB29 RB30
U2 CB18 STB
6
5
4
+12V1 +24V
RB34
1
2
3
Z4 Z2
B B
RB20
+ RB33 SB_1
CB12 +VCC
P102
+VC
CB19 SB_1 D4A D4B
Z9 P103 RB13 +5VSB QB11
RB23
A6 4 1 RB35
C A
RB28 RB31
CB13 3 2 Z1 QB6
RB27 E K
CB16
RB22
QB12 QB13
D5A
RB14 RB24 RB36
CB14 RB15
U101 CB17
RB43 QB8
RB37 RB32 Title

A A

A4
新加进启动假负载电路
Date: 28-Apr-2010 Sheet of
File: E:\PCB归档\MIP988A-J-1.0(2010.04.28)\MIP988A-J-1.0(2010.04.28).ddb
Drawn By:
1 2 3 4
第 57 页，共 122 页
3)INVERTER
1 2 3 4
CK20
CN7
CK19 RK26 CK18 L107A
D VPFC AA1 11 D
C106 AA1 10
RK5
12
9
AA2 8
2
RK1 Q4 1 2
A K 7
1
T2F
12
6
CK1 DK10A
RK31A 5
QK1 1
11
1 VS1 4
T3A DK1 RK6 RK9 CK3
3
RK11
3
2
2
CK5A
11
RK3 HVGND2 1
T2 DK9A RK30A
1 5 1 2
2
A K
DK9B
4 8 3 2
11 14
AA3 A K
11 14
C T2G C
RK7 CN8
2
RK12 Q3 RK10 CK4
13
CK7 DK10B
AA2 11
3
QK4 1 3 2
A K 10
RK2 RK8 CK2
13
AA2 9
T3B
3
3
AA1 8
DK2
RK4 7
L105
RK31B 6
4
RK29 CK17 L106

5
VS2 4
RK17 RK18 RK19 RK21
4
3
CY5 RK30B CK5B
2
CK11
VPFC HVGND1 1
+
CK15
+12V1
CK10 RK20
B B
DK6B
+
2 3
K A
DK4
QK3 RK28
2 1 RK26A
ISEN K A
F2 F3
QK5 DK6A 1 T107 2
12 HVGND1
CK12
RK27
CK14 RK23 RK25
RK14 3 4
34 HVGND2
RK22 RK15
+12V +24V
+VC1
CK13 Title
A A

A4
Drawn By:
1 2 3 4
第 58 页，共 122 页
4)OUTPUT
1 2 3 4
VB 4.7 R6 CN5
12V 1 SGND ISEN 1
+ 2 A/E APWM 2
CN10
SGND 3
C1 SEL
D RES 4 D
4.7u 50V
+5VMCU 5
KEY2 6
CN6
R1 KEY1 7
6P
200 Q7 DRA 8
2N3904
R9 +5VMCU 1 SGND DRB 9
2 3
CE NC 2 RES SGND 10
3 +5VMCU 12V 11
B
R4 4 KEY2 12
4.7K C2
R3 10K 1% 5 KEY1 13
104
1
6 SET+ 14
C117
+ 15
U104 2.2u 50V
SET+ 16
R5 A/E 17
TL431 CN4 CN9
R7 10K 1% 18
NC 1 +24V 1 +24V BK 19
2 +24V 2 +24V EPWM_IN 20
3 SGND 3 SGND VS2 21
4 SGND 4 SGND VS1 22
C 5 +12V 5 +12V 23 C
6 SGND 6 SGND 24
7 +12V 7 +5V
R8 2K
8 SGND 8 +5V
5
DRA 9 +5VSB 9 SGND
10 SGND 10 SGND
T3C
5
11 STB 11 +5VSB
TRANS
12 STB
C3 224
6
8
CN3
DRB
6
3 APWM
T3D
8
D2A D2B 2 BK
TRANS
BAV70 BAV70 1 SGND
7
3P-2.5
7
B B
Title
A A

A4
Drawn By:
1 2 3 4
第 59 页，共 122 页
7.3 IR 板
U1101
RM
IR GND VCC
D1001
1
2
3
J1100 1N4148/NC
1 1 2
2
3 R1108
4 10K_1/6W
5
CON_PIN2.0_5P R1107
75R_1/6W
R1109
1K_1/6W
1
LED1
LED
2
R1110
2
1K_1/6W Q1100
1
1815

Title
IR

第 60 页，共 122 页 A4 IR_Board <01>
Date: Tuesday, July 20, 2010 Sheet 1 of 1

5 4 3 2 1
7.4 按键板
D D
CN1
2
1
P2/2.0MM
CON2/90DJC20
CN2
3
2 ADC1
1 ADC2
P3/2.0MM R813 R812 R814 R818 R817

CON/90/PH2.0/-3 1.8K 3.3K 6.2K 6.2K 0\NC
C C
J811 R811
R815 R816
0/1K 750/1.8K
5.1K 27K/3.3K
8 MENU
6 P-
7 P+
1 V+
B 3 SOURCE B
2 V-
4 POWER
CN3
A A
Title
key conversion
第 61 页，共 122 页 Size Document Number Rev
A4 <Doc> <01>
Date: Friday, July 23, 2010 Sheet 1 of 1

5 4 3 2 1
MSTAR TSUMV36KU (SD) 主要芯片说明规格
第 62 页，共 122 页
9.1 TSUMV36K TSUMV36KU
Full HD LCD TV Controller with VIF
Preliminary Data Sheet Version 0.2
FEATURES
NTSC/PAL/SECAM Video Decoder (HDCP) 1.1 compliant receiver
Supports NTSC M, NTSC-J, NTSC-4.43, PAL High Definition Multimedia Interface (HDMI)
(B,D,G,H,M,N,I,Nc), and SECAM 1.3 compliant receiver with CEC support
Automatic TV standard detection Long-cable tolerant robust receiving
2D NTSC and PAL comb-filter for Y/C separation Support HDTV up to 1080P
4 configurable CVBS & Y/C S-video inputs Auto-Configuration/Auto-Detection
Supports Closed-caption, and V-chip Auto input signal format and mode detection
CVBS video output Auto-tuning function including phasing,
Video IF for Multi-Standard Analog TV positioning, offset, gain, and jitter detection
Digital low IF architecture Sync detection for H/V Sync
Stepped-gain PGA with 26 dB tuning range and High-Performance Scaling Engines
1 dB tuning resolution Fully programmable shrink/zoom capabilities
Maximum IF analog gain of 37dB in addition to Nonlinear video scaling supports various modes
digital gain including Panorama
Programmable TOP to accommodate different Video Processing & Conversion
tuner gain to optimize noise and linearity 3-D motion adaptive video de-interlacer
performance Automatic 3:2 pull-down & 2:2 pull-down
Multi-Standard TV Sound Decoding/Processing
detection and recovery
Supports BTSC/A2/EIA-J demodulation and
Edge-oriented adaptive algorithm for smooth
decoding
low-angle edges
FM stereo & SAP demodulation
MStar 3rd Generation Advanced Color Engine
Audio processing for loudspeaker channel,
(MStarACE-3) automatic picture enhancement
including volume, balance, mute, tone, and P/G
gives:
EQ
Brilliant and fresh color
Mstar surround sound effect
Intensified contrast and details
Digital Audio Interface
Vivid skin tone
HDMI audio channel processing capability
Sharp edge
Audio Line-In L/R x3
Enhanced depth of field perception
Audio Line-Out L/R x2
Accurate and independent color control
Built-in audio DAC
sRGB compliance allows end-user to experience
Built-in audio ADC
the same colors as viewed on CRTs and other
SIF audio input
Analog RGB Compliant Input Ports displays
Two analog ports support up to UXGA Programmable 10-bit RGB gamma CLUT
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG
(Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port
One DVI/HDMI input port
Supports TMDS clock up to 225MHz @ 1080P
60Hz
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection
-1- 6/5/2009
第 63 页，共 122 页
Copyright © 2009 MStar Semiconductor, Inc. All rights reserved.
On-Screen OSD Controller Dithering with 6/8 bits options

128/256 color palette Reduced swing for LVDS for low EMI
512 1/2/3-bit/pixel fonts Supports flexible spread spectrum frequency
Supports 2K attribute/code with 360Hz~11.8MHz and up to 25%
Horizontal and vertical stretch of OSD menus modulation
Pattern generator for production test Integrated Micro Controller
Supports OSD MUX and alpha blending Embedded 8032 micro controller
capability Configurable PWM’s and GPIO’s
Supports blinking and scrolling for closed Low-speed ADC inputs for system control
caption applications SPI bus for external flash
Miscellaneous
LVDS Panel Interface 128-pin QFP package
Supports 8 bit dual link LVDS up to full HD Integrated power management control with
(1920x1080) independent power plant to support deep sleep,
Supports 2 data output formats: Thine & TI and wake-up from various input
data mappings
Compatible with TIA/EIA
GENERAL DESCRIPTION
The TSUMV36KU is a high performance and all-in-one IC for multi-function LCD monitor/TV with resolutions up
to full HD (1920x1080). It is configured with an integrated triple-ADC/PLL, an integrated DVI/HDCP/HDMI
receiver, a multi-standard A/V front-end and baseband decoder, a video de-interlacer, a scaling engine, the
MStarACE-3 color engine, an on-screen display controller and a built-in output panel interface. An embedded
audio DSP processor gives various of audio manipulation functions for greater audience experiences.
To further reduce system costs, the TSUMV36KU also integrates intelligent power management control
capability for green-mode requirements and spread-spectrum support for EMI management.
-2- 9/21/2009
第 64 页，共 122 页
9.1 TSUMV36K TSUMV36KE
Pin Diagram and Description Version 0.1
PIN DIAGRAM (TSUMV36KE)
DDCA_CLK
DDCA-DAT
HOTPLUG
AVDD_33
WAKEUP
GPIOB5
GPIOB4
RXACN
RXA2N
RXA1N
RXA0N
RXACP
RXA2P
RXA1P
RXA0P
RESET
VDDC
VDDP
VDDP
SAR0
SAR1
SAR2
IRIN
GND
CEC
INT
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
GND 1 102 AVDD_PLL
BIN1 2 101 GND
SOGIN1 3 Pin 1 100 LVA0P
GIN1 4 99 LVA0N
GIN1M 5 98 LVA1P
RIN1 6 97 LVA1N
AVDD_33 7 96 LVA2P
HSYNC0 8 95 LVA2N
BIN0 9 94 LVACLKP
GIN0M 10 93 LVACLKN
GIN0 11 92 LVA3P
SOGIN0 12 91 LVA3N
RIN0 13 90 VDDP
VSYNC0 14 89 LVB0P
AVDD_33 15 88 LVB0N
CVBS3 16 87 LVB1P
CVBS2 17 86 LVB1N
CVBS1 18 85 LVB2P
XXXXX
XXXXXXXX
TSUMV36KE-LF
CVBS0 19 84 LVB2N
VCOM0 20 83 LVBCLKP
CVBSOUT 21 82 LVBCLKN
GND 22 81 LVB3P
AVDD_33 23 80 LVB3N
XOUT 24 79 GND
XIN 25 78 VDDC
GND 26 77 GPIOD[0]
AVDD_33 27 76 GPIOD[1]
AVDD_VIF 28 75 SPI_CK
GND 29 74 SPI_CZ
VIFIP 30 73 SPI_DI
VIFIM 31 72 SPI_DO
SIFIM 32 71 AD[0]
SIFIP 33 70 AD[1]
GND 34 69 AD[2]
VR27 35 68 AD[3]
AVDD_VIF 36 67 WRZ
TAGC 37 66 RDZ
AVDD_33 38 65 ALE
39
40
41
42
43
44
45
46
47
48
55
56
57
58
59
60
61
62
63
64
49
50
51
52
53
54
LINE_IN_2L
LINE_IN_2R
LINE_IN_3R
LINE_IN_4L
LINE_OUT_0R
LINE_OUT_1R
LINE_OUT_0L
LINE_OUT_1L
GND
VDDP
PWM3
PWM2
PWM1
GND
AUVAG
VDDC
LINE_IN_3L
LINE_IN_4R
GND
AUCOM
AUVRM
GND
AUVRP
VDDP
VDDP
PWM0
-1- 6/3/2009
第 65 页，共 122 页
9.1 TSUMV36K TSUMV36KE
Pin Diagram and Description Version 0.1
DISCLAIMER
MSTAR SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY MSTAR SEMICONDUCTOR ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge
without detection. TSUMV36KE comes with ESD protection circuitry; however, the device may be
permanently damaged when subjected to high energy discharges. The device should be handled
with proper ESD precautions to prevent malfunction and performance degradation.
REVISION HISTORY
Document Description Date
TSUMV36KE_pd_v01 Initial release Sep 2009
-8- 6/3/2009
第 66 页，共 122 页
ELECTRICAL SPECIFICATIONS
Analog Interface Characteristics
Parameter Min Typ Max Unit
VIDEO ADC Resolution 10 Bits
VIDEO ANALOG INPUT
Input Voltage Range
Minimum 0.5 V p-p
Maximum 1.0 V p-p
Input Bias Current 1 uA
Input Full-Scale Matching 1.5 %FS
Brightness Level Adjustment 62 %FS
SWITCHING PERFORMANCE
Maximum Conversion Rate 165 MSPS
Minimum Conversion Rate 12 MSPS
HSYNC Input Frequency 15 200 kHz
PLL Clock Rate 12 165 MHz
PLL Jitter 500 ps p-p
Sampling Phase Tempco 15 ps/°C
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 250 MHz
DIGITAL INPUTS
Input Voltage, High (VIH) 2.5 V
Input Voltage, Low (VIL) 0.8 V
Input Current, High (IIH) -1.0 uA
Input Current, Low (IIL) 1.0 uA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Output Voltage, High (VOH) VDDP-0.1 V
Output Voltage, Low (VOL) 0.1 V
VIDEO ANALOG OUTPUT
CVBS Buffer Output
Output Low 1.5 V
Output High 2.0 V
-3- 9/21/2009
第 67 页，共 122 页
Parameter Min Typ Max Unit

AUDIO
ADC Input 2.0 V p-p
DAC Output 2.0 V p-p
SIF Input Range
Minimum 0.1 V p-p
Maximum 1.0 V p-p
FSSW Input1 0 1.8 V
SAR ADC Input 0 3.3 V
2
FB ADC Input 0 1.25 V
Specifications subject to change without notice.
Notes:
1. Input full scale is typically 1.8V, but input range is 0 ~ 3.3V.
2. Input full scale is 1.25V, but input range is 0 ~ 3.3V.
Absolute Maximum Ratings

Parameter Symbol Min Max Units
3.3V Supply Voltages VVDD_33 3.14 3.6 V
1.26V Supply Voltages VVDD_126 1.2 1.32 V
Input Voltage (5V tolerant inputs) VIN5Vtol 5.0 V
Input Voltage (non 5V tolerant inputs) VIN VVDD_33 V
Ambient Operating Temperature TA 0 70 °C
Storage Temperature TSTG -40 150 °C
Junction Temperature TJ 150 °C
-4- 9/21/2009
第 68 页，共 122 页
ORDERING GUIDE MARKING INFORMATION

Part Number Temperature Package Package XXXXXXXXXX
Part Number (refer to ORDERING GUIDE)
Range Description Option
Lot Number
TSUMV36KU-LF 0°C to +70°C QFP 128 Operation Code A
Operation Code B
Date Code (YYWW)
.
DISCLAIMER
MSTAR SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY MSTAR SEMICONDUCTOR ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. TSUMV36KU comes with ESD protection circuitry; however, the device may be
permanently damaged when subjected to high energy discharges. The device should be handled
with proper ESD precautions to prevent malfunction and performance degradation.
REVISION HISTORY
Document Description Date
TSUMV36KU_ds_v01 Initial release Aug 2009
TSUMV36KU_ds_v02 Revise typos in features Sep 2009
-5- 9/21/2009
第 69 页，共 122 页
9.2 AT24CXX
Features
• Medium-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K) or 2048 x 8 (16K)
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 100 kHz (2.7V) and 400 kHz (5V) Compatibility
•
•
Write Protect Pin for Hardware Data Protection
8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes
2-wire
•
•
Partial Page Writes are Allowed
Self-timed Write Cycle (10 ms max)
Automotive
• High-reliability
– Endurance: 1 Million Write Cycles Serial EEPROM
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages 1K (128 x 8)
2K (256 x 8)
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec- 4K (512 x 8)
trically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many 8K (1024 x 8)
automotive applications where low-power and low-voltage operation are essential.
The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP and 8-lead 16K (2048 x 8)
JEDEC SOIC packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.
AT24C01A
AT24C02
AT24C04
Pin Configurations
8-lead PDIP
AT24C08(1)
Pin Name Function
A0 1 8 VCC
AT24C16(2)
A0 - A2 Address Inputs
A1 2 7 WP
SDA Serial Data Note: 1. This device is not recom-
A2 3 6 SCL
mended for new designs.
GND 4 5 SDA
SCL Serial Clock Input Please refer to AT24C08A.
WP Write Protect 2. This device is not recom-
mended for new designs.
NC No Connect Please refer to AT24C16A.
8-lead SOIC
A0 1 8 VCC
A1 2 7 WP
A2 3 6 SCL
GND 4 5 SDA
3256D–SEEPR–11/03
1
㄀义ˈ݅义
第 70 页，共 122 页
9.2 AT24CXX
Absolute Maximum Ratings

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA
Block Diagram
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open-
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that are hard wired for the AT24C01A and the AT24C02. As many as
eight 1K/2K devices may be addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no
connects.
2 AT24C01A/02/04/08/16㄀义ˈ݅义
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9.2 AT24CXX
AT24C01A/02/04/08/16
The AT24C16 does not use the device address pins, which limits the number of devices
on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides
hardware data protection. The Write Protect pin allows normal read/write operations
when connected to ground (GND). When the Write Protect pin is connected to VCC, the
write protection feature is enabled and operates as shown in the following table.
Part of the Array Protected

WP Pin
Status 24C01A 24C02 24C04 24C08(1) 24C16(2)
Normal Upper
Full (1K) Full (2K) Full (4K) Read/ Half
At VCC
Array Array Array Write (8K)
Operation Array
At GND Normal Read/Write Operations
Notes: 1. This device is not recommended for new designs. Please refer to AT24C08A.
2. This device is not recommended for new designs. Please refer to AT24C16A.
Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,
the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes
each, the 16K requires an 11-bit data word address for random word addressing.
3
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9.3 AT26DF081A
Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase 8-megabit
• Individual Sector Protection with Global Protect/Unprotect Feature
– One 32-Kbyte Top Boot Sector 2.7-volt Only
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
Serial Firmware
•
– Fifteen 64-Kbyte Sectors
Hardware Controlled Locking of Protected Sectors
DataFlash®
• Flexible Programming Options Memory
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology AT26DF081A
• Low Power Dissipation
– 5 mA Active Read Current (Typical)
– 10 µA Deep Power-down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 200-mil wide)
1. Description
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been opti-
mized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
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9.3 AT26DF081A
The AT26DF081A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro-
tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica-
tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili-
ties, the AT26DF081A incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.
Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.
2 AT26DF081A 第 74 页，共 122 页

3600F–DFLASH–03/07
AT26DF081A
9.3 AT26DF081A
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Asserted
Symbol Name and Function State Type
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
CS accepted on the SI pin. Low Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
SCK Input
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
SI including command and address sequences. Data on the SI pin is always latched on the rising Input
edge of SCK.
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
SO Output
always clocked out on the falling edge of SCK.
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to
section “Protection Commands and Features” on page 15 for more details on protection features
and the WP pin.
WP Low Input
The WP pin is internally pulled-high and may be left floating if hardware-controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an effect
HOLD Low Input
on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”
on page 30 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
VCC Power
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the
GND Power
system ground.
Figure 2-1. 8-SOIC Top View
CS 1 8 VCC
SO 2 7 HOLD
WP 3 6 SCK
GND 4 5 SI
3
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3600F–DFLASH–03/07
9.3 AT26DF081A
3. Block Diagram
CONTROL AND I/O BUFFERS

PROTECTION LOGIC AND LATCHES
CS
SRAM
DATA BUFFER
SCK INTERFACE
CONTROL
SI
AND
LOGIC Y-DECODER Y-GATING
SO
ADDRESS LATCH
FLASH
MEMORY
WP X-DECODER ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-
down of each physical sector.
4 AT26DF081A 第 76 页，共 122 页

3600F–DFLASH–03/07
9.4 TDA7266SA
TDA7266SA
7W+7W DUAL BRIDGE AMPLIFIER
■ WIDE SUPPLY VOLTAGE RANGE (3.5-18V)

TECHNOLOGY BI20II
■ MINIMUM EXTERNAL COMPONENTS
– NO SWR CAPACITOR
– NO BOOTSTRAP
– NO BOUCHEROT CELLS
– INTERNALLY FIXED GAIN
■ STAND-BY & MUTE FUNCTIONS
■ SHORT CIRCUIT PROTECTION
■ THERMAL OVERLOAD PROTECTION CLIPWATT15
ORDERING NUMBER: TDA7266SA
DESCRIPTION
The TDA7266SA is a dual bridge amplifier specially Pin to pin compatible with: TDA7266S, TDA7266,
designed for LCD Monitor, PC Motherboard, TV and TDA7266M, TDA7266MA, TDA7266B, TDA7297SA
Portable Radio applications. & TDA7297.
BLOCK AND APPLICATION DIAGRAM
VCC
470µF 100nF
3 13
0.22µF
4
IN1 + 1 OUT1+
-
ST-BY 7
S-GND
9 - 2 OUT1-
Vref
+
0.22µF
12
IN2 + 15 OUT2+
-
MUTE 6
- 14 OUT2-
PW-GND
8 +
D94AU175B
June 2003 1/11
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9.4 TDA7266SA
TDA7266SA
ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
Vs Supply Voltage 20 V
IO Output Peak Current (internally limited) 2 A
Ptot Total Power Dissipation (Tamb = 70°C) 20 W
Top Operating Temperature 0 to 70 °C
Tstg, Tj Storage and Junction Temperature -40 to 150 °C
THERMAL DATA
Symbol Parameter Value Unit
Rth j-case Thermal Resistance Junction-case Typ = 1.8; Max. = 2.5 °C/W
Rth j-amb Thermal Resistance Junction-ambient 48 °C/W
PIN CONNECTION (Top view)
15 OUT2+
14 OUT2-
13 VCC
12 IN2
11 N.C.
10 N.C.
9 S-GND
8 PW-GND
7 ST-BY
6 MUTE
5 N.C.
4 IN1
3 VCC
2 OUT1-
1 OUT1+
D03AU1463
ELECTRICAL CHARACTERISTCS
(VCC = 11V, RL = 8Ω, f = 1KHz, Tamb = 25°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VCC Supply Range 3 11 18 V
Iq Total Quiescent Current 50 65 mA
VOS Output Offset Voltage 120 mV
PO Output Power THD 10% 6.3 7 W
THD Total Harmonic Distortion PO = 1W 0.05 0.2 %
PO = 0.1W to 2W 1 %
f = 100Hz to 15KHz
SVR Supply Voltage Rejection f = 100Hz, VR =0.5V 40 56 dB
CT Crosstalk 46 60 dB
AMUTE Mute Attenuation 60 80 dB
Tw Thermal Threshold 150 °C
GV Closed Loop Voltage Gain 25 26 27 dB
∆GV Voltage Gain Matching 0.5 dB
2/11
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9.5 LD1117
UTC LD1117/A LINEAR INTEGRATED CIRCUIT

LOW DROP FIXED AND
ADJUSTABLE POSITIVE VOLTAGE 2 1
3
REGULATORS
DESCRIPTION SOT-223 SOP-8

The UTC LD1117/A is a LOW DROP Voltage Regulator
able to provide up to 0.8/1.0A of Output Current, available
even in adjustable version (Vref=1.25V). Concerning fixed
versions, are offered the following Output Voltages: 1.8V, 1
2.5V, 2.85V, 3.0V, 3.3V and 5.0V. The 2.85V type is ideal for 1
SCSI-2 lines active termination. The device is supplied in: TO-220 TO-252
SOT-223, TO-252, TO-263, TO-263-3, SOP-8 and TO-220.
The SOT-223, TO-263, TO-263-3 and TO-252 surface mount
packages optimize the thermal characteristics even offering a
relevant space saving effect. High efficiency is assured by
1 1
NPN pass transistor. In fact in the case, unlike than PNP one,
the Quiescent Current flows mostly into the load. Only a very TO-263 TO-263-3
common 10µF minimum capacitor is needed for stability. On
chip trimming allows the regulator to reach a very tight output
voltage tolerance, within ±1% at 25°C. The ADJUSTABLE SOP-8 1: GND; 2,3,6,7: Vout;
LD1117/A is pin to pin compatible with the other standard 4: Vin; 5,8: NC
Adjustable voltage regulators maintaining the better
performances in terms of Drop and Tolerance.
FEATURES
*Low dropout voltage (1V Typ.)
*2.85V device performances are suitable for SCSI-2 active
termination
*Output current up to 0.8/1.0A
*Fixed output voltage of: 1.8V,2.5V, 2,85V, 3.0V, 3.3V, 5.0V
*Adjustable version availability (Vref=1.25V)
*Internal current and thermal limit
*Available in ±1%(at 25°C) and 2% in all temperature range
*Supply voltage rejection: 75dB (TYP)
*Temperature range: 0°C to 125°C
UTC UNISONIC TECHNOLOGIES CO., LTD. 1

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9.5 LD1117
MARKING INFORMATION
PACKAGE VOLTAGE PIN CODE PIN 1 PIN 2 PIN 3 MARKING
CODE
18:1.8V A GND OUT IN
25:2.5V
B OUT GND IN CURRENT LD1117
PIN CODE
SOT-223 28:2.85V CODE
VOLTAGE
30:3.0V C GND IN OUT CODE
DATE
CODE
33:3.3V
D IN GND OUT 1 2 3
50:5.0V
AD:ADJ A GND OUT IN
TO-220 UTC CURRENT
B OUT GND IN LD1117 CODE
TO-252 PIN CODE
VOLTAGE DATE
TO-263 C GND IN OUT CODE CODE
TO-263-3
D IN GND OUT 1 2 3
Note: The current code “A” means output current up to 1.0A, while without “A” means output current up to 0.8A.

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9.5 LD1117
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL VALUE UNIT
DC Input Voltage VIN 15 V
Power Dissipation Ptot 12 W
Storage temperature Tstg -65 ~ +150 °C
Operating Junction Top 0 ~ +125 °C
Temperature
Note: Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional
operation under there condition is not implied. Over the above suggested Max Power Dissipation a Short Circuit
could definitively damage the device.
THERMAL DATA
PARAMETER SYMBOL VALUE UNIT
Thermal Resistance Junction-case Rth-case
SOT-223 15 °C/W
SOP-8 20 °C/W
TO-252 8 °C/W
TO-220 3 °C/W
TO-263 3 °C/W
Thermal Resistance Junction-ambient Rthj-amb
TO-220 50 °C/W

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9.5 LD1117

APPLICATION CIRCUIT
LD1117/A
UTC LD1117/A-1.8 ELECTRICAL CHARACTERISTICS

(refer to the test circuits, Tj=0 to 125°C, Co=10µF unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Output Voltage Vo Vin=3.8V, Io=10mA, Tj=25°C 1.780 1.800 1.820 V
Output Voltage Vo Io=0 to 800/1000mA, Vin=3.3 to 8V 1.760 1.840 V
Line Regulation ∆Vo Vin=3.3 to 8V, Io=0mA 1 6 mV
Load Regulation ∆Vo Vin=3.3V, Io=0 to 800/1000mA 1 10 mV
Temperature stability ∆Vo 0.5 %
Long Term Stability ∆Vo 1000 hrs, Tj=125°C 0.3 %
Operating Input Voltage Vin Io=100mA 10 V
Quiescent Current Id Vin≤8V 5 10 mA
Output Current Io Vin=6.8V, Tj=25°C 800 950 1200 mA
Output Noise Voltage eN B=10Hz to 10KHz, Tj=25°C 100 µV
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=5.5V, 60 75 dB
Rejection Vripple=1Vpp
Dropout Voltage Vd Io=100mA 1.00 1.10 V
Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V
Thermal Regulation Ta=25°C, 30ms Pulse 0.01 0.10 %/W

Output Voltage Vo Vin=4.5V, Io=10mA, Tj=25°C ±1% 2.475 2.500 2.525 V
±2% 2.450 2.500 2.550 V
Output Voltage Vo Io=0 to 800/1000mA, ±2% 2.450 2.550 V
Vin=3.9 to 10V ±4% 2.400 2.600 V

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9.5 LD1117

Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=5.5V, 60 75 dB
Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V

Output Voltage Vo Vin=4.85V, Io=10mA, Tj=25°C 2.82 2.85 2.88 V
Output Voltage Vo Io=0 to 800/1000mA,Vin=4.25 to 10V 2.79 2.91 V
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=5.85V, 60 75 DB
Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V

Output Voltage Vo Vin=5V, Io=10mA, Tj=25°C ±1% 2.97 3.00 3.03 V
±2% 2.94 3.00 3.06 V
Vin=4.5 to 10V ±4% 2.88 3.12 V
Output Current Io Vin=8V, Tj=25°C 800 950 1200 mA
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=6V, 60 75 dB

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9.5 LD1117

Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V

Output Voltage Vo Vin=5.3V, Io=10mA, Tj=25°C ±1% 3.267 3.300 3.333 V
±2% 3.235 3.300 3.365 V
Vin=4.75 to 10V ±4% 3.160 3.440 V
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=6.3V, 60 75 DB
Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V

Output Voltage Vo Vin=7V, Io=10mA, Tj=25°C ±1% 4.95 5.00 5.05 V
±2% 4.90 5.00 5.10 V
Vin=6.5 to 15V ±4% 4.80 5.20 V
Output Current Io Vin=10V, Tj=25°C 800 950 1200 mA
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, Vin=8V, 60 75 dB

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9.5 LD1117

Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V
UTC LD1117/A-ADJUSTABLE ELECTRICAL CHARACTERISTICS

Reference Voltage Vref Vin-VO=2V, Io=10mA, Tj=25°C 1.238 1.25 1.262 V
Reference Voltage Vref Io=10 to 800/1000mA, Vin-Vo=1.4 to 1.225 1.275 V
10V
Line Regulation ∆Vo Vin-Vo=1.5 to 13.75V, Io=10mA 0.035 0.200 %
Load Regulation ∆Vo Vin-Vo=3V, Io=10 to 800/1000mA 0.10 0.400 %
Operating Input Voltage Vin 15 V
Adjustment Pin Current Iadj Vin≤15V 60 120 µA
Adjustment Pin Current ∆Iadj Vin-Vo=1.4 to 10V, 1 5 µA
Change Io=10 to 800/1000mA
Minimum Load Current Io(min) Vin=15V 2 5 mA
Output Current Io Vin-Vo=5V, Tj=25°C 800 950 1200 mA
Output Noise (%Vo) eN B=10Hz to 10KHz, Tj=25°C 0.003 %
Supply Voltage SVR Io=40mA, f=120Hz, Tj=25°C, 60 75 dB
Rejection Vin-Vo=3V, Vripple=1Vpp
Io=500mA 1.05 1.15 V
Io=800mA 1.10 1.20 V
Io=1000mA 1.15 1.25 V
TYPICAL APPLICATIONS
FIG.1 Negative Supply

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10 屏&电源接口说明
10.1 屏接口说明
1.IVO M260TWR1 R1 昆山龙腾光电有限公司
InfoVision Optoelectronics ( Kunshan ) Co.,LTD.
Document Title M260TWR1 R1 Product Information Page No. 4/32
Document No. Issue Date 2009/03/16 Revision 00
1.0 General Descriptions

1.1 Introduction
The M260TWR1 is a color active matrix thin film transistor (TFT) liquid crystal display
(LCD) that uses amorphous silicon TFT as a switching device. It is composed of a TFT
LCD panel, a timing controller, voltage reference, common voltage, DC-DC converter,
column driver, and row driver circuit. This TFT LCD has a 26-inch diagonally measured
active display area with WXGA resolution (1366 vertical by 768 horizontal pixel array).
1.2 Features
■ 26” WXGA TFT LCD Panel
■ 4U CCFLs Backlight System
■ Supported WXGA (V:1,366 lines, H:768 pixels) resolution
■ Compatible with RoHS Standard
1.3 Product Summary
Items Specifications Unit
Screen Diagonal 26 inch
Active Area 575.769 (H) x 323.712 (V) ` mm
Pixels H x V 1,366 (x3) x 768
Pixel Pitch 0.4215 (per one triad) x 0.4215 mm
Pixel Arrangement R,G,B. Vertical Stripe
Display Mode Normally White
White Luminance 450 typical cd/m2 (CCFL@7mA)
Contrast Ratio 1,000 : 1 typical
Response Time 5 typical msec
Input Voltage 12 typical v
Logic Power Consumption 3.6 typical (Black pattern, 60Hz) watt
Backlight Power Consumption 40 typical (CCFL current 7mA) watt
Weight 3,900 maximum g
Outline Dimension 626 (W) x 373 (H) x 32 (T)* mm
Electrical Interface (Logic) 8 bit LVDS
Support Color 16.7 M
Luminance Uniformity(5points) 80% typical
Optimum Viewing Direction 6 o’clock
Surface Treatment Anti Glare + 3H
*The gibbosities were not calculated in the thickness of the outline dimension.
________________________________________________________________________
第非经书面准许,
昆山龙腾光电有限公司内部文件, 86 页，共 122不得以任何形式复制及对外发行
页
All rights strictly reserved reproduction or issue to third parties in any form what ever is not permitted without written authority from the proprietor.
1.IVO M260TWR1 R1
昆山龙腾光电有限公司
1.4 Functional Block Diagram

.
Figure 1 shows the functional block diagram of the LCD module.
Figure 1 Block Diagram
________________________________________________________________________
页
1.IVO M260TWR1 R1
6.0 Electrical Characteristics

6.1 Interface Connector
Table 6 Connector Name / Designation
Manufacturer UJU (or Equivalent)

Type / Part Number UJU IS100-L30B-C23
Mating Receptacle/Part Number JAE FI-X30H(L), JAE FI-X30C*(L), JAE FI-X30M*
Table 7 Signal Pin Assignment

All input signals shall be low or Hi-Z state when VDD is off.
Pin # Signal Name Description Remarks
1 NC Not connected
2 NC Not connected
3 NC Not connected
4 GND Ground
5 RX0- Negative LVDS differential data input
6 RX0+ Positive LVDS differential data input
7 GND Ground
10 GND Ground
13 GND Ground
14 RXClk - Negative LVDS differential clock input
15 RXClk + Positive LVDS differential clock input
16 GND Ground
19 GND Ground
20 NC Not connected
21 NC Not connected
22 TP Test point
23 GND Ground
________________________________________________________________________
页
1.IVO M260TWR1 R1
24 GND Ground
25 GND Ground
26 VDD power supply +12.0V
________________________________________________________________________
页
1.IVO M260TWR1 R1
11.0 Lot Mark

Model name
Development
product name
H/W: 2nd Source/Version

Lot Mark F/W: EDID version
(NB product only)
23 product code
11.1 Lot Mark
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
code 1,2,4,5,6,7,8,9,10,11,16: IVO internal flow control code.

code 3: production location.
code 12: production year.
code 13: production month.
code 14,15: production date.
Code 17,18,19,20: serial number.
Note (1) Production Year

Year 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
Mark 6 7 8 9 A B C D F G
Note (2) Production Month

Month Jan. Feb. Mar. Apr. May. Jun. Jul. Aug. Sep. Oct Nov. Dec.
Mark 1 2 3 4 5 6 7 8 9 A B C
11.2 23 Product Barcode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
code 1,2: MD Mindtech Display.

code 3,4,5,6,7: MTDis internal module name.
code 8,9,10,13,16: MTDis internal flow control code.
code 11,12: Cell location Suzhou defined as “SZ”.
________________________________________________________________________
页
2.LG LC320WXE SB V1 LC320WXE
Product Specification
1. General Description
The LC320WXE is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 31.51 inch diagonally measured
acti ve d ispl a y area wi th WXGA reso lution (768 ver tica l by 1366 ho r izontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in Horizontal stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot,
thus presenting a palette of more than 16.7M(true) colors.
It has been designed to apply the 8-bit 1-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
EEPROM
SCL SDA
+12.0V
LVDS 1Port Timing Controller
TFT - LCD Panel
CN1 (1366 × 768 x RGB pixels)
(30pin)
LVDS Select #9 [LVDS Rx + Spread Spectrum [Gate In Panel]
integrated]
S1 S1366
Power Circuit RGB
Block Source Driver Circuit
High Input
CN2, 3Pin, 10 Lamps/@65 mA
High Input Back light Assembly (10EEFL)
CN3, 3Pin, 10 Lamps/@65 mA
General Features
Active Screen Size 31.51 inches(800.4mm) diagonal
Outline Dimension 760.0 mm(H) x 450.0 mm(V) x 36.0 mm(D) (Typ.)
Pixel Pitch 510.75㎛ x 170.25㎛ x RGB
Pixel Format 1366 horiz. by 768 vert. pixels RGB horizontal stripe arrangement
Color Depth 8bit, 16,7 M colors
Luminance, White 350 cd/m2 (Center 1 point) (Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178(Min.), U/D 178(Min.))
Power Consumption Total 73.5Watt (Typ.) (Logic=3.5 W, Back Light= 70W @ with Inverter)
Weight 4,500g(Typ.) (TBD)
Display Operating Mode Transmissive mode, normally black
Surface Treatment Hard coating(3H), anti-glare treatment of the front polarizer (Haze 10%)
第 91 页，共 122 页
Ver. 0.1 4 / 27
3-2. Interface Connections
This LCD module employs two kinds of interface connection, a 30-pin connector is used for the module
electronics and 2-pin (BDEMR-02VS) (TBD) connector is used for the integral backlight system.
3-2-1. LCD Module
-LCD Connector(CN1) : FI-X30SSL-HF (Manufactured by JAE) or Equivalent
-Mating Connector : FI-X30C2L (Manufactured by JAE) or Equivalent
Table 4. MODULE CONNECTOR(CN5) PIN CONFIGURATION
Pin No. Symbol Description Note

1 VLCD Power Supply +12.0V
5 GND Ground
6 GND Ground
7 GND Ground
8 GND Ground
9 LVDS Select ‘H’ =JEIDA , ‘L’ or NC = VESA Appendix VII
10 GND Ground
11 GND Ground
12 RA- LVDS Receiver Signal(-)
13 RA+ LVDS Receiver Signal(+)
14 GND Ground
15 RB- LVDS Receiver Signal(-)
16 RB+ LVDS Receiver Signal(+)
17 GND Ground
18 RC- LVDS Receiver Signal(-)
19 RC+ LVDS Receiver Signal(+)
20 GND Ground
21 RCLK- LVDS Receiver Clock Signal(-)
22 RCLK+ LVDS Receiver Clock Signal(+)
23 GND Ground
24 RD- LVDS Receiver Signal(-)
25 RD+ LVDS Receiver Signal(+)
26 GND Ground
27 PWM OUT PWM output (From LCM)
28 Ext VBR-B External VBR (From System)
29 GND Ground
30 GND Ground
Notes : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard. (Please see the Appendix VI)
第 92 页，共 122 页
Ver. 0.1 10 / 27
3-2-2. Backlight Module
[ Master ] [ Slave ]
1) Connector (housing) 1) Connector (housing)
: 65002HS-03 (YEONHO) or equivalent : 65002HS-03 (YEONHO) or equivalent
2) Mating Connector (wafer) 2) Mating Connector (wafer)
: 65002WS-03(YEONHO) or equivalent. : 65002WS-03(YEONHO) or equivalent.
Table 5. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN2,CN3)

No Symbol Master Slave Note
1 H_Input High_Input High_Input
3 FB NC NC
◆ Rear view of LCM
BD
T
1
2
3
3
2
1
第 93 页，共 122 页
Ver. 0.1 11 / 27
4. Optical Specification
Optical characteristics are determined after the unit has been ‘ON’ and for 60 minutes in a dark environment at
25±2°C. The values are specified at an approximate distance 50cm from the LCD surface at a viewing angle of
Φ and θ equal to 0 °.
FIG. 1 shows additional information concerning the measurement equipment and method.
LCD Module Pritchard 880 or
Optical Stage(x,y)
equivalent
50cm
FIG. 1 Optical Characteristic Measurement Equipment and Method
Table 9. OPTICAL CHARACTERISTICS (NOT FIXED)
Ta= 25±2°C, VLCD=12.0V, fV=60Hz, Dclk=72.4MHz, IBL=78mArms
Value
Parameter Symbol Unit Note
Min Typ Max
Contrast Ratio CR 700 1000 - 1
Surface Luminance, white LWH 280 350 cd/m2 2
Luminance Variation δ WHITE 5P - - 1.3 3
Response Time ON/OFF - 22 33 ms 4
Rx 0.620
RED
Ry 0.330
Gx 0.299
GREEN
Color Coordinates Gy Typ 0.592 Typ
[CIE1931] Bx -0.03 0.148 +0.03
BLUE
By 0.073
Wx 0.279
WHITE
Wy 0.292
Viewing Angle (CR>10)
x axis, right(φ=0°) θr 89 - -
x axis, left (φ=180°) θl 89 - -
degree 5
y axis, up (φ=90°) θu 89 - -
y axis, down (φ=270°) θd 89 - -
Gray Scale 2.2 6
第 94 页，共 122 页
Ver. 0.1 16 / 27
3.LG LC370WXE SV V2
LC370WXE
The LC370WXE is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 37.02 inch diagonally
measured active display area with WXGA resolution (768 vertical by 1366 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It has been designed to apply the 8-bit 1-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Mini-LVDS(RGB)
EEPROM
Source Driver Circuit
SCL SDA S1 S1366
+12.0V G1
Gate Driver Circuit
LVDS Timing Controller

5pair CN1
(30pin) [LVDS Rx]
Select #9 TFT - LCD Panel
(1366 × RGB × 768 pixels)
Power Circuit G768

Block
High Input CN2, 3pin, 14 Lamps/@89 mA

Back light Assembly
High Input CN3, 3pin, 14 Lamps/@89mA
General Features
Active Screen Size 37.02 inches(940.3mm) diagonal
Outline Dimension 877.0mm(H) x 516.8mm(V) x 46.9mm(D) (Typ.)
Pixel Pitch 0.200mm x 0.600mm x RGB
Pixel Format 1366 horiz. by 768 vert. pixels RGB stripe arrangement
Color Depth 8-bit, 16.7 M colors
Luminance, White 380 cd/m2 (Center 1 point Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178(Typ.), U/D 178(Typ.))
Power Consumption Total 88.2 Watt (Typ.) (Logic= 3.2 W, Inverter= 85W @ with inverter )
Weight 6,950(Typ.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 13%)
Ver. 0.1 4 /41
第 95 页，共 122 页
3.LG LC370WXE SV V2
LC370WXE
3-2. Interface Connections

This LCD module employs two kinds of interface connection, a 30-pin connector is used for the module electronics and
3-pin Balance PCB connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN5) : FI-X30SSL-HF (Manufactured by JAE) or IS100-L30B-C23(Manufactured by UJU)
- Mating Connector : FI-X30C2L (Manufactured by JAE) or Equivalent
Table 4. MODULE CONNECTOR(CN5) PIN CONFIGURATION

Pin No. Symbol Description Note
5 GND Ground
6 GND Ground
7 GND Ground
8 GND Ground
9 LVDS Select ‘H’ =JEIDA , ‘L’ or NC = VESA Appendix VII
10 NC No Connection
11 GND Ground
12 RA- LVDS Receiver Signal(-)
13 RA+ LVDS Receiver Signal(+)
14 GND Ground
15 RB- LVDS Receiver Signal(-)
16 RB+ LVDS Receiver Signal(+)
17 GND Ground
18 RC- LVDS Receiver Signal(-)
19 RC+ LVDS Receiver Signal(+)
20 GND Ground
21 RCLK- LVDS Receiver Clock Signal(-)
22 RCLK+ LVDS Receiver Clock Signal(+)
23 GND Ground
24 RD- LVDS Receiver Signal(-)
25 RD+ LVDS Receiver Signal(+)
26 GND Ground
27 NC No Connection
28 NC No Connection
29 GND Ground
30 GND Ground
Notes : 1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All VLCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard. (Please see the Appendix VI)
4. Specific pin No. #30 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
Ver. 0.1 10 /41
第 96 页，共 122 页
3.LG LC370WXE SV V2
LC370WXE
3-2-2. Backlight Inverter
[ Master ] [ Slave ]
1) Balance Connector 1) Balance Connector
: 65002WS-03 (manufactured by YEONHO)or equivalent : 65002WS-03 (manufactured by YEONHO)or equivalent
2) Mating Connector 2) Mating Connector
: 65002HS-03 (manufactured by YEONHO) or equivalent. : 65002HS-03 (manufactured by YEONHO) or equivalent.
Table 5. BACKLIGHT CONNECTOR PIN CONFIGURATION(CN2,CN3)

No Symbol Master Slave Note
3 FB NC NC
◆ Rear view of LCM
3 2 1
1 2 3
Master Slave
Ver. 0.1 11 /41
第 97 页，共 122 页
3.LG LC370WXE SV V2
LC370WXE
Optical characteristics are determined after the unit has been ‘ON’ and stable in a dark environment at 25±2°C.
The values specified are at an approximate distance 50cm from the LCD surface at a viewing angle of Φ and θ
equal to 0 °.
FIG. 1 shows additional information concerning the measurement equipment and method.
LCD Module Pritchard 880 or

Optical Stage(x,y)
equivalent
50cm
FIG. 1 Optical Characteristic Measurement Equipment and Method
Table 10. OPTICAL CHARACTERISTICS Ta= 25±2°C, VLCD=12.0V, fV=60Hz, Dclk=72.4MHz, IBL=89mArms
Value
Parameter Symbol Unit Note
Min Typ Max
Contrast Ratio CR 800 1200 - 1
Surface Luminance, white LWH 304 380 - cd/m2 2
Luminance Variation δ WHITE 5P - - 1.3 3
Gray-to-Gray G to G - 8 12 ms 4
Response Time
Uniformity G to G σ - 6 9 5
Rx 0.636
RED
Ry 0.335
Gx 0.290
GREEN
Color Coordinates Gy Typ 0.610 Typ
[CIE1931] BLUE Bx -0.03 0.144 +0.03
By 0.063
WHITE Wx 0.279
Wy 0.292
Viewing Angle (CR>10)
x axis, right(φ=0°) θr 89 - -
x axis, left (φ=180°) θl 89 - -
degree 6
y axis, up (φ=90°) θu 89 - -
y axis, down (φ=270°) θd 89 - -
Gray Scale - 2.2 - 7
Ver. 0.1 16 /41
第 98 页，共 122 页
4.AUO T420HW06 V.3
T420HW06 V3 Product Specification
Rev. 03
This specification applies to the 42.0 inch Color TFT-LCD Module T420HW06 V3. This LCD module has a TFT
active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 42.0 inch. This module supports
1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
The T420HW06 V3 has been designed to apply the 8-bit 2 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important.
* General Information
Items Specification Unit Note

Active Screen Size 42.02 inch
Display Area 930.24(H) x 523.26(V) mm
Outline Dimension 983.0(H) x 576.0(V) x 49(D) mm
Driver Element a-Si TFT active matrix
Display Colors 16.7M Colors
Number of Pixels 1920X1080 Pixel
Pixel Pitch 0.4845 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze=13%
第 99 页，共 122 页
© Copyright AUO Optronics Corp. 2009 All Rights Reserved. Page 4 / 29
4.AUO T420HW06 V.3
Rev. 03
3.2 Interface Connections
LCD connector: 187059-51221 (P-TWO, LVDS connector)
Mating connector:
PIN Symbol Description PIN Symbol Description
1 GND Ground 26 GND Ground
2 NC No connection 27 GND Ground
3 Reserved AUO Internal Use Only 28 CH2_0- LVDS Channel 2, Signal 0-
4 Reserved AUO Internal Use Only 29 CH2_0+ LVDS Channel 2, Signal 0+
5 NC No connection 30 CH2_1- LVDS Channel 2, Signal 1-
6 Reserved AUO Internal Use Only 31 CH2_1+ LVDS Channel 2, Signal 1+
Open/High(3.3V) for NS,
7 LVDS_SEL 32 CH2_2- LVDS Channel 2, Signal 2-
Low(GND) for JEIDA
PWM Dimming signal input
Reserved
8 (AC : 0~3.3V, max:4V, 33 CH2_2+ LVDS Channel 2, Signal 2+
(VBR_EXT)
Duty : 60~100%, freq : 120~240Hz)
Reserved PWM Dimming signal output
9 34 GND Ground
(OPC_OUT) (AC:0~3.3V)
Enable DCR function
Reserved
10 Enable:3.3V(max:4V), 35 CH2_CLK- LVDS Channel 2, Clock -
(OPC Enable)
Disable:0V(or Open)
11 GND Ground 36 CH2_CLK+ LVDS Channel 2, Clock +
12 CH1_0- LVDS Channel 1, Signal 0- 37 GND Ground
13 CH1_0+ LVDS Channel 1, Signal 0+ 38 CH2_3- LVDS Channel 2, Signal 3-
14 CH1_1- LVDS Channel 1, Signal 1- 39 CH2_3+ LVDS Channel 2, Signal 3+
15 CH1_1+ LVDS Channel 1, Signal 1+ 40 Reserved AUO Internal Use Only
16 CH1_2- LVDS Channel 1, Signal 2- 41 Reserved AUO Internal Use Only
17 CH1_2+ LVDS Channel 1, Signal 2+ 42 GND Ground
19 CH1_CLK- LVDS Channel 1, Clock - 44 GND Ground
20 CH1_CLK+ LVDS Channel 1, Clock + 45 GND Ground
22 CH1_3- LVDS Channel 1, Signal 3- 47 NC No connection
23 CH1_3+ LVDS Channel 1, Signal 3+ 48 VDD Power Supply, +12V DC Regulated
24 Reserved AUO Internal Use Only 49 VDD Power Supply, +12V DC Regulated
25 Reserved AUO Internal Use Only 50 VDD Power Supply, +12V DC Regulated
51 VDD Power Supply, +12V DC Regulated
第 100 页，共 122 页

4.AUO T420HW06 V.3
Rev. 03
3.7.2 lamp specification
Spec
Item Symbol Condition Unit Note
Min Typ Max
Lamp voltage VL 800 1000 1200 Vrms 1
Lamp current IL - 13 - mArms
Lamp frequency fL 35 80 kHz
℃
At 0 - - 1840 Vrms
At 25℃
Starting voltage Vs
- - 1157 Vrms
Delayed discharge time TD - - 0.5 sec
Life time TL 50K - - hr
Unsymmetrical ratio UR - - 10% -
Note 1.
Crest factor C.F. 2 − 10% 2 2 + 10% -
The above characteristics are measured under the conditions:
℃
Ambient temperature: 25±2 , Relative Humidity: 65±20%RH.
Note 1: Waveform definition

Please light on the lamp with symmetrical voltage and current waveform (unsymmetrical ratio is less than
10%, crest factor within 2 ± 10% ).
Unsymmetrical Ratio = |Ip-I-p| / Irms*100%

Ip Crest Factor = Ip (or I-p) / Irms
Ip : High side peak value
I-p : Low side peak value
I-p Irms : Root mean square value
第 101 页，共 122 页

4.AUO T420HW06 V.3
Rev. 03
Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45 minutes in a
dark environment at 25°C. The values specified are at an approximate distance 50cm from the LCD surface at a
viewing angle of φ and θ equal to 0°.
Fig.1 presents additional information concerning the measurement equipment and method.
SR3 or equivalent
Values
Parameter Symbol Unit Notes
Min. Typ. Max
Contrast Ratio CR 3200 4000 -- 1
2
Surface Luminance (White) LWH 380 450 -- cd/m 2
Luminance Variation δWHITE(9P) -- -- 1.3 3
Response Time (G to G) Tγ -- 8 -- Ms 4
Color Gamut NTSC 72 %
Color Coordinates
Red RX 0.640
RY 0.330
Green GX 0.281
GY 0.590
Typ.-0.03 Typ.+0.03
Blue BX 0.144
BY 0.060
White WX 0.280
WY 0.290
Viewing Angle 5
x axis, right(φ=0°) θr -- 89 -- degree
x axis, left(φ=180°) θl -- 89 -- degree
y axis, up(φ=90°) θu -- 89 -- degree
y axis, down (φ=270°) θd -- 89 -- degree
Note:
第 102 页，共 122 页
10.2 电源接口规格
1.MIP260B-19
8. Pin Connection (连接器脚位定义)
Table 15 Pin-CN3 Connection And Function
NO. Pin Connection Function
1 +5VSB STANDBY OUTPUT

2.3 +12V +12V OUTPUT
4.5 GND GND RETURN
6.7 5V +5V OUTPUT
8.9 GND GND RETURN
10 SB SMPS ON/OFF CONTROL(ON = HIGH)
11 BK BACKLIGHT ON
12 DM INTERNAL PWM DIMMING
Note: CN3 -- JST VA CONNEETION, TYPE : pitch2.5mm

1 GND +5V RETURN

2 GND +5V RETURN
3.4.7.8 +5V +5V OUTPUT
6 +VS STANDBY OUTPUT
9.10.11 GND +VS. +12V RETURN
12.13 +12V +12V OUTPUT

1 GD GND
3 DM INTERNAL PWM DIMMING
4 BK BACKLIGHT ON
5 PM EXTERNAL PWM DIMMING DUTY
DESCRIPTION:
MEGMEET 麦格米特电气技术有限公司 (规格书)
MEGMEET ELECTRICAL TECHNOLOGY CO., LTD. SPECIFICATION
THESE SPECIFICATION ARE THE PROPERTY OF MEGMEET ELECTRICAL TECHNOLOGY CO., LTD Model No.:
AND SHALL NOT BE REPRODUCED OR USED AS THE BASIS FOR THE MANUFACTURE OR SELL
OF APPARATUSES OR DEVICES WITHOUT PERMISSION. MIP260B
DATE PREPARED CHECKED APPROVED Document No.: REV:
第 ZHANGZHI
103 页，共 122 页
2007/6/28 ZUZHILI GUICHENGCAI MSPS-MIP260B-1.1 1.1
10 OF 13
1.MIP260B-19
Table 18 Pin-CN4；CN5；CN6；CN7 Connection And Function
1、2 CCFL CCFL-VOL. Output
Note:

1 AC-N2OO9 AC INPUT NUTURE FROM SW

2 NC NC
3 AC-L2 AC INPUT LINE FROM SW
4 NC NC
5 AC- N1 AC INPUT LINE TO SW
6 NC NC
7 AC- L1 AC INPUT NUTURE TO SW

① AC-N AC INPUT NUTURE

② NC NC
③ AC-L AC INPUT LINE

Pin Connection Function
PIN① AND PIN② SHORT EXTERNAL PWM DIMMING DUTY ENABLE

PIN①AND PIN② OPEN INTERNAL PWM DIMMING
DESCRIPTION:
OF APPARATUSES OR DEVICES WITHOUT PERMISSION. MIP260B
第 ZHANGZHI
104 页，共 122 页
2007/6/28 ZUZHILI GUICHENGCAI MSPS-MIP260B-1.1 1.1
11 OF 13
2. MIP320G-A
Specification Document No.˖ M-3-WI-RD-004 A0
Issued Date : 2010-03-20
Model˖MIP320G
5.6 Shock˄‫ߏކ‬㗤ফ˅
* 49m/s²(5G),11ms, once each X, Y and Z axis.
6. Dimension ˄⠽⧚ሎᇌ˅
*230 mm X 120mm X 25mm(‫ܗ‬ӊ䴶催) (䭓 L *ᆑ W * 催 H ).
7. Weight ˄䞡䞣˅
8. Pin Connection (䖲᥹఼㛮ԡᅮН)

Table 13 CN2(10Pin)
1 +12V +12V DC OUTPUT
3 SGND RETURN
4 SGND RETURN
5 +5V +5V OUTPUT
6 +5V +5V OUTPUT
7 SGND RETURN
8 SGND RETURN
9 +5VSB +5V OUTPUT
10 STB 6036212))&21752/21 +,*+
Note: DOUBLE ROW CONNEETION, pitch:2.5mm.
Table 14 CN3(4Pin)
3 SGND RETURN
4 SGND RETURN
Note: DOUBLE ROW CONNEETION, pitch:2.5mm
Table 15 CN7(4Pin)
1 BK %$&./,*+721
2 DM ,17(51$/3:0',00,1*
3 NC NC
⠜ᴗሲѢ呺Ḑ㉇⡍, ⽕ℶӏԩ᳾㒣ᥜᴗⱘՓ⫼Ǆ ‫ٻڍڌٻہۊٻڔٻۀۂڼګٻ‬

第 105
The copyright belongs 页，共 Any
to Megmeet. 122 unauthorized
页 use is prohibited.
2. MIP320G-A
Specification Document No.˖ M-3-WI-RD-004 A0
Issued Date : 2010-03-20
Model˖MIP320G
4 SGND RETURN
Table 16 CN1(3Pin)
1 $&/ $&,1387/,1(
2 1& 1&
3 $&1 $&,138718785(
Table 17 CN4,CN5(2Pin)
1,2 (()/ (()/VOL. Output
9. Power Supply Mounting ˄ᅝ㺙ሎᇌ˅ऩԡ mm.
⠜ᴗሲѢ呺Ḑ㉇⡍, ⽕ℶӏԩ᳾㒣ᥜᴗⱘՓ⫼Ǆ ‫ٻڍڌٻہۊٻڋڌٻۀۂڼګٻ‬

第 106
The copyright belongs 页，共 Any
to Megmeet. 122 unauthorized
页 use is prohibited.
3. MIP328B-K-1
* 10-55Hz, 19.6m/s²(2G), 3minutes period, 60minutes each along X, Y and Z axis.
5.6 Impact （冲击耐受）
* 49m/s²(5G),11ms, once each X, Y and Z axis.
6. Dimension （物理尺寸）
* 205mm X 133mm X 30mm (长 L *宽 W * 元件高 H ).
7. Weight （重量）
8. Pin Connection (连接器脚位定义)

1 EPWM-IN EXTERNAL PWM DIMMING DUTY

2 BK BACKLIGHT ON/OFF
3 APWM INTERNAL PWM DIMMING
4 STB SMPS ON/OFF CONTROL(ON = HIGH)
5 GND GND RETURN

2.3.4.5 +12V +12V OUTPUT
6.7.8.9 GND GND RETURN
11 BK BACKLIGHT ON/OFF
12 APWM INTERNAL PWM DIMMING
1.2 GND GND RETURN

3.4 +5V +5V OUTPUT
7.8 +5V +5V OUTPUT
9.10.11 GND GND RETURN
12.13 +12V +12V OUTPUT
DESCRIPTION:
OF APPARATUSES OR DEVICES WITHOUT PERMISSION. MIP328B-K-1
第 107 页，共 122 页
2010/06/08 QIUPENGFEI GUICHENGCAI ZHANGZHI MSPS-MIP328B-K-1.2 1.2
9 OF 11
3. MIP328B-K-1
Table 18 HV Function
HV TFT TFT-VOL. Output

Note:
① AC-N AC INPUT NUTURE

② NC NC
③ AC-L AC INPUT LINE
Pin Connection Function
PIN① AND PIN② SHORT EXTERNAL PWM DIMMING DUTY ENABLE

PIN①AND PIN② OPEN INTERNAL PWM DIMMING
1 HVGND1 HVGND1
2.3 NC NC
4 VS1 VS1
5 GND GND
6.7.8 A2 A2
9.10.11 A1 A1

1 HVGND2 HVGND2
2.3 NC NC
4 VS2 VS2
5 GND GND
6.7.8 A1 A1
9.10.11 A2 A2
DESCRIPTION:
第 108 页，共 122 页
10 OF 11
3. MIP328B-K-1
Table 23 Pin-CN1A Connection And Function
1 HVGND HVGND
2.3 NC NC
4 VS VS
5 GND GND
6.7.8 A1 A1
9.10.11 A2 A2
Note: CN1A -- JST VA CONNEETION, TYPE : pitch2.5mm
DESCRIPTION:
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11 OF 11
4. MIP988-J

2.4.6.8.9 GND GND RETURN
5.7 +12V +12V OUTPUT
10.11 +24V +24V OUTPUT

3,4 ,7,9,10 GND GND RETURN
5,6 +5V +5V OUTPUT
8 +12V +12V OUTPUT
11，12 +24V +24V OUTPUT
1 AC-N AC INPUT NUTURE

2,3,4 NC NC
5 AC-L AC INPUT LINE
Note: CN1 -- JST VA CONNEETION, TYPE : pitch3.96mm,
DESCRIPTION:
OF APPARATUSES OR DEVICES WITHOUT PERMISSION. MIP988A-J
2010/04/22 JiangXiaofeng 第 110 页，共 122 页 1.0
10 OF 12
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第 112 页，共 122 页
第 113 页，共 122 页
第 114 页，共 122 页
MSTAR TSUMV36KU (SD)机芯软件升级说明
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软件升级
一、准备
1. 准备SD机芯升级工具，升级工具是一头并口，一头是VGA口（如图1所示）。
图1
2.连接升级工具并口端到电脑主机并口端，连接升级VGA口到机芯板VGA插座，确认以上连接
无误后打开液晶电视开关（如图2所示）。
注：此系列液晶电视具有关机记忆功能。如果上次关闭电源开关之前是使用遥控先待机，则
再次打开电源开关后，也要使用遥控开机。升级之前液晶电视机一定要处于开机状态（指示灯不
亮），不能处于待机状态（指示灯亮红色）。
图2
二、软件升级
1.释放包裹文件ISP_Tool(SD).rar里面的程序文件ISP_Tool.exe到桌面。
图3
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2，双击桌面ISP_Tool.exe，打开程序运行界面（如图4所示）。
图4
3.单击Config按钮，打开Config对话框，设置升级工具配置选项。
图5
1) 可根据电脑配置适当调节I2C Speed Setting来增加升级速度。
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4.单击Connect按钮，建立电脑与机芯板通信。
1) 如果连接成功则弹出如Isp_tool对话框，显示驱动类型为AT26DF081A
2) 如果连接失败，则弹出Dialog对话框，显示“can’t Find the Device Type!!”。连接失败是
因为机芯板主芯片与flash没有工作，或者双方没有通信而引起。故障排除后重新连接直到成功。
图6 图7
5.单击Read按钮，打开Read对话框。
图8
1)，单击按钮，弹出打开对话框，选择升级文件(bin尾缀)，单击按钮，升

级文件载入并返回主程序对话框。
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图9
6.单击Auto按钮，打开Auto对话框。
升级信息显示
升级进度条
图10
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1) Blank、Program、Verify、Exit ISP建议全部选中。
2) 单击按钮开始升级。
升级中：
图11
3) 升级完成后在升级进度条后面显示PAAS
升级完成
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4）软件升级完成后，将电视机电源开关关闭，等待指示灯从亮变为暗后（型号不一样，时间
不等）约有30S，从新打开电源开关。
7.复位与检查
1）软件升级完成从新开机后，进入工厂模式（图12），按遥控器选择并进入“E2P ADJUST”
子菜单（图13），选中“DEFAULT”项目，按遥控器左软键开始复位。复位过程中屏幕左上角显示
“DEFAULT”（图14）。当“DEFAULT”自动显示后并进入TV模式，复位完成。
进入工厂模式方法：按遥控器“图像模式”键，再连按数字键“5”“8”“0”即可进入工厂
调试菜单。按遥控器“菜单”键可以退出工厂调试模式。
2）进入工厂调试菜单检查软件版本是否正确
进入工厂模式后，在工厂菜单最下方显示的是软件本版号。
图12 工厂菜单
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图13 E2P ADJUST 子菜单，
图13 复位过程中，显示EDFAULT
8.升级完成
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维 修 手 册

二合一电源板 T-CON 板 LCD 显示屏

二合一电源板 T-CON 板 LCD 显示屏

电源板 T-CON 板 LCD 显示屏

电源板 T-CON 板 LCD 显示屏

5.4 SIDE AV板

+3.3V L4 AVDDA VDDP

GPIO Define AMS1117-ADJ

PIN66 RDZ: LVDS Power Switching TO-252封装,贴片SOT-223

CA5 C28 C29 C30 C35

PIN107 SAR2: 4052_CTL 301

EMC DGND POWER

2)HDMI&VGA INPUT INTERFACE

4 R54 10K C45 2.2uF

J406 R- close to MST IC

R40 100R HS-RGB

+5VSTB R46 4.7K R43 R44 VGA_TX R47 100R/NC

VGA5V C44 R51 R52

JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z

HOTPLUG Size Document Number Rev

Draw: Zhangwd Date: Friday, January 22, 2010 Sheet 3 of 8

2.2uF 10nF R66 R67

SDA R78 10R I2C_SDA

R89 10 L11 220uH 40V

or will destroy Q44!

C110 14.318MHZ 1M AVDD_MPLL

2.2uF C112 5VCC

R_TX2+ SOY 3 87 RXE1- +5VSTB

6 HS_RGB SOG GIN0 3

3 BIN+ VS_RGB RIN0

PR+ CVBS0 19 109 do not use GPIO function in PAD_INT

6 PR+ R171 68R C115 47nF CVBS0P SAR0 R172 0R SAR1

6 SV_Y0 GPIOD[1] SC_EN 6 R185

AV_AUR1 AV_AUR2 LINE_IN_4L AD[2] R181 100R I2C_SDA

4 VIFM +5VSTB +3.3STB

Draw: Zhangwd Date: Friday, January 15, 2010 Sheet 5 of 8

Y1_IN R59 33R C52 47nF Y+

AUR1_AVAUR1_AV 10K 2.2uF Pb_IN R60 33R C53 47nF PB+

Close to connector Close to MST IC NC NC NC

Layout Placement close to Mstar IC 5VCC

S-C SV_C0 C103

R123 0 R311 1K 1 Q13

J407 C79 C80

1 A_OUT_R AV_ROUT Close to connector Close to MST IC

Draw: Zhangwd Date: Thursday, January 14, 2010 Sheet 6 of 8

R233 R222 R228

HIGH = > LVDS POWER ON RXE2-

10K I2C_SDA 5 RXE3- RXE3-

R217 C99 5VCC 2,4,6,8

A JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z A

Draw: Zhangwd Date: Wednesday, July 28, 2010 Sheet 7 of 8

R291 R122 C168 C164 C165

C171 AMP-RIN C97 1.5nF C167 P5/2.54mm

R295 220R C172

NC/47K AMP-MUTE PHONEJACK_STEREO

NC/100K mute=H 1 3904 10K C94

JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z

Draw: Zhangwd Date: Wednesday, July 28, 2010 Sheet 8 of 8

RM1 L102A C106 D101

CY3 RP1 L103

RF5 CF1 RF1 RF3 RF12

Size Number Revision

2 RV3 D109 C113

维修手册