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Introduction
SystemVerilog is a set of extensions to the Verilog hardware description
language and is expected to become IEEE standard 1800 later in 2005.
SystemVerilog Assertions (SVA) form an important subset of SystemVerilog, SEARCH SILICON IP
and as such may be introduced into existing Verilog and VHDL design flows.
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Assertions are primarily used to validate the behavior of a design. ("Is it
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working correctly?") They may also be used to provide functional coverage
information for a design ("How good is the test?"). You can add assertions to
your RTL code as you write it " these form "active comments" that document
what you have written and what assumptions you have made. Assertions
may also be used as a formal specification language, making the
requirements clear and unambiguous, and making it possible to automate RELATED ARTICLES
validation of the design against the specification.
How to instrument your design with
simple SystemVerilog assertions
SystemVerilog Assertions are not difficult to learn; in this tutorial, you will
learn the basic syntax, so that you can start using them in your RTL code Using advanced logging techniques to
debug & test SystemVerilog HDL code
and testbenches.
How to raise the RTL abstraction level and
Properties and Assertions design conciseness with SystemVerilog -
Part 2
An assertion is an instruction to a verification tool to check a property.
Properties can be checked dynamically by simulators such as VCS, or How to raise the RTL abstraction level and
design conciseness with SystemVerilog -
statically by a separate property checker tool " such as Magellan. They are Part 1
understood by Design Compiler, which knows to ignore them with a warning.
FPGA Prototyping of Complex SoCs: RTL
Alternatively, you can use the translate_off/translate_on pragmas. code migration and debug strategies
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it is executed immediately after the evaluation of the assert expression. The
statement associated with an else is called a fail statement and is executed
if the assertion fails:
You may omit the pass statement yet still include a fail statement:
The failure of an assertion has a severity associated with it. There are three
severity system tasks that can be included in the fail statement to specify
the severity level: $fatal, $error (the default severity) and $warning. In
addition, the system task $info indicates that the assertion failure carries no
specific severity.
The pass and fail statements can be any legal SystemVerilog procedural
statement. They can be used, for example, to write out a message, set an
error flag, increment a count of errors, or signal a failure to another part of
the testbench.
AeqB: assert (a == b)
else begin error_count++; $error("A should equal B"); end
Concurrent Assertions
The behavior of a design may be specified using statements similar to these:
Concurrent assertions are used to check behavior such as this. These are
statements that assert that specified properties must be true. For example,
asserts that the expression Read && Write is never true at any point during
simulation.
The first assertion example above does not contain a clock. Therefore it is
checked at every point in the simulation. The second assertion is only
checked when a rising clock edge has occurred; the values of Req and Ack
are sampled on the rising edge of Clock.
Implication
The implication construct (|->) allows a user to monitor sequences based on
satisfying some criteria, e.g. attach a precondition to a sequence and
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evaluate the sequence only if the condition is successful. The left-hand side
operand of the implication is called the antecedent sequence expression,
while the right-hand side is called the consequent sequence expression.
There are two forms of implication: overlapped using operator |->, and non-
overlapped using operator |=>.
s1 |-> s2;
s1 |=> s2;
"define true 1
s1 ##1 "true |-> s2;
where `true is a boolean expression, used for visual clarity, that always
evaluates to true.
property not_read_and_write;
! (Read && Write);
endproperty
assert property (not_read_and_write);
Complex properties are often built using sequences. Sequences, too, may be
declared separately:
sequence request
Req;
endsequence
sequence acknowledge
##[1:2] Ack;
endsequence
property handshake;
@(posedge Clock) request |-> acknowledge;
endproperty
Assertion Clocking
Concurrent assertions (assert property and cover property statements)
use a generalized model of a clock and are only evaluated when a clock tick
occurs. In fact, the values of the variables in the property are sampled right
at the end of the previous time step. Everything in between clock ticks is
ignored. This model of execution corresponds to the way a RTL description of
a design is interpreted after synthesis.
A clock tick is an atomic moment in time and a clock ticks only once at any
simulation time. The clock can actually be a single signal, a gated clock (e.g.
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(clk && GatingSig)) or other more complex expression. When monitoring
asynchronous signals, a simulation time step corresponds to a clock tick.
The clock for a property can be specified in several ways, of which the most
common are:
property p1;
@(posedge clk) disable iff (Reset) not b ##1 c;
endproperty
The not negates the result of the sequence following it. So, this assertion
means that if Reset becomes true at any time during the evaluation of the
sequence, then the attempt for p1 is a success. Otherwise, the sequence (b
##1 c) must never evaluate to true.
Sequences
A sequence is a list of boolean expressions in a linear order of increasing
time. The sequence is true over time if the boolean expressions are true at
the specific clock ticks. The expressions used in sequences are interpreted in
the same way as the condition of a procedural if statement.
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This means a is followed by any number of clocks where c is false, and b is
true between one and three times, the last time being the clock before c is
true.
"A request (req high for one or more cycles then returning to zero) is
followed after a period of one or more cycles by an acknowledge (ack high
for one or more cycles before returning to zero). ack must be zero in the
cycle in which req returns to zero."
"After a request, ack must remain high until the cycle before grant is high.
If grant goes high one cycle after req goes high then ack need not be
asserted."
Further Information
Doulos's Modular SystemVerilog training program provides full-scope training
in SystemVerilog and includes a training module specifically on the use of
SystemVerilog assertions. The courses include full support for Synopsys
tools, including Design Compiler and VCS.
Public Modular SystemVerilog classes are scheduled in the USA and Europe,
and team-based training is available worldwide. Dates and locations
currently scheduled are these:
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