In the last 10 years, FPGA circuits have developed rapidly, because of their configurability,

their easy use and the low cost to design a function on them. However, the internal
memories used in FPGA circuits could limit their future development.

FPGA Implementation Technologies

SRAM-based FPGAs

• Most FPGA circuits use SRAM based configuration and Flip-Flop as internal
memory; but as the SRAM is volatile both their configuration and the information
stored in their internal registers are lost when the power is turned down. The
configuration is then stored in an external PROM and downloaded in the FPGA at
startup.

SRAM-based FPGAs with an internal flash memory

The SRAM-based FPGAs with internal flash memory use flash only during startup to load data to the
SRAM configuration cells.

Internal Flash technology is now sometime used to replace the external memory

Flash-based FPGAs
On the contrary, true flash-based FPGA uses flash as a primary resource for configuration storage, and
doesn't require SRAM

the flash-based arrays often have a reduced system footprint and power consumption since an
external configuration memory is not needed. Another benefit of flash-based devices is startup
time — since the configuration memory is on the same chip as the logic, the configuration
pattern loads almost instantly, whereas their SRAM-based cousins are still loading the
configuration.

This type of FPGA is generally like the previous, except that these chips contain internal flash memory
blocks, thus eliminating the need to have an external non-volatile memory

CONCLUDE
Modern SRAM-based FPGAs have highest densities, but consume a lot of power and need an external
non-volatile memory to store configuration bitstream. SRAM-based FPGAs with an internal flash module
doesn't need an external configuration memory. Flash-based and Antifuse based FPGAs consume much
less power than their SRAM-based counterparts.

Spin transfer torque RAM

Each of these technologies has scalability limitations with regard to power consumption, performance
and speed or reliability.

Hence there comes an alternative approach to use a universal memory. It is to use a single universal
memory that embodies all ideal properties of each layer having high performance, high density, high
endurance, low power consumption and storage class nonvolatility. Spin transfer torque RAM (STT-
RAM) built using Magnetic Tunnel Junction (MTJ)

High writing and reading speed makes Spin-RAM (Spin Transfer Torque Magnetization
RAM) technology [5] as one of the best solutions to bring a complete non-volatility to FPGA
circuits while keeping low power dissipation. A MTJ (Magnetic Junction Tunnel), as Spin-
RAM storage element, can be re-programmed more than 1012 times and has a large
retention time of up to 10 years.

Spin-RAM is based on Spin Transfer Torque Magnetization writing approach, which figures
low writing current [7].

Tunnel junctions and magnetic tunnel junctions

In STT-MRAM, MTJ cells are the storing devices in which

values are stored in terms of resistances. The MTJ cell consists
of two ferromagnetic layers, namely, the pinned layer (also
known as reference or fixed layer) where the magnetic
orientation is always fixed and the free layer where the magnetic
orientation can be freely rotated. These two ferromagnetic layers
are separated by a thin barrier oxide layer (e.g., magnesium
oxide, MgO). The structure of an MTJ cell is shown in Fig. 1(a).
When the magnetic orientation of the free layer is in parallel (P)
or antiparallel (AP) to that of the pinned layer, the MTJ cell has
a low resistance or a high resistance states, respectively.

Magnetic Tunnel Junction (MTJ) is used as the storage element

of Spin-RAM. It is mainly composed by three layers (Fig. 2.1),
2 ferromagnetic layers and one oxide barrier. A MTJ behaves as
a resistor with two resistance characteristics (high and low)
depending on the magnetization direction in the two
ferromagnetic layers. A MTJ presents a low (respectively high)
resistance when the spin transport is in the same (resp. opposite)
direction in two ferromagnetic layers. This resistance variation
behavior was observed firstly by Julliere [14] in 1975. The ratio
between the two resistances at zero bias is named TMR
(Tunneling Magnetoresistance Ratio) and is defined in Equ.
(E.1). The TMR is currently up to 70% in an AlxO barrier MTJ
and 230% in an MgO barrier MTJ [15].
TMR=RAP−RPRAp(E.1)
View SourceRight-click on figure for MathML and additional
features. This improvement of TMR allows a simple CMOS
sensing circuit to read the information in MTJs more easily
when the low and high resistance represent different bit of
information. There are currently three MTJ writing approaches,
FIMS [9]–[10][11], TAS (Thermally assisted switching) [16]
and Spin transfer torque. The high switching current (>mA)
requirement of the first writing approache limits its applications
with Standard CMOS chip. Slonczewski [17] showed that there
is a threshold current density for switching MTJ in 1996, named
critical current density. If the current density in the MTJ is
bigger than the critical current density, the MTJ state will
change (Fig. 2.2), the positive and negative directions of current
determines the MTJ state changing from parallel (P) to anti-
parallel (AP) or AP to P. This critical current density has been
found as low as 8∗ 105 A/cm2 [7]; as the dimension of MTJ is
very small, the critical current is about 100uA and can now be
easily generated by some small transistors.

• In non magnetic conductor, electron scatters the same amount

regardless of spin of a current flow. How much they sctter determines
the resistance of device.
 • A spin-polarized current passing through a small magnetic conductor
will deposit spin-angular momentum into the magnetic system.
When two conducting electrodes are separated by a thin dielectric layer with a
thickness ranging from a few angstroms to a few nanometers, electrons can
tunnel through the dielectric layer.
CONCLUSION

STT-MRAM is an emerging nonvolatile memory technology due to its various

beneficial features, such as scalability, high density, no leakage, and high
endurance. However, high dynamic power is still a major concern for this
memory technology. To overcome this, it is required that all the active
components are turned-OFF immediately after they finish their respective
operations. We proposed a self-timed bitwise termination technique for
both read and write operations in which the operation completion is
detected on the fly and an acknowledgment signal is generated, with which
the respective active components can be turned-OFF. Our results for Leon3
main memory show that the proposed technique can reduce the overall
memory energy consumption by 88%.

2 Magnetic StorageThe smallest region with uniform magnetism is called a “domain”

Each bit requires two domains to allow for error identification

If two domains are magnetized in same direction, the bit is a 0

If two domains are magnetized in opposite directions, the bit is a 1Direction of magnetization must change at
the start of each new bit.

An electron moving into a magnetized region will exhibit spin-dependent scattering

Electrons with spins in the direction of the magnetic field will scatter less than electrons with spins opposite
the direction of the magnetic field

Charges traveling through magnetic field experience magnetic force (provided velocity and field are not
aligned):FB = qv x BForce is perpendicular to velocity (and to field), so charges are pushed “off track”,
resulting in more frequent collisions and thus an increased resistance

Advantages
As the MTJs are processed over the chip surface [9], shown in Fig. 1.1, and they are in very
small size (e.g. 100nm×80nm), Spin-RAM based FPGA circuit does not take more die area
than the classical FPGA and the actual layout of semiconductor circuit is barely affected, by
the non-volatile property addition.