Phase Change Memory

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Phase-change memory
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Phase-change memory (also known as PCME, PRAM, PCRAM, Ovonic Unified Memory, Chalcogenide RAM and C-RAM) is a type of non-volatile computer memory. PRAMs exploit the unique behavior of chalcogenide glass. With the application of heat produced by the passage of an electric current, this material can be "switched" between two states, crystalline and amorphous. Recent versions can achieve two additional distinct states, effectively doubling its storage capacity. PRAM is one of a number of new memory technologies competing in the non-volatile role with the almost universal flash memory. The latter technology has a number of practical problems which these replacements hope to address.
Contents
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1 Background 2 PRAM vs. Flash 3 2000 and later 4 Challenges 5 Timeline 6 References 7 External links
[edit] Background
In the 1960s Stanford R. Ovshinsky of Energy Conversion Devices first explored the properties of chalcogenide glasses as a potential memory technology. In 1969, Charles Sie
published a dissertation,[1][2] at Iowa State University that both described and demonstrated the feasibility of a phase change memory device by integrating chalcogenide film with a diode array. A cinematographic study in 1970 established that the phase change memory mechanism in chalcogenide glass involves electric-field-induced crystalline filament growth. [3] In the September 1970 issue of Electronics, Gordon Moore co-founder of Intel published an article on the technology. However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed as flash and DRAM memory technologies are expected to encounter scaling difficulties as chip lithography shrinks.[4] The crystalline and amorphous states of chalcogenide glass have dramatically different electrical resistivity, and this forms the basis by which data are stored. The amorphous, high resistance state is used to represent a binary 0, and the crystalline, low resistance state represents a 1. Chalcogenide is the same material used in re-writable optical media (such as CD-RW and DVD-RW). In those instances, the material's optical properties are manipulated, rather than its electrical resistivity, as chalcogenide's refractive index also changes with the state of the material. Although PRAM has not yet reached the commercialization stage for consumer electronic devices, nearly all prototype devices make use of a chalcogenide alloy of germanium, antimony and tellurium (GeSbTe) called GST. The stoichiometry or Ge:Sb:Te element ratio is 2:2:5. When GST is heated to a high temperature (over 600C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state and its electrical resistance is high. By heating the chalcogenide to a temperature above its crystallization point, but below the melting point, it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. Commonly, a crystallization time scale on the order of 100 ns is used.[5] This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 Samsung Electronics patent application indicates PRAM may achieve switching times as fast as five nanoseconds. A more recent advance pioneered by Intel and ST Microelectronics allows the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states; the previous amorphic or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent two bits, doubling memory density.[6]
A cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other in high resistance amorphous state.
[edit] PRAM vs. Flash

It is the switching time and inherent scalability[7] that makes PRAM most appealing. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology. Flash memory works by modulating charge (electrons) stored within the gate of a MOS transistor. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in insulator "traps"). The presence of charge within the gate shifts the transistor's threshold voltage, higher or lower, corresponding to a 1 to 0, for instance. Changing the bit's state requires removing the accumulated charge, which demands a relatively large voltage to "suck" the electrons off the floating gate. This burst of voltage is provided by a charge pump which takes some time to build up power. General write times for common Flash devices are on the order of 0.1ms (for a block of data), about 10,000 times the typical 10 ns read time, for SRAM for example (for a byte). PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times quicker than conventional hard drives, makes it particularly interesting in nonvolatile memory roles that are currently performancelimited by memory access timing. Additionally, with Flash each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are only rated for, currently, 5,000 writes per sector, and many flash controllers perform wear leveling to spread writes across many physical sectors. PRAM devices also degrade with use, for different reasons than Flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.[8] PRAM lifetime is limited by mechanisms such as degradation due to GST thermal expansion during programming, metal (and other material) migration, and other mechanisms still unknown. Flash parts can be programmed before being soldered on to a board, or even purchased preprogrammed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see reflow soldering or wave soldering). This is made worse by the recent drive to lead-free manufacturing requiring higher soldering temperatures. The manufacturer using PRAM parts must provide a mechanism to program the PRAM "insystem" after it has been soldered in place. The special gates used in Flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The resistivity of the memory element in PCM is more stable; at the normal working temperature of 85C, it is projected to retain data for 300 years.[9] By carefully modulating the amount of charge stored on the gate, Flash devices can store multiple (usually two) bits in each physical cell. This effectively doubles the memory density, reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent advances have removed this problem. Because Flash devices trap electrons to store information, they are susceptible to data corruption from radiation, making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.
PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode or a BJT provides the greatest amount of current for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. The chalcogenide resistance being a necessarily larger resistance than the diode entails that the operating voltage must exceed 1 V by a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most severe consequence of using a diode-selected array, particularly for large arrays, is the total reverse bias leakage current from the unselected bit lines. In transistorselected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete dopants as the p-n junction width scales down.
[edit] 2000 and later

In August 2004, Nanochip licensed PRAM technology for use in MEMS (micro-electricmechanical-systems) probe storage devices. These devices are not solid state. Instead, a very small platter coated in chalcogenide is dragged beneath many (thousands or even millions) of electrical probes which can read and write the chalcogenide. Hewlett-Packard's micro-mover technology can accurately position the platter to 3 nm so densities of more than 1 Tbit (125 GB) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach bears much resemblance to IBM's Millipede technology. In September 2006, Samsung announced a prototype 512 Mb (64 MB) device using diode switches.[10] The announcement was something of a surprise, and it was especially notable for its fairly high density. The prototype featured a cell size of only 46.7 nm, smaller than commercial Flash devices available at the time. Although Flash devices of higher capacity were available (64 Gb, or 8 GB, was just coming to market), other technologies competing to replace Flash generally offered lower densities (larger cell sizes). The only production MRAM and FeRAM devices are only 4 Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable Flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential replacement for NOR Flash, where device capacities typically lag behind those of NAND Flash devices. (State-of-the-art capacities on NAND passed 512 Mb some time ago.) NOR Flash offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time). Samsung's announcement was followed by one from Intel and STMicroelectronics, who demonstrated their own PCM devices at the 2006 Intel Developer Forum in October.[11] They showed a 128 Mb part that recently began manufacture at STMicroelectronics's research fab in Agrate, Italy. Intel stated that the devices were strictly proof-of-concept, but they expect to start sampling within months, and have widespread commercial production within a few years. Intel appears to be aiming their PCM products at the same market as Samsung. PCM is also a promising technology in the military and aerospace industries where radiation effects make the use of standard non-volatile memories such as Flash impractical. PCM memory devices have been introduced by BAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity. Additionally, BAE claims a write cycle endurance of 108, which will allow it to be a contender for replacing PROMs and EEPROMs in space systems. In February 2008, Intel engineers, in cooperation with STMicroelectronics, revealed the first multilevel (MLC) PCM array prototype. The prototype stored two logical bits in each physical cell, effectively 256 Mb of memory stored in a 128 Mb physical array. This means
that instead of the normal two statesfully amorphous and fully crystallinean additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area on the chip.[6] Also in February 2008, Intel and STMicroelectronics began shipping prototype samples of their first PCM product released to customers. The 90 nm, 128 Mb (16 MB) product is called Alverstone.[12] In April 2010,[13] Numonyx announced the Omneo line of 128-Mbit NOR-compatible phasechange memories and Samsung announced shipment of it 512 Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010. In June 2011,[14] IBM announced that they had created stable, reliable, multi-bit phase change memory with high performance and stability.
[edit] Challenges
The greatest challenge for phase-change memory has been the requirement of high programming current density (>107 A/cm, compared to 105-106 A/cm for a typical transistor or diode) in the active volume. This has led to active areas which are much smaller than the driving transistor area. The discrepancy has forced phase-change memory structures to package the heater and sometimes the phase-change material itself in sublithographic dimensions. This is a process cost disadvantage compared to Flash. The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material. Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions which allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions. Probably the biggest challenge for phase change memory is its long-term resistance and threshold voltage drift.[15] The resistance of the amorphous state slowly increases according to a power law (~t0.1). This severely limits the ability for multilevel operation (a lower intermediate state would be confused with a higher intermediate state at a later time) and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value. In April 2010, Numonyx released its Omneo[dead link] line of parallel and serial interface 128 Mb NOR-Flash replacement PCM chips. Although the NOR flash chips they intended to replace operated in the -40-85 C range, the PCM chips operated in the 0-70C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature sensitive p-n junctions to provide the high currents needed for programming.
[edit] Timeline

January 1955: Kolomiets and Gorunova revealed semiconducting properties of chalcogenide glasses.[16][17] September 1966: Stanford Ovshinsky files first patent on phase change technology January 1969: Charles H. Sie published a dissertation at Iowa State University on chalcogenide phase change memory device
June 1969: US Patent 3,448,302 (D. J. Shanefield) licensed to Ovshinsky claims first reliable operation of PCM device September 1970: Gordon Moore publishes research in Electronics Magazine June 1999: Ovonyx joint venture is formed to commercialize PRAM technology November 1999: Lockheed Martin works with Ovonyx on PRAM for space applications February 2000: Intel invests in Ovonyx, licenses technology December 2000: ST Microelectronics licenses PRAM technology from Ovonyx March 2002: Macronix files a patent application for transistor-less PRAM July 2003: Samsung begins work on PRAM technology 2003 through 2005: PRAM-related patent applications filed by Toshiba, Hitachi, Macronix, Renesas, Elpida, Sony, Matsushita, Mitsubishi, Infineon and more August 2004: Nanochip licenses PRAM technology from Ovonyx for use in MEMS probe storage August 2004: Samsung announces successful 64 Mbit PRAM array February 2005: Elpida licenses PRAM technology from Ovonyx September 2005: Samsung announces successful 256 Mbit PRAM array, touts 400 A programming current October 2005: Intel increases investment in Ovonyx December 2005; Hitachi and Renesas announce 1.5 V PRAM with 100 A programming current December 2005: Samsung licenses PRAM technology from Ovonyx July 2006: BAE Systems begins selling the first commercial PRAM, a Radiation Hardened C-RAM 512Kx8 chip September 2006: Samsung announces 512 Mbit PRAM device October 2006: Intel and STMicroelectronics show a 128 Mbit PRAM chip December 2006: IBM Research Labs demonstrate a prototype 3 by 20 nanometers[18] January 2007: Qimonda licenses PRAM technology from Ovonyx April 2007: Intel's chief technology officer Justin Rattner is set to give the first public demonstration of the company's PRAM (phase-change RAM) technology [19] October 2007: Hynix begins pursuing PRAM by licensing Ovonyx' technology February 2008: Intel and STMicroelectronics announce four-state MLC PRAM[6] and begin shipping samples to customers.[12] December 2008: Numonyx announces mass production 128 Mbit PCM device to selected customer. June 2009: Samsung's phase change RAM will go into mass production starting in June[20] September 2009: Samsung announces mass production start of 512 Mbit PRAM device[21] October 2009: Intel and Numonyx announce they have found a way to stack phase change memory arrays on one die[22] December 2009: Numonyx announces 1 Gb 45 nm product[23]
April 2010: Numonyx releases Omneo PCM Series (P8P and P5Q), both in 90 nm.[24] April 2010: Samsung releases 512Mbit PCM with 65 nm process, in Multi-ChipPackage.[25]
[edit] References
1. ^ "Memory Devices Using Bistable Resistivity in Amorphous As-Te-Ge Films" C. H. Sie, PhD dissertation, Iowa State University, Proquest/UMI publication #69-20670, January 1969 2. ^ "Chalcogenide Glass Bistable Resistivity Memory" C.H. Sie, A.V. Pohm, P. Uttecht, A. Kao and R. Agrawal, IEEE, MAG-6, 592, September 1970 3. ^ "Electric-Field Induced Filament Formation in As-Te-Ge Semiconductor" C.H. Sie, R. Uttecht, H. Stevenson, J. D. Griener and K. Raghavan , Journal of Non-Crystalline Solids, 2, 358-370,1970 4. ^ "Is NAND flash memory a dying technology?". Techworld. http://features.techworld.com/storage/3211959/is-nand-flash-memory-a-dying-technology/. Retrieved 2010-02-04. 5. ^ H. Horii et al.,2003 Symposium on VLSI Technology, 177-178 (2003). 6. ^ a b c A Memory Breakthrough, Kate Greene, Technology Review, 04-Feb-2008 7. ^ [1], Toward the Ultimate Limit of Phase Change in Ge2Sb2Te5 8. ^ Intel to Sample Phase Change Memory This Year 9. ^ Pirovano, A. Redaelli, A. Pellizzer, F. Ottogalli, F. Tosi, M. Ielmini, D. Lacaita, A.L. Bez, R. Reliability study of phase-change nonvolatile memories. IEEE Transactions on Device and Materials Reliability. Sept. 2004, vol 4, issue 3, pp. 422427. ISSN 1530-4388. 10.^ SAMSUNG Introduces the Next Generation of Nonvolatile Memory - PRAM 11.^ Intel Previews Potential Replacement for Flash 12.^ a b "Intel, STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes". Numonyx. 2008-02-06. Archived from the original on 2008-06-09. http://web.archive.org/web/20080609215913/http://www.numonyx.com/enUS/About/PressRoom/Releases/Pages/IntelSTDeliverFirstPCMPrototypes.aspx. Retrieved 2008-08-15. 13.^ "Samsung to ship MCP with phase-change". EE Times. 2010-04-28. http://www.eetimes.com/showArticle.jhtml;jsessionid=AZ0IF3RVEBPQVQE1GHPSKHWA TMY32JVN?articleID=224700051. Retrieved 2010-05-03. 14.^ "IBM develops 'instantaneous' memory, 100x faster than flash". engadget. 2011-06-30. http://www.engadget.com/2011/06/30/embargo-ibm-develops-instantaneous-memory-100xfaster-than-fl/. Retrieved 2011-06-30. 15.^ D. Ielmini et al., IEEE Trans. Electron Dev. vol. 54, 308-315 (2007). 16.^ Physica Status Solidi, vol.7, p.359, 1964. 17.^ Physica Status Solidi, vol.7, p.713, 1964. 18.^ Phase Change to Replace Flash? 19.^ Techworld.com - Intel set for first public demo of PRAM 20.^ Engadget Samsung PRAM chips go into mass production 21.^ Samsung moves phase-change memory to production 22.^ Intel and Numonyx Achieve Research Milestone with Stacked, Cross Point Phase Change Memory Technology
23.^ Numonyx to Present Phase Change Memory Research Results at Leading Technology Industry Conference 24.^ Numonyx new PCM devices 25.^ Samsung Ships Industrys First MCP with a PRAM chip for handsets
[edit] External links

Numonyx Ovonyx, Inc. Energy Conversion Devices, Inc. Hitachi/Renesas Low-Power PRAM Hewlett-Packard Probe Storage European\Phase Change and Ovonics Symposium BAE C-RAM Radiation-Hardened NVM press release BAE C-RAM Radiation-Hardened NVM data sheet Introduction to PCM by Numonyx (video) [show]v d eEmerging technologies List of emerging technologies Technology F i Agriculture e l d s Biotechnology and healthcare Agricultural robot In vitro meat Genetically modified food Precision agriculture Vertical farming Ampakine Cryonics Full genome sequencing Genetic engineering (Gene therapy) Personalized medicine Regenerative medicine (Stem cell treatments Tissue engineering) Robotic surgery Strategies for Engineered Negligible Senescence Suspended animation Synthetic biology (Synthetic genomics) Whole-body transplant (Head transplant Isolated brain) Electroencephalography Mind uploading (Brain-reading Neuroinformatics) Neuroprosthetics (Bionic eye Brain implant
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Phase Change Memory: A new memory technology to enable new memory usage models
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By Sean Eilert, Principal Engineer, Numonyx Inc. | Tuesday, January 26, 2010 HotSearch
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Todays advanced applications are creating an insatiable appetite for memory - driving the demand for new memory technology capabilities. As the market for more compact, more powerful electronic systems grows, designers are under increasing pressure to find new ways to fit the volume of code and data needed onto these shrinking devices. Phase Change Memory (PCM) meets these growing density, bandwidth, and scalability needs. Density - With the convergence of consumer, computer and communication electronic systems, an exponential growth of code, and even faster growth of data, is occurring in all electronic systems. To accommodate this growth, memory density ranges must not only meet current needs but must also demonstrate the ability to scale to larger densities as required over time. Bandwidth - In high-level convergent electronic systems, performance is measured in terms of bandwidth, to speed up Internet connections, to reduce power consumption, to enhance mobile use.The memory system design must support the increasing requirements of
bandwidth and reduced power consumption. Subsystem architecture - A key challenge for embedded systems designers, memory parameters such as density, performance, packaging and interfaces all play a significant role in system-level performance. With the variety of memory types available to the system designer, it is viable to partition the memory subsystem according to the specific needs of the higher-level system and application components. In some cases, caching is a reasonable approach to achieve an appropriate balance of performance, power and cost. Scalability - System designers continue to face significant challenges to design reliable embedded and storage systems based on flash memory. With each new generation, the capabilities of existing memory technologies degrade, requiring significant system-level changes to maintain reliability and performance. Both NOR and NAND flash rely on memory structures that become increasingly difficult to shrink at smaller lithographies. PCM, however, is based on a physical state change of a chalcogenide material, commonly referred to as GST. Chalcogenide films have already been proven to have stable characteristics to a 5nm node1. As the PCM memory cell shrinks, the volume of GST material involved in the state change shrinks resulting in reduced power consumption or higher write performance. PCM in Embedded Systems A common use of memory in an embedded system is for code storage. Systems requiring a relatively small amount of memory, less than approximately 2Gb, are architected such that code is executed directly from the NOR flash (XiP). This memory is often used as storage memory for an embedded file system. DRAM is often used in these types of systems as a scratchpad memory. In these types of systems, PCM can be used as a code execution memory. With its bitalterable feature, PCM is able to displace some or all of the DRAM required in the system. (See Figure 1) In SnD memory systems, PCM can reduce the density requirements for DRAM while fulfilling the density requirement of the NAND flash. At the same time, the presence of PCM in this type of system simplifies and improves the performance of file systems stored in the PCM due to the bit-alterability and low latency features.
PCM in Wireless Systems The low-read latencies and fast memory overwrite capabilities of PCM also make it an ideal non-volatile XiP solution that scales from low- to high-density wireless solutions. It is
common to find nearly independent subsystems for baseband and application processing in wireless systems. At the highest level, these can be considered independent embedded systems. Generally speaking, both subsystems have the need for a resident execution memory and for storage of small data structures. In many cases, the applications subsystem is also expected to store and perform operations on larger multimedia content. (See Figure 2) With read latencies that are slower but on the same order of magnitude as the latencies of DRAM, albeit on smaller page sizes, PCM serves as an outstanding code execution memory and read-mostly memory for all but the most frequently manipulated data structures. The bitalterability of PCM eliminates the need for block erase, which reduces the DRAM requirements even further, resulting in a lower cost memory subsystem.
PCM in solid state storage subsystems PCM can be used in SSD systems to store frequently accessed pages and to store those elements which are more easily managed when manipulated in place. Examples of these types of elements include: parity bits for data stored in NAND, bad block tables, and block and page mapping tables. In this scenario, a small amount of PCM could be used to enhance the manageability of NAND. (See Figure 3) By minimizing the stress on the NAND memory, higher density MLC NAND is enabled, thus leveraging the capability of PCM to lower the cost of the NAND flash in the subsystem. This caching with PCM will improve the performance and reliability of the subsystem. Additionally, when erased pages are scattered across many blocks (near full state), PCM can provide further reliability improvement. Managing a block-alterable memory in a near-full state implies that multiple erase cycles are likely required to free space to store the new data being written to the device. This increases the number of cycles on the device and further accelerates the time until the maximum endurance limits are reached. The bit-alterable nature of PCM solves the issue of increased write cycles when the device is full. Higher endurance of PCM addresses the needs of these systems when heavy use is expected.
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Interfacial phase-change memory

R. E. Simpson,1 P. Fons,1, 2 A. V. Kolobov,1, 2
T. Fukaya,1 M. Krbal,1 T. Yagi3 & J. Tominaga1 Affiliations Contributions Corresponding authors Journal name: Nature Nanotechnology Year published: (2011) DOI: doi:10.1038/nnano.2011.96 Received 25 March 2011 Accepted 23 May 2011 Published online 03 July 2011
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Phase-change memory technology relies on the electrical and optical properties of certain materials changing substantially when the atomic structure of the material is altered by heating1 or some other excitation process2, 3, 4, 5. For example, switching the composite Ge2Sb2Te5 (GST) alloy from its covalently bonded amorphous phase to its resonantly bonded metastable cubic crystalline phase decreases the resistivity by three orders of magnitude6, and also increases reflectivity across the visible spectrum7, 8. Moreover, phase-change memory based on GST is scalable9, 10, 11, and is therefore a candidate to replace Flash memory for non-volatile data storage applications. The energy needed to switch between the two phases depends on the intrinsic properties of the phase-change material and the device architecture; this energy is usually supplied by laser or electrical pulses1, 6. The switching energy for GST can be reduced by limiting the movement of the atoms to a single dimension, thus substantially reducing the entropic losses associated with the phase-change process12, 13. In particular, aligning the c-axis of a hexagonal Sb2Te3 layer and the 111 direction of a cubic GeTe layer in a superlattice structure creates a material in which Ge atoms can switch between octahedral sites and lower-coordination sites at the interface of the superlattice layers. Here we demonstrate GeTe/Sb2Te3 interfacial phase-change memory (IPCM) data storage devices with reduced switching energies, improved write-erase cycle lifetimes and faster switching speeds. Figures at a glance left
1. Figure 1: Optical pumpprobe testing of IPCM switching behaviour.
a, High-resolution transmission electron micrograph TEM image of a typical as-grown (GeTe)2(Sb2Te3)4 interfacial phase-change material on silicon. The (GeTe)2 layers are 1 nm thick, and the (Sb2Te3)4 layers are 4 nm thick. b, Time-resolved pumpprobe static tester measurement for the RESET to SET transition process of a 400-nm-radius laser RESET mark in the IPCM film. The RESET mark was created with a laser pulse with a duration of 40 ns and a power of 32 mW. The normalized optical transmission of a 100 W probe beam through the RESET mark is plotted as a function of time during and after the 100 ns laser pump pulse for varying incident optical powers. Four regions can be discerned: (i) no change in transmission, (ii) a reduction in transmission (indicative of a transition from the RESET state to the SET state), (iii) a slight increase followed by a reduction in transmission (indicative of melting then subsequent crystallization into the SET state), and (iv) an increase in transmission (indicative of melting then partial ablation). c, Re-crystallized fraction of the 400-nm-radius RESET mark (created with a 40 ns, 32 mW laser pre-pulse) as a function of time for GST (100 ns, 9.5 mW pump pulses; black); IPCM (100 ns, 9.5 mW pump pulses; red); IPCM (25 ns, 16.5 mW pump pulses; blue), respectively.
2. Figure 2: Electrical switching characteristics of IPCM devices.
a, Plots of resistance versus current for PCRAM devices in the first cycle (upper panel) and after 1 106 cycles (lower panel). Filled squares are from a device fabricated from a single GST target, and filled circles are for a device containing a (GeTe)4(Sb2Te3)2 IPCM. The SET pulse lengths were 50 ns
and 100 ns for the IPCM and GST materials, respectively. The RESET pulse length was fixed at 50 ns for both the IPCM- and GST- based devices. b, Maximum number of SETRESET cycles plotted as a function of phase-change material thickness. The cyclability of phase-change memory cells based on the GST material shows a strong dependence on film thickness (black circles), whereas the cyclability of the IPCM (red triangles) based on repeated blocks of (GeTe)2(Sb2Te3)2 shows little sensitivity to total film thickness. Dashed lines have been included to guide the eye.
3. Figure 3: Analysis of the RESET state.

a, TEM images of a (GeTe)2(Sb2Te3)4 IPCM structure in the RESET state after 1 103 SETRESET cycles. In contrast to GST, the TEM image shows that there is no amorphous region surrounding the TiN heating electrode. be, High-resolution TEM images (top) and SAD patterns (bottom) for the four regions inside the coloured squares in a. The layered IPCM structure and associated superlattice diffraction spots are clearly visible in all images. f, Selective area electron diffraction pattern of the whole IPCM structure. The white concentric rings originate from the TiN electrodes. g, DFT calculations of the inter-planar distances in (GeTe)2(Sb2Te3)4 (left column) are in good agreement with the distances determined from the diffraction pattern. h, Model used in DFT calculations: Ge, Sb and Te atoms are coloured green, purple and orange, respectively. i, An IPCM device that was deliberately RESET with the same high-power pulse conditions required by GST. As with GST, a melt-amorphized dome is formed above the TiN heater, resulting in destruction of the superlattice structure and irreversible damage to the IPCM device. right
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Affiliations 1. Nanoelectronics Research Institute, National Institute of Applied Industrial Science and Technology, Tsukuba Central 4, 1-1-1 Higashi, Tsukuba 305-8562, Japan R. E. Simpson, P. Fons, A. V. Kolobov, T. Fukaya, M. Krbal & J. Tominaga
2. SPring-8, Japan Synchrotron Radiation Research Institute (JASRI), Mikazuki Hyogo 679-5198, Japan P. Fons & A. V. Kolobov
3. National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Tsukuba Central 3, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8563, Japan T. Yagi Contributions J.T. conceived and designed the entropy controlled interfacial phase-change memory structures. J.T., R.E.S. and T.Y. performed the experiments. R.E.S. wrote the paper. All authors analysed the results and contributed to the discussion presented in the manuscript. Competing financial interests The authors declare no competing financial interests. Corresponding authors Correspondence to:
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IBM boffins claim phase change memory breakthrough

Catch my drift
By Timothy Prickett Morgan Get more from this author
Posted in PCs & Chips, 30th June 2011 04:26 GMT
Fast and reliable non-volatile memory of some sort that will replace flash memory is the dream of more than a few semiconductor researchers and chip makers. And boffins at IBM Research in Zurich, Switzerland, think they have come up with a new encoding technique that will allow for multi-level cell (MLC) phase change memory to be commercialized at some point in the not too distant future. Phase change memory is based on an interesting goop called chalcogenide compounds, which are used in rewriteable CD, DVD, and Blu-Ray disks. These chalcogenide compounds have a polycrystalline state as well as an amorphous state, and the state can be changed with the application of a laser beam or an electric current, both of which heat the material to change it from crystal to amorphous state, allowing for the encoding of the 1s and 0s of binary data in spots on the compound. The interesting thing about chalcogenide compounds, explains Haris Pozidis, who worked at Philips Research on encoding techniques for rewritable DVDs and Blu-Rays before joining IBM Research in 2001, is that these compounds have a very high contrast between their states two or three orders of magnitude, in fact, ranging from tens of kilo-ohms to tens of mega-ohms. This wide range allows, in theory, for data to be stored in multiple phases in the chalcogenide structure, just like multi-level cell (MLC) flash does today. There's only one problem. The resistance in the chalcogenide compound will drift over time, and it does so randomly, and that is a bad, bad thing for storage media to do. To further complicate things, the amorphous state drifts more over time than the crystalline state, since it is trying to get into a crystalline state. So you have two sets of drifts you need to cope with if you want to go multi-level with PCM memory.
IBM Research's experimental PCM chip What IBM's boffins have figured out, as you can read in a paper published today (PDF), is that even though the resistance drift is random in PCM crystals, the drift moves in the same general direction in subsets of the PCM memory the state of chunks of the chalcogenide compound affects the state of the chunks around it, as weather moves through the atmosphere. And the trick that IBM Research has come up with is a clever algorithm that allows for the data to be encoded in the chalcogenide compound and then to read the data in a relative fashion for blocks of data. "The absolute resistance levels in the chalcogenide can have nothing to do with their original encoded levels," says Pozidis, but the data is still not lost. The bit error rate is below 1 in 10,000 using a two-level cell PCM chip, which is well within the realm of error detection and correction. And, perhaps more importantly, the gap between the amorphous and crystalline levels in the chalcogenide is wide enough that IBM believes it will be able to do three or four levels of encoding.
DRAM vs flash vs phase change memory (click to enlarge) Current MLC flash memory encodes three bits per cell and it is this multi-level encoding that makes it affordable as relatively cheap non-volatile storage. However, consumer flash memory degrades after 3,000 to 5,000 cycles, and flash deteriorates exponentially with the number of read and write cycles. Even enterprise-grade flash memory is only good for 30,000 cycles or so, says Pozidis, and to get that high reliability, you have to sacrifice performance. PCM memory, by contrast, has the ability to handle hundreds of millions of cycles and will be something like two orders of magnitude faster than flash. There is a bit of research that needs to be done before PCM can be commercialized, of course. But the fact that IBM's boffins have been able to show that a two-level PCM memory chip operating at room temperature could be read after 156 days using an algorithm that was two orders of magnitude more robust than prior decoding methods is a step in the right direction.
June 06, 2011
Researchers Challenge NAND Flash with Phase Change Memory

Michael Feldman A team of researchers at the University of California, San Diego (UCSD) has built a solid state storage system that they claim outperforms state-of-the-art flash memory products. The new system, know as Moneta, uses phase change memory, a technology that some predict will replace the NAND flash memory used in nearly every solid state drive (SSD) today. The UCSD prototype will be on display this week at the Design Automation Conference in San Diego.
Moneta, which is the Latin name for the goddess of memory, uses phase change memory (PCM) module from Micron Technology as the storage medium and employs Xilinx FPGAs as memory controllers. The system DIMM, referred to as Onyx, is a 640 MB device made up of 40 of Micron's 16 MB PCM (P8P) chips.* The entire system houses 16 of these DIMMs, yielding 10 GB of raw storage: 8 GB usable and 2 GB for error correction and metadata. The card connects to a Linux host via a PCIe x8 link. The prototype and its performance characteristics are described in detail here. Like NAND flash memory, phase change memory is non-volatile, but it's a total different digital animal. PCM is based on a metal alloy called chalcogenide and works, as its name suggests, by changing the state of the alloy. To write data, electrical current is applied to generate heat, which switches the alloy between its crystalline and its amorphous state. To read the data back, a smaller current is applied to determine which state the alloy is in. PCM has several significant advantages over NAND. To begin with, it is inherently more robust than NAND, having an average endurance of 100,000,000 write cycles as compared to 100,000 for enterprise-class SLC NAND. That means the wear leveling algorithm can be much simpler, resulting in less software and memory overhead. PCM is also byte addressable, which means it is much more efficient than NAND at accessing smaller chunks of data, again reducing system complexity. Finally, PCM is just faster. The bits can be switched quickly, and can be flipped in place, avoiding the laborious block erase-and-write cycle required by NAND. A longer term advantage cited for PCM is that it will scale better than NAND (or even DRAM) as process geometries shrink below 20nm. This has yet to be proven, but it has certainly encouraged companies like Micron and Intel to invest heavily in the technology.
The PCM hardware is only half of the Moneta story though. The system's real value is contained in the software, which has been tuned for the higher performing PCM. Specifically, they developed a low-level block driver for Moneta that bypasses the Linux I/O scheduler, such that throughput and latency are optimized. Weve found that you can build a much faster storage device, but in order to really make use of it, you have to change the software that manages it as well. Storage systems have evolved over the last 40 years to cater to disks, and disks are very, very slow, said Steven Swanson, professor of Computer Science and Engineering at UCSD and director of its Non-Volatile Systems Lab (NVSL). Designing storage systems that can fully leverage technologies like PCM requires rethinking almost every aspect of how a computer systems software manages and accesses storage. Moneta gives us a window into the future of what computer storage systems are going to look like, and gives us the opportunity now to rethink how we design computer systems in response. To prove the technology's worth, the UCSD team compared Moneta to a well known NAND flash product, in this case, an 80GB Fusion-io ioDrive. However, being a first-generation prototype, the results are somewhat of a mixed bag. For 512-byte block accesses, Moneta can read data at 327 MB/sec and write at 91 MB/sec; which is between two and seven times faster than the Fusion-io ioDrive. For large data blocks (32K and up), Moneta can read data at 1.1 GB/sec and write data at 371 MB/sec. Here the PCM system is still outrunning the ioDrive for reads, but is actually somewhat slower in writes. The researchers attribute this to the ioDrive's better aggregate bandwidth associated with its larger memory capacity, all of which is optimized for large block sizes. Keep in mind that Fusion-io also offers PCIe flash devices with much more capacity and associated bandwidth than the version the UCSD researchers benchmarked. For example, Fusion-io claims 1.5 GB/sec in both reads and writes for its 320 GB ioDrive Duo with 64K block sizes, and 6.0 GB/sec in reads and 4.4 GB/sec in writes for its giant 5TB ioDrive Octal. Obviously size matters. Other NAND SSD vendors are pushing the capacity/bandwidth envelop as well. Micron's 700GB P320h flash drive delivers 3 GB/sec for reading and 2 GB/sec for writing (128K blocks); the latest 900GB RamSan-70 card for Texas Memory Systems manages 2 GB/sec reads and 1.4 GB/sec writes; and Virident Systems' 800GB tachIOn drive tops out at 1.44 GB/sec and 1.2 GB/sec for reads and writes, respectively. Of course, I/O bandwidth is just a single criteria. Performance under various loads and conditions (like when a drive becomes full) is also important. Cost, latency, longevity, power consumption are other factors that need to be considered. In the case of power consumption, the UCSD researchers point out that because of the less idiosyncratic behavior of PCM compared to NAND, the software driver is simpler, thus there is a reduction in CPU usage. The researchers say that their Moneta prototype spends between 20 and 50 percent less CPU time performing I/O operations for small requests. That frees up the CPU to do application work and reduces the overall power consumption of the storage system. The bottom line is that if Moneta can be scaled up to larger memory capacities and aggregate bandwidth on a single PCIe device, its natural advantage in read performance, small (i.e., random) write performance, and endurance will give the NAND-based SSD makers something to think about. The UCSD researchers contend that a PCM-based storage system will be of particular value in applications like high-performance caching systems and keyvalue stores, that require high performance reads and small writes. For example, applications that do a lot of random I/O, like large graph computations, are especially suited to Monetatype architectures.
The UCSD team plans to upgrade Moneta in the next six to nine months, using denser and higher performing PCM devices. No PCM roadmap from Micron or anyone else has been made public, but the researchers say that the Moneta technology could be commercially available in just a few years.
Better insulation makes phase-change memory work faster, more efficiently

June 9, 2011 By Lee Swee Heng
article comments (0) share 2 inShare5
Share to facebook Reddit Google Delicious Slashdot Yahoo! bookmarks Windows Live RSS QR code Enlarge A schematic illustration of a phase-change memory element incorporating a superlattice-like dielectric.
The perfect data storage solution should offer fast access to data, maintain data in the absence of external power, and be able to withstand large numbers of readwrite cycles. Phase-change random access memory (PCRAM), a type of nonvolatile memory that uses the amorphous and crystalline states of phase-change materials for encoding data, can satisfy all of these criteria. Unfortunately, PCRAM also tends to have impractically high power requirements that have impeded its application in many devices. Desmond Loke and co-workers at the A*STAR Data Storage Institute have now demonstrated a technology that could help reduce the power requirements of PCRAM.
IBM DEMOS PHASE CHANGE MEMORY THAT RELIABLY PACKS MULTIPLE DATA BITS INTO SINGLE CELLS
By Clay Dillow Posted 06.30.2011 at 1:17 pm 6 Comments
The Beginning of the End of Flash? Flash has been good to us, but IBM is making strides with phase change memory technology that could someday replace flash as the non-volatile memory of choice. DandyDanny via Flickr IBM researchers in Zurich--working alongside their stateside colleagues--have demonstrated for the first time that phase change memory (PCM) can reliably store multiple data bits per cell over long periods of time. By tweaking their read and write processes to mitigate problems that have dogged PCM for years, the breakthrough could spell the beginning of a long, slow phase out of flash in everything from mobile devices to cloud storage. Like flash, PCM is a non-volatile memory technology. But PCM has the potential to blow flash performance out of the water. PCM could boost overall performance of backbone IT systems by orders of magnitude. Computers could boot instantaneously. The cloud could grow at rates that might actually keep up with all the stuff were shoveling into the cloud.
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Technology, Clay Dillow, computers, COMPUTING, flash memory, memory, memory chips, phase change memory But phase change memory isnt the simplest nut to crack (for fuller explanations of how it works, click through the link below. Or try Wikipedia). Simply put, PCM takes advantage of the change in resistance that takes place when a material changes phases, in this case from a crystalline structure to an amorphous one. Crystalline structures exhibit high resistance and amorphous low resistance. This range of resistance allows computer scientists to store more than one bit per memory cell, hence the huge jump in memory and performance. So in the IBM research to which we refer, scientists were able to store the bit combos 00, 01, 10, and 11 in four distinct resistance levels of a single bit. Its like a four-for-one deal. The problem with PCM is that the resistance in the amorphous state tends to drift, rising over time and leading to read errors. Thats the real problem that was solved here: IBMs novel read/write processes, rather than restricting resistance drift, are now coding in a drift-tolerant way. If the resistance shifts, its no big deal; the PCMs long-term retention of usable, retrievable data is still solid. This demo has been going on successfully for five months, long enough that IBM feels confident that it has a solution that really can hold data in PCM for extended periods. Of course research is ongoing, but if it proves as reliable as this first demo suggests, PCM could potentially become as ubiquitous as flash is today, doing a whole lot more with a lot less space.
Phase Change Memory Trends March 2011

Phase change memories are expected to be used in disk caches in servers, in hybrid nonvolatile memory caches and Flash file systems. They can replace NOR flash in code applications. They are potentially useful as memory in portable smart systems, in industrial systems and smart metering. Several companies have shown integrated process technologies for phase change memory in technologies ranging from 90 nm to 45 nm. Since the PCM is a new technology there are several issues still being addressed such as: resistance drift in the amorphous state in multilevel cells, thermal program disturb of neighboring cells in the RESET state, stability of the PCM at high temperatures using GeTe and inclusions for improved temperature stability, endurance failures due to electromigration and voids in the PCM element, data loss from the amorphous state, reducing write current, and oscillatory behavior due to noise in the amorphous state. Phase Change memories using BJT access devices have been described as have PCM in cross-point cells with scaled diode switches. A number of novel material combinations are being explored for PCM including different percentages of Ge Sb and Te, and the use of GeTe in a PCM cell for high temperature improvement. Multilevel phase change memories have been explored for effects such as resistance drift and effect of doping and type of select device. A significant amount of modeling and reliability characterization is still ongoing for PCM. Designs with various circuits for the PCM have been discussed. Several advanced processes such as superlattices, alloys and epitaxies have been shown. System level reliability was addressed Vendors and developers are noted in the last section. 115+ pages. Overview | Purchase Table of Contents - Phase Change Memory Trends , March 2011 1.0 Overview of Phase Change Memory and Its Characteristics 2.0 Applications For Phase Change Memory 2.1 Main Memory System Using PC-RAM (Penn State University) 2.2 Computing Platforms 2.3 Using Phase-Change Memory in Caches 2.3.1 A Low Power, High Endurance PCM Cache 2.3.2 Using PCM in a as Disk Cache in Servers (University of Michigan) 2.3.3 Hybrid Non-Volatile Memory Caches including MRAM, PC-RAM and SRAM(IBM) 2.4 Flash File System Based on Hybrid Architecture of PCM and NAND(KAIST) 2.5 Including PCM in Stacked TSV DRAM and MPU Systems (Univ. of Florida) 2.6 PC-RAM as NOR Flash Memory Replacement 2.7 Air, Military and Space Applications (BAE Systems) 2.8 Automotive and Consumer Applications (CEA/LETI-Minatec)
2.9 PC-RAM and DRAM Hybrid in Main Memory Architecture in Computing Systems 2.10 Low Power Smart Portable Handheld Systems 2.11 Industrial and Embedded Applications 2.12 Solid State Storage Subsystems 2.13 Set-Top Boxes 2.14 Smart Metering 3.1 Basic Operation of Phase Change Memory 3.2 Cell Sizes vs. Technology for Phase Change Memory 3.3 Overview of PCM Technology Roadmap 3.4 PCM Scaling Trends 3.5 Scaling Behavior of GST Technology 4.1 4-Mb 1T1R GST ePCM in 90 nm CMOS (STMicro, Numonyx) 4.2 Embedded PCRAM in 65 nm CMOS Technology (NXP-TSMC) 4.3 Fast sub-20 nm Dash Confined Cell PRAM (Samsung) 4.4 1-Gb PCM in 45 nm CMOS Technology (Numonyx) 4.5 Integrated PCM Process Module Embedded in 90 nm 6ML CMOS (STM, Numonyx) 4.6 60 nm 512-Mb PCM Technology (Samsung) 5.1 Resistance Drift Due to Structural Relaxation in Amorphous State 5.1.1 Effect of Resistance Drift on Multi-Level PCM Design 5.1.2 Time-Aware Fault Tolerance Reliability of MCL PCM with Resistance Drift (Marvell) 5.1.3 Time Aware Memory Sensing for Resistance Drift Issues (Rensselaer Institute) 5.1.4 Characterization of Resistance Drift in Amorphous GST (U. of Pennsylvania) 5.1.5 Structural Relaxation in the Amorphous State of a MLC PCM (Polit. di Milano) 5.1.6 Study of Resistance Drift and Its Dependence on Temperature (Politecnico di Milano) 5.1.7 Characterization of Structural Relaxation in Amorphous PCMs (Politech. di Milano)
3.0 Technology Overview for the Phase Change Memory
4.0 Integrated Process Technologies For Phase Change Memory
5.0 Issues for Phase Change Memory
5.2 Thermal Programming Disturb 5.2.1 Thermal Programming Disturb of Neighboring Cell in RESET State (Hynix)
5.2.2 Impact of Thermal Disturbance on PCM Reliability(Stanford U&NXPTSMCRes.Ctr) 5.3 Stability of PCM at High Temperatures 5.3.1 GST PCM Alloys with SiO2 Inclusions for Improved Temperature Stability(Ovonyx) 5.3.2. PCM with High Temperature Endurance (Nat. Tsing Hua U., Feng Chia U.) 5.3.3 Stability at Varying Temperature of PCM Using Ge doped SbTe (KIST) 5.3.4 Refresh to improve Endurance at High Temperatures of Ge2Sb2Te5 (Numonyx) 5.3.5 Variation of PCM Device Parameters with Ambient Temperature (KIST) 5.4 Endurance Failure Caused by Electromigration During SET. 5.4.1 Endurance Failure from Electromigration in Asymmetric GST PCM (Macronix, IBM) 5.4.2 Voltage Polarity Effects in GST PCM (IBM) 5.4.3 Electromigration in Molten/Crystalline GST Under High Field (Seoul Nat. Univ.) 5.4.4 SET Stuck Failure in GST Phase Change Memory (KIST) 5.4.5 Doping to Reduce Void Failure in GST Programming Volume (IBM, Macronix) 5.4.6 Phase Separation in Ge2Sb2Te5 Due to High Electrical Stress (Samsung) 5.5 Data Loss from the Amorphous (RESET) State of the Phase Change Memory 5.5.1 Multiple Amorphous States for Undoped Ge15Sb85 Bridge PCM (Aachen Univ.) 5.5.2 Observations of Slow Quenching Crystallization Behavior(Samsung, U. of Texas) 5.5.3 Parasitic Crystal Path in SET Related to Anomalous Tail Bits in RESET(UdiFerrara) 5.6 Reducing Write Current in Phase Change Memory 5.6.1 Reducing Thermal Conductivity in PCM to Reduce Programming Current (Samsung) 5.6.2 Lower RESET Current Using TiO2 Insert in Confined GST PCM (U. Khon Kaen) 5.7 Oscillatory Behavior (Noise Fluctuations) in an Amorphous State PCM 5.7.1 Current Fluctuation Effects of Scaled PCM (Politecnico di Milano) 5.7.2 Low Frequency Noise in Amorphous State of PCM (Numonyx) 5.7.3 Relaxation Oscillation Study of GST PCM Devices (University of Toledo) 5.8 Dynamic Resistance of the PCM Cell
5.8.1 Measurements of Dynamic Resistance of the PCM Cell (IBM, Macronix) 6.0 Characterization of the SET Operation in PC Memories 6.1 Effect of Cycling on the SET State of a high capacity PCM (D. degli Studi di Ferrara) 6.2 Analysis of PCM Transient Current Waveform During Crystallization (A*STAR) 6.3 MicroStructural Evolution of Slow Quenching Crystallization (U. of Texas, Samsung) 7.1 Effect of BJT-PCM Scaling on Reliability and Functionality to 16 nm (Numonyx) 7.2 Comparison of MOS and BJT Selectors for PCM (Numonyx) 7.3 Two Bipolar Transistor and Two PC Device Cell Structure PCM (Fudan U.) 7.4 Vertical BJT Access Device in 180 nm Technology (IBM, Macronix) 7.5 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia) 8.1 MIEC Access Devices for 3D Stacked Crosspoint Arrays (IBM) 8.2 Stacking PCM in Cross-Point Array with Ovonic Threshold Switch (Intel, Numonyx) 8.3 Cross-Point PCM Using Polysilicon Selection Diode (Hitachi) 8.4 Cross-Point Array Using p-GST to n-Si Heterojunction Diodes (Fudan Univ.) 8.5 Circuit and Design of Scaled Diode Switch PCM (Rensselaer Polytechnical Institute) 9.1 Super-Lattice Dielectric of GST and SiO2 for PCM Dielectric (NUS) 9.2 Characteristics of PCM Devices Made with MOCVD GST 325 alloy (Ovonyx) 9.3 Using Silicides for the Bottom Electrode/Heater of a Phase Change Memory (NUS) 9.4 Characteristics of (InTe)x(GeTe) Thin Films for PRAM Applications(Chonnam Nat.U) 9.5 Performance Improvement of a CeO2 Buffer Layer in a PCM Cell (Tongji U.) 9.6 Thermal Conductivity of Ge1Sb4Te7 & N-doped Ge1Sb4Te7 thin films (Yonsei U.) 9.7 Effect of Indium in SbTe on PCM Characteristics (Yonsei U.) 9.8 PCM Electrical Characteristics Using Ga3Te2Sb12 & Ge2Sb2Te5(Nat. Tshing Hua U) 9.9 Properties of Te-less, Sb-Rich GaSb PCM (Nat. Tsing Hua Univ.) 9.10 Carbon Nanotube Heaters with < 5 nm Diameter for GST PCM (Univ. of Illinois) 9.11 Evolution of Band Gap & Fermi Level with Annealing Temp of Ge1Sb2Te4(AachenU)
7.0 Phase Change Memory Using BJT Access Devices
8.0 Phase Change Memory Cross-Point Cells with Scaled Two-Terminal Switches
9.0 Novel Materials Combinations for Phase Change Memory Cells
9.12 Advantage of Ge21Sn10Sb15Te54 (GSST) for MLC PCM (ITRI) 9.13 Study of Ge15Te83Si2 for Use in Phase Change Memories (Indian Institute of Science) 9.14 Phase-Change Memories Using Gallium-Doped Indium Oxide (National Taiwan U.) 9.15 Using GeTe Materials in Phase Change Memory 9.15.1 N-Doped GeTe for Performance in ePCM(CEA-LETI,STM,LTMCNRS,dStudidiPavia) 9.15.2 Electrical Behavior of GeTe PCM Cell (CEA-LETI, STMicroelectronics) 9.15.3 Investigation of Properties of GeTeC Alloy for Using in PCM (CEALETI MINATEC) 9.15.4 Crystal growth rate of GeTe PCM Devices and Switchable Volume (Aachen Univ.) 9.15.5 A GeTe and Sb7Te3 SuperLattice Structure PCM to reduce RESET Current(A*STAR) 9.15.6 Data Retention Improvement at High Temp. Using GeTe (CEA/LETIMinatec)
10.0 Multi-Level Phase Change Memory Operation 10.1 Analysis of Noise in Multi-bit PCM (IBM) 10.2 Multilevel PCM Using Stacked CVD GET and ALD TiO2 thin Films (Seoul Nat. U.) 10.3 45 nm 2-bit/cell MLC PRAM (Samsung) 10.4 Effect of Resistance Drift on Multi-Level PCM Design (Nat. Ilan U.) 10.5 Multilayer Multilevel Lateral PCM Using N-doped Sb70Te20 (A*STAR) 10.6 Multi-Level Storage in Double-Layered TiSiN/GeSbTe PCM (Gunma Univ.) 10.7 Characterizing a PCM Cell Programmed to Intermediate Resistance Levels (IBM) 10.8 Methodologies for Multilevel Programming of PCM (Univ. of Pavia) 10.9 Parallel Multi-Confined PCM Cell for Multi-Level Operation (Samsung) 10.10 Drift During ML Storage Dependence on Amorphous Capacitor Thickness(Uof Pavia) 10.11 90 nm 128-Mb PCM with BJT and Multilevel Storage (Numonyx, STM, U. of Pavia) 10.12 Effect of N-Type Doping on Power and Multi-Level Properties in a PCM (Gunma U.) 11.1 Modeling of PCM Resistance Temp. & Time Dependency(Polit. di Milano, IFNCNR) 11.2 Transient Model for Threshold Switching of Amorphous PCM (Politecnico di Milano)
11.0 Modeling of Phase Change Memory
11.3 Amorphous GST Model for RESET Readout I Distribution(Numonyx, Polit.Milano) 11.4 Model of the Erase Operation in Phase Change Memories (Univ. of Ferrara) 11.5 Conduction Model for Amorphous Phase of PCM (Politecnico di Milano) 11.6 Model of Electrical Conduction Due to Hopping in Amorphous GST (U. of Bologna) 11.7 Modeling of Amorphous State in Mushroom Type PCM Devices (IBM, Macronix) 11.8 System Level Modeling of The Phase Change RAM (Penn State Univ.) 11.9 Transport Model for Amorphous PCM(U.of Bologna,U.of Modena&Reggio Emilia) 11.10 SPICE-like Statistical Model of Bit Distributions in PCN (Numonyx, Univ. of Pavia) 11.11 Threshold Switching as a Requirement for NV PCM Devices (Aachen Univ.) 11.12 Modeling Approaches for PCM (Politecnico di Milano) 11.13 Model for MLC PCM (University of Pavia) 11.14 Temperature Distribution Model in Cylindrical NanoWire PCM (U. of Illinois) 11.15 SPICE macromodel of Phase Change Memory (National Taiwan University) 11.16 Unified Field Induced Nucleation Model to Describe PCM Switching(Univ.of Toledo) 11.17 Model for use in SPICE Simulation of PCM Circuits (U. of Sci & Tech. Hong Kong) 11.18 Model for Write Speed in MLC Phase Change Memory (Nat. Ilan University) 11.19 Phase Transition Model and Resulting Simulations (Peking University) 12.1 Activation Energy of Crystal Growth in Amorphous Chalcogenide(IMEC, NXP, TSMC) 12.2 Study of phase transition behaviour of GST thin Films for PCRAM (IBM, Macronix) 12.3 Thermoelectric Heating During Programming of PC Memory Cells (Samsung) 12.4 Effect of PCM Technology Scaling on Program and Read (U. of Pavia) 12.5 Effect of Parasitic Capacitance on Programming Performance of PCM (A*STAR) 12.6 Thermal Boundary Resistance Measurements for PCM Devices (Stanford U.) 12.7 Overview of PCM Reliability (Numonyx) 12.8 Metal - GST Interface Characterization (Nat. Univ. of Singapore) 12.9 Crystallization Time of Various Compositions of Ge-Te PC Materials(IBM, Macronix) 12.10 Threshold Current Densities in PCM (Onyx International) 12.11 Effect of ESD on PCM Structures (Univ. of Padova) 12.12 Effect of RESET Parameters on the Final RESET State (IMEC, NXP-TSMC)
12.0 Reliability, Test and Characterization of Phase Change Memory Devices
12.13 Various Programming Techniques for Writing a MLC PCM (Nat. Ilan, Univ.) 12.14 Endurance of an Integrated Phase Change Line Cell (IMEC) 13.1 58 nm 1.8 V 1-Gb PRAM with 6.34 MB/s Program Bandwidth (Samsung) 13.2 4-Mb 90 nm PCM Macro with 1.2V 12 ns Read and 1/MB/s Write(STM, Numonyx) 13.3 Design of 45 nm 1 Gb PCM (Numonyx) 13.4 Design Methodology for A PC-RAM Array (Penn State University) 13.5 Slow Quench Pulse Shaper for SET Mode for PC-RAM (Penn State Univ.) 13.6 Using DACs to Replace Write Drivers in PCM Circuits (Boise State Univ.) 13.7 Four Terminal Phase Change Programmable Switch (ETRI) 14.1 Superlattice Phase Change Memory to Reduce Switching Energy (AIST) 14.2 Solid State Alloying to Form Phase-Change Memory (Hanbat National Univ.) 14.3 Making PCM in the Univ. Environment Using Foundry FEOL CMOS (Boise State U) 14.4 GeSbTe Epitaxy on GaSb(001) Grown at Low Temperature(Inst. for Solid State Elec.) 14.5 Role of Nitrogen During Crystallization of Sb-Rich Phase Change Materials (KIST) 15.1 System Architecture to Reduce Write Internsity in PCM (Penn. State U.) 15.2 In-System Programming of PCM After Surface Mount Process (Micron) 15.3 Using "Read-Modify-Write" to Improve Write Endurance (Univ. of Pittsburgh) 15.4 Technique to Improve Cell-Based Non-Uniformity of Writes in a System (IBM) 15.5 Implications of Process Variations in PCM System Design (Univ. of Florida) 15.6 System Level Modeling for Scaling of PC-RAM (Penn State Univ.)
13.0 Design and Circuits for Phase Change Memories
14.0 Processes for the PC-RAM Cell
15.0 Techniques to Improve PCM System Level Reliability
16.0 Labs, Developers and Vendors of Phase Change and Resistance RAMs
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Phase Change Memory: The Next Big Thing in Data Storage?

February 3, 2010 By Herman Mehling Send Email More Articles
Phase change memory (PCM) an emerging non-volatile technology pioneered by Intel (NASDAQ: INTC), Numonyx, Samsung and others could turn out to be a low-
cost, more reliable, faster, and just plain better alternative to flash memory (see I/O Bottlenecks: Biggest Threat to Data Storage). Some industry insiders even believe PCM has the potential to accelerate the data storage market's slow transition from hard disk drives (HDDs) to solid state drives (SSDs). One of the believers is Ed Doller, the chief technology officer of Numonyx, a joint venture created by Intel and STMicroelectronics. "PCM is a very promising alternative to flash that should allow the industry to continue the transition from HDDs to SSDs with confidence," says Doller.

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Early Days for PCM

However, PCM is still at the fab stage, and the technology faces a number of issues still. When will Numonyx and Samsung (which is developing market specs for PCM products with Numonyx) deliver products in commercial quantities? Will the cost of the products be price-competitive with flash memory?
"With high read/write speeds, low volatility, and high storage density, PCM promises to address NAND's shortcomings as well as the limitations of conventional hard drives," said Richard Tomaszewski, HP's product manager for industry standard servers. "As such, some believe PCM will be the next technology after NAND for flash memory."
However, Tomaszewski said there are other interesting non-volatile memory technologies including Resistive RAM (RRAM) and Spin torque transfer RAM (STTRAM) that could prove to be viable alternatives. "These technologies still need further testing and development to demonstrate whether they will be viable," said Tomaszewski. "High volume with high yields with multiple sources producing components is key to a successful technology transition."
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To displace an existing technology, Tomaszewski said, a new one must be equal or better in terms of reliability, endurance and service life. He said a new technology takes several years from fab to production to get to sufficient volumes to reach large-scale viability and meet reliability and endurance expectations.
What Exactly Is Phase Change Memory?

PCM offers high performance and low power consumption, combining the best attributes of NOR, NAND and RAM within a single chip, said Doller.
He said those attributes are: bit-alterable; non-volatile; fast read speed; fast write/erase speed; and good scalability. Bit alterable: Similar to RAM or EEPROM, PCM is bit-alterable meaning that stored information can be switched from one to zero, or zero to one, without a separate erase step. Flash memory technology requires a separate erase step in order to change information. Non-volatile: PCM is non-volatile, as are NOR flash and NAND flash. PCM does not require a constant power supply to retain information, while RAM does. Read performance: Similar to RAM and NOR flash memory, PCM features fast random access times. This enables the execution of code directly from the memory, without an intermediate copy to RAM. The read latency of PCM is comparable to single bit per cell NOR flash, while the read bandwidth can match DRAM. Write/erase performance: PCM will achieve write throughput speeds faster than NAND and with lower latency. These features, when combined with a no separate erase step (bit-alterable), will deliver significant write performance improvement over NOR and NAND flash.
Scalability: Scaling is another area where PCM offers a difference. Both NOR and NAND rely on floating gate memory structures, which are difficult to shrink. As the memory cell shrinks on flash, the number of electrons stored on the floating gate shrinks. Because PCM does not store charge (electrons), it is immune to the charge storage scaling issue. Recently, Intel and Numonyx researchers demonstrated a 64MB test chip that stacks, or places multiple layers of PCM arrays within a single die. The layering of arrays provides the scalability to reach higher memory densities while maintaining high performance rates. So far, the cost of NAND flash technology has been driven to extremely low levels through the use of leading edge lithography, but it remains to be seen how much lower it can go. That is why many are looking for alternatives.
Price Gives NAND the Edge For Now

"At this time, HP believes it is too early to declare a clear winner," said Tomaszewski. "PCM may appear to be in the lead compared to the other technologies from a development timeline; however, it remains to be seen if PCM can deliver in high volumes and continue to scale while meeting power, capacity, reliability and endurance requirements."
PCM could be a strong alternative to flash, as it provides the same benefits as flash with faster speed, said Jim Handy, an SSD analyst at Objective Analysis, a semiconductor market research firm. Despite the growing momentum behind PCM, Handy believes that widespread production and implementation of the technology is years away, perhaps as much as a decade. "Right now, memory production processes are at 34 nanometers, and the process needs to go down to 10 to 12 nanometers," he said.
The biggest challenge facing PCM is cost, said Handy.
The first-generation PCM chips are more than twice as expensive as established chips such as DRAM and flash due to poor economies of scale and limited R&D, he said. PCM may be unable to compete on price with NAND flash, which is used to store images and movies on devices such as smartphones, said Handy, who believes NAND could have enough of a price advantage to hinder PCM adoption. Handy noted that Toshiba recently demonstrated a prototype of a NAND flash based on a 10-nanometer process. NAND could compete with PCM as chip sizes continue to shrink, he said. "At some point, NAND flash will reach the end of its line, which is when PCM or competing memory technologies could take off," said Handy.
PCM's Promise: Better Data Retention

PCM holds tremendous promise, mostly because it decouples data retention from endurance, said Doller.
"This means that if we cycle a PCM memory device a million times or just one time, the data retention will be identical," he said. Another phenomenon that makes it easier to use PCM in system-level designs is that a 'failure' always occurs during a write. "So if we are writing data to the device and a write-verify shows that the data is not there, the data can be immediately written again to another location," said Doller. "PCM is not plagued by intrinsic read disturb mechanisms, as NAND has been." Because of the exceptional reliability attributes of PCM, Doller expects this technology to be first adopted in applications with the most critical requirements. Samsung foresees that its version of PCM called phase change random memory (PRAM) will be used in place of NOR flash in a wide range of mobile applications, said Harry Yoon, senior manager of PRAM marketing for Samsung Semiconductor.
Smaller is better
PHASE-CHANGE MEMORY is, possibly along with Memristors, one of the holy grails of future memory technology. The original promise of non-volatile, lightning-quick RAM has over the course of time been replaced with a more downto-earth approach - a fast storage medium akin to SSD drives. This is precisely what a team of University of California San Diego (UCSD) researchers has been working on. Using kit from Micron Technology, the team has built a prototype phase-change memory (PCM) storage array called the "Onyx". Similar to an SSD drive, Onyx is a data storage device and the first benchmarks of it show how it outperforms commercially available server-grade SSDs by as much as 120 per cent in small block operations. Onyx is a PCIe card equipped with phase-change memory from Micron Technology and a FPGA controller. The Onyx prototype can currently store a total of 10GB of data although only 8GB are usable, while the remainder is reserved for error correction - yes, that's 20 per cent. Still, the team has put the Onyx on the test bench and compared it to an 80GB FusionIO drive, which is just about the fastest SSD silicon out there. According to the published data, preliminary tests on the prototype have yielded better than expected results, that is, a victory over FusionIO and its enterprise solution in small block writes. The Onyx soundly whacks FusionIO in read throughput and it performs even better when dealing with smaller blocks. When it comes to writes, the Onyx dominates the smaller block sizes but falls behind its competitor overall when large block writes are also factored in. The thing is, though, we're talking about first generation silicon, as opposed to the more mature NAND Flash SSDs that already abound. The team promises that there is plenty of room with this phase-change technology for growth and higher performance. To put things in perspective, the first generation of Onyx technology can deliver 1.1GB/s of read throughput and 470MB/s of write throughput. It also has lower CPU overhead than a regular SSD, which will either free up the CPU for other tasks or lower overall system power consumption. The team expects a second generation of PCM prototypes to come out within the next six to nine months with better results.
Read more: http://www.theinquirer.net/inquirer/boffin-watch-blog/2079311/phase-change-memory-makesdebut#ixzz1RylZ2QLH The Inquirer - Computer hardware news and downloads. Visit the download store today.

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Interfacial phase-change memory

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1. Figure 1: Optical pumpprobe testing of IPCM switching behaviour.

2. Figure 2: Electrical switching characteristics of IPCM devices.

3. Figure 3: Analysis of the RESET state.

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