1
Analysis of a Novel Metal Implant Junctionless
Tunnel Field-Effect Transistor for Better DC and
Analog/RF Electrostatic Parameters
Sukeshni Tirkey, Dheeraj Sharma, Dharmendra Singh Yadav and Shivendra Yadav
Abstract—Steep rise in the subthreshold slope, high current
driving capability, and negligible ambipolarity are the major
prerequisite conditions of tunnel field effect transistors (TFETs)
to make it applicable for Analog/RF circuit applications. Along
with that, fabrication of physically doped TFETs is a major
concern in device technology. In this context, this paper deals
with junction-less TFET with a metal implanted in the oxide
at the source/channel and drain/channel junctions to enhance
its ON-current and reduce the ambipolar nature. The metal
introduced at the source/channel junction generates abruptness
and brings improvement in subthreshold slope which increases
the current driving capability of the device. Similarly, the metal
implanted at the drain/channel junction widens the energy gap
at the same junction to reduce the ambipolar behavior of
the device. This also contributes to the enhancement of DC
and analog/RF performance of the device. The selection of
appropriate work function and length of the metal implanted
at both the interfaces is important to maintain the improved
ON-current and ambipolarity. This optimization gives idea of
keeping the appropriate length which provides direction towards
practical feasibility at the experimental level.
Index Terms—Abruptness, ambipolar nature, metal implant
junction-less TFET, and steep subthreshold slope.
I. I NTRODUCTION
T UNNEL field effect transistors have been attracted much
attention lately due to its working phenomena of tunnel-
ing mechanism which allows dissipating less power making
it a potential candidate for low power applications [1]-[3]. It
exhibits very low OFF-state current and steep subthreshold
slope i.e.,(SS ≤ 60 mV/decade) [1]-[4]. Moreover, it is also
immune to short channel effects (SCEs) & drain induced
barrier lowering (DIBL) [1], [3]-[4] unlike metal oxide semi-
conductor FETs (MOSFETs) [5]-[6]. Despite providing these
advantages TFET suffers from low current driving capability
(due to the limited amount of charge carriers tunneling through
the junction) and ambipolar behavior (conduction for both
positive and negative gate voltages) [7]-[8]. TFET being an
ambipolar device with low ON-current hinders its application
at the circuit level. Therefore, these mentioned issues need to
be addressed seriously in order to bring the utility of TFETs
in circuit and chip level applications. A lot of work have been
reported to eliminate these problems and still in process. To
name a few it includes:
(i) Use of hetero material (Band gap engineering) i.e., intro-
ducing low band gap material (in source region) and high
band gap material (in channel & drain region) to increase
The authors are with the Electronics and Communication Discipline,
PDPM-Indian Institute of Information Technology Design and Manufacturing,
Jabalpur, M.P, India. E-mail: (sukeshni04@gmail.com; dheeraj@iiitdmj.ac.in;
dharmendra.yadav@iiitdmj.ac.in; shivendra1307@gmail.com)
ON-current and to reduce ambipolar nature of the device
respectively [9]-[11]. Although, this method creates lattice
mismatch and is also expensive due to the rare availability
of the materials with desired energy gap.
(ii) Gate-drain overlap [8] and gaussian doping in drain region
[12] are also reported for the reduction of ambipolar nature
but not applicable in doping less devices.
(iii) Hetero gate dielectric is also reported to lower down the
ambipolar nature of the device. However, this increases the
parasitic capacitance and makes the RF performance poor [13].
(iv) TFETs with shorter gate configurations have also shown
suppressed ambipolarity as reported in [14]. But this method
is attractive, especially for vertical nanowire-based transistors.
Apart from these, as the device feature size has reached
below 100 nm fabrication complexity is the major concern for
such technology node. In this regard, junctionless TFETs have
garnered much attention in the current scenario of semiconduc-
tor industry which avoids physical doping for the formation
of source, channel and drain region making it free from
random dopant fluctuations (RDFs) with degradation in device
electrostatic behavior [15]-[19]. Keeping this into concern, we
have explored a new technique to form junction-less TFET
where firstly P+ substrate is considered in the silicon body and
then metal electrodes with specific work functions are applied
to form the channel and drain regions. This removes the barrier
present between source and gate electrode of conventional JL
TFET which improves the ON-current of the device. Further to
enhance the device characteristics metal strip [20] is implanted
inside the oxide region between gate/source and gate/drain
electrodes which significantly improves the ON-state current,
subthreshold slope and reduces the ambipolarity of the device.
This also improves the transconductance and high-frequency
performance of the device. Furthermore, the optimization of
work function and misalignment of the length of the metal
implant is investigated for considering its impact on device
performance.
The remaining paper is arranged as follows: Section II
describes the device dimensions, simulations, and technology
aided computer design (TCAD) models followed by results
and discussion in section III which includes device charac-
teristics and optimization process. Finally, some informative
highlights drawn from the investigation are shown as a con-
clusion in section IV.
II. D EVICE S TRUCTURE AND S IMULATION S ETUP
The cross-sectional view of structures considered under
study are shown in Fig. 1(a) junction-less TFET (JL TFET)
(conventional), Fig. 1(b) Metal imposed at source/channel
 2

Fig. 1. Cross-sectional view of (a) junction-less tunnel field-effect transistor (JL-TFET) and (b) Metal Imposed at source/channel interface (MI JL-TFET-1)
and (c) Metal Imposed at drain/channel interface & source/channel interface (MI JL-TFET-2).
(S/C) interface (MI JL TFET-1) and Fig. 1(c) Metal Imposed the allocated temperature window to obtain the desired thin
at drain/channel interface (D/C) & source/channel (S/C) in- film deposition. Deposition of Hf, Pt, Au, Cu etc can be
terface (MI JL TFET-2). MI JL TFET-1 and ML JL TFET-2 done similarly through ALD technique [22]-[26]. Thin film
have one thing in common that they are obtained from P+ layer can also be deposited by low pressure chemical vapor
doped substrate with concentration 1019 cm−3 and then drain deposition [27].
electrode (M1) and the gate electrode (M2) with appropriate Silvaco ATLAS simulator version 5.20.2.R. [28] is used to
work functions are applied to obtain a typical JL TFET. execute the simulation of the considered devices. Performance
Further, a metal is implanted at the S/C and D/C connection calculations are done by using the following models: band
to obtain the improved device performance. Desired work gap narrowing (BGN) model, nonlocal band-to-band tunneling
function can be obtained by the use of Molybdenum with (BTBT) model to consider the tunneling generation rate at the
nitrogen implant dose as metal, as it carries unique properties respective tunneling junctions. Minority recombination effects
like high melting point and low resistivity. It facilitates to are accounted by Shockley-Read-Hall and Auger recombina-
adjust the work function at particular annealing conditions tion. Along with these, quantum confinement model given
thus providing adjustable work function according to the by Hansch and trap-assisted tunneling (TAT) model given by
requirement [21]. The structural and dimensional parameters Schenk are also employed [28]-[30].
used in the simulation are mentioned in table I.
TABLE I
D EVICE DESIGN PARAMETER USED IN SIMULATIONS . III. R ESULTS AND DISCUSSION
parameters Value parameters Value A. Comparative performance analysis of JL TFET, MI JL
Drain Length (LD ) 50 nm M2 work function 4.5 eV [15] TFET-1 with ML JL TFET-2
Source Length (LS ) (Fig. 1(a)) 50 nm M3 work function 5.93 eV [15]
Source Length (LS ) (Fig. 1(b-c)) 55 nm A1 work function (φA1 ) 3.9 eV
In this section, the impact of the metal implant at D/C and
Channel Length (LCH ) 50 nm A2 work function (φA2 ) 4.0 eV S/C interface (Fig. 1(b) and Fig. 1(c)) is shown and compared
Gate/drain space (LGD ) 5 nm Metal implant thickness 0.5 nm with conventional JL TFET in terms of the electron-hole
Gate/source space (LGS ) 5 nm Oxide thickness above/below 0.75 nm concentration, electric field, energy band diagram and IDS vs
A1/A2
VGS curve. Fig. 2(a) and Fig. 2(b) demonstrate the electron
Silicon thickness (tSi ) 10 nm Position of X1 40 nm
and hole concentration under thermal equilibrium state of three
Physical oxide thickness (tOX ) 2 nm [4] Position of X2 60 nm
devices where it is evidently seen that metal implant at S/C
Gate oxide material SiO2 (=3.9) Position of X3 100 nm
M1 work function 3.9 eV [15] Position of X4 105 nm
junction (MI JL TFET-1 & MI JL TFET-2) increases the
electron concentration and decreases the hole concentration.
As far as the practical feasibility of the device is concern the Further to this, the combined effect of the metal implant
metal layer inside the oxide at the source/channel junction and at S/C and D/C junction (MI JL TFET-2) shows enhanced
the drain/channel junction can be done by atomic layer deposi- electron concentration (at S/C interface) and decreased hole
tion (ALD) [22]. ALD is a technique used to deposit different concentration (at D/C interface) in Fig. 2(a) and Fig. 2(b)
thin films through vapour phase and a tunable film composition respectively. This increased electron concentration at the S/C
can be formed at the thickness control of Angstrom level (i.e., junction creates abruptness at the junction which results into
0.1 nm) [22]. This process is mainly processed under modest steeper S/C junction (MI JL TFET-1 & MI JL TFET-2) as
temperature (< 35000 C). In our proposed device the thickness given in Fig. 2(c) to allow more charge carriers (electrons) to
of metal layer is of 0.5 nm and the length of metal layer is tunnel through and provide higher ON-current. This is due to
5 nm which could be easily obtained by ALD method. The enhancement in the electric field for MI JL TFET-1 and MI
range of temperature where the saturation in the growth of JL TFET-2 as compared to JL TFET (Fig. 2(d)). To analyze
thin film occurs is dependent on the specific ALD process the influence of metal implant at D/C interface, band profile is
which is known as ALD temperature window. Temperature shown under OFF-state in Fig. 3(a) where it is observed that
outside this window turns out in slow reaction and poor growth due to the presence of metal at the D/C interface bands are
rates. Hence it is important to operate this ALD technique in uplifted and create a larger barrier at the same interface which

Fig. 2. Comparison between JL-TFET, MI JL-TFET-1 and MI JL-TFET-
2 under thermal equilibrium condition (a) electron concentration, (b) hole
concentration, (c) energy band diagram and (d) electric field.
is helpful in the suppression of ambipolar behavior for negative
gate bias as shown in Fig. 3(b). Now from Fig. 3(b) it is shown
that ON-current is improved and ambipolarity is suppressed
significantly for MI JL TFET-2 due to the combined effect of
the metal implant at D/C and S/C interface. Along with that,
steep subthreshold slope (SS) of 4.91 mV/dec is obtained for
MI JL TFET-1 and MI JL TFET-2 against 16 mV/dec for JL
TFET (conventional) (SS is calculated by point subthreshold
swing which is defined as the minimum swing of transfer
characteristics at any point [3]).
Fig. 3. Comparison between JL-TFET, MI JL-TFET-1 and MI JL TFET-2
for (a) energy band under OFF-state (b) Ids vs Vgs curve.
The reduction in energy barrier (Fig. 2(c)) create steeper
tunneling junction which increases the rate of flow of charge
carriers at a smaller gate voltage (Vgs ) i.e., threshold volt-
age reduces to 0.39 V from 0.78 V when compared to JL
TFET. Transconductance (gm ) and output conductance (gds )
are important parameters to determine the efficiency of the
device. Transconductance is the electrical characteristic of the
device that relates the output current of the device to the
input voltage across the device showing its ability to provide
high current driving capability. Whereas, the gds determines
the dependency of drain current over drain voltage. High gds
shows less resistance and less variation with respect to Vds
3
which provides immunity against SCEs and drain induced
barrier lowering (DIBL). In this regard, gm and gds are
depicted in Fig. 4(a) and Fig. 4(b) respectively. In Fig. 4(a) it
is evident that MI JL TFET-1 and MI JL TFET-2 show higher
gm as compared to conventional JL TFET which ensures its
high current drivability. Similarly, Fig. 4(b) depicts gds where
it is clear that the structures having the metal implant at S/C
interface (MI JL TFET-1 and MI JL TFET-2) show high gds
making it robust against SCEs.
Fig. 4. Comparison of (a) Transconductance and (b) Output conductance
w.r.t. Vgs .
Fig. 5. (a) Shows the comparison of (a) Cgs and (b) Cgd w.r.t. Vgs .
B. Analog/RF Figure of merits (FOMs) comparison
Analog/RF performance determines the ability of devices
to operate in high-frequency regions. This section presents
the comparison of high frequency metrics for all the devices
considered in terms of gate to source capacitance (Cgs ),
gate to drain capacitance (Cgd ), cut off frequency (fT ), gain
bandwidth product (GBP ), transit time (τ ), intrinsic gain (IG),
maximum frequency (fmax ) and transconductance generation
factor (TGF). Parasitic capacitance creates a huge impact on
the high-frequency parameters as it creates parasitic oscilla-
tions. Lower parasitic capacitance provides better control of
gate over the channel to enhance the RF FOMs.
Fig 5(a) and Fig. 5(b) show Cgs and Cgd for the three
devices w.r.t. Vgs and it is seen that MI JL TFET-2 shows lesser
parasitic capacitance due to the influence of A1 at D/C and A2
at S/C interface. fT is the frequency where short circuit current
gain attains value unity and is given by fT =gm /(2 π(Cgs +
Cgd )) whereas GBP is the range of frequency for which a
device can be operated in, and is formulated as GBP =gm /(2
πCgd ). Fig. 6(a) and Fig. 6(b) show the comparison of fT
& GBP where it is shown that MI JL TFET-2 exhibits high
fT and GBP among all due to the enhanced gm (Fig. 4(a))
and reduced parasitic capacitance (Fig. 5) by the combined
effort of presence of metal at D/C & S/C junctions which

Fig. 6. Shows the comparison of (a) cut off frequency, (b) gain bandwidth
product and (c) transit time w.r.t. Vgs .
ensures the applicability of MI JL TFET-2 for high-frequency
applications.
In addition to fT and GBP , transit time (τ ) is another
essential parameter to acknowledge the device for high fre-
quency operation which is given by τ =1/(2πfT ). τ is the time
requirement of charge carriers flowing from source to drain
region. Less τ shows better response and high operational
speed of the device. The comparison of τ for JL TFET, MI
JL TFET-1, and the MI JL TFET-2 is displayed in Fig. 6(c),
which illustrates that τ for MI JL TFET-2 is lesser than JL
TFET for the entire range of Vgs , providing it high operational
speed. Intrinsic gain (IG) is the product of gm and output
resistance (Ro ), where Ro is dominating factor. Variation in
IG with respect to Vgs is shown in Fig. 7(a), where it is shown
that higher IG is under subthreshold region and then it shows
falling graph for higher Vgs . This happens because Ro is very
high below threshold voltage due to lesser drain current, and
after crossing Vth TFET works under band to band tunnelling
(BTBT) phenomena which decreases RO and increases the
gm . This fall in RO and rise in gm causes degradation in IG of
the device w.r.t Vgs [31]. MI JL TFET-2 shows the highest IG
at small values of Vgs compared to JL TFET and MI JL TFET-
1. The other parameter to acknowledge the RF performance
is the fmax . It is the frequency at which the power gain of
the device attains value unity. It is defined as power gain with
very little reverse transmission [32]. It is formulated as:
s work function can be achieved by using nitrogen implant on
fT
fmax = 2 (1)
8πCgd Rgd
The above mentioned equation signifies that fmax depends
upon gm , Cgd , and Cgs which all are the geometrical param-
eters of the device. fmax for all the three devices is shown in
Fig. 7(b) where it is depicted that fmax increases with Vgs and
after attaining peak value it falls for higher values of Vgs . In
4
the figure it is observed that MI JL TFET-2 achieves highest
fmax as compared to the other two devices due to high gm
and low parasitic capacitances. This leads the proposed device
(MI JL TFET-2) best for high frequency applications among
the other devices.
Fig. 7. Shows the comparison of (a) intrinsic gain, (b) fmax (c) TGF of all
the devices .
Apart from these parameters, transconductance generation
factor (TGF) is another key parameter to acknowledge RF
analysis which measures the device efficiency which converts
the drain current into gm formulated as gm /Ids . It also opti-
mizes the drain current for efficient amplification at low power
dissipation. The impact of metal implant over the devices as
shown in Fig. 7(c) which presents that MI JL TFET-2 shows
the highest TGF as compared to JL TFET and MI JL TFET-1
under subthreshold region and then it falls for higher Vgs due
to rapid increment of Ids for higher gate voltages, because in
case of TGF drain current is dominant as compared to gm .
TGF is plotted from 0.2 voltage i.e., near threshold voltage as
drain current is negligible under subthreshold region [32].
C. Optimization of metal implanted work function φA1 and
φA2 for MI JL TFET-2
The selection of proper work function is very important
to obtain desired device characteristics. Therefore, in this
section optimization of work function for the metal implant,
both at D/C and S/C interfaces are demonstrated. Tunable
Molybdenum [21]. Fig. 8(a) and Fig. 8(b) show the band
energies of MI JL TFET-2 under ambipolar and ON-state
respectively at different values of work function (φA1 ) where
it is observed that as φA1 increases, the energy level at D/C
interface increases which provides hurdle to the charge carriers
to cross from channel to drain region under negative gate bias
leading to suppression of ambipolar nature as presented in Fig
8(c).

Fig. 8. Performance of MI JL TFET-2 wrt Vgs at different φA1 (a) Energy band profile under ambipolar-state (b) Energy band profile under ON-state (c)
Ids vs Vgs curve.
Fig. 9. Performance of MI JL TFET-2 wrt Vgs at different φA2 (a) Energy band profile under thermal equilibrium (b) Ids vs Vgs curve.
It can be noticed that ambipolarity is completely suppressed
for φA1 ≥ 4.2 eV but at the same time, few bands for φA1 ≥
4.1 eV gets uplifted under the channel portion and creates
misalignment of bands at the S/C interface (Fig. 8(b)) which is
responsible for the degradation in ON-current as shown in Fig.
8(c) at higher gate voltages. Therefore, φA1 =4.0 eV is selected
as optimized work function to achieve better ON-current and
ambipolarity. In a similar manner, the work function of the
metal implant at the S/C interface is varied and its impact is
demonstrated in the band energies under thermal equilibrium
in Fig. 9(a) along the lateral direction. Here, it is noted that
there is no such significant change in the lateral distance
between the valence and conduction band at the S/C junction
for φA2 ≤ 3.8 eV. Thus there is no significant change in ON-
current for φA2 ≤ 3.8 eV. However, as φA2 exceeds 3.8 eV,
the lateral distance increases continuously with misalignment
in the valence band and conduction band at the S/C interface
with φA2 which degrades the tunneling rate of charge carriers
and degrades the ON-current as depicted in Fig. 9(b). Apart
from these, the ambipolarity remains suppressed in all the
cases (Fig. 9(b)) as the band at D/C interface is not affected
by changing the work function at S/C interface. Thus, this
optimization ensures that low value of φA2 provides higher
ON-current. Thus, in our study φA2 is kept 3.9 eV as optimized
work function.
D. Optimization of length of metal implant for MI JL TFET-2
It is imperative to study the optimization of the length of
metal implant to make this concept applicable not just at the
simulation level but also at the experimental level. This section
therefore describes the impact of length variation of the metal
implant from its position. 1st case is considered where X1 is
5
varied keeping X2 fixed. For this case Fig. 10(a) and Fig. 10(b)
show the band profile of MI JL TFTE-2 under ambipolar and
ON-state respectively. Here, it is noticed that as the length of
metal implant (A1) is increased towards left from X1 position
(original length of A1 is 20 nm, when increased towards left
it becomes 22, 24 and so on) the bands under that portion
also shifts towards left from X1 position. This creates a larger
tunneling barrier at the drain/channel interface (Fig. 10(a) and
Fig. 10(b)) which in turn maintains the suppressed ambipolar
nature of the device for larger negative gate bias as evident in
Fig. 10(c).
At the same time, there is no such alteration in the bands
at S/C interface (Fig. 10(b)), hence, there is no change in
ON-current (Fig. 10(c)). Similarly, the 2nd case is considered
where X2 position is increased towards channel keeping X1
fixed. Fig. 10(d-e) show the band profile of MI JL TFET-
2 under ambipolar and ON-state. Here, it can be noticed
that the energy level for the increment portion of the metal
implant under the channel region remains constant for the
larger distance as in between the gate and drain electrode under
metallic region. This restricts the charge carriers to flow from
channel to drain for the entire range of negative gate bias (Vgs =
0.0 to -1.5) and the ambipolarity is completely suppressed
for larger values of length (>20 nm) as shown in Fig. 10(f).
Therefore from this analysis, it is perceived that 20 nm metal
implant is good enough to suppress ambipolarity of the device
and even if it is misaligned (to and fro) from its position there
will be no adverse effect on the device performance which is
acceptable for the experimental study of the concept. Along
with the optimization of the length of the metal implant at
the D/C interface, it is important to consider the effect of
misalignment of metal implant length at the S/C interface. For
 6

Fig. 10. Performance of MI JL TFET-2 with shift in X1 position (a-b) Energy band profile under ambipolar and ON-state (c) Ids vs Vgs curve. Performance
of MI JL TFET-2 with shift in X2 position (d-e) energy band profile under ambipolar and ON-state (f) Ids vs Vgs curve.

Fig. 11. Performance of MI JL TFET-2 with shift in X3 position (a-b) Energy band profile under thermal and ON-state (c) Ids vs Vgs curve. Performance
of MI JL TFET-2 with shift in X4 position (d-e) energy band profile under thermal and ON-state (f) Ids vs Vgs curve.
TABLE II
DC PARAMETRIC ASSESSMENT FOR DIFFERENT SHIFT IN POSITIONS OF METAL IMPLANT AT THE S/C INTERFACE
Length of Shift in X3 at X4 fixed Shift in X4 at X3 fixed Shift in X3 & X4 simultaneously
metal im-
plant
SS (mV) Vth (V) ION (A/µm) IOF F (A/µm) SS (mV) Vth (V) ION (A/µm) IOF F (A/µm) Length of SS (mV) Vth (V) ION (A/µm) IOF F (A/µm)
metal im-
plant
5 nm 4.91 0.39 8.61 × 10−6 3.01 × 10−21 4.9 0.35 8.6 × 10−6 3.013 × 10−21 5 nm 4.9 0.3 8.6 × 10−6 3.01 × 10−21
6 nm 5.88 0.36 8.49 × 10−6 3.01 × 10−21 4.9 0.35 9.44 × 10−6 3.013 × 10−21 7 nm 6.22 0.35 8.5 × 10−6 1.93 × 10−20
7 nm 7.56 0.36 8.44 × 10−6 3.01 × 10−21 4.8 0.36 6.36 × 10−6 3.014 × 10−21 9 nm 12.34 0.4 6.29 × 10−6 1.51 × 10−20
8 nm 10.86 0.33 8.40 × 10−6 3.01 × 10−21 9.1 0.4 1.8 × 10−6 3.014 × 10−21 11 nm 18.34 0.4 1.77 × 10−6 3.15 × 10−15
9 nm 16.45 0.32 8.38 × 10−6 2.09 × 10−13 20.5 0.8 1.01 × 10−6 3.014 × 10−21 13 nm 29.67 0.87 1.85 × 10−9 4.34 × 10−13
10 nm 20.9 0.32 8.37 × 10−6 3.97 × 10−12 22.6 0.85 9.45 × 10−9 3.014 × 10−21 15 nm 35.41 0.89 1.22 × 10−9 4.44 × 10−12
11 nm 25.78 0.31 8.36 × 10−6 1.49 × 10−11 24.3 1.2 9.11 × 10−9 3.015 × 10−21 17 nm 40.41 1.41 8.73 × 10−10 1.44 × 10−12
12 nm 30.76 0.30 8.36 × 10−6 2.96 × 10−11 24.5 1.48 8.64 × 10−9 3.015 × 10−21 19 nm 44.67 1.49 6.67 × 10−10 1.23 × 10−11

this, we have considered possible cases of metal implant length
misalignment: (1) X3 is increased towards left keeping X4
fixed and (2) X4 is increased towards right keeping X3 fixed
(the original length of A2 is 5 nm, when it is increased from
X3/X4 position it becomes 6, 7, 8... 12 nm). For the 1st case,
band profile is shown under thermal and ON-state in Fig. 11(a-
b). In Fig. 11(a) it is illustrated that the energy of bands under
the channel portion decreases with the increment in length of
metal towards the channel which decreases the barrier between
source and drain region. As a result of this OFF-state current
of the device increases as shown in (Fig. 11(c)). Further, Fig.
11(b) depicts the band energy under ON-state which shows
that the steepness of the bands gets disturbed under channel
portion with increment of X3 towards left which effects the SS
of the device, whereas, the energy barrier at the S/C junction
remains same and hence the ON-current remains unaltered
which is evidenced by Fig. 11(c). Another case is considered
where the position of X4 is increased towards the source. Here,
band profile under thermal and ON-state are illustrated in Fig.
11(d-e). Here it is observed that upto 8 nm increment in the
X4 position there is no such significant disturbance in the
energy bands at the source/channel junction, hence there is no
significant degradation in ON-state current for A2 upto 8 nm.
Further increment in the X4 position beyond 8 nm degrades
the steepness of bands and the lateral distance between the
bands is also increased due to the increase in the length of
X4 in source region which ultimately degrades the transfer
characteristics of the device as shown in Fig. 11(f). For both
the cases (increment of X3 and X4) it is evident that the metal
layer (A1 and A2) can withstand 8 nm length to maintain better
ON current, steep subthreshold slope and lower threshold
voltage. This metal layer deposition could be obtained by ALD
technique where already thin film is deposited at a thickness
control of Angstrom level (0.1 nm) [22]. Thus obtaining 8 nm
length for metal layer is easily possible at experimental level
by ALD technique [22].
DC parameters values for the shift in length of the metal
implant (A2) for the cases studied above are presented in Table
II with one more case i.e., X3 and X4 both are increased
simultaneously towards channel and source respectively. This

analysis brings us to the information that the metal implant
misalignment at the D/C interface can be tolerated as it does
not create much effect on the DC parameters of the device,
but the metal implant length at the S/C interface should not
be more than 6 to 7 nm to maintain the superior performance
of the device.
IV. C ONCLUSION
In summary, we have presented a novel concept of junction-
less TFET derived from P+ substrate which maintains the
traditional CMOS fabrication technology. In this structure new
approach is adopted to create abruptness and widening of
tunneling gap by implanting a metal in the oxide region at the
S/C interface and D/C interface respectively. This brings huge
abruptness at the source/channel tunneling junction which
intensifies the tunneling rate of charge carriers and improves
ION , SS, Vth and gm of the device. Minimum conduction
(Vth ) starts at 0.39 V for MI JL TFET-1 MI JL TFET-2
instead of 0.78 V as in conventional JL TFET. SS becomes
4.9 mV/decade (for MI JL TFET-1 & MI JL TFET-2) against
16 mV/decade. These improvements in the device make the
device suitable for switching and low voltage applications.
Due to increased gm and lowered parasitic capacitances RF
parameters (fT , GBP , τ , IG, fmax , and TGF) also acquires
improvement in case of MI JL TFET-2 which makes the
device applicable in low power RF circuit applications, pro-
vides higher device efficiency and speed. The work function
and optimization shows that φA1 = 4.0 eV, and φA2 = 3.9
eV provides improved DC performance. Whereas, in length
optimization, it is shown that metal implant at D/C interface
(A1) if increased towards the channel or drain, it does not
affect the DC characteristics. This means the length of A1
could be between 20 to 28 nm which can be easily fabricated
at the experimental level [22]. However, metal implant (A2)
at S/C junction should be less (≤ 8 nm) to provide better
performance.
R EFERENCES
[1] A. C. Seabaugh and Q. Zhang, “Low voltage Tunnel Transistor beyond
CMOS logic,” in Proc. IEEE, vol. 98, no. 12, pp. 2095-2110, Dec. 2010.
[2] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect
transistor (TFETs) with subthreshold swing (SS) less than 60 mV/Dec,”
IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007.
[3] Q. Zhang., W. Zhao, A. Seabaugh, “Low-subthreshold-swing tunnel
transistors, ” IEEE Trans. Electron Device Lett, Vol. 27, no.4, pp. 297-
300, Apr 2006.
[4] K. Boucart and A, M. Ionescu, “Double gate Tunnel FET with high κ gate
dielectric, ” IEEE Trans. Electron Devices, vol. 54 , no. 7, pp. 1725-1733,
July. 2007.
[5] P. H. Woerlee, M. J. Knitel, R. van Langevelde, D. B. M. Klaassen,
L. F. Tiemeijer, A. J. Scholten, and A. T. A. Zegers-van Duijnhoven,
“RFCMOS performance trends,” IEEE transaction on Electron Devices,
vol. 48, no. 8, pp. 1776-1782, Aug. 2001.
[6] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-
S. P. Wong, “Device scaling limits of Si MOSFETs and their application
dependencies,” Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
[7] A. Hraziia et al.“An analysis on the ambipolar current in Si double-gate
tunnel FETs,” Solid-State Electron, vol. 70, pp. 67-72, 2012.
[8] D. B. Abdi and M. J. Kumar, “Controlling Ambipolar Current in Tun-
neling FETs Using Overlapping Gate-on-Drain,” Electron device society,
vol. 2, no. 6 pp. 187-190, May. 2014.
[9] B. R. Raad, D. Sharma, K. Nigam and P. Kondekar, “Physics-based
simulation study of high-performance gallium arsenide phosphideindium
gallium arsenide tunnel field-effect transistor,” IET Micro and Nano Lett.,
vol. 11, no. 7, pp. 366-368, Jul. 2016.
7
[10] S. K. Gupta, J. P. Kulkarni, S. Dutta and K. Roy, “Hetero junction intra-
band tunnel FETs for low voltage SRAMs,” IEEE transaction on Electron
devices, vol. 59, no. 12 pp. 3533-3542, Dec. 2012.
[11] B. R. Raad, K. Nigam, D. Sharma and P. N. Kondekar, “Performance
investigation of bandgap, gate material work function and gate dielectric
engineered TFET with device reliability improvement,” Superlattice and
microstructures, vol. 94, no. 6 pp. 138-146, April. 2016.
[12] V. Vijayvargiya and S. K. Vishvakarma, “Effect of Drain Doping Profile
on Double-Gate Tunnel Field-Effect Transistor and its Influence on
Device RF Performance, ” IEEE Trans. on Nanotechnology, vol. 13, no.
5, pp. 974-981, Sept. 2014.
[13] W. Y. Choi and W. Lee, “Hetero-Gate-Dielectric Tunneling Field-Effect
Transistors, ” IEEE Trans. on Nanotechnology, vol. 57, no. 9, pp. 2317-
2319, Sept. 2010.
[14] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken,
“Tunnel field-effect transistor without gate-drain overlap, ” Appl. Phys.
Lett., 91, 053102 (2007).
[15] M. J. Kumar and S. Janardhanan, “Doping-less tunnel field effect
transistor: Design and investigation,” IEEE Trans. Electron Devices, vol.
60, no. 10, pp. 3285-3290, Oct. 2013.
[16] M. S. Ram, D. B. Abdi, “Dopingless PNPN tunnel FET with improved
performance: Design and analysis,” Superlattices and Microstruct., vol.
82, pp. 430-437, 2015.
[17] S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. Murali, S. Ganguly,
and A. Kottantharayil, “Effect of Band-to-Band tunnelling on junctionless
transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1023-1029,
Apr. 2012.
[18] F. Bashir, S. A. Loan, M. Rafat, M. R. M. Alamoud, S. A. Abbasi,
“A high performance gate engineered charge plasma based tunnel field
effect transistor,” Journal of computational electronics, vol. 14, pp. 477-
485, June. 2015.
[19] B. Ghosh and M. W. Akram, “Junctionless Tunnel Field Effect Tran-
sistor,” IEEE Electron Device Lett., vol. 34, no. 5, pp. 584-586, May
2013.
[20] B. R. Raad, S. Tirkey, D. Sharma, And P. N. Kondekar, “A new
design approach of dopingless tunnel FET for enhancement of device
characteristics,”IEEE transaction on Electron Device., vol. 64, no. 4, pp.
1830-1836, Apr. 2017
[21] P. Ranade, H. Takeuchi, T.-J. King, and C. Hu, “Work function en-
gineering of molybdenum gate electrodes by nitrogen implantation,”
Electrochem. Solid State Lett., vol. 4, no. 11, pp. G85-G87 , Apr. 2001.
[22] R. W. Johnson, A. Hultquist, and S. F. Bent, “A brief review of atomic
layer deposition: From fundamentals to applications,” Materials today.,
vol. 17, no. 5, June. 2015.
[23] K. Kim1, H. B. R. Lee, R. W. Johnson, J. T. Tanskanen, N. Liu, M.
G. Kim, C. Pang, C. Ahn, S. F. Bent, and Z. Bao, “Selective metal
deposition at graphene line defects by atomic layer deposition,Nature
Communications,”Sep 2014.
[24] S.M. George, “”Atomic Layer Deposition: An Overview,”Chemical
Reviews, vol. 110, no. 1,pp. 111-131, Nov. 2009.
[25] M. B. E. Griffiths, P. J. Pallister, D. J. Mandia, and S. T. Barry, “Atomic
Layer Deposition of Gold Metal,” Chemistry of materials, vol. 28, no. 1,
pp. 44-46, Dec 2015.
[26] M. B. E. Griffiths, P. J. Pallister, D. J. Mandia, and S. T. Barry, “Growth
of copper metal by atomic layer deposition using copper (I) chloride,
water and hydrogen as precursors,”Thin solid films, vol. 458, pp. 129-
136, 2004.
[27] L. Guo, E. Leobandung, L. Zhuang, and Stephen Y. Chou, “Fabrication
and characterization of room temperature silicon single electron mem-
ory,”American Vacuum Society,, july 1997.
[28] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA,
USA, 2014.
[29] W. Hansch, T. Vogelsang, R. Kirchner, and M. Orlowski,“Carrier trans-
port near the Si/Sio2 interface of a MOSFET, ” Solid State Electron., vol.
32, no. 10, pp. 839-849, Oct. 1989.
[30] A. Schenk,“A model for the field and temperature dependence of SRH
lifetimes in silicon,” Solid State Electron., vol. 35, no. 11, pp. 1585-1596,
Nov. 1992.
[31] Y. Goswami, B. Ghosh, and P. K. Asthana,“Analog performance of
Si junctionless tunnel field effect transistor and its improvisation using
IIIVsemiconductor, ”The Royal Society of Chemistry., vol.4, pp. 10761-
10765, Jan. 2014.
[32] J. Madan and R. Chaujar, “Interfacial Charge Analysis of Heterogeneous
Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reli-
ability, ” IEEE Transactions on Device and Materials Reliability, vol.16,
no. 2 pp. 227-234. June 2016.

Sukeshni Tirkey received the B.E. degree in elec-
tronics and telecommunication engineering from the
Government Engineering College, Bilaspur, India,
in 2011, and the M.Tech. degree from the Maulana
Azad National Institute of Technology, Bhopal, In-
dia, in 2015. She is currently pursuing the Ph.D.
degree in electronics and communication engineer-
ing with the Indian Institute of Information Tech-
nology, Design and Manufacturing, Jabalpur, India.
Her current research interest includes simulation and
modeling of nano-scale devices for low power and
high-frequency applications.
Dheeraj Sharma received the B.E. degree in-
electrical engineering from Rajiv Gandhi Proudyo-
giki Vishwavidyalaya, Bhopal, India, in 2004, the
M.Tech. degree in microelectronics and very large
scale integration design from the Shri Govindram
Seksaria Institute of Technology and Science, In-
dore, India, in 2009, and the Ph.D. degree from IIT
Indore, Indore, in 2014.
8
Dharmendra Singh Yadav received the B.E. degree
in Electronics and Communication Engineering from
Samrat Ashok Technological Institute (affiliated to
Rajiv Gandhi Prodyogiki Vishwavidya Bhopal, In-
dia) Vidisha, Madhya Pradesh, India, in 2009, the
M.E. degree in Electronics and telecommunication
from the Shri Govindram Seksaria Institute of Tech-
nology and Science, Indore, Madhya Pradesh, India,
in 2011, Currently, he is working toward the PhD
degree in the Electronics and Communication En-
gineering Department at the Pandit Dwarka Prasad
Mishra Indian Institute of Information Technology, Design and Manufacturing,
Jabalpur, India. His research interests include simulation and Modeling for
ultra-low power and high frequency application based devices and circuit.
Shivendra Yadav received the B.E. and M.Tech. de-
gree in electronics and communication engineering
from the R.G.P.V, Bhopal, India, in 2010 and 2015
respectively. He is currently pursuing the Ph.D. de-
gree in electronics and communication engineering
with the Indian Institute of Information Technology,
Design and Manufacturing, Jabalpur, India. His re-
search interests include simulation and Modeling of
devices at nanoscale regime and memory designing.