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Sg3525a D PDF
Sg3525a D PDF
• 8.0 V to 35 V Operation A
WL
= Assembly Location
= Wafer Lot
• 5.1 V 1.0% Trimmed Reference YY = Year
• 100 Hz to 400 kHz Oscillator Range WW = Work Week
• Separate Oscillator Sync Pin
• Adjustable Deadtime Control
• Input Undervoltage Lockout
PIN CONNECTIONS
OSC. Output 4 13 VC
CT 5 12 Ground
RT 6 11 Output A
Discharge 7 10 Shutdown
Soft−Start 8 9 Compensation
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
16 VC
Vref To Internal 13
15 Circuitry
Reference Under−
VCC Output A
Regulator Voltage
12 Lockout
Ground 11
NOR
4
OSC Output
3 Q
Sync
6 Oscillator F/F
RT Q NOR 14
5 Output B
CT
7
Discharge R
9 + S
Compensation − PWM Latch SG3525A Output Stage
1 −
INV. Input −
Error 50A S
2 Amp
Noninv. Input + VREF
8
CSoft−Start
10 5.0k
Shutdown 5.0k
ORDERING INFORMATION
Device Package Shipping†
SG3525AN PDIP−16 25 Units / Rail
SG3525ANG PDIP−16 25 Units / Rail
(Pb−Free)
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SG3525A
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC +40 Vdc
Collector Supply Voltage VC +40 Vdc
Logic Inputs −0.3 to +5.5 V
Analog Inputs −0.3 to VCC V
Output Current, Source or Sink IO ±500 mA
Reference Output Current Iref 50 mA
Oscillator Charging Current 5.0 mA
Power Dissipation PD mW
TA = +25°C (Note 1) 1000
TC = +25°C (Note 2) 2000
Thermal Resistance, Junction−to−Air RJA 100 °C/W
Thermal Resistance, Junction−to−Case RJC 60 °C/W
Operating Junction Temperature TJ +150 °C
Storage Temperature Range Tstg −55 to +125 °C
Lead Temperature (Soldering, 10 seconds) TSolder +300 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Derate at 10 mW/°C for ambient temperatures above +50°C.
2. Derate at 16 mW/°C for case temperatures above +25°C.
APPLICATION INFORMATION
Shutdown Options (See Block Diagram, page 2) latch is immediately set providing the fastest turn−off signal
Since both the compensation and soft−start terminals to the outputs; and a 150 A current sink begins to discharge
(Pins 9 and 8) have current source pull−ups, either can the external soft−start capacitor. If the shutdown command
readily accept a pull−down signal which only has to sink a is short, the PWM signal is terminated without significant
maximum of 100 A to turn off the outputs. This is subject discharge of the soft−start capacitor, thus, allowing, for
to the added requirement of discharging whatever external example, a convenient implementation of pulse−by−pulse
capacitance may be attached to these pins. current limiting. Holding Pin 10 high for a longer duration,
An alternate approach is the use of the shutdown circuitry however, will ultimately discharge this external capacitor,
of Pin 10 which has been improved to enhance the available recycling slow turn−on upon release.
shutdown options. Activating this circuit by applying a Pin 10 should not be left floating as noise pickup could
positive signal on Pin 10 performs two functions: the PWM conceivably interrupt normal operation.
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SG3525A
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc
Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline − 10 20 mV
Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload − 20 50 mV
Temperature Stability Vref/T − 20 − mV
Total Output Variation Includes Line and Load Regulation over Temperature Vref 4.95 − 5.25 Vdc
Short Circuit Current (Vref = 0 V, TJ = +25°C) ISC − 80 100 mA
Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Vn − 40 200 Vrms
Long Term Stability (TJ = +125°C) (Note 4) S − 20 50 mV/khr
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SG3525A
Vref
16 15 VCC
Reference Regulator
Clock 0.1 0.1
4 Flip/ 13 VC
Flop
3.0k 0.1
Sync
3 O Out A
PWM
ADJ. s 11
RT c A
1.0k
6 i
l
Deadtime l
1.5k 1.0k, 1.0W
a
0.009 Ramp 7 (2)
t
100 5 o
r
14
0.1 0.001 B
Out B
Comp
10k 9 12
PWM GND
1 = VIO
2 = 1(+) 0.01
3 = 1(−) 50A 8 Softstart
1 1
+
2 2 1 5.0F
− −
3 3 E/A 5.0k 10
2 5.0k Vref
V/I Meter +
1 1 2.0k
+ 2 2
3 3 DUT
Shutdown
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SG3525A
200 500
50
300
* RD = 0
20
200
10
6 5 7
RD * 100
5.0
RT CT
2.0 0
2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
CHARGE TIME (s) DISCHARGE TIME (s)
Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD
1 − 9
100 RZ 3.5
80 3.0
60 2.5
RZ = 20 k 2.0
40
1.5 Source Sat, (VC−VOH)
20
1.0
0 Sink Sat, (VOL)
0.5
−20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0
f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A)
Vref 15
16 VCC
Q1 Q5 Q8
7.4k
Q3
RT Q3
6
CT Q6 Q9
5 Ramp Q4
Inverting
2.0k 14k To PWM Q1 Q2
Input
3 2.0k Q10 Q11 25k 1
Sync Blanking To PWM
5.0pF Noninverting
7 Q14 To Output Input Comparator
Discharge 400A 2
Q4 5.8V 30
Q2 23k 200A 100A
Q7 1.0k Q12 Q13 250
12 1.0k 3.0k 9 Compensation
GND 4
OSC Output
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SG3525A
13
VCC VC
Q5 Q7
Q9
Q10
Q4
5.0k
11, 14
Vref Q8
Q11 Output
Q6
2.0k
Q1 Q2 Q3 Q6 Omitted
in SG3527A
Q1
+Vsupply
+Vsupply To Output Filter
R1
R1
C1
R2 13
11 T1
VC A Q1
13 R2
VC 11
A SG3525A C2
SG3525A 14
14
B Q2
B GND R3
GND
12
12
For single−ended supplies, the driver outputs are grounded. In conventional push−pull bipolar designs, forward base drive is
The VC terminal is switched to ground by the totem−pole controlled by R1−R3. Rapid turn−off times for the power devices
source transistors on alternate oscillator cycles. are achieved with speed−up capacitors C1 and C2.
Figure 10. Single−Ended Supply Figure 11. Push−Pull Configuration
+Vsupply +Vsupply
R1
Q1
T1 C1
13 Q1 T1
11 13 R1 T2
VC A 11
VC A
SG3525A SG3525A Q2
Q2 14
14
GND B GND B C2
12 R2
12
The low source impedance of the output drivers provides Low power transformers can be driven directly by the SG3525A.
rapid charging of power FET input capacitance while Automatic reset occurs during deadtime, when both ends of the
minimizing external components. primary winding are switched to ground.
Figure 12. Driving Power FETS Figure 13. Driving Transformers in a
Half−Bridge Configuration
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SG3525A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9
3. DIMENSION L TO CENTER OF LEADS
B WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
1 8 MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F C
INCHES MILLIMETERS
L DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
S B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
SEATING
−T− PLANE
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
K M G 0.100 BSC 2.54 BSC
H J H 0.050 BSC 1.27 BSC
G J 0.008 0.015 0.21 0.38
D 16 PL K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
0.25 (0.010) M T A M
M 0 10 0 10
S 0.020 0.040 0.51 1.01
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SG3525A
PACKAGE DIMENSIONS
SOIC−16L
DW SUFFIX
CASE 751G−03
ISSUE C
NOTES:
D A 1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
16 9 3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
M
h X 45
M
E
EXCESS OF THE B DIMENSION AT MAXIMUM
8X
0.25
MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
1 8 A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
16X B B C 0.23 0.32
D 10.15 10.45
0.25 M T A S B S E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
0 7
A
q
L
SEATING
14X e PLANE
A1
T C
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SG3525A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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