Design and Parametric Analysis of 32nm
OPAMP in CMOS and CNFET Technology for
Optimum Performance
Fahad Ali Usmani, Naushad Alam and Mohd. Hasan
Department of Electronics Engineering
Aligarh Muslim University Aligarh, India
fahadaliusmani@zhcet.ac.in
Abstract—There is a need to explore emerging technologies
based on carbon nanotube electronics as the CMOS technology is
approaching its limits. This will help in quick commercialization
of these promising technologies. This paper presents the design,
performance analysis and comparison of a carbon nanotube FET
(CNFET) based OPAMP with the one designed in CMOS for
32nm deep submicron technology node. We have designed and
simulated the basic two stage OPAMP for area, power and
performance optimization in Bulk CMOS technology and then
extended a similar transistor size design for CNFET based
OPAMP in terms of operating voltage, diameter and pitch of the
CNFET along with the qualitative explanation of the obtained
results using HSpice®. Furthermore, comparison of CNFET
based design with planar CMOS shows the superiority of the
former in terms of Gain (218% higher), settling times (93%
faster), power consumption (318% lower) and extremely good
noise performance for low power-low bandwidth design
depending upon the selection of the CNT diameter. Additionally,
we propose an optimal design of the output stage by lowering the
pitch (8nm) from normal (12nm) while keeping the width
constant for better slewing performance.
Keywords- Carbon Nanotube (CNT), nanowires, nanoelectronics,
Ballistic, scattering, chirality.
I. INTRODUCTION
CMOS manufacturing technology has continued its
breathtaking pace, scaling to ever-smaller dimensions reaching
beyond the sub 100 nm regime in agreement with the Moore’s
Law. Where the plunge into the deep-submicron space causes
devices to behave differently and brings to the forefront a
number of new challenges such as source to drain tunneling,
device mismatch, random dopant fluctuations, mobility
degradation, etc that impact its cost, reliability and
performance making further scaling almost impossible.
According to the International Technology Roadmap for
Semi- conductors [1], intensive research is needed in order to
continue this process, and indeed, to develop novel devices
and methods that will move the technology improvements
in other directions. A candidate transistor that may allow
for both the shrinking process to continue, and for the
development of novel architectures, is the carbon nanotube
field-effect transistor (CNFET).
Essentially, CNFET is a conventional MOSFET, except
that its semiconducting channel is made up of a carbon
978-1-4244-4495-3/09/$25.00 ©2009 IEEE
nanotube (CNT), and that the source and drain interfaces may
be Schottky contacts. Essentially CNFET can be thought to
resemble a SB-MOSFET but the major difference lies in the
much thinner barrier that exists in case of the CNFET and
therefore, no exponential current increase is observed for low
drain voltages (Vds). In 1991, Iijima first noticed the growth of
Multiwalled CNTs on an arc discharge electrode [2] and in
1998, their use in semiconductor electronics was demonstrated
through simulations and growth techniques [3]. Most attractive
feature of CNTs, for nanoelectronics, is their near-ballistic
transport due to a limited carrier-phonon interaction because of
larger mean free paths of acoustic phonons [4-5]. Additionally,
CNFET shows higher electron mobilities of the order 104 –105
cm2 /Vs [5] compared with 103 cm2 /Vs in bulk silicon and
higher current densities, roughly three orders of magnitude
greater than that reported for silicon nanowires indicating that
CNFET is a high quality semiconducting material [6]. Major
obstacle that remains is that of proper chirality control that
decides the metallic or semiconducting nature of the CNTs,
specific nanotube separation with good precision and surface
state control.
CNFET shows the potential to sustain Moore’s Law in the
nearby future because of its good similarity with CMOS and
capability to reduce the leakage power with continued scaling
[7]. For simulation purposes, we have used BSIM v4.6.1
BPTM models of complementary MOSFET at 32nm using
HSpice software package. High performance Verilog-A
Stanford model is used which successfully accounts for
CNFET practical non-idealities, such as scattering, effects of
the source/drain extension region, and inter-CNT charge
screening effects etc. apart from accurate predictions of
dynamic and transient performance with more than 90%
accuracy [8-9]. In our analysis, we have used top gated
undoped semiconducting (n,0) MOS-CNFETs having 4-nm
thick HfO2, high-k dielectric (k=16). In this paper, first we
design the CMOS OPAMP at 32nm for area, power and
performance optimization then we begin with a similar
geometry for CNFET based design setting the initial design
parameters to their most practical values and then optimizing
sequentially each of them. Finally CMOS and CNFET based
OPAMP is compared to give an idea of advantages and
disadvantages involved in switching the technology trend to
future nanoscale alternatives like CNFETs.
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 Wgate TABLE I. VARIATIONS OF PARAMETERS WITH SUPPLY VOLTAGE
Pitch
Dielectric CNTs
Drain (Kgate )
Gate t
Vdd 0.9V 0.7V 0.5V 0.3V
Ldd Drain Source

Lg Gate Csub
Substrate
DC Gain dB 14.656 14.502 14.8 27.47
Lss
tubes 3 DB BW MHz 0.34635 0.3536 0.379 0.1233
(number Source
of CNTs ) GBP MHz 8.8178 17.52 38.18 171
Figure 1. Schematic CNFET Cross-section Phase
Degrees 154.4 154.83 153.832 111.814
Margin
DC CMRR dB 45.656 37.021 22.831 10.2273
0dB CMRR dB 40.3132 51.531 37.649 37.654
DC PSRR dB 63.87 51.391 35.921 30.032
0-dB PSRR dB 16.483 16.696 18.346 25.726
Rise Slew
rate (20- V/us 107.94 63.041 55.094 27.055
80%)
Fall Slew
rate (20- V/us -17.183 -12.843 -14.908 -29.618
80%)
Settling
us 0.1809 0.2196 0.2746 0.0066
time(1%)
Average
mW 1.058 0.29634 0.1912 0.16047
Power
Figure 2. Two stage loaded CMOS opamp with Miller compensation
and gain bandwidth product of the system under desired
II. OPTIMAL CMOS OPAMP DESIGN AT 32NM limits. Final optimum design parameters values are listed for
Consider the basic two-stage frequency compensated 8T 32nm Bulk-CMOS technology in Table II.
operational amplifier which has been designed at 32nm for
optimum area occupancy i.e. aspect ratios as shown in fig. 2 III. CNFET PERFORMANCE PARAMETERS
and performance in terms of gain, unity gain bandwidth and Experiments have demonstrated that CNFET technology can
power dissipation etc. Practical robust design values of load also be easily clubbed with CMOS on the same chip [12] and
and feedback capacitances are chosen (10pF each) along with hence meaningfully comparable with CMOS but with different
initial constraints on desired parameter values such as keeping device physics involved. Here, we have designed the CNFET
first and second pole frequency sufficiently apart to allow OPAMP with same on chip area occupancy as CMOS by
stability phase margins above 90 degrees. Here, an selecting the similar widths given by eq. (1).
approximate design is used to investigate the best performance
values of aspect ratios for circuit operation in micron region W ( N 1) * S D CNT (1)
[10-11] which are then modified and optimized as per device
design specifications through Iterative simulation runs 0.84 eV
(Optimum Analysis) to very deep submicron regime (32nm) g
d CNT (2)
using HSpice®. Smaller channel lengths tend to introduce non-
idealities in conventional DC biasing schemes leading to A. Selection of supply voltage
instability problems in the biasing currents, hence device
mismatches emerge which requires the transistor widths to be For specified widths and default values of CNT pitch
high to achieve some improvement in matching due to the and diameter in addition to the adjustment of Leff to 12.6 nm
decreased effective channel area below the gate of the MOS to compare fairly with 32nm CMOS technology, the number of
transistor which in turn increases the power dissipation. tubes required is calculated and OPAMP parameters results are
reported in Table I for different value of operating voltages.
We observed the improvement in bandwidth and transient We find that reducing the Vdd significantly hampers the noise
performance as device scaling is performed due to the and transient performance of the amplifier due to reduced
reduction in certain unwanted large device capacitances and output signal swing and pronounced effect of parasitic voltages
increase in transconductance which further improves with the besides giving the best of other worlds due to proportionate
increased transistor widths while on the other hand degrading scaling. Moreover, for 0.3V choice, operation shifts towards
other circuit performance parameters because of reduced the sub threshold region where high sub threshold slope
current drive attributed to lower mobilities, degraded channel directly affects the rise slew rate. Hence, selection of 0.9V is
characteristics and short channel effects etc. in addition to gate made on the basis of overall performance as tabulated above.
leakage and fostered noise problems in very deep submicron B. Optimum Inter-nanotube spacing
region. As a part of the design, large size of biasing transistor
of the input stage, Q5 is kept to control power consumption For optimum Vdd, next we wish to investigate the most
appropriate spacing between the parallel tubes to be spread

127
 Figure 3. Variation of 3-dB Bandwidth and Gain Bandwidth product with
inter CNT Pitch
Figure 4. Variation of CMRR (dB) and PSRR (dB) with CNT Pitch in nm.
Figure 5. Variation of settle timings and worst case transient power
consumption of OPAMP with CNT pitch
between source and drain to make CNFET of some use due to
increased driving capability and current conduction in addition
to suppression of 1/f noise [13]. Fig 3 shows that frequency
response improves with pitch due to the fact that as CNTs
(constant in number) are brought farther, the capacitance from
the gate to each CNT channel, Cgc decreases because each
CNT can mirror a small amount of charge from the gate while
on the other hand, the current carrying capability i.e. I PER TUBE
goes down (but current driving capability per unit device
width improves) which indirectly affects the gain which was
initially increasing due to the increase in overall transistor
width. Moreover, now inter-nanotube (acting as conducting
channels) capacitances are also decreased as the separation
between them broadens. For smaller separations, each CNT
128
Figure 6. Variation of Gain and Bandwidth with CNT diameter in nm
Figure 7. Variation of CMRR(dB) and PSRR(dB) with CNT diameter
Figure 8. Variation of settling time and transient power with CNT diameter.
contributes to the noise due to electrostatic mobile carrier
interactions which stabilizes as the distance is increased,
thereby explaining the graph of fig 4. Slew rates and settle
timings are all better for larger pitch due to increased
transconductance values and reduced parasitics. Additionally
compromise between power and performance comes from the
selection of packing density as unwanted screening,
appreciable leakage and per nanotube current (~20 uA) lead to
the increased power dissipation of the circuit at both very low
and very high spacing. Hence, low power design demands for
optimum selection of pitch (12 nm) which also gives the
balancing advantages of gain and stability margins for robust
circuit operation.
C. Choice of Carbon Nanotube Diameter TABEL II. COMPARISON OF PARAMETERS OF CNFET, HYBRID
TECHNOLOGY AND BULK MOSFET INVERTING AMPLIFIERS AT 32NM NODE
Diameter and helicity decide the electronic properties of
Single wall CNTs resulting from the selective axial folding of Operational amplifier at 32nm-CNFET
32nm Bulk
2-D zero gap semiconducting material, Graphene with an CL = 10pF with S=12nm,
MOSFET
energy gap between the filled hole states and the empty Vdd= 0.9V DCNT= 1.8nm
electron states given by eq (2) [14]. Analytical results show DC Gain dB 19 9.1797
that with diameter increase, all circuit performance parameters 3 DB BW MHz 0.167 14.568
suffer with the exception of some improvement in bandwidth GBP MHz 10.152 37.842
and transient performance as shown in Fig. 6-8. Since Phase Margin Degrees 153.483 126.35
diameter is the main parameter that affects the on-current DC CMRR dB 62.974 -1.9214
proportionally (and hence transconductance) in a CNFET 0-dB CMRR dB 81.968 8.7727
apart from barrier height at the S/D contact (or RS/D), chirality DC PSRR dB 77.028 15.509
and oxide thickness, due to which gain and CMRR drop
0-dB PSRR dB 13.607 15.976
appreciably. Moreover, the power consumption of the
Rise Slew rate V/us 22.452 94.645
amplifier increases due to smaller bandgap as CNTs become
more conducting thereby enhancing the current drive which is Fall Slew rate V/us -4.2053 -71.898
also a reason for better slewing performance obtained. Settling
us 0.3575 0.6481
time(1%)
Bandwidth improves with an increase in diameter due to
Average Power mW 0.30544 1.5866
smaller effective pitch which strongly affects the outer fringe
and Cgc capacitances due to enhanced screening between V. CONCLUSION
adjacent channels. It is also observed that for lower diameters,
stability margins become very low indicating the loss of This work explores the advantages and disadvantages offered
robustness. We conclude that OPAMP could be designed for by newly emerging CNFET technology over the existing
low power-low bandwidth and high power-high bandwidth CMOS amplifier design which ceases to scale further to
applications on the basis of the selection of diameter. Here we deliver the desired performance merits. Moreover, we
select the optimum diameter value to be around 1.8nm. conclude that depending on performance requirements,
diameter (also responsible for scaling) plays an important role
IV. PERFORMANCE COMPARISON OF CNFET WITH CMOS and will limit the performance delivered by CNFET in future
TECHNOLOGY DESIGN e.g. low power design suits to smaller diameter while
Best simulation results obtained after several iterations show sacrificing the higher bandwidth requirements. Moreover, as a
that CNFET based amplifier outperforms the CMOS amplifier future scope of this work, more complex circuits could be
for various parameters like Gain (218% higher), settle timings investigated along with their hybrids and other nanoscale
(93% faster), power consumption (318 % lower) and noise alternatives could also be taken up for performance
performance as shown in Table II. Alongside, we observe that comparison to measure their capabilities for future analog and
CNFET offers low bandwidth for larger loads (~10pF) and mixed signal design.
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